@@ -191,34 +191,34 BEGIN | |||||
191 | sample_filter_in(i, 17) <= sample(i)(15); |
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191 | sample_filter_in(i, 17) <= sample(i)(15); | |
192 | END GENERATE; |
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192 | END GENERATE; | |
193 |
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193 | |||
194 |
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194 | coefs_v2 <= CoefsInitValCst_v2; | |
195 |
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195 | |||
196 |
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196 | IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 | |
197 |
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197 | GENERIC MAP ( | |
198 |
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198 | tech => 0, | |
199 |
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199 | Mem_use => use_RAM, | |
200 |
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200 | Sample_SZ => 18, | |
201 |
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201 | Coef_SZ => Coef_SZ, | |
202 |
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202 | Coef_Nb => 25, | |
203 |
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203 | Coef_sel_SZ => 5, | |
204 |
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204 | Cels_count => Cels_count, | |
205 |
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205 | ChanelsCount => ChanelCount) | |
206 |
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206 | PORT MAP ( | |
207 |
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207 | rstn => rstn, | |
208 |
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208 | clk => clk, | |
209 |
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209 | virg_pos => 7, | |
210 |
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210 | coefs => coefs_v2, | |
211 |
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211 | sample_in_val => sample_val_delay, | |
212 |
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212 | sample_in => sample_filter_in, | |
213 |
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213 | sample_out_val => sample_filter_v2_out_val, | |
214 |
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214 | sample_out => sample_filter_v2_out); | |
215 |
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215 | |||
216 | sample_filter_v2_out_val <= sample_val_delay; |
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216 | --sample_filter_v2_out_val <= sample_val_delay; | |
217 |
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217 | |||
218 | ChanelLoopOut : FOR i IN 0 TO 5 GENERATE |
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218 | ChanelLoopOut : FOR i IN 0 TO 5 GENERATE | |
219 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE |
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219 | SampleLoopOut : FOR j IN 0 TO 15 GENERATE | |
220 |
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220 | sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j); | |
221 | sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); |
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221 | --sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j); | |
222 | END GENERATE; |
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222 | END GENERATE; | |
223 | END GENERATE; |
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223 | END GENERATE; | |
224 | ----------------------------------------------------------------------------- |
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224 | ----------------------------------------------------------------------------- |
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