@@ -0,0 +1,76 | |||
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | ||
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4 | ||
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5 | LIBRARY lpp; | |
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6 | USE lpp.lpp_memory.ALL; | |
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7 | USE lpp.iir_filter.ALL; | |
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8 | USE lpp.spectral_matrix_package.ALL; | |
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9 | USE lpp.lpp_dma_pkg.ALL; | |
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10 | USE lpp.lpp_Header.ALL; | |
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11 | USE lpp.lpp_matrix.ALL; | |
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12 | USE lpp.lpp_matrix.ALL; | |
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13 | USE lpp.lpp_lfr_pkg.ALL; | |
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14 | USE lpp.lpp_fft.ALL; | |
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15 | USE lpp.fft_components.ALL; | |
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16 | ||
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17 | ENTITY lpp_lfr_ms_FFT IS | |
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18 | PORT ( | |
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19 | clk : IN STD_LOGIC; | |
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20 | rstn : IN STD_LOGIC; | |
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21 | -- IN | |
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22 | sample_valid : IN STD_LOGIC; | |
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23 | fft_read : IN STD_LOGIC; | |
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24 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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25 | sample_load : OUT STD_LOGIC; | |
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26 | ||
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27 | --OUT | |
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28 | fft_pong : OUT STD_LOGIC; | |
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29 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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30 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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31 | fft_data_valid : OUT STD_LOGIC; | |
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32 | fft_ready : OUT STD_LOGIC | |
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33 | ||
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34 | ); | |
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35 | END; | |
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36 | ||
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37 | ARCHITECTURE Behavioral OF lpp_lfr_ms_FFT IS | |
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38 | ||
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39 | BEGIN | |
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40 | ||
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41 | ----------------------------------------------------------------------------- | |
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42 | -- FFT | |
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43 | ----------------------------------------------------------------------------- | |
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44 | CoreFFT_1 : CoreFFT | |
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45 | GENERIC MAP ( | |
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46 | LOGPTS => gLOGPTS, | |
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47 | LOGLOGPTS => gLOGLOGPTS, | |
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48 | WSIZE => gWSIZE, | |
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49 | TWIDTH => gTWIDTH, | |
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50 | DWIDTH => gDWIDTH, | |
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51 | TDWIDTH => gTDWIDTH, | |
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52 | RND_MODE => gRND_MODE, | |
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53 | SCALE_MODE => gSCALE_MODE, | |
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54 | PTS => gPTS, | |
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55 | HALFPTS => gHALFPTS, | |
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56 | inBuf_RWDLY => gInBuf_RWDLY) | |
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57 | PORT MAP ( | |
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58 | clk => clk, | |
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59 | ifiStart => '0', -- '1' | |
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60 | ifiNreset => rstn, | |
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61 | ||
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62 | ifiD_valid => sample_valid, -- IN | |
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63 | ifiRead_y => fft_read, | |
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64 | ifiD_im => (OTHERS => '0'), -- IN | |
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65 | ifiD_re => sample_data, -- IN | |
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66 | ifoLoad => sample_load, -- IN | |
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67 | ||
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68 | ifoPong => fft_pong, | |
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69 | ifoY_im => fft_data_im, | |
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70 | ifoY_re => fft_data_re, | |
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71 | ifoY_valid => fft_data_valid, | |
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72 | ifoY_rdy => fft_ready); | |
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73 | ||
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74 | ----------------------------------------------------------------------------- | |
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75 | ||
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76 | END Behavioral; |
@@ -426,7 +426,7 BEGIN -- beh | |||
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426 | 426 | pirq_ms => 6, |
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427 | 427 | pirq_wfp => 14, |
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428 | 428 | hindex => 2, |
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429 |
top_lfr_version => X"00010 |
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429 | top_lfr_version => X"00010C") -- aa.bb.cc version | |
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430 | 430 | PORT MAP ( |
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431 | 431 | clk => clk_25, |
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432 | 432 | rstn => reset, |
This diff has been collapsed as it changes many lines, (1532 lines changed) Show them Hide them | |||
@@ -1,762 +1,770 | |||
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1 | LIBRARY ieee; | |
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2 | USE ieee.std_logic_1164.ALL; | |
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3 | USE ieee.numeric_std.ALL; | |
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4 | ||
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5 | LIBRARY lpp; | |
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6 | USE lpp.lpp_ad_conv.ALL; | |
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7 | USE lpp.iir_filter.ALL; | |
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8 | USE lpp.FILTERcfg.ALL; | |
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9 | USE lpp.lpp_memory.ALL; | |
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10 | USE lpp.lpp_waveform_pkg.ALL; | |
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11 | USE lpp.lpp_dma_pkg.ALL; | |
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12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
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13 | USE lpp.lpp_lfr_pkg.ALL; | |
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14 | USE lpp.general_purpose.ALL; | |
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15 | ||
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16 | LIBRARY techmap; | |
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17 | USE techmap.gencomp.ALL; | |
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18 | ||
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19 | LIBRARY grlib; | |
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20 | USE grlib.amba.ALL; | |
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21 | USE grlib.stdlib.ALL; | |
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22 | USE grlib.devices.ALL; | |
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23 | USE GRLIB.DMA2AHB_Package.ALL; | |
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24 | ||
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25 | ENTITY lpp_lfr IS | |
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26 | GENERIC ( | |
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27 | Mem_use : INTEGER := use_RAM; | |
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28 | nb_data_by_buffer_size : INTEGER := 11; | |
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29 | nb_word_by_buffer_size : INTEGER := 11; | |
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30 | nb_snapshot_param_size : INTEGER := 11; | |
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31 | delta_vector_size : INTEGER := 20; | |
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32 | delta_vector_size_f0_2 : INTEGER := 7; | |
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33 | ||
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34 | pindex : INTEGER := 4; | |
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35 | paddr : INTEGER := 4; | |
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36 | pmask : INTEGER := 16#fff#; | |
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37 | pirq_ms : INTEGER := 0; | |
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38 | pirq_wfp : INTEGER := 1; | |
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39 | ||
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40 | hindex : INTEGER := 2; | |
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41 | ||
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42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
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43 | ||
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44 | ); | |
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45 | PORT ( | |
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46 | clk : IN STD_LOGIC; | |
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47 | rstn : IN STD_LOGIC; | |
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48 | -- SAMPLE | |
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49 | sample_B : IN Samples(2 DOWNTO 0); | |
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50 | sample_E : IN Samples(4 DOWNTO 0); | |
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51 | sample_val : IN STD_LOGIC; | |
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52 | -- APB | |
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53 | apbi : IN apb_slv_in_type; | |
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54 | apbo : OUT apb_slv_out_type; | |
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55 | -- AHB | |
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56 | ahbi : IN AHB_Mst_In_Type; | |
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57 | ahbo : OUT AHB_Mst_Out_Type; | |
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58 | -- TIME | |
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59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
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60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
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61 | -- | |
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62 | data_shaping_BW : OUT STD_LOGIC; | |
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63 | -- | |
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64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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65 | ||
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66 | --debug | |
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67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
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69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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70 | --debug_f1_data_valid : OUT STD_LOGIC; | |
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71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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72 | --debug_f2_data_valid : OUT STD_LOGIC; | |
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73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
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74 | --debug_f3_data_valid : OUT STD_LOGIC; | |
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75 | ||
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76 | ---- debug FIFO_IN | |
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77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
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79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
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81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
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83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
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85 | ||
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86 | ----debug FIFO OUT | |
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87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
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89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
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91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
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93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
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95 | ||
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96 | ----debug DMA IN | |
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97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
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99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
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101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
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103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
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105 | ); | |
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106 | END lpp_lfr; | |
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107 | ||
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108 | ARCHITECTURE beh OF lpp_lfr IS | |
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109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); | |
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110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
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111 | -- | |
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112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
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113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
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114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
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115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
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116 | -- | |
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117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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120 | -- | |
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121 | SIGNAL sample_f0_val : STD_LOGIC; | |
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122 | SIGNAL sample_f1_val : STD_LOGIC; | |
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123 | SIGNAL sample_f2_val : STD_LOGIC; | |
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124 | SIGNAL sample_f3_val : STD_LOGIC; | |
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125 | -- | |
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126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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130 | -- | |
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131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
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134 | ||
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135 | -- SM | |
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136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
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137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
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138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
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139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
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140 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
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141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
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142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
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144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
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145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
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146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
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147 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
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148 | SIGNAL status_error_bad_component_error : STD_LOGIC; | |
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149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
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150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
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151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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152 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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155 | ||
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156 | -- WFP | |
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157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
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164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
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166 | ||
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167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
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168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
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169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
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170 | SIGNAL enable_f0 : STD_LOGIC; | |
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171 | SIGNAL enable_f1 : STD_LOGIC; | |
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172 | SIGNAL enable_f2 : STD_LOGIC; | |
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173 | SIGNAL enable_f3 : STD_LOGIC; | |
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174 | SIGNAL burst_f0 : STD_LOGIC; | |
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175 | SIGNAL burst_f1 : STD_LOGIC; | |
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176 | SIGNAL burst_f2 : STD_LOGIC; | |
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177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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181 | ||
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182 | SIGNAL run : STD_LOGIC; | |
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183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
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184 | ||
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185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
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188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
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189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
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190 | --f1 | |
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191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
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194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
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195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
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196 | --f2 | |
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197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
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200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
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201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
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202 | --f3 | |
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203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
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206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
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207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
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208 | ||
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209 | ----------------------------------------------------------------------------- | |
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210 | -- | |
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211 | ----------------------------------------------------------------------------- | |
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212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
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214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
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215 | --f1 | |
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216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
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218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
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219 | --f2 | |
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220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
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222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
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223 | --f3 | |
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224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
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226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
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227 | ||
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228 | ----------------------------------------------------------------------------- | |
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229 | -- DMA RR | |
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230 | ----------------------------------------------------------------------------- | |
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231 | SIGNAL dma_sel_valid : STD_LOGIC; | |
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232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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236 | ||
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237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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239 | ||
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240 | ----------------------------------------------------------------------------- | |
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241 | -- DMA_REG | |
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242 | ----------------------------------------------------------------------------- | |
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243 | SIGNAL ongoing_reg : STD_LOGIC; | |
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244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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245 | SIGNAL dma_send_reg : STD_LOGIC; | |
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246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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249 | ||
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250 | ||
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251 | ----------------------------------------------------------------------------- | |
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252 | -- DMA | |
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253 | ----------------------------------------------------------------------------- | |
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254 | SIGNAL dma_send : STD_LOGIC; | |
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255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
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256 | SIGNAL dma_done : STD_LOGIC; | |
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257 | SIGNAL dma_ren : STD_LOGIC; | |
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258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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261 | ||
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262 | ----------------------------------------------------------------------------- | |
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263 | -- DEBUG | |
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264 | ----------------------------------------------------------------------------- | |
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265 | -- | |
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266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
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270 | ||
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
279 | ||
|
280 | ----------------------------------------------------------------------------- | |
|
281 | -- MS | |
|
282 | ----------------------------------------------------------------------------- | |
|
283 | ||
|
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
286 | SIGNAL data_ms_valid : STD_LOGIC; | |
|
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
|
288 | SIGNAL data_ms_ren : STD_LOGIC; | |
|
289 | SIGNAL data_ms_done : STD_LOGIC; | |
|
290 | ||
|
291 | SIGNAL run_ms : STD_LOGIC; | |
|
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
|
293 | ||
|
294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
295 | SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
298 | ||
|
299 | ||
|
300 | BEGIN | |
|
301 | ||
|
302 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
|
303 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
|
304 | ||
|
305 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
|
306 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
|
307 | --END GENERATE all_channel; | |
|
308 | ||
|
309 | ----------------------------------------------------------------------------- | |
|
310 | lpp_lfr_filter_1 : lpp_lfr_filter | |
|
311 | GENERIC MAP ( | |
|
312 | Mem_use => Mem_use) | |
|
313 | PORT MAP ( | |
|
314 | sample => sample_s, | |
|
315 | sample_val => sample_val, | |
|
316 | clk => clk, | |
|
317 |
|
|
|
318 | data_shaping_SP0 => data_shaping_SP0, | |
|
319 | data_shaping_SP1 => data_shaping_SP1, | |
|
320 | data_shaping_R0 => data_shaping_R0, | |
|
321 |
data_shaping_ |
|
|
322 | sample_f0_val => sample_f0_val, | |
|
323 | sample_f1_val => sample_f1_val, | |
|
324 | sample_f2_val => sample_f2_val, | |
|
325 |
sample_f |
|
|
326 |
sample_f |
|
|
327 |
sample_f |
|
|
328 |
sample_f |
|
|
329 |
sample_f |
|
|
330 | ||
|
331 | ----------------------------------------------------------------------------- | |
|
332 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
|
333 | GENERIC MAP ( | |
|
334 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
|
335 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
|
336 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
337 |
|
|
|
338 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
|
339 | pindex => pindex, | |
|
340 | paddr => paddr, | |
|
341 | pmask => pmask, | |
|
342 |
pi |
|
|
343 |
p |
|
|
344 | top_lfr_version => top_lfr_version) | |
|
345 | PORT MAP ( | |
|
346 | HCLK => clk, | |
|
347 | HRESETn => rstn, | |
|
348 | apbi => apbi, | |
|
349 |
|
|
|
350 | ||
|
351 | run_ms => run_ms, | |
|
352 | ||
|
353 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
354 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
355 | ready_matrix_f1 => ready_matrix_f1, | |
|
356 |
ready_matrix_f |
|
|
357 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
358 | error_bad_component_error => error_bad_component_error, | |
|
359 |
|
|
|
360 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
361 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
362 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
363 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
364 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
365 | status_error_bad_component_error => status_error_bad_component_error, | |
|
366 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
367 | config_active_interruption_onError => config_active_interruption_onError, | |
|
368 | ||
|
369 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
370 | matrix_time_f0_1 => matrix_time_f0_1, | |
|
371 | matrix_time_f1 => matrix_time_f1, | |
|
372 | matrix_time_f2 => matrix_time_f2, | |
|
373 | ||
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
|
378 | status_full => status_full, | |
|
379 | status_full_ack => status_full_ack, | |
|
380 | status_full_err => status_full_err, | |
|
381 | status_new_err => status_new_err, | |
|
382 | data_shaping_BW => data_shaping_BW, | |
|
383 | data_shaping_SP0 => data_shaping_SP0, | |
|
384 | data_shaping_SP1 => data_shaping_SP1, | |
|
385 | data_shaping_R0 => data_shaping_R0, | |
|
386 | data_shaping_R1 => data_shaping_R1, | |
|
387 | delta_snapshot => delta_snapshot, | |
|
388 | delta_f0 => delta_f0, | |
|
389 | delta_f0_2 => delta_f0_2, | |
|
390 | delta_f1 => delta_f1, | |
|
391 | delta_f2 => delta_f2, | |
|
392 | nb_data_by_buffer => nb_data_by_buffer, | |
|
393 | nb_word_by_buffer => nb_word_by_buffer, | |
|
394 | nb_snapshot_param => nb_snapshot_param, | |
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
|
398 | enable_f3 => enable_f3, | |
|
399 | burst_f0 => burst_f0, | |
|
400 | burst_f1 => burst_f1, | |
|
401 |
|
|
|
402 |
|
|
|
403 | addr_data_f0 => addr_data_f0, | |
|
404 | addr_data_f1 => addr_data_f1, | |
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
|
408 | --------------------------------------------------------------------------- | |
|
409 | debug_reg0 => debug_reg0, | |
|
410 | debug_reg1 => debug_reg1, | |
|
411 | debug_reg2 => debug_reg2, | |
|
412 | debug_reg3 => debug_reg3, | |
|
413 | debug_reg4 => debug_reg4, | |
|
414 | debug_reg5 => debug_reg5, | |
|
415 |
debug_reg |
|
|
416 |
debug_reg |
|
|
417 | ||
|
418 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
|
419 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
|
420 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
|
421 | ----------------------------------------------------------------------------- | |
|
422 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
|
423 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
|
424 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
|
425 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
|
426 | ||
|
427 | ||
|
428 | ----------------------------------------------------------------------------- | |
|
429 | lpp_waveform_1 : lpp_waveform | |
|
430 | GENERIC MAP ( | |
|
431 | tech => inferred, | |
|
432 | data_size => 6*16, | |
|
433 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
|
434 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
|
435 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
436 | delta_vector_size => delta_vector_size, | |
|
437 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
|
438 | ) | |
|
439 | PORT MAP ( | |
|
440 | clk => clk, | |
|
441 | rstn => rstn, | |
|
442 | ||
|
443 | reg_run => run, | |
|
444 | reg_start_date => start_date, | |
|
445 | reg_delta_snapshot => delta_snapshot, | |
|
446 | reg_delta_f0 => delta_f0, | |
|
447 | reg_delta_f0_2 => delta_f0_2, | |
|
448 | reg_delta_f1 => delta_f1, | |
|
449 |
reg_ |
|
|
450 | ||
|
451 | enable_f0 => enable_f0, | |
|
452 | enable_f1 => enable_f1, | |
|
453 |
|
|
|
454 | enable_f3 => enable_f3, | |
|
455 | burst_f0 => burst_f0, | |
|
456 | burst_f1 => burst_f1, | |
|
457 | burst_f2 => burst_f2, | |
|
458 | ||
|
459 | nb_data_by_buffer => nb_data_by_buffer, | |
|
460 | nb_word_by_buffer => nb_word_by_buffer, | |
|
461 | nb_snapshot_param => nb_snapshot_param, | |
|
462 | status_full => status_full, | |
|
463 | status_full_ack => status_full_ack, | |
|
464 | status_full_err => status_full_err, | |
|
465 | status_new_err => status_new_err, | |
|
466 | ||
|
467 | coarse_time => coarse_time, | |
|
468 | fine_time => fine_time, | |
|
469 | ||
|
470 | --f0 | |
|
471 | addr_data_f0 => addr_data_f0, | |
|
472 | data_f0_in_valid => sample_f0_val, | |
|
473 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
|
474 | --f1 | |
|
475 | addr_data_f1 => addr_data_f1, | |
|
476 | data_f1_in_valid => sample_f1_val, | |
|
477 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
|
478 | --f2 | |
|
479 | addr_data_f2 => addr_data_f2, | |
|
480 | data_f2_in_valid => sample_f2_val, | |
|
481 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
|
482 | --f3 | |
|
483 | addr_data_f3 => addr_data_f3, | |
|
484 | data_f3_in_valid => sample_f3_val, | |
|
485 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
|
486 | -- OUTPUT -- DMA interface | |
|
487 | --f0 | |
|
488 | data_f0_addr_out => data_f0_addr_out_s, | |
|
489 |
|
|
|
490 |
data_f |
|
|
491 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
|
492 | data_f0_data_out_ren => data_f0_data_out_ren, | |
|
493 |
--f |
|
|
494 |
data_f |
|
|
495 |
data_f |
|
|
496 |
data_f |
|
|
497 |
data_f |
|
|
498 |
data_f |
|
|
499 |
--f |
|
|
500 |
data_f |
|
|
501 |
data_f |
|
|
502 |
data_f |
|
|
503 |
data_f |
|
|
504 |
data_f |
|
|
505 |
--f |
|
|
506 |
data_f |
|
|
507 |
data_f |
|
|
508 |
data_f |
|
|
509 |
data_f |
|
|
510 |
data_f |
|
|
511 | ||
|
512 | ------------------------------------------------------------------------- | |
|
513 | observation_reg => OPEN | |
|
514 | ||
|
515 | ); | |
|
516 | ||
|
517 | ||
|
518 |
|
|
|
519 | -- TEMP | |
|
520 | ----------------------------------------------------------------------------- | |
|
521 | ||
|
522 | PROCESS (clk, rstn) | |
|
523 | BEGIN -- PROCESS | |
|
524 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
525 | data_f0_data_out_valid <= '0'; | |
|
526 | data_f0_data_out_valid_burst <= '0'; | |
|
527 | data_f1_data_out_valid <= '0'; | |
|
528 | data_f1_data_out_valid_burst <= '0'; | |
|
529 | data_f2_data_out_valid <= '0'; | |
|
530 | data_f2_data_out_valid_burst <= '0'; | |
|
531 |
data_f |
|
|
532 |
data_f |
|
|
533 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
534 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
|
535 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
|
536 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
|
537 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
|
538 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
|
539 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
|
540 |
data_f |
|
|
541 |
data_f |
|
|
542 | END IF; | |
|
543 | END PROCESS; | |
|
544 | ||
|
545 |
data_f |
|
|
546 |
data_f |
|
|
547 |
data_f |
|
|
548 | data_f3_addr_out <= data_f3_addr_out_s; | |
|
549 | ||
|
550 | ----------------------------------------------------------------------------- | |
|
551 | -- RoundRobin Selection For DMA | |
|
552 | ----------------------------------------------------------------------------- | |
|
553 | ||
|
554 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
|
555 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
|
556 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
|
557 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
|
558 | ||
|
559 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
|
560 | PORT MAP ( | |
|
561 | clk => clk, | |
|
562 | rstn => rstn, | |
|
563 | in_valid => dma_rr_valid, | |
|
564 | out_grant => dma_rr_grant_s); | |
|
565 | ||
|
566 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
|
567 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
|
568 | dma_rr_valid_ms(2) <= '0'; | |
|
569 | dma_rr_valid_ms(3) <= '0'; | |
|
570 | ||
|
571 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
|
572 | PORT MAP ( | |
|
573 | clk => clk, | |
|
574 | rstn => rstn, | |
|
575 | in_valid => dma_rr_valid_ms, | |
|
576 | out_grant => dma_rr_grant_ms); | |
|
577 | ||
|
578 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
|
579 | ||
|
580 | ||
|
581 | ----------------------------------------------------------------------------- | |
|
582 | -- in : dma_rr_grant | |
|
583 | -- send | |
|
584 | -- out : dma_sel | |
|
585 | -- dma_valid_burst | |
|
586 | -- dma_sel_valid | |
|
587 | ----------------------------------------------------------------------------- | |
|
588 | PROCESS (clk, rstn) | |
|
589 | BEGIN -- PROCESS | |
|
590 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
591 | dma_sel <= (OTHERS => '0'); | |
|
592 | dma_send <= '0'; | |
|
593 | dma_valid_burst <= '0'; | |
|
594 | data_ms_done <= '0'; | |
|
595 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
596 | IF run = '1' THEN | |
|
597 | data_ms_done <= '0'; | |
|
598 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
|
599 | dma_sel <= dma_rr_grant; | |
|
600 | IF dma_rr_grant(0) = '1' THEN | |
|
601 | dma_send <= '1'; | |
|
602 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
|
603 | dma_sel_valid <= data_f0_data_out_valid; | |
|
604 |
|
|
|
605 |
|
|
|
606 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
|
607 |
dma_se |
|
|
608 | ELSIF dma_rr_grant(2) = '1' THEN | |
|
609 | dma_send <= '1'; | |
|
610 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
|
611 | dma_sel_valid <= data_f2_data_out_valid; | |
|
612 | ELSIF dma_rr_grant(3) = '1' THEN | |
|
613 |
dma_se |
|
|
614 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
|
615 | dma_sel_valid <= data_f3_data_out_valid; | |
|
616 | ELSIF dma_rr_grant(4) = '1' THEN | |
|
617 | dma_send <= '1'; | |
|
618 | dma_valid_burst <= data_ms_valid_burst; | |
|
619 |
dma_se |
|
|
620 | END IF; | |
|
621 | ||
|
622 |
IF dma_ |
|
|
623 |
d |
|
|
624 | END IF; | |
|
625 | ELSE | |
|
626 | dma_sel <= dma_sel; | |
|
627 | dma_send <= '0'; | |
|
628 | END IF; | |
|
629 | ELSE | |
|
630 | data_ms_done <= '0'; | |
|
631 | dma_sel <= (OTHERS => '0'); | |
|
632 |
dma_se |
|
|
633 |
|
|
|
634 | END IF; | |
|
635 | END IF; | |
|
636 | END PROCESS; | |
|
637 | ||
|
638 | ||
|
639 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
|
640 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
|
641 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
|
642 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
|
643 | data_ms_addr; | |
|
644 | ||
|
645 |
dma_ |
|
|
646 |
data_f1_ |
|
|
647 |
data_f2_ |
|
|
648 |
data_f3_ |
|
|
649 |
data_ms_ |
|
|
650 | ||
|
651 |
d |
|
|
652 |
data_f1_data_out |
|
|
653 |
data_f2_data_out |
|
|
654 |
data_f3_data_out |
|
|
655 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |
|
656 | ||
|
657 | dma_data_2 <= dma_data; | |
|
658 | ||
|
659 | ||
|
660 | ||
|
661 | ||
|
662 | ||
|
663 | ----------------------------------------------------------------------------- | |
|
664 | -- DEBUG -- DMA IN | |
|
665 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
|
666 | --debug_f0_data_dma_in <= dma_data; | |
|
667 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
|
668 | --debug_f1_data_dma_in <= dma_data; | |
|
669 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
|
670 | --debug_f2_data_dma_in <= dma_data; | |
|
671 |
--debug_f |
|
|
672 |
--debug_f |
|
|
673 | ----------------------------------------------------------------------------- | |
|
674 | ||
|
675 | ----------------------------------------------------------------------------- | |
|
676 | -- DMA | |
|
677 | ----------------------------------------------------------------------------- | |
|
678 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
|
679 | GENERIC MAP ( | |
|
680 | tech => inferred, | |
|
681 | hindex => hindex) | |
|
682 | PORT MAP ( | |
|
683 | HCLK => clk, | |
|
684 | HRESETn => rstn, | |
|
685 | run => run, | |
|
686 | AHB_Master_In => ahbi, | |
|
687 | AHB_Master_Out => ahbo, | |
|
688 | ||
|
689 |
|
|
|
690 | valid_burst => dma_valid_burst, | |
|
691 |
|
|
|
692 | ren => dma_ren, | |
|
693 | address => dma_address, | |
|
694 | data => dma_data_2); | |
|
695 | ||
|
696 | ----------------------------------------------------------------------------- | |
|
697 | -- Matrix Spectral | |
|
698 | ----------------------------------------------------------------------------- | |
|
699 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
|
700 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
|
701 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
|
702 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
|
703 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
|
704 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
|
705 | ||
|
706 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
|
707 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
|
708 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
|
709 | ||
|
710 | ------------------------------------------------------------------------------- | |
|
711 | ||
|
712 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
|
713 | ||
|
714 | ----------------------------------------------------------------------------- | |
|
715 | lpp_lfr_ms_1 : lpp_lfr_ms | |
|
716 | GENERIC MAP ( | |
|
717 | Mem_use => Mem_use) | |
|
718 | PORT MAP ( | |
|
719 | clk => clk, | |
|
720 | rstn => ms_softandhard_rstn, --rstn, | |
|
721 | ||
|
722 | coarse_time => coarse_time, | |
|
723 | fine_time => fine_time, | |
|
724 | ||
|
725 | sample_f0_wen => sample_f0_wen, | |
|
726 | sample_f0_wdata => sample_f0_wdata, | |
|
727 | sample_f1_wen => sample_f1_wen, | |
|
728 | sample_f1_wdata => sample_f1_wdata, | |
|
729 | sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data | |
|
730 | sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data | |
|
731 | ||
|
732 | dma_addr => data_ms_addr, -- | |
|
733 | dma_data => data_ms_data, -- | |
|
734 | dma_valid => data_ms_valid, -- | |
|
735 | dma_valid_burst => data_ms_valid_burst, -- | |
|
736 | dma_ren => data_ms_ren, -- | |
|
737 | dma_done => data_ms_done, -- | |
|
738 | ||
|
739 | ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename | |
|
740 | ready_matrix_f1 => ready_matrix_f1, | |
|
741 | ready_matrix_f2 => ready_matrix_f2, | |
|
742 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
743 | error_bad_component_error => error_bad_component_error, | |
|
744 | error_buffer_full => OPEN, -- TODO | |
|
745 | error_input_fifo_write => OPEN, -- TODO | |
|
746 |
|
|
|
747 |
|
|
|
748 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
749 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
750 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
|
751 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
|
752 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
753 | config_active_interruption_onError => config_active_interruption_onError, | |
|
754 | addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename | |
|
755 |
|
|
|
756 |
|
|
|
757 | ||
|
758 | matrix_time_f0 => matrix_time_f0_0,-- TODO rename | |
|
759 | matrix_time_f1 => matrix_time_f1, | |
|
760 | matrix_time_f2 => matrix_time_f2); | |
|
761 | ||
|
762 | END beh; | |
|
1 | LIBRARY ieee; | |
|
2 | USE ieee.std_logic_1164.ALL; | |
|
3 | USE ieee.numeric_std.ALL; | |
|
4 | ||
|
5 | LIBRARY lpp; | |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
|
7 | USE lpp.iir_filter.ALL; | |
|
8 | USE lpp.FILTERcfg.ALL; | |
|
9 | USE lpp.lpp_memory.ALL; | |
|
10 | USE lpp.lpp_waveform_pkg.ALL; | |
|
11 | USE lpp.lpp_dma_pkg.ALL; | |
|
12 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
13 | USE lpp.lpp_lfr_pkg.ALL; | |
|
14 | USE lpp.general_purpose.ALL; | |
|
15 | ||
|
16 | LIBRARY techmap; | |
|
17 | USE techmap.gencomp.ALL; | |
|
18 | ||
|
19 | LIBRARY grlib; | |
|
20 | USE grlib.amba.ALL; | |
|
21 | USE grlib.stdlib.ALL; | |
|
22 | USE grlib.devices.ALL; | |
|
23 | USE GRLIB.DMA2AHB_Package.ALL; | |
|
24 | ||
|
25 | ENTITY lpp_lfr IS | |
|
26 | GENERIC ( | |
|
27 | Mem_use : INTEGER := use_RAM; | |
|
28 | nb_data_by_buffer_size : INTEGER := 11; | |
|
29 | nb_word_by_buffer_size : INTEGER := 11; | |
|
30 | nb_snapshot_param_size : INTEGER := 11; | |
|
31 | delta_vector_size : INTEGER := 20; | |
|
32 | delta_vector_size_f0_2 : INTEGER := 7; | |
|
33 | ||
|
34 | pindex : INTEGER := 4; | |
|
35 | paddr : INTEGER := 4; | |
|
36 | pmask : INTEGER := 16#fff#; | |
|
37 | pirq_ms : INTEGER := 0; | |
|
38 | pirq_wfp : INTEGER := 1; | |
|
39 | ||
|
40 | hindex : INTEGER := 2; | |
|
41 | ||
|
42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') | |
|
43 | ||
|
44 | ); | |
|
45 | PORT ( | |
|
46 | clk : IN STD_LOGIC; | |
|
47 | rstn : IN STD_LOGIC; | |
|
48 | -- SAMPLE | |
|
49 | sample_B : IN Samples(2 DOWNTO 0); | |
|
50 | sample_E : IN Samples(4 DOWNTO 0); | |
|
51 | sample_val : IN STD_LOGIC; | |
|
52 | -- APB | |
|
53 | apbi : IN apb_slv_in_type; | |
|
54 | apbo : OUT apb_slv_out_type; | |
|
55 | -- AHB | |
|
56 | ahbi : IN AHB_Mst_In_Type; | |
|
57 | ahbo : OUT AHB_Mst_Out_Type; | |
|
58 | -- TIME | |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
|
61 | -- | |
|
62 | data_shaping_BW : OUT STD_LOGIC; | |
|
63 | -- | |
|
64 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
65 | ||
|
66 | --debug | |
|
67 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
|
68 | --debug_f0_data_valid : OUT STD_LOGIC; | |
|
69 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
|
70 | --debug_f1_data_valid : OUT STD_LOGIC; | |
|
71 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
|
72 | --debug_f2_data_valid : OUT STD_LOGIC; | |
|
73 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
|
74 | --debug_f3_data_valid : OUT STD_LOGIC; | |
|
75 | ||
|
76 | ---- debug FIFO_IN | |
|
77 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
78 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
|
79 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
80 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
|
81 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
82 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
|
83 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
84 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
|
85 | ||
|
86 | ----debug FIFO OUT | |
|
87 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
88 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
|
89 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
90 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
|
91 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
92 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
|
93 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
94 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
|
95 | ||
|
96 | ----debug DMA IN | |
|
97 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
98 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
|
99 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
100 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
|
101 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
102 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
|
103 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
104 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
|
105 | ); | |
|
106 | END lpp_lfr; | |
|
107 | ||
|
108 | ARCHITECTURE beh OF lpp_lfr IS | |
|
109 | --SIGNAL sample : Samples14v(7 DOWNTO 0); | |
|
110 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
|
111 | -- | |
|
112 | SIGNAL data_shaping_SP0 : STD_LOGIC; | |
|
113 | SIGNAL data_shaping_SP1 : STD_LOGIC; | |
|
114 | SIGNAL data_shaping_R0 : STD_LOGIC; | |
|
115 | SIGNAL data_shaping_R1 : STD_LOGIC; | |
|
116 | -- | |
|
117 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
118 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
119 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
120 | -- | |
|
121 | SIGNAL sample_f0_val : STD_LOGIC; | |
|
122 | SIGNAL sample_f1_val : STD_LOGIC; | |
|
123 | SIGNAL sample_f2_val : STD_LOGIC; | |
|
124 | SIGNAL sample_f3_val : STD_LOGIC; | |
|
125 | -- | |
|
126 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
127 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
128 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
129 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
130 | -- | |
|
131 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
132 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
133 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
|
134 | ||
|
135 | -- SM | |
|
136 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; | |
|
137 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; | |
|
138 | SIGNAL ready_matrix_f1 : STD_LOGIC; | |
|
139 | SIGNAL ready_matrix_f2 : STD_LOGIC; | |
|
140 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; | |
|
141 | SIGNAL error_bad_component_error : STD_LOGIC; | |
|
142 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
143 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; | |
|
144 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; | |
|
145 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; | |
|
146 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; | |
|
147 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
148 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; | |
|
149 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; | |
|
150 | SIGNAL config_active_interruption_onError : STD_LOGIC; | |
|
151 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
152 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
153 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
154 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
155 | ||
|
156 | -- WFP | |
|
157 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
158 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
159 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
160 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
161 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
162 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
163 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
|
164 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
165 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
|
166 | ||
|
167 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
|
168 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
|
169 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
|
170 | SIGNAL enable_f0 : STD_LOGIC; | |
|
171 | SIGNAL enable_f1 : STD_LOGIC; | |
|
172 | SIGNAL enable_f2 : STD_LOGIC; | |
|
173 | SIGNAL enable_f3 : STD_LOGIC; | |
|
174 | SIGNAL burst_f0 : STD_LOGIC; | |
|
175 | SIGNAL burst_f1 : STD_LOGIC; | |
|
176 | SIGNAL burst_f2 : STD_LOGIC; | |
|
177 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
178 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
179 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
180 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
181 | ||
|
182 | SIGNAL run : STD_LOGIC; | |
|
183 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
184 | ||
|
185 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
186 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
187 | SIGNAL data_f0_data_out_valid : STD_LOGIC; | |
|
188 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; | |
|
189 | SIGNAL data_f0_data_out_ren : STD_LOGIC; | |
|
190 | --f1 | |
|
191 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
192 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
193 | SIGNAL data_f1_data_out_valid : STD_LOGIC; | |
|
194 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; | |
|
195 | SIGNAL data_f1_data_out_ren : STD_LOGIC; | |
|
196 | --f2 | |
|
197 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
198 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
199 | SIGNAL data_f2_data_out_valid : STD_LOGIC; | |
|
200 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; | |
|
201 | SIGNAL data_f2_data_out_ren : STD_LOGIC; | |
|
202 | --f3 | |
|
203 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
204 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
205 | SIGNAL data_f3_data_out_valid : STD_LOGIC; | |
|
206 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; | |
|
207 | SIGNAL data_f3_data_out_ren : STD_LOGIC; | |
|
208 | ||
|
209 | ----------------------------------------------------------------------------- | |
|
210 | -- | |
|
211 | ----------------------------------------------------------------------------- | |
|
212 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
213 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; | |
|
214 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; | |
|
215 | --f1 | |
|
216 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
217 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; | |
|
218 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; | |
|
219 | --f2 | |
|
220 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
221 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; | |
|
222 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; | |
|
223 | --f3 | |
|
224 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
225 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; | |
|
226 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; | |
|
227 | ||
|
228 | ----------------------------------------------------------------------------- | |
|
229 | -- DMA RR | |
|
230 | ----------------------------------------------------------------------------- | |
|
231 | SIGNAL dma_sel_valid : STD_LOGIC; | |
|
232 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
233 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
234 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
235 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
236 | ||
|
237 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
238 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
239 | ||
|
240 | ----------------------------------------------------------------------------- | |
|
241 | -- DMA_REG | |
|
242 | ----------------------------------------------------------------------------- | |
|
243 | SIGNAL ongoing_reg : STD_LOGIC; | |
|
244 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
245 | SIGNAL dma_send_reg : STD_LOGIC; | |
|
246 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
|
247 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
248 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
249 | ||
|
250 | ||
|
251 | ----------------------------------------------------------------------------- | |
|
252 | -- DMA | |
|
253 | ----------------------------------------------------------------------------- | |
|
254 | SIGNAL dma_send : STD_LOGIC; | |
|
255 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) | |
|
256 | SIGNAL dma_done : STD_LOGIC; | |
|
257 | SIGNAL dma_ren : STD_LOGIC; | |
|
258 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
259 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
260 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
261 | ||
|
262 | ----------------------------------------------------------------------------- | |
|
263 | -- DEBUG | |
|
264 | ----------------------------------------------------------------------------- | |
|
265 | -- | |
|
266 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
267 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
268 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
269 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); | |
|
270 | ||
|
271 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
272 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
273 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
274 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
275 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
276 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
277 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
278 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
279 | ||
|
280 | ----------------------------------------------------------------------------- | |
|
281 | -- MS | |
|
282 | ----------------------------------------------------------------------------- | |
|
283 | ||
|
284 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
285 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
286 | SIGNAL data_ms_valid : STD_LOGIC; | |
|
287 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |
|
288 | SIGNAL data_ms_ren : STD_LOGIC; | |
|
289 | SIGNAL data_ms_done : STD_LOGIC; | |
|
290 | ||
|
291 | SIGNAL run_ms : STD_LOGIC; | |
|
292 | SIGNAL ms_softandhard_rstn : STD_LOGIC; | |
|
293 | ||
|
294 | SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
295 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
296 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
297 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
298 | ||
|
299 | ||
|
300 | SIGNAL error_buffer_full : STD_LOGIC; | |
|
301 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
302 | ||
|
303 | BEGIN | |
|
304 | ||
|
305 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
|
306 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
|
307 | ||
|
308 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE | |
|
309 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); | |
|
310 | --END GENERATE all_channel; | |
|
311 | ||
|
312 | ----------------------------------------------------------------------------- | |
|
313 | lpp_lfr_filter_1 : lpp_lfr_filter | |
|
314 | GENERIC MAP ( | |
|
315 | Mem_use => Mem_use) | |
|
316 | PORT MAP ( | |
|
317 | sample => sample_s, | |
|
318 | sample_val => sample_val, | |
|
319 | clk => clk, | |
|
320 | rstn => rstn, | |
|
321 | data_shaping_SP0 => data_shaping_SP0, | |
|
322 | data_shaping_SP1 => data_shaping_SP1, | |
|
323 | data_shaping_R0 => data_shaping_R0, | |
|
324 | data_shaping_R1 => data_shaping_R1, | |
|
325 | sample_f0_val => sample_f0_val, | |
|
326 | sample_f1_val => sample_f1_val, | |
|
327 | sample_f2_val => sample_f2_val, | |
|
328 | sample_f3_val => sample_f3_val, | |
|
329 | sample_f0_wdata => sample_f0_data, | |
|
330 | sample_f1_wdata => sample_f1_data, | |
|
331 | sample_f2_wdata => sample_f2_data, | |
|
332 | sample_f3_wdata => sample_f3_data); | |
|
333 | ||
|
334 | ----------------------------------------------------------------------------- | |
|
335 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg | |
|
336 | GENERIC MAP ( | |
|
337 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
|
338 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
|
339 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
340 | delta_vector_size => delta_vector_size, | |
|
341 | delta_vector_size_f0_2 => delta_vector_size_f0_2, | |
|
342 | pindex => pindex, | |
|
343 | paddr => paddr, | |
|
344 | pmask => pmask, | |
|
345 | pirq_ms => pirq_ms, | |
|
346 | pirq_wfp => pirq_wfp, | |
|
347 | top_lfr_version => top_lfr_version) | |
|
348 | PORT MAP ( | |
|
349 | HCLK => clk, | |
|
350 | HRESETn => rstn, | |
|
351 | apbi => apbi, | |
|
352 | apbo => apbo, | |
|
353 | ||
|
354 | run_ms => run_ms, | |
|
355 | ||
|
356 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
357 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |
|
358 | ready_matrix_f1 => ready_matrix_f1, | |
|
359 | ready_matrix_f2 => ready_matrix_f2, | |
|
360 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
361 | error_bad_component_error => error_bad_component_error, | |
|
362 | error_buffer_full => error_buffer_full, -- TODO | |
|
363 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
|
364 | debug_reg => debug_reg, | |
|
365 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
|
366 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
|
367 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
368 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
369 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
370 | -- status_error_bad_component_error => status_error_bad_component_error, | |
|
371 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
372 | config_active_interruption_onError => config_active_interruption_onError, | |
|
373 | ||
|
374 | matrix_time_f0_0 => matrix_time_f0_0, | |
|
375 | -- matrix_time_f0_1 => matrix_time_f0_1, | |
|
376 | matrix_time_f1 => matrix_time_f1, | |
|
377 | matrix_time_f2 => matrix_time_f2, | |
|
378 | ||
|
379 | addr_matrix_f0_0 => addr_matrix_f0_0, | |
|
380 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |
|
381 | addr_matrix_f1 => addr_matrix_f1, | |
|
382 | addr_matrix_f2 => addr_matrix_f2, | |
|
383 | ------------------------------------------------------------------------- | |
|
384 | status_full => status_full, | |
|
385 | status_full_ack => status_full_ack, | |
|
386 | status_full_err => status_full_err, | |
|
387 | status_new_err => status_new_err, | |
|
388 | data_shaping_BW => data_shaping_BW, | |
|
389 | data_shaping_SP0 => data_shaping_SP0, | |
|
390 | data_shaping_SP1 => data_shaping_SP1, | |
|
391 | data_shaping_R0 => data_shaping_R0, | |
|
392 | data_shaping_R1 => data_shaping_R1, | |
|
393 | delta_snapshot => delta_snapshot, | |
|
394 | delta_f0 => delta_f0, | |
|
395 | delta_f0_2 => delta_f0_2, | |
|
396 | delta_f1 => delta_f1, | |
|
397 | delta_f2 => delta_f2, | |
|
398 | nb_data_by_buffer => nb_data_by_buffer, | |
|
399 | nb_word_by_buffer => nb_word_by_buffer, | |
|
400 | nb_snapshot_param => nb_snapshot_param, | |
|
401 | enable_f0 => enable_f0, | |
|
402 | enable_f1 => enable_f1, | |
|
403 | enable_f2 => enable_f2, | |
|
404 | enable_f3 => enable_f3, | |
|
405 | burst_f0 => burst_f0, | |
|
406 | burst_f1 => burst_f1, | |
|
407 | burst_f2 => burst_f2, | |
|
408 | run => run, | |
|
409 | addr_data_f0 => addr_data_f0, | |
|
410 | addr_data_f1 => addr_data_f1, | |
|
411 | addr_data_f2 => addr_data_f2, | |
|
412 | addr_data_f3 => addr_data_f3, | |
|
413 | start_date => start_date, | |
|
414 | --------------------------------------------------------------------------- | |
|
415 | debug_reg0 => debug_reg0, | |
|
416 | debug_reg1 => debug_reg1, | |
|
417 | debug_reg2 => debug_reg2, | |
|
418 | debug_reg3 => debug_reg3, | |
|
419 | debug_reg4 => debug_reg4, | |
|
420 | debug_reg5 => debug_reg5, | |
|
421 | debug_reg6 => debug_reg6, | |
|
422 | debug_reg7 => debug_reg7); | |
|
423 | ||
|
424 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); | |
|
425 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); | |
|
426 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); | |
|
427 | ----------------------------------------------------------------------------- | |
|
428 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug | |
|
429 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug | |
|
430 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug | |
|
431 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug | |
|
432 | ||
|
433 | ||
|
434 | ----------------------------------------------------------------------------- | |
|
435 | lpp_waveform_1 : lpp_waveform | |
|
436 | GENERIC MAP ( | |
|
437 | tech => inferred, | |
|
438 | data_size => 6*16, | |
|
439 | nb_data_by_buffer_size => nb_data_by_buffer_size, | |
|
440 | nb_word_by_buffer_size => nb_word_by_buffer_size, | |
|
441 | nb_snapshot_param_size => nb_snapshot_param_size, | |
|
442 | delta_vector_size => delta_vector_size, | |
|
443 | delta_vector_size_f0_2 => delta_vector_size_f0_2 | |
|
444 | ) | |
|
445 | PORT MAP ( | |
|
446 | clk => clk, | |
|
447 | rstn => rstn, | |
|
448 | ||
|
449 | reg_run => run, | |
|
450 | reg_start_date => start_date, | |
|
451 | reg_delta_snapshot => delta_snapshot, | |
|
452 | reg_delta_f0 => delta_f0, | |
|
453 | reg_delta_f0_2 => delta_f0_2, | |
|
454 | reg_delta_f1 => delta_f1, | |
|
455 | reg_delta_f2 => delta_f2, | |
|
456 | ||
|
457 | enable_f0 => enable_f0, | |
|
458 | enable_f1 => enable_f1, | |
|
459 | enable_f2 => enable_f2, | |
|
460 | enable_f3 => enable_f3, | |
|
461 | burst_f0 => burst_f0, | |
|
462 | burst_f1 => burst_f1, | |
|
463 | burst_f2 => burst_f2, | |
|
464 | ||
|
465 | nb_data_by_buffer => nb_data_by_buffer, | |
|
466 | nb_word_by_buffer => nb_word_by_buffer, | |
|
467 | nb_snapshot_param => nb_snapshot_param, | |
|
468 | status_full => status_full, | |
|
469 | status_full_ack => status_full_ack, | |
|
470 | status_full_err => status_full_err, | |
|
471 | status_new_err => status_new_err, | |
|
472 | ||
|
473 | coarse_time => coarse_time, | |
|
474 | fine_time => fine_time, | |
|
475 | ||
|
476 | --f0 | |
|
477 | addr_data_f0 => addr_data_f0, | |
|
478 | data_f0_in_valid => sample_f0_val, | |
|
479 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug | |
|
480 | --f1 | |
|
481 | addr_data_f1 => addr_data_f1, | |
|
482 | data_f1_in_valid => sample_f1_val, | |
|
483 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, | |
|
484 | --f2 | |
|
485 | addr_data_f2 => addr_data_f2, | |
|
486 | data_f2_in_valid => sample_f2_val, | |
|
487 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, | |
|
488 | --f3 | |
|
489 | addr_data_f3 => addr_data_f3, | |
|
490 | data_f3_in_valid => sample_f3_val, | |
|
491 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, | |
|
492 | -- OUTPUT -- DMA interface | |
|
493 | --f0 | |
|
494 | data_f0_addr_out => data_f0_addr_out_s, | |
|
495 | data_f0_data_out => data_f0_data_out, | |
|
496 | data_f0_data_out_valid => data_f0_data_out_valid_s, | |
|
497 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, | |
|
498 | data_f0_data_out_ren => data_f0_data_out_ren, | |
|
499 | --f1 | |
|
500 | data_f1_addr_out => data_f1_addr_out_s, | |
|
501 | data_f1_data_out => data_f1_data_out, | |
|
502 | data_f1_data_out_valid => data_f1_data_out_valid_s, | |
|
503 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, | |
|
504 | data_f1_data_out_ren => data_f1_data_out_ren, | |
|
505 | --f2 | |
|
506 | data_f2_addr_out => data_f2_addr_out_s, | |
|
507 | data_f2_data_out => data_f2_data_out, | |
|
508 | data_f2_data_out_valid => data_f2_data_out_valid_s, | |
|
509 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, | |
|
510 | data_f2_data_out_ren => data_f2_data_out_ren, | |
|
511 | --f3 | |
|
512 | data_f3_addr_out => data_f3_addr_out_s, | |
|
513 | data_f3_data_out => data_f3_data_out, | |
|
514 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
|
515 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
|
516 | data_f3_data_out_ren => data_f3_data_out_ren , | |
|
517 | ||
|
518 | ------------------------------------------------------------------------- | |
|
519 | observation_reg => OPEN | |
|
520 | ||
|
521 | ); | |
|
522 | ||
|
523 | ||
|
524 | ----------------------------------------------------------------------------- | |
|
525 | -- TEMP | |
|
526 | ----------------------------------------------------------------------------- | |
|
527 | ||
|
528 | PROCESS (clk, rstn) | |
|
529 | BEGIN -- PROCESS | |
|
530 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
531 | data_f0_data_out_valid <= '0'; | |
|
532 | data_f0_data_out_valid_burst <= '0'; | |
|
533 | data_f1_data_out_valid <= '0'; | |
|
534 | data_f1_data_out_valid_burst <= '0'; | |
|
535 | data_f2_data_out_valid <= '0'; | |
|
536 | data_f2_data_out_valid_burst <= '0'; | |
|
537 | data_f3_data_out_valid <= '0'; | |
|
538 | data_f3_data_out_valid_burst <= '0'; | |
|
539 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
540 | data_f0_data_out_valid <= data_f0_data_out_valid_s; | |
|
541 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; | |
|
542 | data_f1_data_out_valid <= data_f1_data_out_valid_s; | |
|
543 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; | |
|
544 | data_f2_data_out_valid <= data_f2_data_out_valid_s; | |
|
545 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; | |
|
546 | data_f3_data_out_valid <= data_f3_data_out_valid_s; | |
|
547 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; | |
|
548 | END IF; | |
|
549 | END PROCESS; | |
|
550 | ||
|
551 | data_f0_addr_out <= data_f0_addr_out_s; | |
|
552 | data_f1_addr_out <= data_f1_addr_out_s; | |
|
553 | data_f2_addr_out <= data_f2_addr_out_s; | |
|
554 | data_f3_addr_out <= data_f3_addr_out_s; | |
|
555 | ||
|
556 | ----------------------------------------------------------------------------- | |
|
557 | -- RoundRobin Selection For DMA | |
|
558 | ----------------------------------------------------------------------------- | |
|
559 | ||
|
560 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; | |
|
561 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; | |
|
562 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; | |
|
563 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; | |
|
564 | ||
|
565 | RR_Arbiter_4_1 : RR_Arbiter_4 | |
|
566 | PORT MAP ( | |
|
567 | clk => clk, | |
|
568 | rstn => rstn, | |
|
569 | in_valid => dma_rr_valid, | |
|
570 | out_grant => dma_rr_grant_s); | |
|
571 | ||
|
572 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |
|
573 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |
|
574 | dma_rr_valid_ms(2) <= '0'; | |
|
575 | dma_rr_valid_ms(3) <= '0'; | |
|
576 | ||
|
577 | RR_Arbiter_4_2 : RR_Arbiter_4 | |
|
578 | PORT MAP ( | |
|
579 | clk => clk, | |
|
580 | rstn => rstn, | |
|
581 | in_valid => dma_rr_valid_ms, | |
|
582 | out_grant => dma_rr_grant_ms); | |
|
583 | ||
|
584 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |
|
585 | ||
|
586 | ||
|
587 | ----------------------------------------------------------------------------- | |
|
588 | -- in : dma_rr_grant | |
|
589 | -- send | |
|
590 | -- out : dma_sel | |
|
591 | -- dma_valid_burst | |
|
592 | -- dma_sel_valid | |
|
593 | ----------------------------------------------------------------------------- | |
|
594 | PROCESS (clk, rstn) | |
|
595 | BEGIN -- PROCESS | |
|
596 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
597 | dma_sel <= (OTHERS => '0'); | |
|
598 | dma_send <= '0'; | |
|
599 | dma_valid_burst <= '0'; | |
|
600 | data_ms_done <= '0'; | |
|
601 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
602 | IF run = '1' THEN | |
|
603 | data_ms_done <= '0'; | |
|
604 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
|
605 | dma_sel <= dma_rr_grant; | |
|
606 | IF dma_rr_grant(0) = '1' THEN | |
|
607 | dma_send <= '1'; | |
|
608 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
|
609 | dma_sel_valid <= data_f0_data_out_valid; | |
|
610 | ELSIF dma_rr_grant(1) = '1' THEN | |
|
611 | dma_send <= '1'; | |
|
612 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
|
613 | dma_sel_valid <= data_f1_data_out_valid; | |
|
614 | ELSIF dma_rr_grant(2) = '1' THEN | |
|
615 | dma_send <= '1'; | |
|
616 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
|
617 | dma_sel_valid <= data_f2_data_out_valid; | |
|
618 | ELSIF dma_rr_grant(3) = '1' THEN | |
|
619 | dma_send <= '1'; | |
|
620 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
|
621 | dma_sel_valid <= data_f3_data_out_valid; | |
|
622 | ELSIF dma_rr_grant(4) = '1' THEN | |
|
623 | dma_send <= '1'; | |
|
624 | dma_valid_burst <= data_ms_valid_burst; | |
|
625 | dma_sel_valid <= data_ms_valid; | |
|
626 | END IF; | |
|
627 | ||
|
628 | IF dma_sel(4) = '1' THEN | |
|
629 | data_ms_done <= '1'; | |
|
630 | END IF; | |
|
631 | ELSE | |
|
632 | dma_sel <= dma_sel; | |
|
633 | dma_send <= '0'; | |
|
634 | END IF; | |
|
635 | ELSE | |
|
636 | data_ms_done <= '0'; | |
|
637 | dma_sel <= (OTHERS => '0'); | |
|
638 | dma_send <= '0'; | |
|
639 | dma_valid_burst <= '0'; | |
|
640 | END IF; | |
|
641 | END IF; | |
|
642 | END PROCESS; | |
|
643 | ||
|
644 | ||
|
645 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
|
646 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
|
647 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
|
648 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
|
649 | data_ms_addr; | |
|
650 | ||
|
651 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
|
652 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
|
653 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
|
654 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
|
655 | data_ms_data; | |
|
656 | ||
|
657 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
|
658 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
|
659 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
|
660 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
|
661 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |
|
662 | ||
|
663 | dma_data_2 <= dma_data; | |
|
664 | ||
|
665 | ||
|
666 | ||
|
667 | ||
|
668 | ||
|
669 | ----------------------------------------------------------------------------- | |
|
670 | -- DEBUG -- DMA IN | |
|
671 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
|
672 | --debug_f0_data_dma_in <= dma_data; | |
|
673 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
|
674 | --debug_f1_data_dma_in <= dma_data; | |
|
675 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
|
676 | --debug_f2_data_dma_in <= dma_data; | |
|
677 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
|
678 | --debug_f3_data_dma_in <= dma_data; | |
|
679 | ----------------------------------------------------------------------------- | |
|
680 | ||
|
681 | ----------------------------------------------------------------------------- | |
|
682 | -- DMA | |
|
683 | ----------------------------------------------------------------------------- | |
|
684 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |
|
685 | GENERIC MAP ( | |
|
686 | tech => inferred, | |
|
687 | hindex => hindex) | |
|
688 | PORT MAP ( | |
|
689 | HCLK => clk, | |
|
690 | HRESETn => rstn, | |
|
691 | run => run, | |
|
692 | AHB_Master_In => ahbi, | |
|
693 | AHB_Master_Out => ahbo, | |
|
694 | ||
|
695 | send => dma_send, | |
|
696 | valid_burst => dma_valid_burst, | |
|
697 | done => dma_done, | |
|
698 | ren => dma_ren, | |
|
699 | address => dma_address, | |
|
700 | data => dma_data_2); | |
|
701 | ||
|
702 | ----------------------------------------------------------------------------- | |
|
703 | -- Matrix Spectral | |
|
704 | ----------------------------------------------------------------------------- | |
|
705 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
|
706 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
|
707 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
|
708 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
|
709 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
|
710 | NOT(sample_f3_val) & NOT(sample_f3_val); | |
|
711 | ||
|
712 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
|
713 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
|
714 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
|
715 | ||
|
716 | ------------------------------------------------------------------------------- | |
|
717 | ||
|
718 | ms_softandhard_rstn <= rstn AND run_ms AND run; | |
|
719 | ||
|
720 | ----------------------------------------------------------------------------- | |
|
721 | lpp_lfr_ms_1 : lpp_lfr_ms | |
|
722 | GENERIC MAP ( | |
|
723 | Mem_use => Mem_use) | |
|
724 | PORT MAP ( | |
|
725 | clk => clk, | |
|
726 | rstn => ms_softandhard_rstn, --rstn, | |
|
727 | ||
|
728 | coarse_time => coarse_time, | |
|
729 | fine_time => fine_time, | |
|
730 | ||
|
731 | sample_f0_wen => sample_f0_wen, | |
|
732 | sample_f0_wdata => sample_f0_wdata, | |
|
733 | sample_f1_wen => sample_f1_wen, | |
|
734 | sample_f1_wdata => sample_f1_wdata, | |
|
735 | sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data | |
|
736 | sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data | |
|
737 | ||
|
738 | dma_addr => data_ms_addr, -- | |
|
739 | dma_data => data_ms_data, -- | |
|
740 | dma_valid => data_ms_valid, -- | |
|
741 | dma_valid_burst => data_ms_valid_burst, -- | |
|
742 | dma_ren => data_ms_ren, -- | |
|
743 | dma_done => data_ms_done, -- | |
|
744 | ||
|
745 | ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename | |
|
746 | ready_matrix_f1 => ready_matrix_f1, | |
|
747 | ready_matrix_f2 => ready_matrix_f2, | |
|
748 | --error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
749 | error_bad_component_error => error_bad_component_error, | |
|
750 | error_buffer_full => error_buffer_full, -- TODO | |
|
751 | error_input_fifo_write => error_input_fifo_write, -- TODO | |
|
752 | ||
|
753 | debug_reg => observation_reg, | |
|
754 | ||
|
755 | status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename | |
|
756 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
757 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
758 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO | |
|
759 | -- status_error_bad_component_error => status_error_bad_component_error,-- TODO | |
|
760 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
|
761 | config_active_interruption_onError => config_active_interruption_onError, | |
|
762 | addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename | |
|
763 | addr_matrix_f1 => addr_matrix_f1, | |
|
764 | addr_matrix_f2 => addr_matrix_f2, | |
|
765 | ||
|
766 | matrix_time_f0 => matrix_time_f0_0,-- TODO rename | |
|
767 | matrix_time_f1 => matrix_time_f1, | |
|
768 | matrix_time_f2 => matrix_time_f2); | |
|
769 | ||
|
770 | END beh; No newline at end of file |
@@ -62,31 +62,30 ENTITY lpp_lfr_apbreg IS | |||
|
62 | 62 | run_ms : OUT STD_LOGIC; |
|
63 | 63 | -- IN |
|
64 | 64 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
65 | ready_matrix_f0_1 : IN STD_LOGIC; | |
|
66 | 65 | ready_matrix_f1 : IN STD_LOGIC; |
|
67 | 66 | ready_matrix_f2 : IN STD_LOGIC; |
|
68 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
67 | ||
|
69 | 68 | error_bad_component_error : IN STD_LOGIC; |
|
69 | error_buffer_full : in STD_LOGIC; -- TODO | |
|
70 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
|
71 | ||
|
70 | 72 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | 73 | |
|
72 | 74 | -- OUT |
|
73 | 75 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
74 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
75 | 76 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
76 | 77 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
77 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
78 | status_error_bad_component_error : OUT STD_LOGIC; | |
|
79 | 78 | |
|
80 | 79 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
81 | 80 | config_active_interruption_onError : OUT STD_LOGIC; |
|
82 | 81 | |
|
83 | 82 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
85 | 84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | 85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | 86 | |
|
88 | 87 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
88 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
90 | 89 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
91 | 90 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
92 | 91 | |
@@ -158,18 +157,20 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
158 | 157 | config_active_interruption_onError : STD_LOGIC; |
|
159 | 158 | config_ms_run : STD_LOGIC; |
|
160 | 159 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
161 | status_ready_matrix_f0_1 : STD_LOGIC; | |
|
160 | -- status_ready_matrix_f0_1 : STD_LOGIC; | |
|
162 | 161 | status_ready_matrix_f1 : STD_LOGIC; |
|
163 | 162 | status_ready_matrix_f2 : STD_LOGIC; |
|
164 | status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
163 | -- status_error_anticipating_empty_fifo : STD_LOGIC; | |
|
165 | 164 | status_error_bad_component_error : STD_LOGIC; |
|
165 | status_error_buffer_full : STD_LOGIC; -- TODO | |
|
166 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
|
166 | 167 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
168 | -- addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
168 | 169 | addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
169 | 170 | addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
170 | 171 | |
|
171 | 172 | coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
172 | coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
173 | -- coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
173 | 174 | coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | 175 | coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
175 | 176 | |
@@ -228,16 +229,16 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||
|
228 | 229 | BEGIN -- beh |
|
229 | 230 | |
|
230 | 231 | status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0; |
|
231 | status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
|
232 | -- status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1; | |
|
232 | 233 | status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
233 | 234 | status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
234 | status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
235 | status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
235 | -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo; | |
|
236 | -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error; | |
|
236 | 237 | |
|
237 | 238 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
238 | 239 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
239 | 240 | addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0; |
|
240 | addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
241 | -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1; | |
|
241 | 242 | addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
|
242 | 243 | addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
|
243 | 244 | |
@@ -283,18 +284,21 BEGIN -- beh | |||
|
283 | 284 | reg_sp.config_active_interruption_onError <= '0'; |
|
284 | 285 | reg_sp.config_ms_run <= '1'; |
|
285 | 286 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
286 | reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
287 | -- reg_sp.status_ready_matrix_f0_1 <= '0'; | |
|
287 | 288 | reg_sp.status_ready_matrix_f1 <= '0'; |
|
288 | 289 | reg_sp.status_ready_matrix_f2 <= '0'; |
|
289 | reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
|
290 | -- reg_sp.status_error_anticipating_empty_fifo <= '0'; | |
|
290 | 291 | reg_sp.status_error_bad_component_error <= '0'; |
|
292 | reg_sp.status_error_buffer_full <= '0'; | |
|
293 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); | |
|
294 | ||
|
291 | 295 |
|
|
292 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
296 | -- reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); | |
|
293 | 297 | reg_sp.addr_matrix_f1 <= (OTHERS => '0'); |
|
294 | 298 | reg_sp.addr_matrix_f2 <= (OTHERS => '0'); |
|
295 | 299 | |
|
296 | 300 | reg_sp.coarse_time_f0_0 <= (OTHERS => '0'); |
|
297 | reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
|
301 | -- reg_sp.coarse_time_f0_1 <= (OTHERS => '0'); | |
|
298 | 302 | reg_sp.coarse_time_f1 <= (OTHERS => '0'); |
|
299 | 303 | reg_sp.coarse_time_f2 <= (OTHERS => '0'); |
|
300 | 304 | --reg_sp.fine_time_f0_0 <= (OTHERS => '0'); |
@@ -340,7 +344,7 BEGIN -- beh | |||
|
340 | 344 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
341 | 345 | |
|
342 | 346 | reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0); |
|
343 | reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
347 | -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0); | |
|
344 | 348 | reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0); |
|
345 | 349 | reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0); |
|
346 | 350 | |
@@ -352,12 +356,20 BEGIN -- beh | |||
|
352 | 356 | status_full_ack <= (OTHERS => '0'); |
|
353 | 357 | |
|
354 | 358 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0; |
|
355 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
359 | -- reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1; | |
|
356 | 360 | reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1; |
|
357 | 361 | reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2; |
|
358 | 362 | |
|
359 | reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
363 | -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; | |
|
360 | 364 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
365 | ||
|
366 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; | |
|
367 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); | |
|
368 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); | |
|
369 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); | |
|
370 | ||
|
371 | ||
|
372 | ||
|
361 | 373 |
|
|
362 | 374 | --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run; |
|
363 | 375 | --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run; |
@@ -378,22 +390,26 BEGIN -- beh | |||
|
378 | 390 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
379 | 391 | prdata(2) <= reg_sp.config_ms_run; |
|
380 | 392 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
381 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
393 | -- prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
382 | 394 | prdata(2) <= reg_sp.status_ready_matrix_f1; |
|
383 | 395 | prdata(3) <= reg_sp.status_ready_matrix_f2; |
|
384 | prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
396 | -- prdata(4) <= reg_sp.status_error_anticipating_empty_fifo; | |
|
385 | 397 | prdata(5) <= reg_sp.status_error_bad_component_error; |
|
398 | prdata(6) <= reg_sp.status_error_buffer_full; | |
|
399 | prdata(7) <= reg_sp.status_error_input_fifo_write(0); | |
|
400 | prdata(8) <= reg_sp.status_error_input_fifo_write(1); | |
|
401 | prdata(9) <= reg_sp.status_error_input_fifo_write(2); | |
|
386 | 402 |
|
|
387 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
403 | -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; | |
|
388 | 404 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1; |
|
389 | 405 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f2; |
|
390 | 406 | |
|
391 | 407 | WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0; |
|
392 | WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
408 | -- WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1; | |
|
393 | 409 | WHEN "001000" => prdata <= reg_sp.coarse_time_f1; |
|
394 | 410 | WHEN "001001" => prdata <= reg_sp.coarse_time_f2; |
|
395 | 411 | WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0; |
|
396 | WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
412 | -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1; | |
|
397 | 413 | WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1; |
|
398 | 414 | WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2; |
|
399 | 415 | |
@@ -450,13 +466,17 BEGIN -- beh | |||
|
450 | 466 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
451 | 467 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
452 | 468 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); |
|
453 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
469 | -- reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
454 | 470 | reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2); |
|
455 | 471 | reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3); |
|
456 | reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
472 | -- reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4); | |
|
457 | 473 | reg_sp.status_error_bad_component_error <= apbi.pwdata(5); |
|
474 | reg_sp.status_error_buffer_full <= apbi.pwdata(6); | |
|
475 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(7); | |
|
476 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(8); | |
|
477 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(9); | |
|
458 | 478 |
|
|
459 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
479 | -- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
460 | 480 | WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata; |
|
461 | 481 | WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata; |
|
462 | 482 | -- |
@@ -500,13 +520,18 BEGIN -- beh | |||
|
500 | 520 | END IF; |
|
501 | 521 | |
|
502 | 522 | apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR |
|
503 | ready_matrix_f0_1 OR | |
|
523 | -- ready_matrix_f0_1 OR | |
|
504 | 524 | ready_matrix_f1 OR |
|
505 | 525 | ready_matrix_f2) |
|
506 | 526 | ) |
|
507 | 527 | OR |
|
508 |
(reg_sp.config_active_interruption_onError AND ( |
|
|
509 | error_bad_component_error) | |
|
528 | (reg_sp.config_active_interruption_onError AND ( | |
|
529 | --error_anticipating_empty_fifo OR | |
|
530 | error_bad_component_error | |
|
531 | OR error_buffer_full | |
|
532 | OR error_input_fifo_write(0) | |
|
533 | OR error_input_fifo_write(1) | |
|
534 | OR error_input_fifo_write(2)) | |
|
510 | 535 | )); |
|
511 | 536 | |
|
512 | 537 | apbo.pirq(pirq_wfp) <= ored_irq_wfp; |
@@ -541,4 +566,4 BEGIN -- beh | |||
|
541 | 566 | |
|
542 | 567 | run_ms <= reg_sp.config_ms_run; |
|
543 | 568 | |
|
544 | END beh; No newline at end of file | |
|
569 | END beh; |
This diff has been collapsed as it changes many lines, (616 lines changed) Show them Hide them | |||
@@ -49,37 +49,29 ENTITY lpp_lfr_ms IS | |||
|
49 | 49 | dma_done : IN STD_LOGIC; |
|
50 | 50 | |
|
51 | 51 | -- Reg out |
|
52 |
ready_matrix_f0 |
|
|
53 |
|
|
|
54 |
ready_matrix_f |
|
|
55 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
56 |
|
|
|
57 | error_bad_component_error : OUT STD_LOGIC; | |
|
58 | error_buffer_full : OUT STD_LOGIC; | |
|
59 |
|
|
|
60 | ||
|
61 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
52 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
53 | ready_matrix_f1 : OUT STD_LOGIC; | |
|
54 | ready_matrix_f2 : OUT STD_LOGIC; | |
|
55 | error_bad_component_error : OUT STD_LOGIC; | |
|
56 | error_buffer_full : OUT STD_LOGIC; | |
|
57 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
58 | ||
|
59 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
62 | 60 | |
|
63 | 61 | -- Reg In |
|
64 |
status_ready_matrix_f0 |
|
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65 |
|
|
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66 |
status_ready_matrix_f |
|
|
67 | status_ready_matrix_f2 : IN STD_LOGIC; | |
|
68 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
69 | -- status_error_bad_component_error : IN STD_LOGIC; | |
|
70 | -- status_error_buffer_full : IN STD_LOGIC; | |
|
62 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
63 | status_ready_matrix_f1 : IN STD_LOGIC; | |
|
64 | status_ready_matrix_f2 : IN STD_LOGIC; | |
|
71 | 65 | |
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72 | 66 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
73 | 67 | config_active_interruption_onError : IN STD_LOGIC; |
|
74 | -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
75 | 68 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
76 | 69 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | 70 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | 71 | |
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79 | 72 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
80 |
|
|
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81 |
matrix_time_f |
|
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82 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
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73 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
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74 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) | |
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83 | 75 | |
|
84 | 76 | ); |
|
85 | 77 | END; |
@@ -148,87 +140,67 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
148 | 140 | ----------------------------------------------------------------------------- |
|
149 | 141 | -- FFT |
|
150 | 142 | ----------------------------------------------------------------------------- |
|
151 | SIGNAL fft_read : STD_LOGIC; | |
|
152 | SIGNAL fft_pong : STD_LOGIC; | |
|
153 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
154 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
155 | SIGNAL fft_data_valid : STD_LOGIC; | |
|
156 | SIGNAL fft_ready : STD_LOGIC; | |
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143 | SIGNAL fft_read : STD_LOGIC; | |
|
144 | SIGNAL fft_pong : STD_LOGIC; | |
|
145 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
146 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
147 | SIGNAL fft_data_valid : STD_LOGIC; | |
|
148 | SIGNAL fft_ready : STD_LOGIC; | |
|
157 | 149 | ----------------------------------------------------------------------------- |
|
158 | 150 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
159 | 151 | ----------------------------------------------------------------------------- |
|
160 | 152 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
161 | 153 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
162 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
163 | SIGNAL current_fifo_empty : STD_LOGIC; | |
|
164 | SIGNAL current_fifo_locked : STD_LOGIC; | |
|
165 | SIGNAL current_fifo_full : STD_LOGIC; | |
|
166 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
167 | ||
|
154 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
155 | SIGNAL current_fifo_empty : STD_LOGIC; | |
|
156 | SIGNAL current_fifo_locked : STD_LOGIC; | |
|
157 | SIGNAL current_fifo_full : STD_LOGIC; | |
|
158 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
159 | ||
|
168 | 160 | ----------------------------------------------------------------------------- |
|
169 |
SIGNAL MEM_IN_SM_ReUse |
|
|
170 |
SIGNAL MEM_IN_SM_wen |
|
|
171 |
SIGNAL MEM_IN_SM_wen_s |
|
|
172 |
SIGNAL MEM_IN_SM_ren |
|
|
173 |
SIGNAL MEM_IN_SM_wData |
|
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174 |
SIGNAL MEM_IN_SM_rData |
|
|
175 |
SIGNAL MEM_IN_SM_Full |
|
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176 |
SIGNAL MEM_IN_SM_Empty |
|
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161 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
162 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
163 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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164 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
165 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
|
166 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
|
167 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
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168 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
|
177 | 169 | ----------------------------------------------------------------------------- |
|
178 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
179 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
180 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
170 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
|
171 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
172 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
181 | 173 | |
|
182 | SIGNAL SM_correlation_start : STD_LOGIC; | |
|
183 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
|
184 | SIGNAL SM_correlation_done : STD_LOGIC; | |
|
174 | SIGNAL SM_correlation_start : STD_LOGIC; | |
|
175 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
|
176 | SIGNAL SM_correlation_done : STD_LOGIC; | |
|
185 | 177 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
186 | 178 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
187 | 179 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; |
|
188 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
|
189 | ||
|
190 | -- SIGNAL temp_ongoing : STD_LOGIC; | |
|
191 | -- SIGNAL temp_auto : STD_LOGIC; | |
|
180 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
|
192 | 181 | |
|
193 |
SIGNAL MEM_OUT_SM_Full_s |
|
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194 |
SIGNAL MEM_OUT_SM_Data_in_s |
|
|
195 |
SIGNAL MEM_OUT_SM_Write_s |
|
|
182 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
|
183 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
184 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
|
196 | 185 | |
|
197 |
SIGNAL |
|
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198 |
SIGNAL |
|
|
199 | ||
|
200 | --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
201 | ||
|
186 | SIGNAL current_matrix_write : STD_LOGIC; | |
|
187 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
|
202 | 188 | ----------------------------------------------------------------------------- |
|
203 |
SIGNAL |
|
|
204 |
SIGNAL |
|
|
205 |
SIGNAL |
|
|
189 | SIGNAL fifo_0_ready : STD_LOGIC; | |
|
190 | SIGNAL fifo_1_ready : STD_LOGIC; | |
|
191 | SIGNAL fifo_ongoing : STD_LOGIC; | |
|
206 | 192 | |
|
207 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
|
208 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
|
209 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
193 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
|
194 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
|
195 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
210 | 196 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
211 | ||
|
212 | 197 | ----------------------------------------------------------------------------- |
|
213 | -- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
214 | --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
215 | --SIGNAL HEAD_SM_Wen : STD_LOGIC; | |
|
216 | --SIGNAL HEAD_Valid : STD_LOGIC; | |
|
217 | --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
218 | --SIGNAL HEAD_Empty : STD_LOGIC; | |
|
219 | --SIGNAL HEAD_Read : STD_LOGIC; | |
|
220 | ----------------------------------------------------------------------------- | |
|
221 | -- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
222 | 198 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
223 | 199 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
224 | 200 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
225 | 201 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
226 | 202 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
227 | 203 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
228 | ----------------------------------------------------------------------------- | |
|
229 | --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
230 | --SIGNAL DMA_Header_Val : STD_LOGIC; | |
|
231 | --SIGNAL DMA_Header_Ack : STD_LOGIC; | |
|
232 | 204 | |
|
233 | 205 | ----------------------------------------------------------------------------- |
|
234 | 206 | -- TIME REG & INFOs |
@@ -248,23 +220,19 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||
|
248 | 220 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
249 | 221 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
250 | 222 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
251 | ||
|
252 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
253 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
254 | -- SIGNAL status_component_fifo_0_new : STD_LOGIC; | |
|
255 | -- SIGNAL status_component_fifo_1_new : STD_LOGIC; | |
|
223 | ||
|
224 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
225 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
|
256 | 226 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
257 | 227 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
258 | ||
|
259 | SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
260 | 228 | ----------------------------------------------------------------------------- |
|
261 | 229 | |
|
262 | 230 | BEGIN |
|
263 | 231 | |
|
264 | 232 | |
|
265 |
error_input_fifo_write <= |
|
|
233 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
|
266 | 234 | |
|
267 | ||
|
235 | ||
|
268 | 236 | switch_f0_inst : spectral_matrix_switch_f0 |
|
269 | 237 | PORT MAP ( |
|
270 | 238 | clk => clk, |
@@ -287,67 +255,67 BEGIN | |||
|
287 | 255 | ----------------------------------------------------------------------------- |
|
288 | 256 | lppFIFOxN_f0_a : lppFIFOxN |
|
289 | 257 | GENERIC MAP ( |
|
290 |
tech |
|
|
291 |
Mem_use |
|
|
292 |
Data_sz |
|
|
293 |
Addr_sz |
|
|
294 |
FifoCnt |
|
|
258 | tech => 0, | |
|
259 | Mem_use => Mem_use, | |
|
260 | Data_sz => 16, | |
|
261 | Addr_sz => 8, | |
|
262 | FifoCnt => 5) | |
|
295 | 263 | PORT MAP ( |
|
296 |
clk |
|
|
297 |
rstn |
|
|
298 | ||
|
264 | clk => clk, | |
|
265 | rstn => rstn, | |
|
266 | ||
|
299 | 267 | ReUse => (OTHERS => '0'), |
|
300 | 268 | |
|
301 |
wen |
|
|
302 |
wdata |
|
|
303 | ||
|
304 |
ren |
|
|
305 |
rdata |
|
|
306 | ||
|
307 |
empty => sample_f0_A_empty, |
|
|
308 |
full => sample_f0_A_full, |
|
|
269 | wen => sample_f0_A_wen, | |
|
270 | wdata => sample_f0_wdata, | |
|
271 | ||
|
272 | ren => sample_f0_A_ren, | |
|
273 | rdata => sample_f0_A_rdata, | |
|
274 | ||
|
275 | empty => sample_f0_A_empty, | |
|
276 | full => sample_f0_A_full, | |
|
309 | 277 | almost_full => OPEN); |
|
310 | 278 | |
|
311 | 279 | lppFIFOxN_f0_b : lppFIFOxN |
|
312 | 280 | GENERIC MAP ( |
|
313 |
tech |
|
|
314 |
Mem_use |
|
|
315 |
Data_sz |
|
|
316 |
Addr_sz |
|
|
317 |
FifoCnt |
|
|
281 | tech => 0, | |
|
282 | Mem_use => Mem_use, | |
|
283 | Data_sz => 16, | |
|
284 | Addr_sz => 8, | |
|
285 | FifoCnt => 5) | |
|
318 | 286 | PORT MAP ( |
|
319 |
clk |
|
|
320 |
rstn |
|
|
321 | ||
|
287 | clk => clk, | |
|
288 | rstn => rstn, | |
|
289 | ||
|
322 | 290 | ReUse => (OTHERS => '0'), |
|
323 | 291 | |
|
324 |
wen => sample_f0_B_wen, |
|
|
325 |
wdata => sample_f0_wdata, |
|
|
326 |
ren => sample_f0_B_ren, |
|
|
327 |
rdata => sample_f0_B_rdata, |
|
|
328 |
empty => sample_f0_B_empty, |
|
|
329 |
full => sample_f0_B_full, |
|
|
292 | wen => sample_f0_B_wen, | |
|
293 | wdata => sample_f0_wdata, | |
|
294 | ren => sample_f0_B_ren, | |
|
295 | rdata => sample_f0_B_rdata, | |
|
296 | empty => sample_f0_B_empty, | |
|
297 | full => sample_f0_B_full, | |
|
330 | 298 | almost_full => OPEN); |
|
331 | 299 | |
|
332 | 300 | lppFIFOxN_f1 : lppFIFOxN |
|
333 | 301 | GENERIC MAP ( |
|
334 |
tech |
|
|
335 |
Mem_use |
|
|
336 |
Data_sz |
|
|
337 |
Addr_sz |
|
|
338 |
FifoCnt |
|
|
302 | tech => 0, | |
|
303 | Mem_use => Mem_use, | |
|
304 | Data_sz => 16, | |
|
305 | Addr_sz => 8, | |
|
306 | FifoCnt => 5) | |
|
339 | 307 | PORT MAP ( |
|
340 |
clk |
|
|
341 |
rstn |
|
|
342 | ||
|
308 | clk => clk, | |
|
309 | rstn => rstn, | |
|
310 | ||
|
343 | 311 | ReUse => (OTHERS => '0'), |
|
344 | 312 | |
|
345 |
wen => sample_f1_wen, |
|
|
346 |
wdata => sample_f1_wdata, |
|
|
347 |
ren => sample_f1_ren, |
|
|
348 |
rdata => sample_f1_rdata, |
|
|
349 |
empty => sample_f1_empty, |
|
|
350 |
full => sample_f1_full, |
|
|
313 | wen => sample_f1_wen, | |
|
314 | wdata => sample_f1_wdata, | |
|
315 | ren => sample_f1_ren, | |
|
316 | rdata => sample_f1_rdata, | |
|
317 | empty => sample_f1_empty, | |
|
318 | full => sample_f1_full, | |
|
351 | 319 | almost_full => sample_f1_almost_full); |
|
352 | 320 | |
|
353 | 321 | |
@@ -371,23 +339,23 BEGIN | |||
|
371 | 339 | |
|
372 | 340 | lppFIFOxN_f2 : lppFIFOxN |
|
373 | 341 | GENERIC MAP ( |
|
374 |
tech |
|
|
375 |
Mem_use |
|
|
376 |
Data_sz |
|
|
377 |
Addr_sz |
|
|
378 |
FifoCnt |
|
|
342 | tech => 0, | |
|
343 | Mem_use => Mem_use, | |
|
344 | Data_sz => 16, | |
|
345 | Addr_sz => 8, | |
|
346 | FifoCnt => 5) | |
|
379 | 347 | PORT MAP ( |
|
380 |
clk |
|
|
381 |
rstn |
|
|
382 | ||
|
348 | clk => clk, | |
|
349 | rstn => rstn, | |
|
350 | ||
|
383 | 351 | ReUse => (OTHERS => '0'), |
|
384 | 352 | |
|
385 |
wen => sample_f2_wen, |
|
|
386 |
wdata => sample_f2_wdata, |
|
|
387 |
ren => sample_f2_ren, |
|
|
388 |
rdata => sample_f2_rdata, |
|
|
389 |
empty => sample_f2_empty, |
|
|
390 |
full => sample_f2_full, |
|
|
353 | wen => sample_f2_wen, | |
|
354 | wdata => sample_f2_wdata, | |
|
355 | ren => sample_f2_ren, | |
|
356 | rdata => sample_f2_rdata, | |
|
357 | empty => sample_f2_empty, | |
|
358 | full => sample_f2_full, | |
|
391 | 359 | almost_full => OPEN); |
|
392 | 360 | |
|
393 | 361 | |
@@ -505,7 +473,7 BEGIN | |||
|
505 | 473 | IF rstn = '0' THEN |
|
506 | 474 | sample_ren_s <= (OTHERS => '1'); |
|
507 | 475 | state_fsm_load_FFT <= IDLE; |
|
508 | status_MS_input <= (OTHERS => '0'); | |
|
476 | status_MS_input <= (OTHERS => '0'); | |
|
509 | 477 | --next_state_fsm_load_FFT <= IDLE; |
|
510 | 478 | --sample_valid <= '0'; |
|
511 | 479 | ELSIF clk'EVENT AND clk = '1' THEN |
@@ -515,7 +483,7 BEGIN | |||
|
515 | 483 | sample_ren_s <= (OTHERS => '1'); |
|
516 | 484 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
517 | 485 | state_fsm_load_FFT <= FIFO_1; |
|
518 | status_MS_input <= status_channel; | |
|
486 | status_MS_input <= status_channel; | |
|
519 | 487 | END IF; |
|
520 | 488 | |
|
521 | 489 | WHEN FIFO_1 => |
@@ -583,7 +551,7 BEGIN | |||
|
583 | 551 | ----------------------------------------------------------------------------- |
|
584 | 552 | -- FFT |
|
585 | 553 | ----------------------------------------------------------------------------- |
|
586 | lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT | |
|
554 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT | |
|
587 | 555 | PORT MAP ( |
|
588 | 556 | clk => clk, |
|
589 | 557 | rstn => rstn, |
@@ -598,16 +566,12 BEGIN | |||
|
598 | 566 | fft_ready => fft_ready); |
|
599 | 567 | |
|
600 | 568 | ----------------------------------------------------------------------------- |
|
601 | -- in fft_data_im & fft_data_re | |
|
602 | -- in fft_data_valid | |
|
603 | -- in fft_ready | |
|
604 | -- out fft_read | |
|
605 | 569 | PROCESS (clk, rstn) |
|
606 | 570 | BEGIN |
|
607 | 571 | IF rstn = '0' THEN |
|
608 | 572 | state_fsm_load_MS_memory <= IDLE; |
|
609 | current_fifo_load <= "00001"; | |
|
610 |
ELSIF clk' |
|
|
573 | current_fifo_load <= "00001"; | |
|
574 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
611 | 575 | CASE state_fsm_load_MS_memory IS |
|
612 | 576 | WHEN IDLE => |
|
613 | 577 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
@@ -620,38 +584,38 BEGIN | |||
|
620 | 584 | WHEN TRASH_FFT => |
|
621 | 585 | IF fft_ready = '0' THEN |
|
622 | 586 | state_fsm_load_MS_memory <= IDLE; |
|
623 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
|
624 |
END IF; |
|
|
587 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
|
588 | END IF; | |
|
625 | 589 | WHEN OTHERS => NULL; |
|
626 | 590 | END CASE; |
|
627 | 591 | |
|
628 | 592 | END IF; |
|
629 | 593 | END PROCESS; |
|
630 | ||
|
594 | ||
|
631 | 595 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
632 | 596 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
633 | 597 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
634 | 598 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
635 | MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
|
636 | ||
|
637 |
current_fifo_full |
|
|
638 |
|
|
|
639 |
|
|
|
640 |
|
|
|
641 |
|
|
|
642 | ||
|
599 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
|
600 | ||
|
601 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
|
602 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
|
603 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
|
604 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
|
605 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
|
606 | ||
|
643 | 607 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
644 | 608 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
645 | 609 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
646 | 610 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
647 | MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE | |
|
648 | ||
|
611 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
|
612 | ||
|
649 | 613 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
650 | 614 | |
|
651 | all_fifo: FOR I IN 4 DOWNTO 0 GENERATE | |
|
652 |
|
|
|
653 |
|
|
|
654 |
|
|
|
615 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE | |
|
616 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
|
617 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
|
618 | AND current_fifo_load(I) = '1' | |
|
655 | 619 | ELSE '1'; |
|
656 | 620 | END GENERATE all_fifo; |
|
657 | 621 | |
@@ -659,101 +623,58 BEGIN | |||
|
659 | 623 | BEGIN |
|
660 | 624 | IF rstn = '0' THEN |
|
661 | 625 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
662 |
ELSIF clk' |
|
|
663 |
MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
|
626 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
627 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
|
664 | 628 | END IF; |
|
665 | 629 | END PROCESS; |
|
666 | ||
|
630 | ||
|
667 | 631 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
668 | 632 | (fft_data_im & fft_data_re) & |
|
669 | 633 | (fft_data_im & fft_data_re) & |
|
670 | 634 | (fft_data_im & fft_data_re) & |
|
671 | 635 | (fft_data_im & fft_data_re); |
|
672 | ||
|
673 | 636 | |
|
674 | -- out SM_MEM_IN_wData | |
|
675 | -- out SM_MEM_IN_wen | |
|
676 | -- out SM_MEM_IN_Full | |
|
677 | ||
|
678 | -- out SM_MEM_IN_locked | |
|
679 | ----------------------------------------------------------------------------- | |
|
680 | ----------------------------------------------------------------------------- | |
|
681 | ----------------------------------------------------------------------------- | |
|
682 | ----------------------------------------------------------------------------- | |
|
683 | --Linker_FFT_1 : Linker_FFT | |
|
684 | -- GENERIC MAP ( | |
|
685 | -- Data_sz => 16, | |
|
686 | -- NbData => 256) | |
|
687 | -- PORT MAP ( | |
|
688 | -- clk => clk, | |
|
689 | -- rstn => rstn, | |
|
690 | ||
|
691 | -- Ready => fft_ready, | |
|
692 | -- Valid => fft_data_valid, | |
|
693 | ||
|
694 | -- Full => MEM_IN_SM_Full, | |
|
695 | ||
|
696 | -- Data_re => fft_data_re, | |
|
697 | -- Data_im => fft_data_im, | |
|
698 | -- Read => fft_read, | |
|
699 | ||
|
700 | -- Write => MEM_IN_SM_wen, | |
|
701 | -- ReUse => fft_linker_ReUse, | |
|
702 | -- DATA => MEM_IN_SM_wData); | |
|
703 | ||
|
704 | 637 | ----------------------------------------------------------------------------- |
|
705 | 638 | Mem_In_SpectralMatrix : lppFIFOxN |
|
706 | 639 | GENERIC MAP ( |
|
707 |
tech |
|
|
708 |
Mem_use |
|
|
709 |
Data_sz |
|
|
710 |
Addr_sz |
|
|
711 |
FifoCnt |
|
|
640 | tech => 0, | |
|
641 | Mem_use => Mem_use, | |
|
642 | Data_sz => 32, --16, | |
|
643 | Addr_sz => 7, --8 | |
|
644 | FifoCnt => 5) | |
|
712 | 645 | PORT MAP ( |
|
713 | clk => clk, | |
|
646 | clk => clk, | |
|
714 | 647 | rstn => rstn, |
|
715 | 648 | |
|
716 | 649 | ReUse => MEM_IN_SM_ReUse, |
|
717 | ||
|
650 | ||
|
718 | 651 | wen => MEM_IN_SM_wen, |
|
719 | 652 | wdata => MEM_IN_SM_wData, |
|
720 | ||
|
721 | ren => MEM_IN_SM_ren, | |
|
722 | rdata => MEM_IN_SM_rData, | |
|
723 | full => MEM_IN_SM_Full, | |
|
724 |
empty => MEM_IN_SM_Empty, |
|
|
653 | ||
|
654 | ren => MEM_IN_SM_ren, | |
|
655 | rdata => MEM_IN_SM_rData, | |
|
656 | full => MEM_IN_SM_Full, | |
|
657 | empty => MEM_IN_SM_Empty, | |
|
725 | 658 | almost_full => OPEN); |
|
726 | 659 | |
|
727 | ||
|
728 | --all_lock: FOR I IN 4 DOWNTO 0 GENERATE | |
|
729 | -- PROCESS (clk, rstn) | |
|
730 | -- BEGIN | |
|
731 | -- IF rstn = '0' THEN | |
|
732 | -- MEM_IN_SM_locked(I) <= '0'; | |
|
733 | -- ELSIF clk'event AND clk = '1' THEN | |
|
734 | -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO | |
|
735 | -- END IF; | |
|
736 | -- END PROCESS; | |
|
737 | --END GENERATE all_lock; | |
|
738 | ||
|
739 | 660 | ----------------------------------------------------------------------------- |
|
740 | MS_control_1: MS_control | |
|
661 | MS_control_1 : MS_control | |
|
741 | 662 | PORT MAP ( |
|
742 |
clk |
|
|
743 |
rstn |
|
|
663 | clk => clk, | |
|
664 | rstn => rstn, | |
|
744 | 665 | |
|
745 | 666 | current_status_ms => status_MS_input, |
|
746 | ||
|
747 |
fifo_in_lock |
|
|
748 |
fifo_in_data |
|
|
749 |
fifo_in_full |
|
|
750 |
fifo_in_empty |
|
|
751 |
fifo_in_ren |
|
|
752 |
fifo_in_reuse |
|
|
753 | ||
|
754 |
fifo_out_data |
|
|
755 |
fifo_out_ren |
|
|
756 |
fifo_out_empty |
|
|
667 | ||
|
668 | fifo_in_lock => MEM_IN_SM_locked, | |
|
669 | fifo_in_data => MEM_IN_SM_rdata, | |
|
670 | fifo_in_full => MEM_IN_SM_Full, | |
|
671 | fifo_in_empty => MEM_IN_SM_Empty, | |
|
672 | fifo_in_ren => MEM_IN_SM_ren, | |
|
673 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
|
674 | ||
|
675 | fifo_out_data => SM_in_data, | |
|
676 | fifo_out_ren => SM_in_ren, | |
|
677 | fifo_out_empty => SM_in_empty, | |
|
757 | 678 | |
|
758 | 679 | current_status_component => status_component, |
|
759 | 680 | |
@@ -762,72 +683,62 BEGIN | |||
|
762 | 683 | correlation_done => SM_correlation_done); |
|
763 | 684 | |
|
764 | 685 | |
|
765 | MS_calculation_1: MS_calculation | |
|
686 | MS_calculation_1 : MS_calculation | |
|
766 | 687 | PORT MAP ( |
|
767 |
clk |
|
|
768 |
rstn |
|
|
769 | ||
|
770 |
fifo_in_data |
|
|
771 |
fifo_in_ren |
|
|
772 |
fifo_in_empty |
|
|
773 | ||
|
774 |
fifo_out_data |
|
|
775 |
fifo_out_wen |
|
|
776 |
fifo_out_full |
|
|
777 | ||
|
688 | clk => clk, | |
|
689 | rstn => rstn, | |
|
690 | ||
|
691 | fifo_in_data => SM_in_data, | |
|
692 | fifo_in_ren => SM_in_ren, | |
|
693 | fifo_in_empty => SM_in_empty, | |
|
694 | ||
|
695 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
|
696 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
|
697 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
|
698 | ||
|
778 | 699 | correlation_start => SM_correlation_start, |
|
779 | 700 | correlation_auto => SM_correlation_auto, |
|
780 | 701 | correlation_begin => SM_correlation_begin, |
|
781 | 702 | correlation_done => SM_correlation_done); |
|
782 | ||
|
703 | ||
|
783 | 704 | ----------------------------------------------------------------------------- |
|
784 | 705 | PROCESS (clk, rstn) |
|
785 | 706 | BEGIN -- PROCESS |
|
786 | 707 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
787 | current_matrix_write <= '0'; | |
|
788 | current_matrix_wait_empty <= '1'; | |
|
789 | status_component_fifo_0 <= (OTHERS => '0'); | |
|
790 | status_component_fifo_1 <= (OTHERS => '0'); | |
|
791 | -- status_component_fifo_0_new <= '0'; | |
|
792 | -- status_component_fifo_1_new <= '0'; | |
|
708 | current_matrix_write <= '0'; | |
|
709 | current_matrix_wait_empty <= '1'; | |
|
710 | status_component_fifo_0 <= (OTHERS => '0'); | |
|
711 | status_component_fifo_1 <= (OTHERS => '0'); | |
|
793 | 712 | status_component_fifo_0_end <= '0'; |
|
794 | 713 | status_component_fifo_1_end <= '0'; |
|
795 | SM_correlation_done_reg1 <= '0'; | |
|
796 | SM_correlation_done_reg2 <= '0'; | |
|
797 | SM_correlation_done_reg3 <= '0'; | |
|
714 | SM_correlation_done_reg1 <= '0'; | |
|
715 | SM_correlation_done_reg2 <= '0'; | |
|
716 | SM_correlation_done_reg3 <= '0'; | |
|
798 | 717 | |
|
799 |
ELSIF clk' |
|
|
800 | SM_correlation_done_reg1 <= SM_correlation_done; | |
|
801 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
|
802 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
|
803 | ||
|
804 | -- status_component_fifo_0_new <= '0'; | |
|
805 | -- status_component_fifo_1_new <= '0'; | |
|
718 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
|
719 | SM_correlation_done_reg1 <= SM_correlation_done; | |
|
720 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
|
721 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
|
806 | 722 | status_component_fifo_0_end <= '0'; |
|
807 | 723 | status_component_fifo_1_end <= '0'; |
|
808 | ||
|
809 | ||
|
810 | ||
|
811 | 724 | IF SM_correlation_begin = '1' THEN |
|
812 | 725 | IF current_matrix_write = '0' THEN |
|
813 |
|
|
|
814 | status_component_fifo_0 <= status_component; | |
|
726 | status_component_fifo_0 <= status_component; | |
|
815 | 727 | ELSE |
|
816 |
|
|
|
817 | status_component_fifo_1 <= status_component; | |
|
728 | status_component_fifo_1 <= status_component; | |
|
818 | 729 | END IF; |
|
819 | 730 | END IF; |
|
820 | ||
|
731 | ||
|
821 | 732 | IF SM_correlation_done_reg3 = '1' THEN |
|
822 | 733 | IF current_matrix_write = '0' THEN |
|
823 |
status_component_fifo_0_end |
|
|
734 | status_component_fifo_0_end <= '1'; | |
|
824 | 735 | ELSE |
|
825 |
status_component_fifo_1_end |
|
|
736 | status_component_fifo_1_end <= '1'; | |
|
826 | 737 | END IF; |
|
827 | 738 | current_matrix_wait_empty <= '1'; |
|
828 | 739 | current_matrix_write <= NOT current_matrix_write; |
|
829 | 740 | END IF; |
|
830 | ||
|
741 | ||
|
831 | 742 | IF current_matrix_wait_empty <= '1' THEN |
|
832 | 743 | IF current_matrix_write = '0' THEN |
|
833 | 744 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
@@ -839,69 +750,69 BEGIN | |||
|
839 | 750 | END IF; |
|
840 | 751 | END PROCESS; |
|
841 | 752 | |
|
842 |
MEM_OUT_SM_Full_s <= '1' |
|
|
843 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
|
844 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
|
845 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
|
753 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
|
754 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
|
755 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
|
756 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
|
846 | 757 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
847 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
|
758 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
|
848 | 759 | MEM_OUT_SM_Full(1); |
|
849 | 760 | |
|
850 | 761 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
851 | 762 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
852 | 763 | |
|
853 |
MEM_OUT_SM_Data_in |
|
|
764 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
|
854 | 765 | ----------------------------------------------------------------------------- |
|
855 | ||
|
766 | ||
|
856 | 767 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
857 | 768 | GENERIC MAP ( |
|
858 |
tech |
|
|
859 |
Mem_use |
|
|
860 |
Data_sz |
|
|
861 |
Addr_sz |
|
|
862 |
FifoCnt |
|
|
769 | tech => 0, | |
|
770 | Mem_use => Mem_use, | |
|
771 | Data_sz => 32, | |
|
772 | Addr_sz => 8, | |
|
773 | FifoCnt => 2) | |
|
863 | 774 | PORT MAP ( |
|
864 | clk => clk, | |
|
775 | clk => clk, | |
|
865 | 776 | rstn => rstn, |
|
866 | 777 | |
|
867 | 778 | ReUse => (OTHERS => '0'), |
|
868 | 779 | |
|
869 | 780 | wen => MEM_OUT_SM_Write, |
|
870 | 781 | wdata => MEM_OUT_SM_Data_in, |
|
871 | ||
|
782 | ||
|
872 | 783 | ren => MEM_OUT_SM_Read, |
|
873 | 784 | rdata => MEM_OUT_SM_Data_out, |
|
874 | 785 | |
|
875 | full => MEM_OUT_SM_Full, | |
|
876 | empty => MEM_OUT_SM_Empty, | |
|
786 | full => MEM_OUT_SM_Full, | |
|
787 | empty => MEM_OUT_SM_Empty, | |
|
877 | 788 | almost_full => OPEN); |
|
878 | ||
|
789 | ||
|
879 | 790 | ----------------------------------------------------------------------------- |
|
880 | 791 | -- MEM_OUT_SM_Read <= "00"; |
|
881 | 792 | PROCESS (clk, rstn) |
|
882 |
BEGIN |
|
|
883 |
IF rstn = '0' THEN |
|
|
793 | BEGIN | |
|
794 | IF rstn = '0' THEN | |
|
884 | 795 | fifo_0_ready <= '0'; |
|
885 | 796 | fifo_1_ready <= '0'; |
|
886 | 797 | fifo_ongoing <= '0'; |
|
887 |
ELSIF clk' |
|
|
798 | ELSIF clk'EVENT AND clk = '1' THEN | |
|
888 | 799 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
889 |
fifo_ongoing <= '1'; |
|
|
800 | fifo_ongoing <= '1'; | |
|
890 | 801 | fifo_0_ready <= '0'; |
|
891 | 802 | ELSIF status_component_fifo_0_end = '1' THEN |
|
892 |
fifo_0_ready <= '1'; |
|
|
803 | fifo_0_ready <= '1'; | |
|
893 | 804 | END IF; |
|
894 | ||
|
805 | ||
|
895 | 806 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
896 | 807 | fifo_ongoing <= '0'; |
|
897 | 808 | fifo_1_ready <= '0'; |
|
898 | 809 | ELSIF status_component_fifo_1_end = '1' THEN |
|
899 |
fifo_1_ready <= '1'; |
|
|
810 | fifo_1_ready <= '1'; | |
|
900 | 811 | END IF; |
|
901 | 812 | |
|
902 | 813 | END IF; |
|
903 | 814 | END PROCESS; |
|
904 | ||
|
815 | ||
|
905 | 816 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
906 | 817 | '1' WHEN fifo_0_ready = '0' ELSE |
|
907 | 818 | FSM_DMA_fifo_ren; |
@@ -910,15 +821,15 BEGIN | |||
|
910 | 821 | '1' WHEN fifo_1_ready = '0' ELSE |
|
911 | 822 | FSM_DMA_fifo_ren; |
|
912 | 823 | |
|
913 |
FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) |
|
|
914 |
MEM_OUT_SM_Empty(1) |
|
|
824 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
|
825 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
|
915 | 826 | '1'; |
|
916 | 827 | |
|
917 |
FSM_DMA_fifo_status <= |
|
|
918 |
|
|
|
828 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
|
829 | status_component_fifo_1; | |
|
919 | 830 | |
|
920 |
FSM_DMA_fifo_data |
|
|
921 |
|
|
|
831 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
|
832 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
|
922 | 833 | |
|
923 | 834 | ----------------------------------------------------------------------------- |
|
924 | 835 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
@@ -926,23 +837,12 BEGIN | |||
|
926 | 837 | HCLK => clk, |
|
927 | 838 | HRESETn => rstn, |
|
928 | 839 | |
|
929 |
fifo_matrix_type => FSM_DMA_fifo_status( |
|
|
930 |
fifo_matrix_component => FSM_DMA_fifo_status( |
|
|
840 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
|
841 | fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), | |
|
931 | 842 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
932 | 843 | fifo_data => FSM_DMA_fifo_data, |
|
933 | 844 | fifo_empty => FSM_DMA_fifo_empty, |
|
934 | 845 | fifo_ren => FSM_DMA_fifo_ren, |
|
935 | ||
|
936 | ---- FIFO IN | |
|
937 | --data_time => dma_time, | |
|
938 | ||
|
939 | --fifo_data => HEAD_Data, | |
|
940 | --fifo_empty => HEAD_Empty, | |
|
941 | --fifo_ren => HEAD_Read, | |
|
942 | ||
|
943 | --header => DMA_Header, | |
|
944 | --header_val => DMA_Header_Val, | |
|
945 | --header_ack => DMA_Header_Ack, | |
|
946 | 846 | |
|
947 | 847 | dma_addr => dma_addr, |
|
948 | 848 | dma_data => dma_data, |
@@ -951,32 +851,28 BEGIN | |||
|
951 | 851 | dma_ren => dma_ren, |
|
952 | 852 | dma_done => dma_done, |
|
953 | 853 | |
|
954 |
ready_matrix_f0 |
|
|
955 |
|
|
|
956 |
ready_matrix_f |
|
|
957 | ready_matrix_f2 => ready_matrix_f2, | |
|
958 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
|
959 | error_bad_component_error => error_bad_component_error, | |
|
960 | error_buffer_full => error_buffer_full, | |
|
961 |
debug_reg |
|
|
962 |
status_ready_matrix_f0 |
|
|
963 |
|
|
|
964 |
status_ready_matrix_f |
|
|
965 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
966 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
967 | -- status_error_bad_component_error => status_error_bad_component_error, | |
|
968 | -- status_error_buffer_full => status_error_buffer_full, | |
|
854 | ready_matrix_f0 => ready_matrix_f0, | |
|
855 | ready_matrix_f1 => ready_matrix_f1, | |
|
856 | ready_matrix_f2 => ready_matrix_f2, | |
|
857 | ||
|
858 | error_bad_component_error => error_bad_component_error, | |
|
859 | error_buffer_full => error_buffer_full, | |
|
860 | ||
|
861 | debug_reg => debug_reg, | |
|
862 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
|
863 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
|
864 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
|
865 | ||
|
969 | 866 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
970 | 867 | config_active_interruption_onError => config_active_interruption_onError, |
|
971 | addr_matrix_f0 => addr_matrix_f0, | |
|
972 |
|
|
|
973 |
addr_matrix_f1 |
|
|
974 |
addr_matrix_f2 |
|
|
868 | ||
|
869 | addr_matrix_f0 => addr_matrix_f0, | |
|
870 | addr_matrix_f1 => addr_matrix_f1, | |
|
871 | addr_matrix_f2 => addr_matrix_f2, | |
|
975 | 872 | |
|
976 | 873 | matrix_time_f0 => matrix_time_f0, |
|
977 |
|
|
|
978 |
matrix_time_f |
|
|
979 | matrix_time_f2 => matrix_time_f2 | |
|
874 | matrix_time_f1 => matrix_time_f1, | |
|
875 | matrix_time_f2 => matrix_time_f2 | |
|
980 | 876 | ); |
|
981 | 877 | ----------------------------------------------------------------------------- |
|
982 | 878 | |
@@ -984,24 +880,6 BEGIN | |||
|
984 | 880 | |
|
985 | 881 | |
|
986 | 882 | |
|
987 | ||
|
988 | ||
|
989 | ||
|
990 | ||
|
991 | ||
|
992 | ||
|
993 | ----------------------------------------------------------------------------- | |
|
994 | ----------------------------------------------------------------------------- | |
|
995 | ----------------------------------------------------------------------------- | |
|
996 | ----------------------------------------------------------------------------- | |
|
997 | ----------------------------------------------------------------------------- | |
|
998 | ----------------------------------------------------------------------------- | |
|
999 | ||
|
1000 | ||
|
1001 | ||
|
1002 | ||
|
1003 | ||
|
1004 | ||
|
1005 | 883 | ----------------------------------------------------------------------------- |
|
1006 | 884 | -- TIME MANAGMENT |
|
1007 | 885 | ----------------------------------------------------------------------------- |
@@ -1059,8 +937,6 BEGIN | |||
|
1059 | 937 | time_out => time_reg_f2); |
|
1060 | 938 | |
|
1061 | 939 | ----------------------------------------------------------------------------- |
|
1062 | dma_time <= (OTHERS => '0'); -- TODO | |
|
1063 | ----------------------------------------------------------------------------- | |
|
1064 | 940 | |
|
1065 | 941 | |
|
1066 | 942 |
@@ -65,32 +65,25 ENTITY lpp_lfr_ms_fsmdma IS | |||
|
65 | 65 | --------------------------------------------------------------------------- |
|
66 | 66 | -- Reg out |
|
67 | 67 | ready_matrix_f0 : OUT STD_LOGIC; |
|
68 | -- ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
69 | 68 | ready_matrix_f1 : OUT STD_LOGIC; |
|
70 | 69 | ready_matrix_f2 : OUT STD_LOGIC; |
|
71 | --error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
70 | ||
|
72 | 71 |
|
|
73 | 72 | error_buffer_full : OUT STD_LOGIC; |
|
74 | 73 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | 74 | |
|
76 | 75 | -- Reg In |
|
77 | 76 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
78 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; | |
|
79 | 77 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
80 | 78 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
81 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
82 | -- status_error_bad_component_error : IN STD_LOGIC; | |
|
83 | -- status_error_buffer_full : IN STD_LOGIC; | |
|
84 | 79 | |
|
85 | 80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
86 | 81 | config_active_interruption_onError : IN STD_LOGIC; |
|
87 | 82 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
89 | 83 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
90 | 84 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 85 | |
|
92 | 86 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
93 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
94 | 87 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
95 | 88 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
96 | 89 | |
@@ -114,27 +107,20 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs | |||
|
114 | 107 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
115 | 108 | SIGNAL header_check_ok : STD_LOGIC; |
|
116 | 109 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
117 | -- SIGNAL send_matrix : STD_LOGIC; | |
|
118 | 110 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | 111 | ----------------------------------------------------------------------------- |
|
120 | 112 | ----------------------------------------------------------------------------- |
|
121 | 113 | |
|
122 | 114 | SIGNAL component_send : STD_LOGIC; |
|
123 | 115 | SIGNAL component_send_ok : STD_LOGIC; |
|
124 | -- SIGNAL component_send_ko : STD_LOGIC; | |
|
125 | 116 | ----------------------------------------------------------------------------- |
|
126 | 117 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
127 | -- SIGNAL component_fifo_ren : STD_LOGIC; | |
|
128 | 118 | |
|
129 | 119 | ----------------------------------------------------------------------------- |
|
130 | 120 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
131 | 121 | ----------------------------------------------------------------------------- |
|
132 | 122 | SIGNAL log_empty_fifo : STD_LOGIC; |
|
133 | 123 | ----------------------------------------------------------------------------- |
|
134 | --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
135 | --SIGNAL header_reg_val : STD_LOGIC; | |
|
136 | --SIGNAL header_reg_ack : STD_LOGIC; | |
|
137 | -- SIGNAL header_error : STD_LOGIC; | |
|
138 | 124 | |
|
139 | 125 | SIGNAL matrix_buffer_ready : STD_LOGIC; |
|
140 | 126 | BEGIN |
@@ -143,7 +129,6 BEGIN | |||
|
143 | 129 | |
|
144 | 130 | |
|
145 | 131 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE |
|
146 | --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE | |
|
147 | 132 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE |
|
148 | 133 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE |
|
149 | 134 | '0'; |
@@ -154,12 +139,11 BEGIN | |||
|
154 | 139 | '0'; |
|
155 | 140 | |
|
156 | 141 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE |
|
157 | --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE | |
|
158 | 142 | addr_matrix_f1 WHEN matrix_type = "01" ELSE |
|
159 | 143 | addr_matrix_f2 WHEN matrix_type = "10" ELSE |
|
160 | 144 | (OTHERS => '0'); |
|
161 | 145 | |
|
162 |
debug_reg_s(31 DOWNTO |
|
|
146 | debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); | |
|
163 | 147 | ----------------------------------------------------------------------------- |
|
164 | 148 | -- DMA control |
|
165 | 149 | ----------------------------------------------------------------------------- |
@@ -170,10 +154,8 BEGIN | |||
|
170 | 154 | component_type <= (OTHERS => '0'); |
|
171 | 155 | state <= IDLE; |
|
172 | 156 | ready_matrix_f0 <= '0'; |
|
173 | -- ready_matrix_f0_1 <= '0'; | |
|
174 | 157 | ready_matrix_f1 <= '0'; |
|
175 | 158 | ready_matrix_f2 <= '0'; |
|
176 | -- error_anticipating_empty_fifo <= '0'; | |
|
177 | 159 | error_bad_component_error <= '0'; |
|
178 | 160 | error_buffer_full <= '0'; -- TODO |
|
179 | 161 | component_type_pre <= "0000"; |
@@ -182,6 +164,10 BEGIN | |||
|
182 | 164 | address <= (OTHERS => '0'); |
|
183 | 165 | |
|
184 | 166 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); |
|
167 | debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0'); | |
|
168 | debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0'); | |
|
169 | debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0'); | |
|
170 | debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0'); | |
|
185 | 171 | |
|
186 | 172 | log_empty_fifo <= '0'; |
|
187 | 173 | |
@@ -189,10 +175,22 BEGIN | |||
|
189 | 175 | matrix_time_f1 <= (OTHERS => '0'); |
|
190 | 176 | matrix_time_f2 <= (OTHERS => '0'); |
|
191 | 177 | |
|
192 |
ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
|
178 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
|
179 | -- | |
|
180 | debug_reg_s(3) <= status_ready_matrix_f0; | |
|
181 | debug_reg_s(4) <= status_ready_matrix_f0; | |
|
182 | debug_reg_s(5) <= status_ready_matrix_f0; | |
|
183 | debug_reg_s(6) <= '0'; | |
|
184 | debug_reg_s(7) <= '0'; | |
|
185 | debug_reg_s(8) <= '0'; | |
|
186 | debug_reg_s(10 DOWNTO 9) <= matrix_type; | |
|
187 | debug_reg_s(14 DOWNTO 11) <= component_type; | |
|
188 | ||
|
189 | -- | |
|
190 | ||
|
191 | ||
|
193 | 192 | |
|
194 | 193 | ready_matrix_f0 <= '0'; |
|
195 | -- ready_matrix_f0_1 <= '0'; | |
|
196 | 194 | ready_matrix_f1 <= '0'; |
|
197 | 195 | ready_matrix_f2 <= '0'; |
|
198 | 196 | error_bad_component_error <= '0'; |
@@ -237,7 +235,6 BEGIN | |||
|
237 | 235 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
238 | 236 | |
|
239 | 237 | error_bad_component_error <= '0'; |
|
240 | -- error_anticipating_empty_fifo <= '0'; | |
|
241 | 238 | IF fifo_empty = '1' THEN |
|
242 | 239 | state <= IDLE; |
|
243 | 240 | fifo_ren_trash <= '1'; |
@@ -246,15 +243,21 BEGIN | |||
|
246 | 243 | END IF; |
|
247 | 244 | |
|
248 | 245 | WHEN SEND_DATA => |
|
249 |
debug_reg_s(2 DOWNTO 0) <= " |
|
|
246 | debug_reg_s(2 DOWNTO 0) <= "010"; | |
|
250 | 247 | |
|
251 | 248 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
252 | 249 | state <= IDLE; |
|
253 | 250 | IF component_type = "1110" THEN |
|
254 | 251 | CASE matrix_type IS |
|
255 |
WHEN "00" => |
|
|
256 |
|
|
|
257 |
|
|
|
252 | WHEN "00" => | |
|
253 | ready_matrix_f0 <= '1'; | |
|
254 | debug_reg_s(6) <= '1'; | |
|
255 | WHEN "01" => | |
|
256 | ready_matrix_f1 <= '1'; | |
|
257 | debug_reg_s(7) <= '1'; | |
|
258 | WHEN "10" => | |
|
259 | ready_matrix_f2 <= '1'; | |
|
260 | debug_reg_s(8) <= '1'; | |
|
258 | 261 | WHEN OTHERS => NULL; |
|
259 | 262 | END CASE; |
|
260 | 263 | END IF; |
@@ -267,15 +270,12 BEGIN | |||
|
267 | 270 | WHEN WAIT_DATA_ACK => |
|
268 | 271 | log_empty_fifo <= fifo_empty OR log_empty_fifo; |
|
269 | 272 | |
|
270 |
debug_reg_s(2 DOWNTO 0) <= "11 |
|
|
273 | debug_reg_s(2 DOWNTO 0) <= "011"; | |
|
271 | 274 | |
|
272 | 275 | component_send <= '0'; |
|
273 | 276 | IF component_send_ok = '1' THEN |
|
274 | 277 | address <= address + 64; |
|
275 | 278 | state <= SEND_DATA; |
|
276 | -- ELSIF component_send_ko = '1' THEN | |
|
277 | -- error_anticipating_empty_fifo <= '0'; | |
|
278 | -- state <= TRASH_FIFO; | |
|
279 | 279 | END IF; |
|
280 | 280 | |
|
281 | 281 | WHEN OTHERS => NULL; |
@@ -291,6 +291,5 BEGIN | |||
|
291 | 291 | fifo_ren <= dma_ren AND fifo_ren_trash; |
|
292 | 292 | |
|
293 | 293 | component_send_ok <= dma_done; |
|
294 | -- component_send_ko <= '0'; | |
|
295 | 294 | |
|
296 | 295 | END Behavioral; |
@@ -277,8 +277,6 PACKAGE lpp_lfr_pkg IS | |||
|
277 | 277 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
278 | 278 | END COMPONENT; |
|
279 | 279 | ----------------------------------------------------------------------------- |
|
280 | ||
|
281 | ||
|
282 | 280 | COMPONENT lpp_lfr_apbreg |
|
283 | 281 | GENERIC ( |
|
284 | 282 | nb_data_by_buffer_size : INTEGER; |
@@ -299,30 +297,25 PACKAGE lpp_lfr_pkg IS | |||
|
299 | 297 | apbo : OUT apb_slv_out_type; |
|
300 | 298 | run_ms : OUT STD_LOGIC; |
|
301 | 299 | ready_matrix_f0_0 : IN STD_LOGIC; |
|
302 | ready_matrix_f0_1 : IN STD_LOGIC; | |
|
303 | 300 | ready_matrix_f1 : IN STD_LOGIC; |
|
304 | 301 | ready_matrix_f2 : IN STD_LOGIC; |
|
305 | error_anticipating_empty_fifo : IN STD_LOGIC; | |
|
306 | 302 | error_bad_component_error : IN STD_LOGIC; |
|
303 | error_buffer_full : in STD_LOGIC; | |
|
304 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); | |
|
307 | 305 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
308 | 306 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
|
309 | status_ready_matrix_f0_1 : OUT STD_LOGIC; | |
|
310 | 307 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
311 | 308 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
312 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; | |
|
313 | status_error_bad_component_error : OUT STD_LOGIC; | |
|
314 | 309 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
315 | 310 | config_active_interruption_onError : OUT STD_LOGIC; |
|
316 | 311 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
317 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
312 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
318 | 313 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
319 | 314 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
320 | ||
|
321 |
matrix_time_f0_ |
|
|
322 |
matrix_time_f |
|
|
323 |
matrix_time_f |
|
|
324 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
325 | ||
|
315 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
316 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
317 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
318 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
326 | 319 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
327 | 320 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
328 | 321 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
@@ -353,7 +346,6 PACKAGE lpp_lfr_pkg IS | |||
|
353 | 346 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
354 | 347 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
355 | 348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
356 | --------------------------------------------------------------------------- | |
|
357 | 349 | debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
358 | 350 | debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
359 | 351 | debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
@@ -363,6 +355,8 PACKAGE lpp_lfr_pkg IS | |||
|
363 | 355 | debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
364 | 356 | debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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365 | 357 | END COMPONENT; |
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358 | ||
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359 | ||
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366 | 360 |
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367 | 361 |
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368 | 362 | GENERIC ( |
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