HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r642:d1feb5a41a44

Improved testbench for LFR's F0 IIR Filter, now processed input is read from...

Jeandet Alexis -

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r642:d1feb5a41a44

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designs/Validation_IIR_f0_LFR/make_signals.ipynb created 644 +60 0

@@ -0,0 +1,60
	1	{
	2	"cells": [
	3	{
	4	"cell_type": "code",
	5	"execution_count": 8,
	6	"metadata": {
	7	"collapsed": true
	8	},
	9	"outputs": [],
	10	"source": [
	11	"import numpy as np\n",
	12	"import matplotlib.pyplot as plt\n",
	13	"import random"
	14	]
	15	},
	16	{
	17	"cell_type": "code",
	18	"execution_count": 32,
	19	"metadata": {
	20	"collapsed": false
	21	},
	22	"outputs": [],
	23	"source": [
	24	"W,H=8,1000\n",
	25	"test = np.ones((H,W))[(random.random()65535)-32768 for col in range(W)]\n",
	26	"np.savetxt(\"input.txt\", test,fmt=\"%d\", delimiter=\" \")"
	27	]
	28	},
	29	{
	30	"cell_type": "code",
	31	"execution_count": 28,
	32	"metadata": {
	33	"collapsed": false
	34	},
	35	"outputs": [],
	36	"source": []
	37	}
	38	],
	39	"metadata": {
	40	"kernelspec": {
	41	"display_name": "Python 3",
	42	"language": "python",
	43	"name": "python3"
	44	},
	45	"language_info": {
	46	"codemirror_mode": {
	47	"name": "ipython",
	48	"version": 3
	49	},
	50	"file_extension": ".py",
	51	"mimetype": "text/x-python",
	52	"name": "python",
	53	"nbconvert_exporter": "python",
	54	"pygments_lexer": "ipython3",
	55	"version": "3.5.2"
	56	}
	57	},
	58	"nbformat": 4,
	59	"nbformat_minor": 1
	60	}

designs/Validation_IIR_f0_LFR/sig_reader.vhd created 644 +53 0

@@ -0,0 +1,53
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3	USE ieee.numeric_std.ALL;
	4
	5	LIBRARY std;
	6	USE std.textio.ALL;
	7
	8	LIBRARY lpp;
	9	USE lpp.data_type_pkg.ALL;
	10
	11	ENTITY sig_reader IS
	12	GENERIC(
	13	FNAME : STRING := "input.txt";
	14	WIDTH : INTEGER := 1;
	15	RESOLUTION : INTEGER := 8;
	16	GAIN : REAL := 1.0
	17	);
	18	PORT(
	19	clk : IN std_logic;
	20	end_of_simu : out std_logic;
	21	out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
	22	);
	23	END sig_reader;
	24
	25	ARCHITECTURE beh OF sig_reader IS
	26	FILE input_file : TEXT OPEN read_mode IS FNAME;
	27	SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
	28	SIGNAL end_of_simu_reg : std_logic:='0';
	29	BEGIN
	30	out_signal <= out_signal_reg;
	31	end_of_simu <= end_of_simu_reg;
	32	PROCESS
	33	VARIABLE line_var : LINE;
	34	VARIABLE value : INTEGER;
	35	VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
	36	BEGIN
	37	WAIT UNTIL clk = '1';
	38	IF endfile(input_file) THEN
	39	end_of_simu_reg <= '1';
	40	ELSE
	41	end_of_simu_reg <= '0';
	42	readline(input_file,line_var);
	43	FOR COL IN 0 TO WIDTH-1 LOOP
	44	read(line_var, value);
	45	cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
	46	FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
	47	out_signal_reg(COL,bit_idx) <= cell(bit_idx);
	48	END LOOP;
	49	END LOOP;
	50	END IF;
	51	END PROCESS;
	52
	53	END beh;

designs/Validation_IIR_f0_LFR/Makefile +2 -2

             #GRLIB=../..
             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=testbench
             BOARD=LFR-EQM
             include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
             DEVICE=$(PART)-$(PACKAGE)$(SPEED)
             UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
             QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
             EFFORT=high
             XSTOPT=
             SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
             #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
-            VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
+            VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
-            VHDLSIMFILES= tb.vhd
+            VHDLSIMFILES= tb.vhd sig_reader.vhd
             SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
             PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
             SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
             BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean
             TECHLIBS = axcelerator
             LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
             	tmtc openchip hynix ihp gleichmann micron usbhc  opencores
             DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
             	pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
             	./dsp/lpp_fft_rtax \
             	./amba_lcd_16x2_ctrlr \
             	./general_purpose/lpp_AMR \
             	./general_purpose/lpp_balise \
             	./general_purpose/lpp_delay \
             	./lpp_bootloader \
             	./lfr_management \
             	./lpp_sim \
             	./lpp_sim/CY7C1061DV33 \
             	./lpp_cna \
             	./lpp_uart \
             	./lpp_usb \
             	./dsp/lpp_fft \
             	./lpp_leon3_soc \
             	./lpp_debug_lfr
             FILESKIP = i2cmst.vhd \
             	APB_MULTI_DIODE.vhd \
             	APB_MULTI_DIODE.vhd \
             	Top_MatrixSpec.vhd \
             	APB_FFT.vhd \
                     lpp_lfr_ms_FFT.vhd \
             	lpp_lfr_apbreg.vhd \
             	CoreFFT.vhd \
             	lpp_lfr_ms.vhd
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile
             ##################  project specific targets ##########################

designs/Validation_IIR_f0_LFR/generator.vhd +2 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             use ieee.numeric_std.all;
             USE IEEE.std_logic_signed.ALL;
             USE IEEE.MATH_real.ALL;
             ENTITY generator IS
               GENERIC (
                 AMPLITUDE            : INTEGER := 100;
-                NB_BITS              : INTEGER := 16);
+                NB_BITS              : INTEGER := 16
+                );
               PORT (
                 clk      : IN  STD_LOGIC;
                 rstn     : IN  STD_LOGIC;
                 run      : IN  STD_LOGIC;
                 data_ack : IN  STD_LOGIC;
                 offset   : IN  STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
                 data     : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
                 );
             END generator;
             ARCHITECTURE beh OF generator IS
               SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
             BEGIN  -- beh
               PROCESS (clk, rstn)
                 variable seed1, seed2: positive; -- seed values for random generator
                 variable rand: real; -- random real-number value in range 0 to 1.0
               BEGIN  -- PROCESS
                 uniform(seed1, seed2, rand);--more entropy by skipping values
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF run = '0' THEN
                     reg <= (OTHERS => '0');
                   ELSE
                     IF data_ack = '1' THEN
                         reg <= std_logic_vector(to_signed(INTEGER( (REAL(AMPLITUDE) * rand) + REAL(to_integer(SIGNED(offset))) ),NB_BITS));
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               data <= reg;
             END beh;

designs/Validation_IIR_f0_LFR/tb.vhd +45 -44

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             USE IEEE.std_logic_signed.ALL;
             USE IEEE.MATH_real.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY std;
             USE std.textio.ALL;
             LIBRARY lpp;
             USE lpp.iir_filter.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_lfr_filter_coeff.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY testbench IS
             GENERIC(
-                tech          : INTEGER := 0; --axcel,
+                tech          : INTEGER := 0; --axcel,0
-                Mem_use       : INTEGER := use_CEL --use_RAM
+                Mem_use       : INTEGER := use_CEL --use_RAM,use_CEL
             );
             END;
             ARCHITECTURE behav OF testbench IS
               CONSTANT ChanelCount   : INTEGER := 8;
               CONSTANT Coef_SZ       : INTEGER := 9;
               CONSTANT CoefCntPerCel : INTEGER := 6;
               CONSTANT CoefPerCel    : INTEGER := 5;
               CONSTANT Cels_count    : INTEGER := 5;
               SIGNAL sample     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_val : STD_LOGIC;
               SIGNAL sample_fx     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_fx_val : STD_LOGIC;
               SIGNAL TSTAMP    : INTEGER   := 0;
               SIGNAL clk       : STD_LOGIC := '0';
               SIGNAL clk_24k   : STD_LOGIC := '0';
               SIGNAL clk_24k_r : STD_LOGIC := '0';
               SIGNAL rstn      : STD_LOGIC;
-              SIGNAL signal_gen : Samples(7 DOWNTO 0);
+              SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,17 downto 0);
-              SIGNAL offset_gen : Samples(7 DOWNTO 0);
               --SIGNAL sample_fx_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_fx_wdata : Samples(ChanelCount-1 DOWNTO 0);
               COMPONENT generator IS
                 GENERIC (
                   AMPLITUDE : INTEGER := 100;
                   NB_BITS   : INTEGER := 16);
                 PORT (
                   clk  : IN STD_LOGIC;
                   rstn : IN STD_LOGIC;
                   run  : IN STD_LOGIC;
                   data_ack : IN  STD_LOGIC;
                   offset   : IN  STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
                   data     : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
                   );
               END COMPONENT;
+              COMPONENT sig_reader IS
+                GENERIC(
+                    FNAME       : STRING  := "input.txt";
+                    WIDTH       : INTEGER := 1;
+                    RESOLUTION  : INTEGER := 8;
+                    GAIN        : REAL    := 1.0
+                );
+                PORT(
+                    clk             : IN std_logic;
+                    end_of_simu     : out std_logic;
+                    out_signal      : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
+                );
+              END COMPONENT;
-              FILE log_input     : TEXT OPEN write_mode IS "log_input.txt";
+              FILE input     : TEXT OPEN read_mode IS "input.txt";
-              FILE log_output_fx : TEXT OPEN write_mode IS "log_output_fx.txt";
+              FILE output_fx : TEXT OPEN write_mode IS "output_fx.txt";
               SIGNAL end_of_simu : STD_LOGIC := '0';
             BEGIN
               -----------------------------------------------------------------------------
               -- CLOCK and RESET
               -----------------------------------------------------------------------------
-              clk <= NOT clk AFTER 5 ns;
+              clk <= NOT clk AFTER 20 ns;
               PROCESS
               BEGIN  -- PROCESS
-                end_of_simu <= '0';
                 WAIT UNTIL clk = '1';
                 rstn <= '0';
                 WAIT UNTIL clk = '1';
                 WAIT UNTIL clk = '1';
                 WAIT UNTIL clk = '1';
                 rstn <= '1';
-                WAIT FOR 2000 ms;
+                WAIT UNTIL end_of_simu = '1';
-                end_of_simu <= '1';
                 WAIT UNTIL clk = '1';
                 REPORT "*** END simulation ***" SEVERITY failure;
                 WAIT;
               END PROCESS;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- COMMON TIMESTAMPS
               -----------------------------------------------------------------------------
               PROCESS(clk)
               BEGIN
                 IF clk'EVENT AND clk = '1' THEN
                   TSTAMP <= TSTAMP+1;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- LPP_LFR_FILTER f0
               -----------------------------------------------------------------------------
               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => tech,
                   Mem_use      => use_RAM,
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
                   Coef_Nb      => 25,
                   Coef_sel_SZ  => 5,
                   Cels_count   => Cels_count,
                   ChanelsCount => ChanelCount,
-                  FILENAME     => "RAM.txt")
+                  FILENAME     => "")
                 PORT MAP (
                   rstn     => rstn,
                   clk      => clk,
                   virg_pos => 7,
                   coefs    => CoefsInitValCst_v2,
                   sample_in_val  => sample_val,
                   sample_in      => sample,
                   sample_out_val => sample_fx_val,
                   sample_out     => sample_fx);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SAMPLE GENERATION
               -----------------------------------------------------------------------------
               clk_24k <= NOT clk_24k AFTER 20345 ns;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_val <= '0';
                   clk_24k_r  <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   clk_24k_r <= clk_24k;
                   IF clk_24k = '1' AND clk_24k_r = '0' THEN
                     sample_val <= '1';
                   ELSE
                     sample_val <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
-              generators : FOR I IN 0 TO 7 GENERATE
-                gen1 : generator
-                  GENERIC MAP (
-                    AMPLITUDE => 100,
-                    NB_BITS   => 16)
-                  PORT MAP (
-                    clk      => clk,
-                    rstn     => rstn,
-                    run      => '1',
-                    data_ack => sample_val,
-                    offset   => offset_gen(I),
-                    data     => signal_gen(I)
-                    );
-                offset_gen(I) <= STD_LOGIC_VECTOR(to_signed((I*200), 16));
-              END GENERATE generators;
               ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
                 SampleLoop : FOR j IN 0 TO 15 GENERATE
-                  sample(i,j) <= signal_gen(i)(j);
                   sample_fx_wdata(i)(j) <= sample_fx(i,j);
+                  sample(i,j) <= signal_gen(i,j);
                 END GENERATE;
+                  sample(i,16) <= signal_gen(i,16);
-                sample(i, 16) <= signal_gen(i)(15);
+                  sample(i,17) <= signal_gen(i,17);
-                sample(i, 17) <= signal_gen(i)(15);
               END GENERATE;
               -----------------------------------------------------------------------------
-              --  RECORD SIGNALS
+              --  READ INPUT SIGNALS
               -----------------------------------------------------------------------------
-              -- PROCESS(sample_val)
+              gen: sig_reader
-              --   VARIABLE line_var : LINE;
+              GENERIC MAP(
-              -- BEGIN
+                    FNAME       => "input.txt",
-              --   IF sample_val'EVENT AND sample_val = '1' THEN
+                    WIDTH       => ChanelCount,
-              --     write(line_var, INTEGER'IMAGE(TSTAMP));
+                    RESOLUTION  => 18,
-              --     FOR I IN 0 TO 7 LOOP
+                    GAIN        => 1.0
-              --       write(line_var, "  " & INTEGER'IMAGE(to_integer(SIGNED(signal_gen(I)))));
-              --     END LOOP;
+                PORT MAP(
-              --     writeline(log_input, line_var);
+                    clk             => sample_val,
-              --   END IF;
+                    end_of_simu     => end_of_simu,
-              --  END PROCESS;
+                    out_signal      => signal_gen
+                );
+              -----------------------------------------------------------------------------
+              --  RECORD OUTPUT SIGNALS
+              -----------------------------------------------------------------------------
               PROCESS(sample_fx_val,end_of_simu)
                 VARIABLE line_var : LINE;
               BEGIN
                 IF sample_fx_val'EVENT AND sample_fx_val = '1' THEN
                   write(line_var, INTEGER'IMAGE(TSTAMP));
                   FOR I IN 0 TO 5 LOOP
                     write(line_var, "  " & INTEGER'IMAGE(to_integer(SIGNED(sample_fx_wdata(I)))));
                   END LOOP;
-                  writeline(log_output_fx, line_var);
+                  writeline(output_fx, line_var);
                 END IF;
                 IF end_of_simu = '1' THEN
-                  file_close(log_output_fx);
+                  file_close(output_fx);
                 END IF;
               END PROCESS;
             END;

lib/lpp/dsp/iir_filter/RAM_CEL.vhd +2 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.std_logic_textio.ALL;
             USE IEEE.numeric_std.ALL;
             LIBRARY std;
             USE std.textio.ALL;
             ENTITY RAM_CEL IS
               GENERIC(
                 DataSz : INTEGER RANGE 1 TO 32 := 8;
                 abits  : INTEGER RANGE 2 TO 12 := 8;
                 FILENAME : string:= ""
                 );
               PORT(
                 WD           : IN  STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
                 RD           : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
                 WEN, REN     : IN  STD_LOGIC;
                 WADDR        : IN  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
                 RADDR        : IN  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
                 RWCLK, RESET : IN  STD_LOGIC
                 ) ;
             END RAM_CEL;
             ARCHITECTURE ar_RAM_CEL OF RAM_CEL IS
               CONSTANT VectInit : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0) := (OTHERS => '0');
               CONSTANT MAX      : INTEGER                             := 2**(abits);
               TYPE RAMarrayT IS ARRAY (0 TO MAX-1) OF STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
               SIGNAL RD_int   : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
               SIGNAL RADDR_reg        :  STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
               -- Read a *.hex file
                 impure function ReadMemFile(FileName : STRING) return RAMarrayT is
                   file FileHandle       : TEXT open READ_MODE is FileName;
                   variable CurrentLine  : LINE;
                   variable TempWord     : STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
                   variable Result       : RAMarrayT    := (others => (others => '0'));
                 begin
                   for i in 0 to MAX - 1 loop
                     exit when endfile(FileHandle);
                     readline(FileHandle, CurrentLine);
                     hread(CurrentLine, TempWord);
                     Result(i)    := TempWord;
                   end loop;
                   return Result;
                 end function;
                 impure function InitMem(FileName : STRING) return RAMarrayT is
                     variable Result       : RAMarrayT    := (others => (others => '0'));
                 begin
                     if FileName'length /= 0 then
+                        report "initialysing RAM CEL From file "& FileName;
                         Result := ReadMemFile(FileName);
                     end if;
+                    report "initialysing RAM CEL To 0";
                     return Result;
                 end function;
                 SIGNAL RAMarray : RAMarrayT := InitMem(FILENAME);
             BEGIN
               RD_int <= RAMarray(to_integer(UNSIGNED(RADDR)));
               PROCESS(RWclk, reset)
               BEGIN
                 IF reset = '0' THEN
                   RD <= VectInit;
             --      rst : FOR i IN 0 TO MAX-1 LOOP
             --        RAMarray(i) <= (OTHERS => '0');
             --      END LOOP;
                 ELSIF RWclk'EVENT AND RWclk = '1' THEN
                   RD <= RD_int;
                   IF REN = '0' THEN
                     RADDR_reg <= RADDR;
                   END IF;
                   IF WEN = '0' THEN
                     RAMarray(to_integer(UNSIGNED(WADDR))) <= WD;
                   END IF;
                 END IF;
               END PROCESS;
             END ar_RAM_CEL;

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