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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 2 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- APB_CNA.vhd | |||
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20 | ||||
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21 | library ieee; | |||
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22 | use ieee.std_logic_1164.all; | |||
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23 | library grlib; | |||
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24 | use grlib.amba.all; | |||
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25 | use grlib.stdlib.all; | |||
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26 | use grlib.devices.all; | |||
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27 | library lpp; | |||
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28 | use lpp.lpp_CNA_amba.all; | |||
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29 | ||||
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30 | ||||
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31 | entity APB_CNA is | |||
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32 | generic ( | |||
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33 | pindex : integer := 0; | |||
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34 | paddr : integer := 0; | |||
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35 | pmask : integer := 16#fff#; | |||
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36 | pirq : integer := 0; | |||
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37 | abits : integer := 8); | |||
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38 | port ( | |||
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39 | clk : in std_logic; | |||
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40 | rst : in std_logic; | |||
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41 | apbi : in apb_slv_in_type; | |||
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42 | apbo : out apb_slv_out_type; | |||
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43 | SYNC : out std_logic; | |||
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44 | SCLK : out std_logic; | |||
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45 | DATA : out std_logic | |||
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46 | ); | |||
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47 | end APB_CNA; | |||
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48 | ||||
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49 | ||||
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50 | architecture ar_APB_CNA of APB_CNA is | |||
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51 | ||||
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52 | constant REVISION : integer := 1; | |||
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53 | ||||
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54 | constant pconfig : apb_config_type := ( | |||
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55 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |||
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56 | 1 => apb_iobar(paddr, pmask)); | |||
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57 | ||||
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58 | signal flag_nw : std_logic; | |||
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59 | signal bp : std_logic; | |||
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60 | signal Rz : std_logic; | |||
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61 | signal flag_sd : std_logic; | |||
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62 | signal Rdata : std_logic_vector(31 downto 0); | |||
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63 | ||||
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64 | type CNA_ctrlr_Reg is record | |||
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65 | CNA_Cfg : std_logic_vector(3 downto 0); | |||
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66 | CNA_Data : std_logic_vector(15 downto 0); | |||
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67 | end record; | |||
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68 | ||||
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69 | signal Rec : CNA_ctrlr_Reg; | |||
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70 | --signal ConfigREG : std_logic_vector(3 downto 0); | |||
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71 | --signal DataREG : std_logic_vector(15 downto 0); | |||
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72 | ||||
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73 | begin | |||
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74 | ||||
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75 | bp <= Rec.CNA_Cfg(0); | |||
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76 | flag_nw <= Rec.CNA_Cfg(1); | |||
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77 | Rec.CNA_Cfg(2) <= flag_sd; | |||
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78 | Rec.CNA_Cfg(3) <= Rz; | |||
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79 | ||||
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80 | ||||
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81 | ||||
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82 | CONVERTER : entity Work.CNA_TabloC | |||
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83 | port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data); | |||
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84 | ||||
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85 | ||||
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86 | ||||
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87 | process(rst,clk) | |||
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88 | begin | |||
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89 | if(rst='0')then | |||
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90 | Rec.CNA_Data <= (others => '0'); | |||
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91 | ||||
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92 | elsif(clk'event and clk='1')then | |||
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93 | ||||
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94 | ||||
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95 | --APB Write OP | |||
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96 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |||
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97 | case apbi.paddr(abits-1 downto 2) is | |||
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98 | when "000000" => | |||
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99 | Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0); | |||
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100 | when "000001" => | |||
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101 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); | |||
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102 | when others => | |||
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103 | null; | |||
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104 | end case; | |||
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105 | end if; | |||
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106 | ||||
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107 | --APB READ OP | |||
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108 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |||
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109 | case apbi.paddr(abits-1 downto 2) is | |||
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110 | when "000000" => | |||
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111 | Rdata(31 downto 4) <= X"ABCDEF5"; | |||
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112 | Rdata(3 downto 0) <= Rec.CNA_Cfg; | |||
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113 | when "000001" => | |||
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114 | Rdata(31 downto 16) <= X"FD18"; | |||
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115 | Rdata(15 downto 0) <= Rec.CNA_Data; | |||
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116 | when others => | |||
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117 | Rdata <= (others => '0'); | |||
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118 | end case; | |||
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119 | end if; | |||
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120 | ||||
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121 | end if; | |||
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122 | apbo.pconfig <= pconfig; | |||
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123 | end process; | |||
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124 | ||||
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125 | apbo.prdata <= Rdata when apbi.penable = '1'; | |||
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126 | end ar_APB_CNA; No newline at end of file |
@@ -0,0 +1,71 | |||||
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1 | -- CNA_TabloC.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | use work.Convertisseur_config.all; | |||
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6 | ||||
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7 | entity CNA_TabloC is | |||
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8 | port( | |||
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9 | clock : in std_logic; | |||
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10 | rst : in std_logic; | |||
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11 | flag_nw : in std_logic; | |||
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12 | bp : in std_logic; | |||
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13 | Data_C : in std_logic_vector(15 downto 0); | |||
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14 | SYNC : out std_logic; | |||
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15 | SCLK : out std_logic; | |||
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16 | Rz : out std_logic; | |||
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17 | flag_sd : out std_logic; | |||
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18 | Data : out std_logic | |||
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19 | ); | |||
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20 | end CNA_TabloC; | |||
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21 | ||||
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22 | ||||
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23 | architecture ar_CNA_TabloC of CNA_TabloC is | |||
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24 | ||||
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25 | component CLKINT | |||
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26 | port( A : in std_logic := 'U'; | |||
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27 | Y : out std_logic); | |||
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28 | end component; | |||
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29 | ||||
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30 | signal clk : std_logic; | |||
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31 | --signal reset : std_logic; | |||
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32 | ||||
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33 | signal raz : std_logic; | |||
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34 | signal sys_clk : std_logic; | |||
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35 | signal Data_int : std_logic_vector(15 downto 0); | |||
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36 | signal OKAI_send : std_logic; | |||
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37 | ||||
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38 | begin | |||
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39 | ||||
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40 | ||||
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41 | CLKINT_0 : CLKINT | |||
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42 | port map(A => clock, Y => clk); | |||
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43 | ||||
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44 | CLKINT_1 : CLKINT | |||
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45 | port map(A => rst, Y => raz); | |||
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46 | ||||
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47 | ||||
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48 | SystemCLK : entity work.Clock_Serie | |||
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49 | generic map (nb_serial) | |||
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50 | port map (clk,raz,sys_clk); | |||
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51 | ||||
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52 | ||||
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53 | Signal_sync : entity work.GeneSYNC_flag | |||
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54 | port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC); | |||
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55 | ||||
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56 | ||||
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57 | Serial : entity work.serialize | |||
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58 | port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data); | |||
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59 | ||||
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60 | ||||
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61 | --raz <= not reset; | |||
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62 | Rz <= raz; | |||
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63 | SCLK <= not sys_clk; | |||
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64 | --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); | |||
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65 | --Data_TOT <= "0001" & Data_Cvec; | |||
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66 | ||||
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67 | with bp select | |||
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68 | Data_int <= X"9555" when '1', | |||
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69 | Data_C when others; | |||
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70 | ||||
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71 | end ar_CNA_TabloC; No newline at end of file |
@@ -0,0 +1,24 | |||||
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1 | -- Convertisseur_config.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | ||||
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6 | Package Convertisseur_config is | |||
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7 | ||||
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8 | ||||
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9 | --===========================================================| | |||
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10 | --================= Valeurs Sinus 1Khz ======================| | |||
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11 | --===========================================================| | |||
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12 | type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); | |||
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13 | constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); | |||
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14 | ||||
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15 | --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); | |||
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16 | ||||
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17 | ||||
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18 | --===========================================================| | |||
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19 | --============= Fr�quence de s�rialisation ==================| | |||
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20 | --===========================================================| | |||
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21 | constant Freq_serial : integer := 1_000_000; | |||
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22 | constant nb_serial : integer := 40_000_000 / Freq_serial; | |||
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23 | ||||
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24 | end; No newline at end of file |
@@ -0,0 +1,94 | |||||
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1 | -- GeneSYNC_flag.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | ||||
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6 | entity GeneSYNC_flag is | |||
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7 | ||||
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8 | port( | |||
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9 | clk,raz : in std_logic; | |||
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10 | flag_nw : in std_logic; | |||
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11 | Sysclk : in std_logic; | |||
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12 | OKAI_send : out std_logic; | |||
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13 | SYNC : out std_logic | |||
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14 | ); | |||
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15 | ||||
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16 | end GeneSYNC_flag; | |||
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17 | ||||
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18 | ||||
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19 | architecture ar_GeneSYNC_flag of GeneSYNC_flag is | |||
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20 | ||||
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21 | signal Sysclk_reg : std_logic; | |||
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22 | signal flag_nw_reg : std_logic; | |||
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23 | signal count : integer; | |||
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24 | ||||
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25 | type etat is (e0,e1,e2,eX); | |||
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26 | signal ect : etat; | |||
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27 | ||||
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28 | begin | |||
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29 | process (clk,raz) | |||
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30 | begin | |||
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31 | if(raz='0')then | |||
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32 | SYNC <= '0'; | |||
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33 | Sysclk_reg <= '0'; | |||
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34 | flag_nw_reg <= '0'; | |||
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35 | count <= 14; | |||
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36 | OKAI_send <= '0'; | |||
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37 | ect <= e0; | |||
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38 | ||||
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39 | elsif(clk' event and clk='1')then | |||
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40 | Sysclk_reg <= Sysclk; | |||
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41 | flag_nw_reg <= flag_nw; | |||
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42 | ||||
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43 | case ect is | |||
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44 | when e0 => | |||
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45 | if(flag_nw_reg='0' and flag_nw='1')then | |||
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46 | ect <= e1; | |||
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47 | else | |||
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48 | count <= 14; | |||
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49 | ect <= e0; | |||
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50 | end if; | |||
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51 | ||||
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52 | ||||
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53 | when e1 => | |||
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54 | if(Sysclk_reg='1' and Sysclk='0')then | |||
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55 | if(count=15)then | |||
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56 | SYNC <= '1'; | |||
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57 | count <= count+1; | |||
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58 | ect <= e2; | |||
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59 | elsif(count=16)then | |||
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60 | count <= 0; | |||
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61 | OKAI_send <= '1'; | |||
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62 | ect <= eX; | |||
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63 | else | |||
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64 | count <= count+1; | |||
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65 | OKAI_send <= '0'; | |||
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66 | ect <= e1; | |||
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67 | end if; | |||
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68 | end if; | |||
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69 | ||||
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70 | ||||
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71 | when e2 => | |||
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72 | if(Sysclk_reg='0' and Sysclk='1')then | |||
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73 | if(count=16)then | |||
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74 | SYNC <= '0'; | |||
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75 | ect <= e1; | |||
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76 | end if; | |||
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77 | end if; | |||
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78 | ||||
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79 | when eX => | |||
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80 | if(Sysclk_reg='0' and Sysclk='1')then | |||
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81 | if(count=15)then | |||
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82 | OKAI_send <= '0'; | |||
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83 | ect <= e0; | |||
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84 | else | |||
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85 | count <= count+1; | |||
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86 | ect <= eX; | |||
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87 | end if; | |||
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88 | end if; | |||
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89 | ||||
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90 | end case; | |||
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91 | end if; | |||
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92 | ||||
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93 | end process; | |||
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94 | end ar_GeneSYNC_flag; No newline at end of file |
@@ -0,0 +1,86 | |||||
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1 | -- Serialize.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.numeric_std.all; | |||
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4 | use IEEE.std_logic_1164.all; | |||
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5 | ||||
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6 | entity Serialize is | |||
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7 | ||||
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8 | port( | |||
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9 | clk,raz : in std_logic; | |||
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10 | sclk : in std_logic; | |||
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11 | vectin : in std_logic_vector(15 downto 0); | |||
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12 | send : in std_logic; | |||
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13 | sended : out std_logic; | |||
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14 | Data : out std_logic); | |||
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15 | ||||
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16 | end Serialize; | |||
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17 | ||||
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18 | ||||
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19 | architecture ar_Serialize of Serialize is | |||
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20 | ||||
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21 | type etat is (attente,serialize); | |||
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22 | signal ect : etat; | |||
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23 | ||||
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24 | signal vector_int : std_logic_vector(16 downto 0); | |||
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25 | signal vectin_reg : std_logic_vector(15 downto 0); | |||
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26 | signal load : std_logic; | |||
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27 | signal N : integer range 0 to 16; | |||
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28 | signal CPT_ended : std_logic:='0'; | |||
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29 | ||||
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30 | begin | |||
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31 | process(clk,raz) | |||
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32 | begin | |||
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33 | if(raz='0')then | |||
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34 | ect <= attente; | |||
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35 | vectin_reg <= (others=> '0'); | |||
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36 | load <= '0'; | |||
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37 | sended <= '1'; | |||
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38 | ||||
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39 | elsif(clk'event and clk='1')then | |||
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40 | vectin_reg <= vectin; | |||
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41 | ||||
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42 | case ect is | |||
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43 | when attente => | |||
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44 | if (send='1') then | |||
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45 | sended <= '0'; | |||
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46 | load <= '1'; | |||
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47 | ect <= serialize; | |||
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48 | else | |||
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49 | ect <= attente; | |||
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50 | end if; | |||
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51 | ||||
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52 | when serialize => | |||
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53 | load <= '0'; | |||
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54 | if(CPT_ended='1')then | |||
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55 | ect <= attente; | |||
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56 | sended <= '1'; | |||
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57 | end if; | |||
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58 | ||||
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59 | end case; | |||
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60 | end if; | |||
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61 | end process; | |||
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62 | ||||
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63 | process(sclk,load,raz) | |||
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64 | begin | |||
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65 | if (raz='0')then | |||
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66 | vector_int <= (others=> '0'); | |||
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67 | N <= 16; | |||
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68 | elsif(load='1')then | |||
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69 | vector_int <= vectin & '0'; | |||
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70 | N <= 0; | |||
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71 | elsif(sclk'event and sclk='0')then | |||
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72 | if (CPT_ended='0') then | |||
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73 | vector_int <= vector_int(15 downto 0) & '0'; | |||
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74 | N <= N+1; | |||
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75 | end if; | |||
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76 | end if; | |||
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77 | end process; | |||
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78 | ||||
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79 | CPT_ended <= '1' when N = 16 else '0'; | |||
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80 | ||||
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81 | with ect select | |||
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82 | Data <= vector_int(16) when serialize, | |||
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83 | '0' when others; | |||
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84 | ||||
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85 | end ar_Serialize; | |||
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86 |
@@ -0,0 +1,41 | |||||
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1 | -- clock.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | ||||
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6 | ||||
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7 | entity Clock_Serie is | |||
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8 | ||||
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9 | generic(N :integer := 695); | |||
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10 | ||||
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11 | port( | |||
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12 | clk, raz : in std_logic ; | |||
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13 | clock : out std_logic); | |||
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14 | ||||
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15 | end Clock_Serie; | |||
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16 | ||||
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17 | ||||
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18 | architecture ar_Clock_Serie of Clock_Serie is | |||
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19 | ||||
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20 | signal clockint : std_logic; | |||
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21 | signal countint : integer range 0 to N/2-1; | |||
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22 | ||||
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23 | begin | |||
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24 | process (clk,raz) | |||
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25 | begin | |||
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26 | if(raz = '0') then | |||
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27 | countint <= 0; | |||
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28 | clockint <= '0'; | |||
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29 | elsif (clk' event and clk='1') then | |||
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30 | if (countint = N/2-1) then | |||
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31 | countint <= 0; | |||
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32 | clockint <= not clockint; | |||
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33 | else | |||
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34 | countint <= countint+1; | |||
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35 | end if; | |||
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36 | end if; | |||
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37 | end process; | |||
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38 | ||||
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39 | clock <= clockint; | |||
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40 | ||||
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41 | end ar_Clock_Serie; No newline at end of file |
@@ -0,0 +1,52 | |||||
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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 2 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | ||||
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20 | library ieee; | |||
|
21 | use ieee.std_logic_1164.all; | |||
|
22 | library grlib; | |||
|
23 | use grlib.amba.all; | |||
|
24 | -- pragma translate_off | |||
|
25 | use std.textio.all; | |||
|
26 | -- pragma translate_on | |||
|
27 | library lpp; | |||
|
28 | use lpp.lpp_amba.all; | |||
|
29 | ||||
|
30 | ||||
|
31 | package lpp_CNA_amba is | |||
|
32 | ||||
|
33 | ||||
|
34 | component APB_CNA is | |||
|
35 | generic ( | |||
|
36 | pindex : integer := 0; | |||
|
37 | paddr : integer := 0; | |||
|
38 | pmask : integer := 16#fff#; | |||
|
39 | pirq : integer := 0; | |||
|
40 | abits : integer := 8); | |||
|
41 | port ( | |||
|
42 | clk : in std_logic; | |||
|
43 | rst : in std_logic; | |||
|
44 | apbi : in apb_slv_in_type; | |||
|
45 | apbo : out apb_slv_out_type; | |||
|
46 | SYNC : out std_logic; | |||
|
47 | SCLK : out std_logic; | |||
|
48 | DATA : out std_logic | |||
|
49 | ); | |||
|
50 | end component; | |||
|
51 | ||||
|
52 | end; |
@@ -0,0 +1,128 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- APB_UART.vhd | |||
|
20 | ||||
|
21 | library ieee; | |||
|
22 | use ieee.std_logic_1164.all; | |||
|
23 | library grlib; | |||
|
24 | use grlib.amba.all; | |||
|
25 | use grlib.stdlib.all; | |||
|
26 | use grlib.devices.all; | |||
|
27 | library lpp; | |||
|
28 | use lpp.lpp_amba.all; | |||
|
29 | use lpp.lpp_uart.all; | |||
|
30 | ||||
|
31 | entity APB_UART is | |||
|
32 | generic ( | |||
|
33 | pindex : integer := 0; | |||
|
34 | paddr : integer := 0; | |||
|
35 | pmask : integer := 16#fff#; | |||
|
36 | pirq : integer := 0; | |||
|
37 | abits : integer := 8; | |||
|
38 | Data_sz : integer := 8); | |||
|
39 | port ( | |||
|
40 | clk : in std_logic; | |||
|
41 | rst : in std_logic; | |||
|
42 | apbi : in apb_slv_in_type; | |||
|
43 | apbo : out apb_slv_out_type; | |||
|
44 | TXD : out std_logic; | |||
|
45 | RXD : in std_logic | |||
|
46 | ); | |||
|
47 | end APB_UART; | |||
|
48 | ||||
|
49 | ||||
|
50 | architecture ar_APB_UART of APB_UART is | |||
|
51 | ||||
|
52 | constant REVISION : integer := 1; | |||
|
53 | ||||
|
54 | constant pconfig : apb_config_type := ( | |||
|
55 | 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), | |||
|
56 | 1 => apb_iobar(paddr, pmask)); | |||
|
57 | ||||
|
58 | signal NwData : std_logic; | |||
|
59 | signal ACK : std_logic; | |||
|
60 | signal Capture : std_logic; | |||
|
61 | signal Send : std_logic; | |||
|
62 | signal Sended : std_logic; | |||
|
63 | ||||
|
64 | type UART_ctrlr_Reg is record | |||
|
65 | UART_Cfg : std_logic_vector(4 downto 0); | |||
|
66 | UART_Wdata : std_logic_vector(7 downto 0); | |||
|
67 | UART_Rdata : std_logic_vector(7 downto 0); | |||
|
68 | UART_BTrig : std_logic_vector(11 downto 0); | |||
|
69 | end record; | |||
|
70 | ||||
|
71 | signal Rec : UART_ctrlr_Reg; | |||
|
72 | ||||
|
73 | begin | |||
|
74 | ||||
|
75 | Capture <= Rec.UART_Cfg(0); | |||
|
76 | ACK <= Rec.UART_Cfg(1); | |||
|
77 | Send <= Rec.UART_Cfg(2); | |||
|
78 | Rec.UART_Cfg(3) <= Sended; | |||
|
79 | Rec.UART_Cfg(4) <= NwData; | |||
|
80 | ||||
|
81 | ||||
|
82 | COM0 : entity work.UART | |||
|
83 | generic map (Data_sz) | |||
|
84 | port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); | |||
|
85 | ||||
|
86 | ||||
|
87 | process(rst,clk) | |||
|
88 | begin | |||
|
89 | if(rst='0')then | |||
|
90 | Rec.UART_Wdata <= (others => '0'); | |||
|
91 | apbo.prdata <= (others => '0'); | |||
|
92 | ||||
|
93 | elsif(clk'event and clk='1')then | |||
|
94 | ||||
|
95 | ||||
|
96 | --APB Write OP | |||
|
97 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |||
|
98 | case apbi.paddr(abits-1 downto 2) is | |||
|
99 | when "000000" => | |||
|
100 | Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0); | |||
|
101 | when "000001" => | |||
|
102 | Rec.UART_Wdata <= apbi.pwdata(7 downto 0); | |||
|
103 | when others => | |||
|
104 | null; | |||
|
105 | end case; | |||
|
106 | end if; | |||
|
107 | ||||
|
108 | --APB READ OP | |||
|
109 | if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then | |||
|
110 | case apbi.paddr(abits-1 downto 2) is | |||
|
111 | when "000000" => | |||
|
112 | apbo.prdata(31 downto 27) <= Rec.UART_Cfg; | |||
|
113 | apbo.prdata(26 downto 12) <= (others => '0'); | |||
|
114 | apbo.prdata(11 downto 0) <= Rec.UART_BTrig; | |||
|
115 | when "000001" => | |||
|
116 | apbo.prdata(7 downto 0) <= Rec.UART_Wdata; | |||
|
117 | when "000010" => | |||
|
118 | apbo.prdata(7 downto 0) <= Rec.UART_Rdata; | |||
|
119 | when others => | |||
|
120 | apbo.prdata <= (others => '0'); | |||
|
121 | end case; | |||
|
122 | end if; | |||
|
123 | ||||
|
124 | end if; | |||
|
125 | apbo.pconfig <= pconfig; | |||
|
126 | end process; | |||
|
127 | ||||
|
128 | end ar_APB_UART; No newline at end of file |
@@ -0,0 +1,82 | |||||
|
1 | -- BaudGen.vhd | |||
|
2 | library IEEE; | |||
|
3 | use IEEE.numeric_std.all; | |||
|
4 | use IEEE.std_logic_1164.all; | |||
|
5 | ||||
|
6 | --! Generateur de Bauds | |||
|
7 | ||||
|
8 | entity BaudGen is | |||
|
9 | ||||
|
10 | port( | |||
|
11 | clk : in std_logic; | |||
|
12 | reset : in std_logic; | |||
|
13 | Capture : in std_logic; | |||
|
14 | Bclk : out std_logic; | |||
|
15 | RXD : in std_logic; | |||
|
16 | BTrigger : out std_logic_vector(11 downto 0) | |||
|
17 | ); | |||
|
18 | end BaudGen; | |||
|
19 | ||||
|
20 | ||||
|
21 | architecture ar_BaudGen of BaudGen is | |||
|
22 | signal cpt : std_logic_vector(11 downto 0) := (others => '0'); | |||
|
23 | signal errorFlag : std_logic; | |||
|
24 | signal triger : std_logic_vector(11 downto 0) := (others => '0'); | |||
|
25 | signal RX_reg : std_logic:='1'; | |||
|
26 | ||||
|
27 | begin | |||
|
28 | ||||
|
29 | ||||
|
30 | BTrigger <= triger; | |||
|
31 | ||||
|
32 | ||||
|
33 | BaudGeneration: | |||
|
34 | process(clk,reset) | |||
|
35 | begin | |||
|
36 | if reset = '0' then | |||
|
37 | cpt <= (others => '0'); | |||
|
38 | triger <= (others => '1'); | |||
|
39 | errorFlag <= '0'; | |||
|
40 | elsif clk'event and clk = '1'then | |||
|
41 | RX_reg <= RXD; | |||
|
42 | if capture = '1' then | |||
|
43 | cpt <= (others => '0'); | |||
|
44 | triger <= (others => '1'); | |||
|
45 | errorFlag <= '0'; | |||
|
46 | else | |||
|
47 | if RX_reg /= RXD then | |||
|
48 | cpt <= (others => '0'); | |||
|
49 | if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then | |||
|
50 | errorFlag <= '1'; | |||
|
51 | elsif errorFlag = '1' then | |||
|
52 | triger <= cpt; | |||
|
53 | errorFlag <= '0'; | |||
|
54 | else | |||
|
55 | errorFlag <= '1'; | |||
|
56 | end if; | |||
|
57 | else | |||
|
58 | if cpt = triger then | |||
|
59 | cpt <= (others => '0'); | |||
|
60 | errorFlag <= '0'; | |||
|
61 | else | |||
|
62 | cpt <= std_logic_vector(unsigned(cpt) + 1); | |||
|
63 | end if; | |||
|
64 | end if; | |||
|
65 | end if; | |||
|
66 | end if; | |||
|
67 | end process; | |||
|
68 | ||||
|
69 | ||||
|
70 | process(clk) | |||
|
71 | begin | |||
|
72 | if clk'event and clk = '1' then | |||
|
73 | if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then | |||
|
74 | Bclk <= '0'; | |||
|
75 | elsif cpt = '0' & triger(11 downto 1) then | |||
|
76 | Bclk <= '1'; | |||
|
77 | end if; | |||
|
78 | end if; | |||
|
79 | end process; | |||
|
80 | ||||
|
81 | ||||
|
82 | end ar_BaudGen; No newline at end of file |
@@ -0,0 +1,94 | |||||
|
1 | -- Shift_REG.vhd | |||
|
2 | library IEEE; | |||
|
3 | use IEEE.numeric_std.all; | |||
|
4 | use IEEE.std_logic_1164.all; | |||
|
5 | ||||
|
6 | --! Gestion Reception/Transmission | |||
|
7 | ||||
|
8 | entity Shift_REG is | |||
|
9 | generic(Data_sz : integer := 10); | |||
|
10 | port( | |||
|
11 | clk : in std_logic; | |||
|
12 | Sclk : in std_logic; | |||
|
13 | reset : in std_logic; | |||
|
14 | SIN : in std_logic; | |||
|
15 | SOUT : out std_logic; | |||
|
16 | Serialize : in std_logic; | |||
|
17 | Serialized : out std_logic; | |||
|
18 | D : in std_logic_vector(Data_sz-1 downto 0); | |||
|
19 | Q : out std_logic_vector(Data_sz-1 downto 0) | |||
|
20 | ||||
|
21 | ); | |||
|
22 | end entity; | |||
|
23 | ||||
|
24 | ||||
|
25 | architecture ar_Shift_REG of Shift_REG is | |||
|
26 | ||||
|
27 | signal REG : std_logic_vector(Data_sz-1 downto 0); | |||
|
28 | signal Serialized_int : std_logic; | |||
|
29 | signal Serialize_reg : std_logic; | |||
|
30 | signal CptBits : std_logic_vector(Data_sz-1 downto 0); | |||
|
31 | constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); | |||
|
32 | signal CptBits_flag : std_logic; | |||
|
33 | signal CptBits_flag_reg : std_logic; | |||
|
34 | ||||
|
35 | begin | |||
|
36 | ||||
|
37 | Serialized <= Serialized_int; | |||
|
38 | CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; | |||
|
39 | ||||
|
40 | process(reset,clk) | |||
|
41 | begin | |||
|
42 | if reset = '0' then | |||
|
43 | Serialized_int <= '1'; | |||
|
44 | CptBits_flag_reg <= '0'; | |||
|
45 | Q <= (others => '0'); | |||
|
46 | elsif clk'event and clk = '1' then | |||
|
47 | CptBits_flag_reg <= CptBits_flag; | |||
|
48 | ||||
|
49 | if CptBits_flag = '1' and CptBits_flag_reg = '0' then | |||
|
50 | Serialized_int <= '1'; | |||
|
51 | Q <= REG; | |||
|
52 | elsif Serialize = '1' then | |||
|
53 | Serialized_int <= '0'; | |||
|
54 | end if; | |||
|
55 | end if; | |||
|
56 | end process; | |||
|
57 | ||||
|
58 | ||||
|
59 | process(reset,Sclk) | |||
|
60 | begin | |||
|
61 | if reset = '0' then | |||
|
62 | CptBits <= (others => '0'); | |||
|
63 | REG <= (others => '0'); | |||
|
64 | SOUT <= '1'; | |||
|
65 | Serialize_reg <= '0'; | |||
|
66 | elsif Sclk'event and Sclk = '1' then | |||
|
67 | Serialize_reg <= Serialized_int; | |||
|
68 | if (Serialized_int = '0' and Serialize_reg ='1') then | |||
|
69 | REG <= SIN & D(Data_sz-1 downto 1); | |||
|
70 | SOUT <= D(0); | |||
|
71 | elsif CptBits_flag ='1' then | |||
|
72 | REG <= SIN & D(Data_sz-1 downto 1); | |||
|
73 | SOUT <= D(0); | |||
|
74 | elsif Serialized_int = '0' then | |||
|
75 | REG <= SIN & REG(Data_sz-1 downto 1); | |||
|
76 | SOUT <= REG(0); | |||
|
77 | else | |||
|
78 | SOUT <= '1'; | |||
|
79 | end if; | |||
|
80 | if Serialized_int = '0' then | |||
|
81 | if CptBits_flag = '1' then | |||
|
82 | CptBits <= (others => '0'); | |||
|
83 | else | |||
|
84 | CptBits <= '1' & CptBits(Data_sz-1 downto 1); | |||
|
85 | end if; | |||
|
86 | ||||
|
87 | else | |||
|
88 | CptBits <= (others => '0'); | |||
|
89 | end if; | |||
|
90 | ||||
|
91 | end if; | |||
|
92 | end process; | |||
|
93 | ||||
|
94 | end ar_Shift_REG; No newline at end of file |
@@ -0,0 +1,81 | |||||
|
1 | -- UART.vhd | |||
|
2 | library IEEE; | |||
|
3 | use IEEE.numeric_std.all; | |||
|
4 | use IEEE.std_logic_1164.all; | |||
|
5 | library lpp; | |||
|
6 | use lpp.lpp_uart.all; | |||
|
7 | ||||
|
8 | --! Programme qui va gerer toute la communication entre le PC et le FPGA | |||
|
9 | ||||
|
10 | entity UART is | |||
|
11 | generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee | |||
|
12 | port( | |||
|
13 | clk : in std_logic; --! Horloge a 25Mhz du systeme | |||
|
14 | reset : in std_logic; --! Reset du systeme | |||
|
15 | TXD : out std_logic; --! Transmission, cote PC | |||
|
16 | RXD : in std_logic; --! Reception, cote PC | |||
|
17 | Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global | |||
|
18 | NwDat : out std_logic; --! Flag, Nouvelle donnee presente | |||
|
19 | ACK : in std_logic; --! Flag, Reponse au flag precedent | |||
|
20 | Send : in std_logic; --! Flag, Demande d'envoi sur le bus | |||
|
21 | Sended : out std_logic; --! Flag, Envoi termine | |||
|
22 | BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission | |||
|
23 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur | |||
|
24 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur | |||
|
25 | ); | |||
|
26 | end entity; | |||
|
27 | ||||
|
28 | ||||
|
29 | --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation | |||
|
30 | --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds) | |||
|
31 | architecture ar_UART of UART is | |||
|
32 | signal Bclk : std_logic; | |||
|
33 | ||||
|
34 | signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); | |||
|
35 | signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); | |||
|
36 | ||||
|
37 | signal TXD_Dummy : std_logic; | |||
|
38 | signal NwDat_int : std_logic; | |||
|
39 | signal NwDat_int_reg : std_logic; | |||
|
40 | signal receive : std_logic; | |||
|
41 | ||||
|
42 | begin | |||
|
43 | ||||
|
44 | ||||
|
45 | RDATA <= RDATA_int(8 downto 1); | |||
|
46 | WDATA_int <= '1' & WDATA & '0'; | |||
|
47 | ||||
|
48 | BaudGenerator : BaudGen | |||
|
49 | port map(clk,reset,Capture,Bclk,RXD,BTrigger); | |||
|
50 | ||||
|
51 | ||||
|
52 | RX_REG : Shift_REG | |||
|
53 | generic map(Data_sz+2) | |||
|
54 | port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,(others => '0'),RDATA_int); | |||
|
55 | ||||
|
56 | TX_REG : Shift_REG | |||
|
57 | generic map(Data_sz+2) | |||
|
58 | port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int); | |||
|
59 | ||||
|
60 | ||||
|
61 | ||||
|
62 | process(clk,reset) | |||
|
63 | begin | |||
|
64 | if reset = '0' then | |||
|
65 | NwDat <= '0'; | |||
|
66 | elsif clk'event and clk = '1' then | |||
|
67 | NwDat_int_reg <= NwDat_int; | |||
|
68 | if RXD = '1' and NwDat_int = '1' then | |||
|
69 | receive <= '0'; | |||
|
70 | elsif RXD = '0' then | |||
|
71 | receive <= '1'; | |||
|
72 | end if; | |||
|
73 | if NwDat_int_reg = '0' and NwDat_int = '1' then | |||
|
74 | NwDat <= '1'; | |||
|
75 | elsif ack = '1' then | |||
|
76 | NwDat <= '0'; | |||
|
77 | end if; | |||
|
78 | end if; | |||
|
79 | end process; | |||
|
80 | ||||
|
81 | end ar_UART; No newline at end of file |
@@ -0,0 +1,79 | |||||
|
1 | library ieee; | |||
|
2 | use ieee.std_logic_1164.all; | |||
|
3 | library grlib; | |||
|
4 | use grlib.amba.all; | |||
|
5 | -- pragma translate_off | |||
|
6 | use std.textio.all; | |||
|
7 | -- pragma translate_on | |||
|
8 | library lpp; | |||
|
9 | use lpp.lpp_amba.all; | |||
|
10 | ||||
|
11 | package lpp_uart is | |||
|
12 | ||||
|
13 | component UART is | |||
|
14 | generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee | |||
|
15 | port( | |||
|
16 | clk : in std_logic; --! Horloge a 25Mhz du systeme | |||
|
17 | reset : in std_logic; --! Reset du systeme | |||
|
18 | TXD : out std_logic; --! Transmission, cote PC | |||
|
19 | RXD : in std_logic; --! Reception, cote PC | |||
|
20 | Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global | |||
|
21 | NwDat : out std_logic; --! Flag, Nouvelle donnee presente | |||
|
22 | ACK : in std_logic; --! Flag, Reponse au flag precedent | |||
|
23 | Send : in std_logic; --! Flag, Demande d'envoi sur le bus | |||
|
24 | Sended : out std_logic; --! Flag, Envoi termine | |||
|
25 | BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission | |||
|
26 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur | |||
|
27 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur | |||
|
28 | ); | |||
|
29 | end component; | |||
|
30 | ||||
|
31 | ||||
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32 | component Shift_REG is | |||
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33 | generic(Data_sz : integer := 10); | |||
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34 | port( | |||
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35 | clk : in std_logic; | |||
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36 | Sclk : in std_logic; | |||
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37 | reset : in std_logic; | |||
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38 | SIN : in std_logic; | |||
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39 | SOUT : out std_logic; | |||
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40 | Serialize : in std_logic; | |||
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41 | Serialized : out std_logic; | |||
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42 | D : in std_logic_vector(Data_sz-1 downto 0); | |||
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43 | Q : out std_logic_vector(Data_sz-1 downto 0) | |||
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44 | ||||
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45 | ); | |||
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46 | end component; | |||
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47 | ||||
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48 | ||||
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49 | component BaudGen is | |||
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50 | port( | |||
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51 | clk : in std_logic; | |||
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52 | reset : in std_logic; | |||
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53 | Capture : in std_logic; | |||
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54 | Bclk : out std_logic; | |||
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55 | RXD : in std_logic; | |||
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56 | BTrigger : out std_logic_vector(11 downto 0) | |||
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57 | ); | |||
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58 | end component; | |||
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59 | ||||
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60 | component APB_UART is | |||
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61 | generic ( | |||
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62 | pindex : integer := 0; | |||
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63 | paddr : integer := 0; | |||
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64 | pmask : integer := 16#fff#; | |||
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65 | pirq : integer := 0; | |||
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66 | abits : integer := 8; | |||
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67 | Data_sz : integer := 8); | |||
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68 | port ( | |||
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69 | clk : in std_logic; | |||
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70 | rst : in std_logic; | |||
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71 | apbi : in apb_slv_in_type; | |||
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72 | apbo : out apb_slv_out_type; | |||
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73 | TXD : out std_logic; | |||
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74 | RXD : in std_logic | |||
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75 | ); | |||
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76 | end component; | |||
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77 | ||||
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78 | ||||
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79 | end lpp_uart; No newline at end of file |
@@ -38,6 +38,8 constant otherCore : am | |||||
38 | constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#; |
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38 | constant LPP_SIMPLE_DIODE : amba_device_type := 16#003#; | |
39 | constant LPP_MULTI_DIODE : amba_device_type := 16#004#; |
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39 | constant LPP_MULTI_DIODE : amba_device_type := 16#004#; | |
40 | constant LPP_LCD_CTRLR : amba_device_type := 16#005#; |
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40 | constant LPP_LCD_CTRLR : amba_device_type := 16#005#; | |
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41 | constant LPP_UART : amba_device_type := 16#006#; | |||
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42 | constant LPP_CNA : amba_device_type := 16#007#; | |||
41 |
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43 | |||
42 |
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44 | |||
43 | component APB_SIMPLE_DIODE is |
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45 | component APB_SIMPLE_DIODE is |
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