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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 LIBRARY lpp;
27 USE lpp.general_purpose.ALL;
28
29 ENTITY SYNC_VALID_BIT IS
30 GENERIC (
31 NB_FF_OF_SYNC : INTEGER := 2);
32 PORT (
33 clk_in : IN STD_LOGIC;
34 clk_out : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 sin : IN STD_LOGIC;
37 sout : OUT STD_LOGIC);
38 END SYNC_VALID_BIT;
39
40 ARCHITECTURE beh OF SYNC_VALID_BIT IS
41 SIGNAL s_1 : STD_LOGIC;
42 SIGNAL s_2 : STD_LOGIC;
43 BEGIN -- beh
44
45 lpp_front_to_level_1: lpp_front_to_level
46 PORT MAP (
47 clk => clk_in,
48 rstn => rstn,
49 sin => sin,
50 sout => s_1);
51
52 SYNC_FF_1: SYNC_FF
53 GENERIC MAP (
54 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
55 PORT MAP (
56 clk => clk_out,
57 rstn => rstn,
58 A => s_1,
59 A_sync => s_2);
60
61 lpp_front_detection_1: lpp_front_detection
62 PORT MAP (
63 clk => clk_out,
64 rstn => rstn,
65 sin => s_2,
66 sout => sout);
67
68 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_detection IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_detection;
34
35 ARCHITECTURE beh OF lpp_front_detection IS
36
37 SIGNAL reg : STD_LOGIC;
38 SIGNAL sout_reg : STD_LOGIC;
39
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = NOT reg THEN
50 sout_reg <= '1';
51 ELSE
52 sout_reg <= '0';
53 END IF;
54 END IF;
55 END PROCESS;
56
57 sout <= sout_reg;
58
59 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_to_level IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_to_level;
34
35 ARCHITECTURE beh OF lpp_front_to_level IS
36
37 SIGNAL reg : STD_LOGIC;
38
39 SIGNAL sout_reg : STD_LOGIC;
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = '1' AND reg = '0' THEN
50 sout_reg <= NOT sout_reg;
51 END IF;
52 END IF;
53 END PROCESS;
54
55 sout <= sout_reg;
56
57 END beh;
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY lpp_counter IS
6
7 GENERIC (
8 nb_wait_period : INTEGER := 750;
9 nb_bit_of_data : INTEGER := 16
10 );
11 PORT (
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 clear : IN STD_LOGIC;
15 full : OUT STD_LOGIC;
16 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
17 new_data : OUT STD_LOGIC
18 );
19
20 END lpp_counter;
21
22 ARCHITECTURE beh OF lpp_counter IS
23
24 SIGNAL counter_wait : INTEGER;
25 SIGNAL counter_data : INTEGER;
26
27 SIGNAL new_data_s : STD_LOGIC;
28 BEGIN -- beh
29
30 PROCESS (clk, rstn)
31 BEGIN -- PROCESS
32 IF rstn = '0' THEN -- asynchronous reset (active low)
33 counter_wait <= 0;
34 counter_data <= 0;
35 full <= '0';
36 new_data_s <= '0';
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
38 IF clear = '1' THEN
39 counter_wait <= 0;
40 counter_data <= 0;
41 full <= '0';
42 new_data_s <= NOT new_data_s;
43 ELSE
44 IF counter_wait = nb_wait_period-1 THEN
45 counter_wait <= 0;
46 new_data_s <= NOT new_data_s;
47 IF counter_data = (2**nb_bit_of_data)-1 THEN
48 full <= '1';
49 counter_data <= 0;
50 ELSE
51 full <= '0';
52 counter_data <= counter_data +1;
53 END IF;
54 ELSE
55 full <= '0';
56 counter_wait <= counter_wait +1;
57 END IF;
58 END IF;
59 END IF;
60 END PROCESS;
61
62 data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data));
63 new_data <= new_data_s;
64
65 END beh;
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1 iir_filter.vhd
1 iir_filter.vhd
2 FILTERcfg.vhd
2 FILTERcfg.vhd
3 RAM.vhd
3 RAM.vhd
4 RAM_CEL.vhd
4 RAM_CEL.vhd
5 RAM_CEL_N.vhd
5 RAM_CTRLR_v2.vhd
6 RAM_CTRLR_v2.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2.vhd
9 IIR_CEL_CTRLR_v2.vhd
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30
30
31
31
32
32
33 PACKAGE general_purpose IS
33 PACKAGE general_purpose IS
34
34
35
35
36
36
37 COMPONENT Clk_divider IS
37 COMPONENT Clk_divider IS
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 TargetFreq_Hz : INTEGER := 50000);
39 TargetFreq_Hz : INTEGER := 50000);
40 PORT (clk : IN STD_LOGIC;
40 PORT (clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clk_divided : OUT STD_LOGIC);
42 clk_divided : OUT STD_LOGIC);
43 END COMPONENT;
43 END COMPONENT;
44
44
45
45
46 COMPONENT Clk_divider2 IS
46 COMPONENT Clk_divider2 IS
47 generic(N : integer := 16);
47 generic(N : integer := 16);
48 port(
48 port(
49 clk_in : in std_logic;
49 clk_in : in std_logic;
50 clk_out : out std_logic);
50 clk_out : out std_logic);
51 END COMPONENT;
51 END COMPONENT;
52
52
53 COMPONENT Adder IS
53 COMPONENT Adder IS
54 GENERIC(
54 GENERIC(
55 Input_SZ_A : INTEGER := 16;
55 Input_SZ_A : INTEGER := 16;
56 Input_SZ_B : INTEGER := 16
56 Input_SZ_B : INTEGER := 16
57
57
58 );
58 );
59 PORT(
59 PORT(
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
63 load : IN STD_LOGIC;
63 load : IN STD_LOGIC;
64 add : IN STD_LOGIC;
64 add : IN STD_LOGIC;
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 );
68 );
69 END COMPONENT;
69 END COMPONENT;
70
70
71 COMPONENT ADDRcntr IS
71 COMPONENT ADDRcntr IS
72 PORT(
72 PORT(
73 clk : IN STD_LOGIC;
73 clk : IN STD_LOGIC;
74 reset : IN STD_LOGIC;
74 reset : IN STD_LOGIC;
75 count : IN STD_LOGIC;
75 count : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 );
78 );
79 END COMPONENT;
79 END COMPONENT;
80
80
81 COMPONENT ALU IS
81 COMPONENT ALU IS
82 GENERIC(
82 GENERIC(
83 Arith_en : INTEGER := 1;
83 Arith_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
85 Input_SZ_1 : INTEGER := 16;
85 Input_SZ_1 : INTEGER := 16;
86 Input_SZ_2 : INTEGER := 9;
86 Input_SZ_2 : INTEGER := 9;
87 COMP_EN : INTEGER := 0 -- 1 => No Comp
87 COMP_EN : INTEGER := 0 -- 1 => No Comp
88
88
89 );
89 );
90 PORT(
90 PORT(
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 reset : IN STD_LOGIC;
92 reset : IN STD_LOGIC;
93 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
93 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
94 comp : IN STD_LOGIC_VECTOR(1 downto 0);
94 comp : IN STD_LOGIC_VECTOR(1 downto 0);
95 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
95 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
96 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
96 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
97 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
97 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
98 );
98 );
99 END COMPONENT;
99 END COMPONENT;
100
100
101 ---------------------------------------------------------
101 ---------------------------------------------------------
102 -------- // SοΏ½lection grace a l'entrοΏ½e "ctrl" \\ --------
102 -------- // SοΏ½lection grace a l'entrοΏ½e "ctrl" \\ --------
103 ---------------------------------------------------------
103 ---------------------------------------------------------
104 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
104 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
105 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
105 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
106 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
106 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
107 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
107 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
108 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
108 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
109 ---------------------------------------------------------
109 ---------------------------------------------------------
110
110
111 COMPONENT MAC IS
111 COMPONENT MAC IS
112 GENERIC(
112 GENERIC(
113 Input_SZ_A : INTEGER := 8;
113 Input_SZ_A : INTEGER := 8;
114 Input_SZ_B : INTEGER := 8;
114 Input_SZ_B : INTEGER := 8;
115 COMP_EN : INTEGER := 0 -- 1 => No Comp
115 COMP_EN : INTEGER := 0 -- 1 => No Comp
116 );
116 );
117 PORT(
117 PORT(
118 clk : IN STD_LOGIC;
118 clk : IN STD_LOGIC;
119 reset : IN STD_LOGIC;
119 reset : IN STD_LOGIC;
120 clr_MAC : IN STD_LOGIC;
120 clr_MAC : IN STD_LOGIC;
121 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
123 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
123 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
124 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
124 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
125 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
125 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
126 );
126 );
127 END COMPONENT;
127 END COMPONENT;
128
128
129 COMPONENT TwoComplementer is
129 COMPONENT TwoComplementer is
130 generic(
130 generic(
131 Input_SZ : integer := 16);
131 Input_SZ : integer := 16);
132 port(
132 port(
133 clk : in std_logic; --! Horloge du composant
133 clk : in std_logic; --! Horloge du composant
134 reset : in std_logic; --! Reset general du composant
134 reset : in std_logic; --! Reset general du composant
135 clr : in std_logic; --! Un reset spοΏ½cifique au programme
135 clr : in std_logic; --! Un reset spοΏ½cifique au programme
136 TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment
136 TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment
137 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e
137 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e
138 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non
138 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non
139 );
139 );
140 end COMPONENT;
140 end COMPONENT;
141
141
142 COMPONENT MAC_CONTROLER IS
142 COMPONENT MAC_CONTROLER IS
143 PORT(
143 PORT(
144 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
144 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
145 MULT : OUT STD_LOGIC;
145 MULT : OUT STD_LOGIC;
146 ADD : OUT STD_LOGIC;
146 ADD : OUT STD_LOGIC;
147 LOAD_ADDER : out std_logic;
147 LOAD_ADDER : out std_logic;
148 MACMUX_sel : OUT STD_LOGIC;
148 MACMUX_sel : OUT STD_LOGIC;
149 MACMUX2_sel : OUT STD_LOGIC
149 MACMUX2_sel : OUT STD_LOGIC
150 );
150 );
151 END COMPONENT;
151 END COMPONENT;
152
152
153 COMPONENT MAC_MUX IS
153 COMPONENT MAC_MUX IS
154 GENERIC(
154 GENERIC(
155 Input_SZ_A : INTEGER := 16;
155 Input_SZ_A : INTEGER := 16;
156 Input_SZ_B : INTEGER := 16
156 Input_SZ_B : INTEGER := 16
157
157
158 );
158 );
159 PORT(
159 PORT(
160 sel : IN STD_LOGIC;
160 sel : IN STD_LOGIC;
161 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
161 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
163 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
163 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
164 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
164 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
165 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
165 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
166 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
166 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
167 );
167 );
168 END COMPONENT;
168 END COMPONENT;
169
169
170
170
171 COMPONENT MAC_MUX2 IS
171 COMPONENT MAC_MUX2 IS
172 GENERIC(Input_SZ : INTEGER := 16);
172 GENERIC(Input_SZ : INTEGER := 16);
173 PORT(
173 PORT(
174 sel : IN STD_LOGIC;
174 sel : IN STD_LOGIC;
175 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
175 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
176 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
176 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
177 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
177 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
178 );
178 );
179 END COMPONENT;
179 END COMPONENT;
180
180
181
181
182 COMPONENT MAC_REG IS
182 COMPONENT MAC_REG IS
183 GENERIC(size : INTEGER := 16);
183 GENERIC(size : INTEGER := 16);
184 PORT(
184 PORT(
185 reset : IN STD_LOGIC;
185 reset : IN STD_LOGIC;
186 clk : IN STD_LOGIC;
186 clk : IN STD_LOGIC;
187 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
187 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
188 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
188 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
189 );
189 );
190 END COMPONENT;
190 END COMPONENT;
191
191
192
192
193 COMPONENT MUX2 IS
193 COMPONENT MUX2 IS
194 GENERIC(Input_SZ : INTEGER := 16);
194 GENERIC(Input_SZ : INTEGER := 16);
195 PORT(
195 PORT(
196 sel : IN STD_LOGIC;
196 sel : IN STD_LOGIC;
197 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
197 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
198 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
198 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
199 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
199 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
200 );
200 );
201 END COMPONENT;
201 END COMPONENT;
202
202
203 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
203 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
204 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
204 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
205
205
206 COMPONENT MUXN
206 COMPONENT MUXN
207 GENERIC (
207 GENERIC (
208 Input_SZ : INTEGER;
208 Input_SZ : INTEGER;
209 NbStage : INTEGER);
209 NbStage : INTEGER);
210 PORT (
210 PORT (
211 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
211 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
212 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
212 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
213 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
213 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
214 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
214 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
215 END COMPONENT;
215 END COMPONENT;
216
216
217
217
218
218
219 COMPONENT Multiplier IS
219 COMPONENT Multiplier IS
220 GENERIC(
220 GENERIC(
221 Input_SZ_A : INTEGER := 16;
221 Input_SZ_A : INTEGER := 16;
222 Input_SZ_B : INTEGER := 16
222 Input_SZ_B : INTEGER := 16
223
223
224 );
224 );
225 PORT(
225 PORT(
226 clk : IN STD_LOGIC;
226 clk : IN STD_LOGIC;
227 reset : IN STD_LOGIC;
227 reset : IN STD_LOGIC;
228 mult : IN STD_LOGIC;
228 mult : IN STD_LOGIC;
229 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
229 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
230 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
230 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
231 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
231 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
232 );
232 );
233 END COMPONENT;
233 END COMPONENT;
234
234
235 COMPONENT REG IS
235 COMPONENT REG IS
236 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
236 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
237 PORT(
237 PORT(
238 reset : IN STD_LOGIC;
238 reset : IN STD_LOGIC;
239 clk : IN STD_LOGIC;
239 clk : IN STD_LOGIC;
240 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
240 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
241 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
241 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
242 );
242 );
243 END COMPONENT;
243 END COMPONENT;
244
244
245
245
246
246
247 COMPONENT RShifter IS
247 COMPONENT RShifter IS
248 GENERIC(
248 GENERIC(
249 Input_SZ : INTEGER := 16;
249 Input_SZ : INTEGER := 16;
250 shift_SZ : INTEGER := 4
250 shift_SZ : INTEGER := 4
251 );
251 );
252 PORT(
252 PORT(
253 clk : IN STD_LOGIC;
253 clk : IN STD_LOGIC;
254 reset : IN STD_LOGIC;
254 reset : IN STD_LOGIC;
255 shift : IN STD_LOGIC;
255 shift : IN STD_LOGIC;
256 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
256 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
257 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
257 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
259 );
259 );
260 END COMPONENT;
260 END COMPONENT;
261
261
262 COMPONENT SYNC_FF
262 COMPONENT SYNC_FF
263 GENERIC (
263 GENERIC (
264 NB_FF_OF_SYNC : INTEGER);
264 NB_FF_OF_SYNC : INTEGER);
265 PORT (
265 PORT (
266 clk : IN STD_LOGIC;
266 clk : IN STD_LOGIC;
267 rstn : IN STD_LOGIC;
267 rstn : IN STD_LOGIC;
268 A : IN STD_LOGIC;
268 A : IN STD_LOGIC;
269 A_sync : OUT STD_LOGIC);
269 A_sync : OUT STD_LOGIC);
270 END COMPONENT;
270 END COMPONENT;
271
271
272 COMPONENT lpp_front_to_level
273 PORT (
274 clk : IN STD_LOGIC;
275 rstn : IN STD_LOGIC;
276 sin : IN STD_LOGIC;
277 sout : OUT STD_LOGIC);
278 END COMPONENT;
279
280 COMPONENT lpp_front_detection
281 PORT (
282 clk : IN STD_LOGIC;
283 rstn : IN STD_LOGIC;
284 sin : IN STD_LOGIC;
285 sout : OUT STD_LOGIC);
286 END COMPONENT;
287
288 COMPONENT SYNC_VALID_BIT
289 GENERIC (
290 NB_FF_OF_SYNC : INTEGER);
291 PORT (
292 clk_in : IN STD_LOGIC;
293 clk_out : IN STD_LOGIC;
294 rstn : IN STD_LOGIC;
295 sin : IN STD_LOGIC;
296 sout : OUT STD_LOGIC);
297 END COMPONENT;
298
272 END;
299 END;
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@@ -1,18 +1,22
1 general_purpose.vhd
1 general_purpose.vhd
2 ADDRcntr.vhd
2 ADDRcntr.vhd
3 ALU.vhd
3 ALU.vhd
4 Adder.vhd
4 Adder.vhd
5 Clk_Divider2.vhd
5 Clk_Divider2.vhd
6 Clk_divider.vhd
6 Clk_divider.vhd
7 MAC.vhd
7 MAC.vhd
8 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
9 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
10 MAC_MUX2.vhd
11 MAC_REG.vhd
11 MAC_REG.vhd
12 MUX2.vhd
12 MUX2.vhd
13 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
14 Multiplier.vhd
15 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
16 SYNC_FF.vhd
17 Shifter.vhd
17 Shifter.vhd
18 TwoComplementer.vhd
18 TwoComplementer.vhd
19 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
21 SYNC_VALID_BIT.vhd
22
Show file before | Show file after | Hide comments
@@ -1,208 +1,286
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30
31
31 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
32
33
33 GENERIC(
34 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used
38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
41 );
39 );
42
40
43 PORT (
41 PORT (
44 clk25MHz : IN STD_LOGIC; --! Clock
42 clk25MHz : IN STD_LOGIC; --! Clock
45 clk49_152MHz : IN STD_LOGIC; --! secondary clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
46 resetn : IN STD_LOGIC; --! Reset
44 resetn : IN STD_LOGIC; --! Reset
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45
48 apbi : IN apb_slv_in_type; --! APB slave input signals
46 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
47 apbi : IN apb_slv_in_type; --! APB slave input signals
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
48 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52 );
51 );
53
52
54 END apb_lfr_time_management;
53 END apb_lfr_time_management;
55
54
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
55 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57
56
58 CONSTANT REVISION : INTEGER := 1;
57 CONSTANT REVISION : INTEGER := 1;
59
60 --! the following types are defined in the grlib amba package
61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 CONSTANT pconfig : apb_config_type := (
58 CONSTANT pconfig : apb_config_type := (
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
59 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
66 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask)
61 );
67
62
68 TYPE apb_lfr_time_management_Reg IS RECORD
63 TYPE apb_lfr_time_management_Reg IS RECORD
69 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 END RECORD;
68 END RECORD;
75
69
76 SIGNAL r : apb_lfr_time_management_Reg;
70 SIGNAL r : apb_lfr_time_management_Reg;
77 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL force_tick : STD_LOGIC;
72 SIGNAL force_tick : STD_LOGIC;
79 SIGNAL previous_force_tick : STD_LOGIC;
73 SIGNAL previous_force_tick : STD_LOGIC;
80 SIGNAL soft_tick : STD_LOGIC;
74 SIGNAL soft_tick : STD_LOGIC;
81 -- SIGNAL reset_next_commutation : STD_LOGIC;
75
82
83 SIGNAL irq1 : STD_LOGIC;
76 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
77 SIGNAL irq2 : STD_LOGIC;
85
78
86 BEGIN
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
81
88 lfrtimemanagement0 : lfr_time_management
82 SIGNAL coarse_time_new : STD_LOGIC;
89 GENERIC MAP(
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
90 masterclk => masterclk,
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
91 timeclk => timeclk,
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
92 finetimeclk => finetimeclk,
86
93 nb_clk_div_ticks => 1)
87 SIGNAL fine_time_new : STD_LOGIC;
94 PORT MAP(
88 SIGNAL fine_time_new_temp : STD_LOGIC;
95 master_clock => clk25MHz,
89 SIGNAL fine_time_new_49 : STD_LOGIC;
96 time_clock => clk49_152MHz,
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
97 resetn => resetn,
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 grspw_tick => grspw_tick,
92 SIGNAL tick : STD_LOGIC;
99 soft_tick => soft_tick,
93 SIGNAL new_timecode : STD_LOGIC;
100 coarse_time_load => r.coarse_time_load,
94 SIGNAL new_coarsetime : STD_LOGIC;
101 coarse_time => r.coarse_time,
95
102 fine_time => r.fine_time,
96 BEGIN
103 next_commutation => r.next_commutation,
97 -----------------------------------------------------------------------------
104 -- reset_next_commutation => reset_next_commutation,
98 -- TODO
105 irq1 => irq1,--apbo.pirq(pirq),
99 -- IRQ 1 & 2
106 irq2 => irq2);--apbo.pirq(pirq+1));
100 -----------------------------------------------------------------------------
101 irq2 <= '0';
102 irq1 <= '0';
107
103
108 --apbo.pirq <= (OTHERS => '0');
104
105 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
106 --irq1_gen : IF I = pirq GENERATE
107 apbo.pirq(pirq) <= irq1;
108 --END GENERATE irq1_gen;
109 --irq2_gen : IF I = pirq+1 GENERATE
110 apbo.pirq(pirq+1) <= irq2;
111 -- END GENERATE irq2_gen;
112 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
113 -- apbo.pirq(I) <= '0';
114 -- END GENERATE others_irq;
115 --END GENERATE all_irq_gen;
109
116
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
117 PROCESS(resetn, clk25MHz)
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
124
125 PROCESS(resetn, clk25MHz)--, reset_next_commutation)
126 BEGIN
118 BEGIN
127
119
128 IF resetn = '0' THEN
120 IF resetn = '0' THEN
129 Rdata <= (OTHERS => '0');
121 Rdata <= (OTHERS => '0');
130 r.coarse_time_load <= x"80000000";
122 r.coarse_time_load <= x"80000000";
131 r.ctrl <= x"00000000";
123 r.ctrl <= x"00000000";
132 r.next_commutation <= x"ffffffff";
133 force_tick <= '0';
124 force_tick <= '0';
134 previous_force_tick <= '0';
125 previous_force_tick <= '0';
135 soft_tick <= '0';
126 soft_tick <= '0';
136
127
137 --ELSIF reset_next_commutation = '1' THEN
128 coarsetime_reg_updated <= '0';
138 -- r.next_commutation <= x"ffffffff";
139
129
140 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
130 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
131 coarsetime_reg_updated <= '0';
141
132
133 force_tick <= r.ctrl(0);
142 previous_force_tick <= force_tick;
134 previous_force_tick <= force_tick;
143 force_tick <= r.ctrl(0);
144 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
135 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
145 soft_tick <= '1';
136 soft_tick <= '1';
146 ELSE
137 ELSE
147 soft_tick <= '0';
138 soft_tick <= '0';
148 END IF;
139 END IF;
149
140
150 --APB Write OP
141 --APB Write OP
151 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
142 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
152 CASE apbi.paddr(7 DOWNTO 2) IS
143 CASE apbi.paddr(7 DOWNTO 2) IS
153 WHEN "000000" =>
144 WHEN "000000" =>
154 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
145 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
155 WHEN "000001" =>
146 WHEN "000001" =>
156 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
147 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
157 WHEN "000100" =>
148 coarsetime_reg_updated <= '1';
158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
159 WHEN OTHERS =>
149 WHEN OTHERS =>
160 r.coarse_time_load <= x"00000000";
161 END CASE;
150 END CASE;
162 ELSIF r.ctrl(0) = '1' THEN
151 ELSIF r.ctrl(0) = '1' THEN
163 r.ctrl(0) <= '0';
152 r.ctrl(0) <= '0';
164 END IF;
153 END IF;
165
154
166 --APB READ OP
155 --APB READ OP
167 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
156 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
168 CASE apbi.paddr(7 DOWNTO 2) IS
157 CASE apbi.paddr(7 DOWNTO 2) IS
169 WHEN "000000" =>
158 WHEN "000000" =>
170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
159 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
174 WHEN "000001" =>
160 WHEN "000001" =>
175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
161 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
179 WHEN "000010" =>
162 WHEN "000010" =>
180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
163 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
184 WHEN "000011" =>
164 WHEN "000011" =>
185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
165 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
166 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
189 WHEN "000100" =>
190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
194 WHEN OTHERS =>
167 WHEN OTHERS =>
195 Rdata(31 DOWNTO 0) <= x"00000000";
168 Rdata(31 DOWNTO 0) <= x"00000000";
196 END CASE;
169 END CASE;
197 END IF;
170 END IF;
198
171
199 END IF;
172 END IF;
200 END PROCESS;
173 END PROCESS;
201
174
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
175 apbo.prdata <= Rdata;
176 apbo.pconfig <= pconfig;
177 apbo.pindex <= pindex;
178
203 coarse_time <= r.coarse_time;
179 coarse_time <= r.coarse_time;
204 fine_time <= r.fine_time;
180 fine_time <= r.fine_time;
205 apbo.pconfig <= pconfig;
181 -----------------------------------------------------------------------------
206 apbo.pindex <= pindex;
182
183 coarsetime_reg <= r.coarse_time_load;
184 r.coarse_time <= coarse_time_s;
185 r.fine_time <= fine_time_s;
186 -----------------------------------------------------------------------------
187 -- IN coarsetime_reg_updated
188 -- IN coarsetime_reg
189
190 -- OUT coarse_time_s -- ok
191 -- OUT fine_time_s -- ok
192 -----------------------------------------------------------------------------
193
194 tick <= grspw_tick OR soft_tick;
195
196 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
197 GENERIC MAP (
198 NB_FF_OF_SYNC => 2)
199 PORT MAP (
200 clk_in => clk25MHz,
201 clk_out => clk49_152MHz,
202 rstn => resetn,
203 sin => tick,
204 sout => new_timecode);
205
206 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
207 GENERIC MAP (
208 NB_FF_OF_SYNC => 2)
209 PORT MAP (
210 clk_in => clk25MHz,
211 clk_out => clk49_152MHz,
212 rstn => resetn,
213 sin => coarsetime_reg_updated,
214 sout => new_coarsetime);
215
216 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
217 -- GENERIC MAP (
218 -- NB_FF_OF_SYNC => 2)
219 -- PORT MAP (
220 -- clk_in => clk49_152MHz,
221 -- clk_out => clk25MHz,
222 -- rstn => resetn,
223 -- sin => 9,
224 -- sout => );
225
226 SYNC_FF_1: SYNC_FF
227 GENERIC MAP (
228 NB_FF_OF_SYNC => 2)
229 PORT MAP (
230 clk => clk25MHz,
231 rstn => resetn,
232 A => fine_time_new_49,
233 A_sync => fine_time_new_temp);
234
235 lpp_front_detection_1: lpp_front_detection
236 PORT MAP (
237 clk => clk25MHz,
238 rstn => resetn,
239 sin => fine_time_new_temp,
240 sout => fine_time_new);
241
242 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
243 GENERIC MAP (
244 NB_FF_OF_SYNC => 2)
245 PORT MAP (
246 clk_in => clk49_152MHz,
247 clk_out => clk25MHz,
248 rstn => resetn,
249 sin => coarse_time_new_49,
250 sout => coarse_time_new);
251
252 PROCESS (clk25MHz, resetn)
253 BEGIN -- PROCESS
254 IF resetn = '0' THEN -- asynchronous reset (active low)
255 fine_time_s <= (OTHERS => '0');
256 coarse_time_s <= (OTHERS => '0');
257 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
258 IF fine_time_new = '1' THEN
259 fine_time_s <= fine_time_49;
260 END IF;
261 IF coarse_time_new = '1' THEN
262 coarse_time_s <= coarse_time_49;
263 END IF;
264 END IF;
265 END PROCESS;
266
267 -----------------------------------------------------------------------------
268 -- LFR_TIME_MANAGMENT
269 -----------------------------------------------------------------------------
270 lfr_time_management_1 : lfr_time_management
271 GENERIC MAP (
272 nb_time_code_missing_limit => 60)
273 PORT MAP (
274 clk => clk49_152MHz,
275 rstn => resetn,
276
277 new_timecode => new_timecode,
278 new_coarsetime => new_coarsetime,
279 coarsetime_reg => coarsetime_reg,
280
281 fine_time => fine_time_49,
282 fine_time_new => fine_time_new_49,
283 coarse_time => coarse_time_49,
284 coarse_time_new => coarse_time_new_49);
207
285
208 END Behavioral;
286 END Behavioral;
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@@ -1,267 +1,103
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:14:05 07/02/2012
5 -- Create Date: 11:14:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lfr_time_management - Behavioral
7 -- Module Name: lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.general_purpose.Clk_divider;
24 USE lpp.lpp_lfr_time_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 masterclk : INTEGER := 25000000; -- master clock in Hz
28 nb_time_code_missing_limit : INTEGER := 60
29 timeclk : INTEGER := 49152000; -- 2nd clock in Hz
30 finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter
31 nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state
32 );
29 );
33 PORT (
30 PORT (
34 master_clock : IN STD_LOGIC; --! Clock -- 25MHz
31 clk : IN STD_LOGIC;
35 time_clock : IN STD_LOGIC; --! 2nd Clock -- 49MHz
32 rstn : IN STD_LOGIC;
36 resetn : IN STD_LOGIC; --! Reset
33
37 grspw_tick : IN STD_LOGIC;
34 new_timecode : IN STD_LOGIC; -- transition signal information
38 soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value -- 25MHz
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
39 coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
36 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
37
41 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
42 next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
39 fine_time_new : OUT STD_LOGIC;
43 -- reset_next_commutation : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 irq1 : OUT STD_LOGIC; -- 25MHz
41 coarse_time_new : OUT STD_LOGIC
45 irq2 : OUT STD_LOGIC -- 25MHz
46 );
42 );
47 END lfr_time_management;
43 END lfr_time_management;
48
44
49 ARCHITECTURE Behavioral OF lfr_time_management IS
45 ARCHITECTURE Behavioral OF lfr_time_management IS
50
46
51 SIGNAL resetn_clk_div : STD_LOGIC;
47 SIGNAL counter_clear : STD_LOGIC;
52 SIGNAL clk_div : STD_LOGIC;
48 SIGNAL counter_full : STD_LOGIC;
53 --
54 SIGNAL flag : STD_LOGIC;
55 SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL cpt : INTEGER RANGE 0 TO 100000;
58 SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000;
59 --
60 SIGNAL sirq1 : STD_LOGIC;
61 SIGNAL sirq2 : STD_LOGIC;
62 SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000;
63 SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 SIGNAL p_clk_div : STD_LOGIC;
66 --
67 TYPE state_type IS (auto, slave);
68 SIGNAL state : state_type;
69 TYPE timer_type IS (idle, engaged);
70 SIGNAL commutation_timer : timer_type;
71
49
50 SIGNAL nb_time_code_missing : INTEGER;
51 SIGNAL coarse_time_s : INTEGER;
52
72 BEGIN
53 BEGIN
73
54
74 --*******************************************
55 lpp_counter_1 : lpp_counter
75 -- COMMUTATION TIMER AND INTERRUPT GENERATION
56 GENERIC MAP (
76 PROCESS(master_clock, resetn)
57 nb_wait_period => 750,
77 BEGIN
58 nb_bit_of_data => 16)
59 PORT MAP (
60 clk => clk,
61 rstn => rstn,
62 clear => counter_clear,
63 full => counter_full,
64 data => fine_time,
65 new_data => fine_time_new);
78
66
79 IF resetn = '0' THEN
67 PROCESS (clk, rstn)
80 commutation_timer <= idle;
68 BEGIN -- PROCESS
81 cpt_next_commutation <= 0;
69 IF rstn = '0' THEN -- asynchronous reset (active low)
82 sirq1 <= '0';
70 nb_time_code_missing <= 0;
83 sirq2 <= '0';
71 counter_clear <= '0';
84 latched_next_commutation <= x"ffffffff";
72 coarse_time_s <= 0;
85 p_next_commutation <= (others => '0');
73 coarse_time_new <= '0';
86 p_clk_div <= '0';
74 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
87 ELSIF master_clock'EVENT AND master_clock = '1' THEN
75 IF new_timecode = '1' THEN
88
76 coarse_time_new <= '1';
89 CASE commutation_timer IS
77 IF new_coarsetime = '1' THEN
90
78 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
91 WHEN idle =>
79 ELSE
92 sirq1 <= '0';
80 coarse_time_s <= coarse_time_s + 1;
93 sirq2 <= '0';
81 END IF;
94 IF s_coarse_time = latched_next_commutation THEN
82 nb_time_code_missing <= 0;
95 commutation_timer <= engaged; -- transition to state "engaged"
83 counter_clear <= '1';
96 sirq1 <= '1'; -- start the pulse on sirq1
84 ELSE
97 latched_next_commutation <= x"ffffffff";
85 coarse_time_new <= '0';
98 ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed
86 counter_clear <= '0';
99 latched_next_commutation <= next_commutation; -- latch the value
87 IF counter_full = '1' THEN
88 coarse_time_new <= '1';
89 coarse_time_s <= coarse_time_s + 1;
90 IF nb_time_code_missing = nb_time_code_missing_limit THEN
91 nb_time_code_missing <= nb_time_code_missing_limit;
100 ELSE
92 ELSE
101 commutation_timer <= idle;
93 nb_time_code_missing <= nb_time_code_missing + 1;
102 END IF;
94 END IF;
103
95 END IF;
104 WHEN engaged =>
96 END IF;
105 sirq1 <= '0'; -- stop the pulse on sirq1
106 IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge
107 IF cpt_next_commutation = 65536 THEN
108 cpt_next_commutation <= 0;
109 commutation_timer <= idle;
110 sirq2 <= '1'; -- start the pulse on sirq2
111 ELSE
112 cpt_next_commutation <= cpt_next_commutation + 1;
113 END IF;
114 END IF;
115
116 WHEN OTHERS =>
117 commutation_timer <= idle;
118
119 END CASE;
120
121 p_next_commutation <= next_commutation;
122 p_clk_div <= clk_div;
123
124 END IF;
97 END IF;
125
126 END PROCESS;
98 END PROCESS;
127
99
128 irq1 <= sirq1;
100 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
129 irq2 <= sirq2;
101 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
130 -- reset_next_commutation <= '0';
102
131
132 --
133 --*******************************************
134
135 --**********************
136 -- synchronization stage
137 PROCESS(master_clock, resetn) -- resynchronisation with clk
138 BEGIN
139
140 IF resetn = '0' THEN
141 coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
142
143 ELSIF master_clock'EVENT AND master_clock = '1' THEN
144 coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk
145 END IF;
146
147 END PROCESS;
148 --
149 --**********************
150
151
152 -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC
153 PROCESS(clk_div, resetn) -- JC
154 BEGIN
155
156 IF resetn = '0' THEN
157 flag <= '0';
158 cpt <= 0;
159 secondary_cpt <= 0;
160 s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
161 previous_coarse_time_load <= x"80000000";
162 state <= auto;
163
164 --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN
165 -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
166 -- -- s_coarse_time <= coarse_time_load;
167 -- -- flag <= '0';
168 -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously
169 -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
170 -- --END IF;
171
172 -- cpt <= 0;
173 -- secondary_cpt <= 0;
174 -- state <= slave;
175
176 ELSIF clk_div'EVENT AND clk_div = '1' THEN
177
178 CASE state IS
179
180 WHEN auto =>
181 IF grspw_tick = '1' OR soft_tick = '1' THEN
182 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
183 s_coarse_time <= coarse_time_load;
184 ELSE -- if coarse_time_load has not changed, increment the value autonomously
185 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
186 END IF;
187 flag <= '0';
188 cpt <= 0;
189 secondary_cpt <= 0;
190 state <= slave;
191 ELSE
192 IF cpt = 65535 THEN
193 IF flag = '1' THEN
194 s_coarse_time <= coarse_time_load;
195 flag <= '0';
196 ELSE
197 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
198 END IF;
199 cpt <= 0;
200 secondary_cpt <= secondary_cpt + 1;
201 ELSE
202 cpt <= cpt + 1;
203 END IF;
204 END IF;
205
206 WHEN slave =>
207 IF grspw_tick = '1' OR soft_tick = '1' THEN
208 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
209 s_coarse_time <= coarse_time_load;
210 ELSE -- if coarse_time_load has not changed, increment the value autonomously
211 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
212 END IF;
213 flag <= '0';
214 cpt <= 0;
215 secondary_cpt <= 0;
216 state <= slave;
217 ELSE
218 IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us
219 state <= auto; -- commutation to AUTO state
220 IF flag = '1' THEN
221 s_coarse_time <= coarse_time_load;
222 flag <= '0';
223 ELSE
224 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
225 END IF;
226 cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
227 secondary_cpt <= secondary_cpt + 1;
228 ELSE
229 cpt <= cpt + 1;
230 END IF;
231 END IF;
232
233 WHEN OTHERS =>
234 state <= auto;
235
236 END CASE;
237
238 IF secondary_cpt > 60 THEN
239 s_coarse_time(31) <= '1';
240 END IF;
241
242 IF NOT(previous_coarse_time_load = coarse_time_load) THEN
243 flag <= '1';
244 END IF;
245
246 previous_coarse_time_load <= coarse_time_load;
247
248 END IF;
249
250 END PROCESS;
251
252 fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32));
253
254 -- resetn grspw_tick soft_tick resetn_clk_div
255 -- 0 0 0 0
256 -- 0 0 1 0
257 -- 0 1 0 0
258 -- 0 1 1 0
259 -- 1 0 0 1
260 -- 1 0 1 0
261 -- 1 1 0 0
262 -- 1 1 1 0
263 resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0';
264 Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
265 GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div);
266
267 END Behavioral;
103 END Behavioral;
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@@ -1,83 +1,84
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 13:04:01 07/02/2012
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 library IEEE;
20 LIBRARY IEEE;
21 use IEEE.STD_LOGIC_1164.all;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 library grlib;
22 LIBRARY grlib;
23 use grlib.amba.all;
23 USE grlib.amba.ALL;
24 use grlib.stdlib.all;
24 USE grlib.stdlib.ALL;
25 use grlib.devices.all;
25 USE grlib.devices.ALL;
26
26
27 package lpp_lfr_time_management is
27 PACKAGE lpp_lfr_time_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_TIME_MANAGEMENT
31
31
32 component apb_lfr_time_management is
32 COMPONENT apb_lfr_time_management IS
33
33
34 generic(
34 GENERIC(
35 pindex : integer := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : integer := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : integer := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : integer := 0; --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0
39 masterclk : integer := 25000000; --! master clock in Hz
39 );
40 timeclk : integer := 49152000; --! other clock in Hz
41 finetimeclk : integer := 65536 --! divided clock used for the fine time counter
42 );
43
40
44 Port (
41 PORT (
45 clk25MHz : in STD_LOGIC; --! Clock
42 clk25MHz : IN STD_LOGIC; --! Clock
46 clk49_152MHz : in STD_LOGIC; --! secondary clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
47 resetn : in STD_LOGIC; --! Reset
44 resetn : IN STD_LOGIC; --! Reset
48 grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbi : in apb_slv_in_type; --! APB slave input signals
46 apbi : IN apb_slv_in_type; --! APB slave input signals
50 apbo : out apb_slv_out_type; --! APB slave output signals
47 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 coarse_time : out std_logic_vector(31 downto 0); --! coarse time
48 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
52 fine_time : out std_logic_vector(31 downto 0) --! fine time
49 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 );
50 );
54
51
55 end component;
52 END COMPONENT;
56
53
57 component lfr_time_management is
54 COMPONENT lfr_time_management
55 GENERIC (
56 nb_time_code_missing_limit : INTEGER);
57 PORT (
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 new_timecode : IN STD_LOGIC;
61 new_coarsetime : IN STD_LOGIC;
62 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
64 fine_time_new : OUT STD_LOGIC;
65 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_new : OUT STD_LOGIC
67 );
68 END COMPONENT;
58
69
59 generic (
70 COMPONENT lpp_counter
60 masterclk : integer := 25000000; -- master clock in Hz
71 GENERIC (
61 timeclk : integer := 49152000; -- 2nd clock in Hz
72 nb_wait_period : INTEGER;
62 finetimeclk : integer := 65536; -- divided clock used for the fine time counter
73 nb_bit_of_data : INTEGER);
63 nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state
74 PORT (
64 );
75 clk : IN STD_LOGIC;
65 Port (
76 rstn : IN STD_LOGIC;
66 master_clock : in std_logic; --! Clock
77 clear : IN STD_LOGIC;
67 time_clock : in std_logic; --! 2nd Clock
78 full : OUT STD_LOGIC;
68 resetn : in std_logic; --! Reset
79 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
69 grspw_tick : in std_logic;
80 new_data : OUT STD_LOGIC );
70 soft_tick : in std_logic; --! soft tick, load the coarse_time value
81 END COMPONENT;
71 coarse_time_load : in std_logic_vector(31 downto 0);
72 coarse_time : out std_logic_vector(31 downto 0);
73 fine_time : out std_logic_vector(31 downto 0);
74 next_commutation : in std_logic_vector(31 downto 0);
75 -- reset_next_commutation: out std_logic;
76 irq1 : out std_logic;
77 irq2 : out std_logic
78 );
79
80 end component;
81
82
82 end lpp_lfr_time_management;
83 END lpp_lfr_time_management;
83
84
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@@ -1,3 +1,4
1 lpp_lfr_time_management.vhd
1 lpp_lfr_time_management.vhd
2 lpp_counter.vhd
2 lfr_time_management.vhd
3 lfr_time_management.vhd
3 apb_lfr_time_management.vhd
4 apb_lfr_time_management.vhd
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@@ -1,365 +1,365
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_amba.ALL;
37 USE lpp.lpp_amba.ALL;
38 USE lpp.apb_devices_list.ALL;
38 USE lpp.apb_devices_list.ALL;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_ip IS
45 ENTITY lpp_dma_ip IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
48 hindex : INTEGER := 2
49 );
49 );
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- fifo interface
59 -- fifo interface
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 fifo_empty : IN STD_LOGIC;
61 fifo_empty : IN STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
62 fifo_ren : OUT STD_LOGIC;
63
63
64 -- header
64 -- header
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 header_val : IN STD_LOGIC;
66 header_val : IN STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
67 header_ack : OUT STD_LOGIC;
68
68
69 -- Reg out
69 -- Reg out
70 ready_matrix_f0_0 : OUT STD_LOGIC;
70 ready_matrix_f0_0 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
71 ready_matrix_f0_1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
72 ready_matrix_f1 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
73 ready_matrix_f2 : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
74 error_anticipating_empty_fifo : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
75 error_bad_component_error : OUT STD_LOGIC;
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77
77
78 -- Reg In
78 -- Reg In
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
79 status_ready_matrix_f0_0 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
80 status_ready_matrix_f0_1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
81 status_ready_matrix_f1 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
82 status_ready_matrix_f2 :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
83 status_error_anticipating_empty_fifo :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
84 status_error_bad_component_error :IN STD_LOGIC;
85
85
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
86 config_active_interruption_onNewMatrix : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
87 config_active_interruption_onError : IN STD_LOGIC;
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
91 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 );
92 );
93 END;
93 END;
94
94
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
95 ARCHITECTURE Behavioral OF lpp_dma_ip IS
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL DMAIn : DMA_In_Type;
97 SIGNAL DMAIn : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
98 SIGNAL header_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
99 SIGNAL component_dmai : DMA_In_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
100 SIGNAL DMAOut : DMA_OUt_Type;
101 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
102
102
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 TYPE state_DMAWriteBurst IS (IDLE,
105 TYPE state_DMAWriteBurst IS (IDLE,
106 CHECK_COMPONENT_TYPE,
106 CHECK_COMPONENT_TYPE,
107 TRASH_FIFO,
107 TRASH_FIFO,
108 WAIT_HEADER_ACK,
108 WAIT_HEADER_ACK,
109 SEND_DATA,
109 SEND_DATA,
110 WAIT_DATA_ACK,
110 WAIT_DATA_ACK,
111 CHECK_LENGTH
111 CHECK_LENGTH
112 );
112 );
113 SIGNAL state : state_DMAWriteBurst := IDLE;
113 SIGNAL state : state_DMAWriteBurst;-- := IDLE;
114
114
115 SIGNAL nbSend : INTEGER;
115 -- SIGNAL nbSend : INTEGER;
116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL header_check_ok : STD_LOGIC;
119 SIGNAL header_check_ok : STD_LOGIC;
120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL send_matrix : STD_LOGIC;
121 SIGNAL send_matrix : STD_LOGIC;
122 SIGNAL request : STD_LOGIC;
122 -- SIGNAL request : STD_LOGIC;
123 SIGNAL remaining_data_request : INTEGER;
123 -- SIGNAL remaining_data_request : INTEGER;
124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
127 SIGNAL header_select : STD_LOGIC;
127 SIGNAL header_select : STD_LOGIC;
128
128
129 SIGNAL header_send : STD_LOGIC;
129 SIGNAL header_send : STD_LOGIC;
130 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL header_send_ok : STD_LOGIC;
131 SIGNAL header_send_ok : STD_LOGIC;
132 SIGNAL header_send_ko : STD_LOGIC;
132 SIGNAL header_send_ko : STD_LOGIC;
133
133
134 SIGNAL component_send : STD_LOGIC;
134 SIGNAL component_send : STD_LOGIC;
135 SIGNAL component_send_ok : STD_LOGIC;
135 SIGNAL component_send_ok : STD_LOGIC;
136 SIGNAL component_send_ko : STD_LOGIC;
136 SIGNAL component_send_ko : STD_LOGIC;
137 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
138 SIGNAL fifo_ren_trash : STD_LOGIC;
138 SIGNAL fifo_ren_trash : STD_LOGIC;
139 SIGNAL component_fifo_ren : STD_LOGIC;
139 SIGNAL component_fifo_ren : STD_LOGIC;
140
140
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
143
143
144 BEGIN
144 BEGIN
145
145
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 -- DMA to AHB interface
147 -- DMA to AHB interface
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149
149
150 DMA2AHB_1 : DMA2AHB
150 DMA2AHB_1 : DMA2AHB
151 GENERIC MAP (
151 GENERIC MAP (
152 hindex => hindex,
152 hindex => hindex,
153 vendorid => VENDOR_LPP,
153 vendorid => VENDOR_LPP,
154 deviceid => 11,
154 deviceid => 11,
155 version => 0,
155 version => 0,
156 syncrst => 1,
156 syncrst => 1,
157 boundary => 1) -- FIX 11/01/2013
157 boundary => 1) -- FIX 11/01/2013
158 PORT MAP (
158 PORT MAP (
159 HCLK => HCLK,
159 HCLK => HCLK,
160 HRESETn => HRESETn,
160 HRESETn => HRESETn,
161 DMAIn => DMAIn,
161 DMAIn => DMAIn,
162 DMAOut => DMAOut,
162 DMAOut => DMAOut,
163 AHBIn => AHB_Master_In,
163 AHBIn => AHB_Master_In,
164 AHBOut => AHB_Master_Out);
164 AHBOut => AHB_Master_Out);
165
165
166 debug_reg <= debug_reg_s;
166 debug_reg <= debug_reg_s;
167
167
168 debug_info: PROCESS (HCLK, HRESETn)
168 debug_info: PROCESS (HCLK, HRESETn)
169 BEGIN -- PROCESS debug_info
169 BEGIN -- PROCESS debug_info
170 IF HRESETn = '0' THEN -- asynchronous reset (active low)
170 IF HRESETn = '0' THEN -- asynchronous reset (active low)
171 debug_reg_s <= (OTHERS => '0');
171 debug_reg_s <= (OTHERS => '0');
172 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
172 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
173 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
173 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
174 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
174 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
175 IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF;
175 IF state = TRASH_FIFO THEN debug_reg_s(2) <= '1'; END IF;
176 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
176 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
177 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
177 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
178 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
178 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
179 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
179 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
180
180
181 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
181 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
182 END IF;
182 END IF;
183 END PROCESS debug_info;
183 END PROCESS debug_info;
184
184
185
185
186
186
187
187
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
188 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
189 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
190 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
191 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
192 '0';
192 '0';
193
193
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
194 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
195 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
195 '1' WHEN component_type = "0000" AND component_type_pre = "0000" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
196 '1' WHEN component_type = component_type_pre + "0001" ELSE
197 '0';
197 '0';
198
198
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
199 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
200 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
201 addr_matrix_f1 WHEN matrix_type = "10" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
202 addr_matrix_f2 WHEN matrix_type = "11" ELSE
203 (OTHERS => '0');
203 (OTHERS => '0');
204
204
205 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
206 -- DMA control
206 -- DMA control
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
208 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
209 BEGIN -- PROCESS DMAWriteBurst_p
209 BEGIN -- PROCESS DMAWriteBurst_p
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
210 IF HRESETn = '0' THEN -- asynchronous reset (active low)
211 matrix_type <= (others => '0');
211 matrix_type <= (others => '0');
212 component_type <= (others => '0');
212 component_type <= (others => '0');
213 state <= IDLE;
213 state <= IDLE;
214 header_ack <= '0';
214 header_ack <= '0';
215 ready_matrix_f0_0 <= '0';
215 ready_matrix_f0_0 <= '0';
216 ready_matrix_f0_1 <= '0';
216 ready_matrix_f0_1 <= '0';
217 ready_matrix_f1 <= '0';
217 ready_matrix_f1 <= '0';
218 ready_matrix_f2 <= '0';
218 ready_matrix_f2 <= '0';
219 error_anticipating_empty_fifo <= '0';
219 error_anticipating_empty_fifo <= '0';
220 error_bad_component_error <= '0';
220 error_bad_component_error <= '0';
221 component_type_pre <= "0000";
221 component_type_pre <= "0000";
222 fifo_ren_trash <= '1';
222 fifo_ren_trash <= '1';
223 component_send <= '0';
223 component_send <= '0';
224 address <= (OTHERS => '0');
224 address <= (OTHERS => '0');
225 header_select <= '0';
225 header_select <= '0';
226 header_send <= '0';
226 header_send <= '0';
227 header_data <= (OTHERS => '0');
227 header_data <= (OTHERS => '0');
228 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
228 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
229
229
230 CASE state IS
230 CASE state IS
231 WHEN IDLE =>
231 WHEN IDLE =>
232 matrix_type <= header(1 DOWNTO 0);
232 matrix_type <= header(1 DOWNTO 0);
233 --component_type <= header(5 DOWNTO 2);
233 --component_type <= header(5 DOWNTO 2);
234
234
235 ready_matrix_f0_0 <= '0';
235 ready_matrix_f0_0 <= '0';
236 ready_matrix_f0_1 <= '0';
236 ready_matrix_f0_1 <= '0';
237 ready_matrix_f1 <= '0';
237 ready_matrix_f1 <= '0';
238 ready_matrix_f2 <= '0';
238 ready_matrix_f2 <= '0';
239 error_bad_component_error <= '0';
239 error_bad_component_error <= '0';
240 header_select <= '1';
240 header_select <= '1';
241 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
241 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
242 matrix_type <= header(1 DOWNTO 0);
242 matrix_type <= header(1 DOWNTO 0);
243 component_type <= header(5 DOWNTO 2);
243 component_type <= header(5 DOWNTO 2);
244 component_type_pre <= component_type;
244 component_type_pre <= component_type;
245 state <= CHECK_COMPONENT_TYPE;
245 state <= CHECK_COMPONENT_TYPE;
246 END IF;
246 END IF;
247
247
248 WHEN CHECK_COMPONENT_TYPE =>
248 WHEN CHECK_COMPONENT_TYPE =>
249 IF header_check_ok = '1' THEN
249 IF header_check_ok = '1' THEN
250 header_ack <= '1';
250 header_ack <= '1';
251 --
251 --
252 header_send <= '1';
252 header_send <= '1';
253 IF component_type = "0000" THEN
253 IF component_type = "0000" THEN
254 address <= address_matrix;
254 address <= address_matrix;
255 END IF;
255 END IF;
256 header_data <= header;
256 header_data <= header;
257 --
257 --
258 state <= WAIT_HEADER_ACK;
258 state <= WAIT_HEADER_ACK;
259 ELSE
259 ELSE
260 error_bad_component_error <= '1';
260 error_bad_component_error <= '1';
261 component_type_pre <= "0000";
261 component_type_pre <= "0000";
262 header_ack <= '1';
262 header_ack <= '1';
263 state <= TRASH_FIFO;
263 state <= TRASH_FIFO;
264 END IF;
264 END IF;
265
265
266
266
267 WHEN TRASH_FIFO =>
267 WHEN TRASH_FIFO =>
268 header_ack <= '0';
268 header_ack <= '0';
269 error_bad_component_error <= '0';
269 error_bad_component_error <= '0';
270 error_anticipating_empty_fifo <= '0';
270 error_anticipating_empty_fifo <= '0';
271 IF fifo_empty = '1' THEN
271 IF fifo_empty = '1' THEN
272 state <= IDLE;
272 state <= IDLE;
273 fifo_ren_trash <= '1';
273 fifo_ren_trash <= '1';
274 ELSE
274 ELSE
275 fifo_ren_trash <= '0';
275 fifo_ren_trash <= '0';
276 END IF;
276 END IF;
277
277
278 WHEN WAIT_HEADER_ACK =>
278 WHEN WAIT_HEADER_ACK =>
279 header_ack <= '0';
279 header_ack <= '0';
280 header_send <= '0';
280 header_send <= '0';
281 IF header_send_ko = '1' THEN
281 IF header_send_ko = '1' THEN
282 state <= TRASH_FIFO;
282 state <= TRASH_FIFO;
283 error_anticipating_empty_fifo <= '1';
283 error_anticipating_empty_fifo <= '1';
284 -- TODO : error sending header
284 -- TODO : error sending header
285 ELSIF header_send_ok = '1' THEN
285 ELSIF header_send_ok = '1' THEN
286 header_select <= '0';
286 header_select <= '0';
287 state <= SEND_DATA;
287 state <= SEND_DATA;
288 address <= address + 4;
288 address <= address + 4;
289 END IF;
289 END IF;
290
290
291 WHEN SEND_DATA =>
291 WHEN SEND_DATA =>
292 IF fifo_empty = '1' THEN
292 IF fifo_empty = '1' THEN
293 state <= IDLE;
293 state <= IDLE;
294 IF component_type = "1110" THEN --"1110" -- JC
294 IF component_type = "1110" THEN --"1110" -- JC
295 CASE matrix_type IS
295 CASE matrix_type IS
296 WHEN "00" => ready_matrix_f0_0 <= '1';
296 WHEN "00" => ready_matrix_f0_0 <= '1';
297 WHEN "01" => ready_matrix_f0_1 <= '1';
297 WHEN "01" => ready_matrix_f0_1 <= '1';
298 WHEN "10" => ready_matrix_f1 <= '1';
298 WHEN "10" => ready_matrix_f1 <= '1';
299 WHEN "11" => ready_matrix_f2 <= '1';
299 WHEN "11" => ready_matrix_f2 <= '1';
300 WHEN OTHERS => NULL;
300 WHEN OTHERS => NULL;
301 END CASE;
301 END CASE;
302
302
303 END IF;
303 END IF;
304 ELSE
304 ELSE
305 component_send <= '1';
305 component_send <= '1';
306 address <= address;
306 address <= address;
307 state <= WAIT_DATA_ACK;
307 state <= WAIT_DATA_ACK;
308 END IF;
308 END IF;
309
309
310 WHEN WAIT_DATA_ACK =>
310 WHEN WAIT_DATA_ACK =>
311 component_send <= '0';
311 component_send <= '0';
312 IF component_send_ok = '1' THEN
312 IF component_send_ok = '1' THEN
313 address <= address + 64;
313 address <= address + 64;
314 state <= SEND_DATA;
314 state <= SEND_DATA;
315 ELSIF component_send_ko = '1' THEN
315 ELSIF component_send_ko = '1' THEN
316 error_anticipating_empty_fifo <= '0';
316 error_anticipating_empty_fifo <= '0';
317 state <= TRASH_FIFO;
317 state <= TRASH_FIFO;
318 END IF;
318 END IF;
319
319
320 WHEN CHECK_LENGTH =>
320 WHEN CHECK_LENGTH =>
321 state <= IDLE;
321 state <= IDLE;
322 WHEN OTHERS => NULL;
322 WHEN OTHERS => NULL;
323 END CASE;
323 END CASE;
324
324
325 END IF;
325 END IF;
326 END PROCESS DMAWriteFSM_p;
326 END PROCESS DMAWriteFSM_p;
327
327
328 -----------------------------------------------------------------------------
328 -----------------------------------------------------------------------------
329 -- SEND 1 word by DMA
329 -- SEND 1 word by DMA
330 -----------------------------------------------------------------------------
330 -----------------------------------------------------------------------------
331 lpp_dma_send_1word_1 : lpp_dma_send_1word
331 lpp_dma_send_1word_1 : lpp_dma_send_1word
332 PORT MAP (
332 PORT MAP (
333 HCLK => HCLK,
333 HCLK => HCLK,
334 HRESETn => HRESETn,
334 HRESETn => HRESETn,
335 DMAIn => header_dmai,
335 DMAIn => header_dmai,
336 DMAOut => DMAOut,
336 DMAOut => DMAOut,
337
337
338 send => header_send,
338 send => header_send,
339 address => address,
339 address => address,
340 data => header_data,
340 data => header_data,
341 send_ok => header_send_ok,
341 send_ok => header_send_ok,
342 send_ko => header_send_ko
342 send_ko => header_send_ko
343 );
343 );
344
344
345 -----------------------------------------------------------------------------
345 -----------------------------------------------------------------------------
346 -- SEND 16 word by DMA (in burst mode)
346 -- SEND 16 word by DMA (in burst mode)
347 -----------------------------------------------------------------------------
347 -----------------------------------------------------------------------------
348 lpp_dma_send_16word_1 : lpp_dma_send_16word
348 lpp_dma_send_16word_1 : lpp_dma_send_16word
349 PORT MAP (
349 PORT MAP (
350 HCLK => HCLK,
350 HCLK => HCLK,
351 HRESETn => HRESETn,
351 HRESETn => HRESETn,
352 DMAIn => component_dmai,
352 DMAIn => component_dmai,
353 DMAOut => DMAOut,
353 DMAOut => DMAOut,
354
354
355 send => component_send,
355 send => component_send,
356 address => address,
356 address => address,
357 data => fifo_data,
357 data => fifo_data,
358 ren => component_fifo_ren,
358 ren => component_fifo_ren,
359 send_ok => component_send_ok,
359 send_ok => component_send_ok,
360 send_ko => component_send_ko);
360 send_ko => component_send_ko);
361
361
362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
364
364
365 END Behavioral;
365 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,187 +1,187
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2011, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY ieee;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
23 USE ieee.std_logic_1164.ALL;
24 LIBRARY gaisler;
24 LIBRARY gaisler;
25 USE gaisler.misc.ALL;
25 USE gaisler.misc.ALL;
26 USE gaisler.memctrl.ALL;
26 USE gaisler.memctrl.ALL;
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29 USE techmap.allclkgen.ALL;
29 USE techmap.allclkgen.ALL;
30
30
31
31
32
32
33
33
34 ENTITY ssram_plugin IS
34 ENTITY ssram_plugin IS
35 GENERIC (tech : INTEGER := 0);
35 GENERIC (tech : INTEGER := 0);
36 PORT
36 PORT
37 (
37 (
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 mem_ctrlr_o : IN memory_out_type;
39 mem_ctrlr_o : IN memory_out_type;
40 SSRAM_CLK : OUT STD_LOGIC;
40 SSRAM_CLK : OUT STD_LOGIC;
41 nBWa : OUT STD_LOGIC;
41 nBWa : OUT STD_LOGIC;
42 nBWb : OUT STD_LOGIC;
42 nBWb : OUT STD_LOGIC;
43 nBWc : OUT STD_LOGIC;
43 nBWc : OUT STD_LOGIC;
44 nBWd : OUT STD_LOGIC;
44 nBWd : OUT STD_LOGIC;
45 nBWE : OUT STD_LOGIC;
45 nBWE : OUT STD_LOGIC;
46 nADSC : OUT STD_LOGIC;
46 nADSC : OUT STD_LOGIC;
47 nADSP : OUT STD_LOGIC;
47 nADSP : OUT STD_LOGIC;
48 nADV : OUT STD_LOGIC;
48 nADV : OUT STD_LOGIC;
49 nGW : OUT STD_LOGIC;
49 nGW : OUT STD_LOGIC;
50 nCE1 : OUT STD_LOGIC;
50 nCE1 : OUT STD_LOGIC;
51 CE2 : OUT STD_LOGIC;
51 CE2 : OUT STD_LOGIC;
52 nCE3 : OUT STD_LOGIC;
52 nCE3 : OUT STD_LOGIC;
53 nOE : OUT STD_LOGIC;
53 nOE : OUT STD_LOGIC;
54 MODE : OUT STD_LOGIC;
54 MODE : OUT STD_LOGIC;
55 ZZ : OUT STD_LOGIC
55 ZZ : OUT STD_LOGIC
56 );
56 );
57 END ENTITY;
57 END ENTITY;
58
58
59
59
60
60
61
61
62
62
63
63
64 ARCHITECTURE ar_ssram_plugin OF ssram_plugin IS
64 ARCHITECTURE ar_ssram_plugin OF ssram_plugin IS
65
65
66
66
67 SIGNAL nADSPint : STD_LOGIC := '1';
67 SIGNAL nADSPint : STD_LOGIC := '1';
68 SIGNAL nOEint : STD_LOGIC := '1';
68 SIGNAL nOEint : STD_LOGIC := '1';
69 SIGNAL RAMSN_reg : STD_LOGIC := '1';
69 SIGNAL RAMSN_reg : STD_LOGIC := '1';
70 SIGNAL OEreg : STD_LOGIC := '1';
70 SIGNAL OEreg : STD_LOGIC := '1';
71 SIGNAL nBWaint : STD_LOGIC := '1';
71 SIGNAL nBWaint : STD_LOGIC := '1';
72 SIGNAL nBWbint : STD_LOGIC := '1';
72 SIGNAL nBWbint : STD_LOGIC := '1';
73 SIGNAL nBWcint : STD_LOGIC := '1';
73 SIGNAL nBWcint : STD_LOGIC := '1';
74 SIGNAL nBWdint : STD_LOGIC := '1';
74 SIGNAL nBWdint : STD_LOGIC := '1';
75 SIGNAL nBWEint : STD_LOGIC := '1';
75 SIGNAL nBWEint : STD_LOGIC := '1';
76 SIGNAL nCE1int : STD_LOGIC := '1';
76 SIGNAL nCE1int : STD_LOGIC := '1';
77 SIGNAL CE2int : STD_LOGIC := '0';
77 SIGNAL CE2int : STD_LOGIC := '0';
78 SIGNAL nCE3int : STD_LOGIC := '1';
78 SIGNAL nCE3int : STD_LOGIC := '1';
79
79
80 TYPE stateT IS (idle, st1, st2, st3, st4);
80 TYPE stateT IS (idle, st1, st2, st3, st4);
81 SIGNAL state : stateT;
81 SIGNAL state : stateT;
82
82
83 --SIGNAL nclk : STD_LOGIC;
83 --SIGNAL nclk : STD_LOGIC;
84
84
85 BEGIN
85 BEGIN
86
86
87 PROCESS(clk , mem_ctrlr_o.RAMSN(0))
87 PROCESS(clk , mem_ctrlr_o.RAMSN(0))
88 BEGIN
88 BEGIN
89 IF mem_ctrlr_o.RAMSN(0) = '1' then
89 IF mem_ctrlr_o.RAMSN(0) = '1' then
90 state <= idle;
90 state <= idle;
91 ELSIF clk = '1' and clk'event then
91 ELSIF clk = '1' and clk'event then
92 CASE state IS
92 CASE state IS
93 WHEN idle =>
93 WHEN idle =>
94 state <= st1;
94 state <= st1;
95 WHEN st1 =>
95 WHEN st1 =>
96 state <= st2;
96 state <= st2;
97 WHEN st2 =>
97 WHEN st2 =>
98 state <= st3;
98 state <= st3;
99 WHEN st3 =>
99 WHEN st3 =>
100 state <= st4;
100 state <= st4;
101 WHEN st4 =>
101 WHEN st4 =>
102 state <= st1;
102 state <= st1;
103 END CASE;
103 END CASE;
104 END IF;
104 END IF;
105 END PROCESS;
105 END PROCESS;
106
106
107 --nclk <= NOT clk;
107 --nclk <= NOT clk;
108 ssram_clk_pad : outpad GENERIC MAP (tech => tech)
108 ssram_clk_pad : outpad GENERIC MAP (tech => tech)
109 PORT MAP (SSRAM_CLK, NOT clk);
109 PORT MAP (SSRAM_CLK, NOT clk);
110
110
111
111
112 nBWaint <= mem_ctrlr_o.WRN(3)OR mem_ctrlr_o.ramsn(0);
112 nBWaint <= mem_ctrlr_o.WRN(3)OR mem_ctrlr_o.ramsn(0);
113 nBWa_pad : outpad GENERIC MAP (tech => tech)
113 nBWa_pad : outpad GENERIC MAP (tech => tech)
114 PORT MAP (nBWa, nBWaint);
114 PORT MAP (nBWa, nBWaint);
115
115
116 nBWbint <= mem_ctrlr_o.WRN(2)OR mem_ctrlr_o.ramsn(0);
116 nBWbint <= mem_ctrlr_o.WRN(2)OR mem_ctrlr_o.ramsn(0);
117 nBWb_pad : outpad GENERIC MAP (tech => tech)
117 nBWb_pad : outpad GENERIC MAP (tech => tech)
118 PORT MAP (nBWb, nBWbint);
118 PORT MAP (nBWb, nBWbint);
119
119
120 nBWcint <= mem_ctrlr_o.WRN(1)OR mem_ctrlr_o.ramsn(0);
120 nBWcint <= mem_ctrlr_o.WRN(1)OR mem_ctrlr_o.ramsn(0);
121 nBWc_pad : outpad GENERIC MAP (tech => tech)
121 nBWc_pad : outpad GENERIC MAP (tech => tech)
122 PORT MAP (nBWc, nBWcint);
122 PORT MAP (nBWc, nBWcint);
123
123
124 nBWdint <= mem_ctrlr_o.WRN(0)OR mem_ctrlr_o.ramsn(0);
124 nBWdint <= mem_ctrlr_o.WRN(0)OR mem_ctrlr_o.ramsn(0);
125 nBWd_pad : outpad GENERIC MAP (tech => tech)
125 nBWd_pad : outpad GENERIC MAP (tech => tech)
126 PORT MAP (nBWd, nBWdint);
126 PORT MAP (nBWd, nBWdint);
127
127
128 nBWEint <= mem_ctrlr_o.WRITEN OR mem_ctrlr_o.ramsn(0);
128 nBWEint <= mem_ctrlr_o.WRITEN OR mem_ctrlr_o.ramsn(0);
129 nBWE_pad : outpad GENERIC MAP (tech => tech)
129 nBWE_pad : outpad GENERIC MAP (tech => tech)
130 PORT MAP (nBWE, nBWEint);
130 PORT MAP (nBWE, nBWEint);
131
131
132 nADSC_pad : outpad GENERIC MAP (tech => tech)
132 nADSC_pad : outpad GENERIC MAP (tech => tech)
133 PORT MAP (nADSC, '1');
133 PORT MAP (nADSC, '1');
134
134
135 --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
135 --nADSPint <= not((RAMSN_reg xor mem_ctrlr_o.RAMSN(0)) and RAMSN_reg);
136 nADSPint <= '0' WHEN state = st1 ELSE '1';
136 nADSPint <= '0' WHEN state = st1 ELSE '1';
137
137
138 PROCESS(clk)
138 PROCESS(clk)
139 BEGIN
139 BEGIN
140 IF clk'EVENT AND clk = '1' THEN
140 IF clk'EVENT AND clk = '1' THEN
141 RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
141 RAMSN_reg <= mem_ctrlr_o.RAMSN(0);
142 END IF;
142 END IF;
143 END PROCESS;
143 END PROCESS;
144
144
145 nADSP_pad : outpad GENERIC MAP (tech => tech)
145 nADSP_pad : outpad GENERIC MAP (tech => tech)
146 PORT MAP (nADSP, nADSPint);
146 PORT MAP (nADSP, nADSPint);
147
147
148 nADV_pad : outpad GENERIC MAP (tech => tech)
148 nADV_pad : outpad GENERIC MAP (tech => tech)
149 PORT MAP (nADV, '1');
149 PORT MAP (nADV, '1');
150
150
151 nGW_pad : outpad GENERIC MAP (tech => tech)
151 nGW_pad : outpad GENERIC MAP (tech => tech)
152 PORT MAP (nGW, '1');
152 PORT MAP (nGW, '1');
153
153
154 nCE1int <= nADSPint OR mem_ctrlr_o.address(31) OR (NOT mem_ctrlr_o.address(30)) OR mem_ctrlr_o.address(29) OR mem_ctrlr_o.address(28);
154 nCE1int <= nADSPint OR mem_ctrlr_o.address(31) OR (NOT mem_ctrlr_o.address(30)) OR mem_ctrlr_o.address(29) OR mem_ctrlr_o.address(28);
155 CE2int <= (NOT mem_ctrlr_o.address(27)) AND (NOT mem_ctrlr_o.address(26)) AND (NOT mem_ctrlr_o.address(25)) AND (NOT mem_ctrlr_o.address(24));
155 CE2int <= (NOT mem_ctrlr_o.address(27)) AND (NOT mem_ctrlr_o.address(26)) AND (NOT mem_ctrlr_o.address(25)) AND (NOT mem_ctrlr_o.address(24));
156 nCE3int <= mem_ctrlr_o.address(23) OR mem_ctrlr_o.address(22) OR mem_ctrlr_o.address(21) OR mem_ctrlr_o.address(20);
156 nCE3int <= mem_ctrlr_o.address(23) OR mem_ctrlr_o.address(22) OR mem_ctrlr_o.address(21) OR mem_ctrlr_o.address(20);
157
157
158 nCE1_pad : outpad GENERIC MAP (tech => tech)
158 nCE1_pad : outpad GENERIC MAP (tech => tech)
159 PORT MAP (nCE1, nCE1int);
159 PORT MAP (nCE1, nCE1int);
160
160
161 CE2_pad : outpad GENERIC MAP (tech => tech)
161 CE2_pad : outpad GENERIC MAP (tech => tech)
162 PORT MAP (CE2, CE2int);
162 PORT MAP (CE2, CE2int);
163
163
164 nCE3_pad : outpad GENERIC MAP (tech => tech)
164 nCE3_pad : outpad GENERIC MAP (tech => tech)
165 PORT MAP (nCE3, nCE3int);
165 PORT MAP (nCE3, nCE3int);
166
166
167 nOE_pad : outpad GENERIC MAP (tech => tech)
167 nOE_pad : outpad GENERIC MAP (tech => tech)
168 PORT MAP (nOE, nOEint);
168 PORT MAP (nOE, nOEint);
169
169
170 PROCESS(clk)
170 PROCESS(clk)
171 BEGIN
171 BEGIN
172 IF clk'EVENT AND clk = '1' THEN
172 IF clk'EVENT AND clk = '1' THEN
173 OEreg <= mem_ctrlr_o.OEN;
173 OEreg <= mem_ctrlr_o.OEN;
174 END IF;
174 END IF;
175 END PROCESS;
175 END PROCESS;
176
176
177
177
178 --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
178 --nOEint <= OEreg or mem_ctrlr_o.RAMOEN(0);
179 nOEint <= '0' WHEN state = st2 OR state = st3 OR state = st4 ELSE '1';
179 nOEint <= '0' WHEN state = st2 OR state = st3 OR state = st4 ELSE '1';
180
180
181 MODE_pad : outpad GENERIC MAP (tech => tech)
181 MODE_pad : outpad GENERIC MAP (tech => tech)
182 PORT MAP (MODE, '0');
182 PORT MAP (MODE, '0');
183
183
184 ZZ_pad : outpad GENERIC MAP (tech => tech)
184 ZZ_pad : outpad GENERIC MAP (tech => tech)
185 PORT MAP (ZZ, '0');
185 PORT MAP (ZZ, '0');
186
186
187 END ARCHITECTURE;
187 END ARCHITECTURE; No newline at end of file
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@@ -1,342 +1,344
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_lfr_pkg.ALL;
12 USE lpp.lpp_lfr_pkg.ALL;
13
13
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY grlib;
17 LIBRARY grlib;
18 USE grlib.amba.ALL;
18 USE grlib.amba.ALL;
19 USE grlib.stdlib.ALL;
19 USE grlib.stdlib.ALL;
20 USE grlib.devices.ALL;
20 USE grlib.devices.ALL;
21 USE GRLIB.DMA2AHB_Package.ALL;
21 USE GRLIB.DMA2AHB_Package.ALL;
22
22
23 ENTITY lpp_lfr IS
23 ENTITY lpp_lfr IS
24 GENERIC (
24 GENERIC (
25 Mem_use : INTEGER := use_RAM;
25 Mem_use : INTEGER := use_RAM;
26 nb_burst_available_size : INTEGER := 11;
26 nb_burst_available_size : INTEGER := 11;
27 nb_snapshot_param_size : INTEGER := 11;
27 nb_snapshot_param_size : INTEGER := 11;
28 delta_snapshot_size : INTEGER := 16;
28 delta_snapshot_size : INTEGER := 16;
29 delta_f2_f0_size : INTEGER := 10;
29 delta_f2_f0_size : INTEGER := 10;
30 delta_f2_f1_size : INTEGER := 10;
30 delta_f2_f1_size : INTEGER := 10;
31
31
32 pindex : INTEGER := 4;
32 pindex : INTEGER := 4;
33 paddr : INTEGER := 4;
33 paddr : INTEGER := 4;
34 pmask : INTEGER := 16#fff#;
34 pmask : INTEGER := 16#fff#;
35 pirq_ms : INTEGER := 0;
35 pirq_ms : INTEGER := 0;
36 pirq_wfp : INTEGER := 1;
36 pirq_wfp : INTEGER := 1;
37
37
38 hindex_wfp : INTEGER := 2;
38 hindex_wfp : INTEGER := 2;
39 hindex_ms : INTEGER := 3
39 hindex_ms : INTEGER := 3
40
40
41 );
41 );
42 PORT (
42 PORT (
43 clk : IN STD_LOGIC;
43 clk : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
45 --
45 --
46 sample_B : IN Samples14v(2 DOWNTO 0);
46 sample_B : IN Samples14v(2 DOWNTO 0);
47 sample_E : IN Samples14v(4 DOWNTO 0);
47 sample_E : IN Samples14v(4 DOWNTO 0);
48 sample_val : IN STD_LOGIC;
48 sample_val : IN STD_LOGIC;
49 --
49 --
50 apbi : IN apb_slv_in_type;
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
51 apbo : OUT apb_slv_out_type;
52 --
52 --
53 ahbi_wfp : IN AHB_Mst_In_Type;
53 ahbi_wfp : IN AHB_Mst_In_Type;
54 ahbo_wfp : OUT AHB_Mst_Out_Type;
54 ahbo_wfp : OUT AHB_Mst_Out_Type;
55 --
55 --
56 ahbi_ms : IN AHB_Mst_In_Type;
56 ahbi_ms : IN AHB_Mst_In_Type;
57 ahbo_ms : OUT AHB_Mst_Out_Type;
57 ahbo_ms : OUT AHB_Mst_Out_Type;
58 --
58 --
59 coarse_time_0 : IN STD_LOGIC;
59 coarse_time_0 : IN STD_LOGIC;
60 --
60 --
61 data_shaping_BW : OUT STD_LOGIC
61 data_shaping_BW : OUT STD_LOGIC
62 );
62 );
63 END lpp_lfr;
63 END lpp_lfr;
64
64
65 ARCHITECTURE beh OF lpp_lfr IS
65 ARCHITECTURE beh OF lpp_lfr IS
66 SIGNAL sample : Samples14v(7 DOWNTO 0);
66 SIGNAL sample : Samples14v(7 DOWNTO 0);
67 SIGNAL sample_s : Samples(7 DOWNTO 0);
67 SIGNAL sample_s : Samples(7 DOWNTO 0);
68 --
68 --
69 SIGNAL data_shaping_SP0 : STD_LOGIC;
69 SIGNAL data_shaping_SP0 : STD_LOGIC;
70 SIGNAL data_shaping_SP1 : STD_LOGIC;
70 SIGNAL data_shaping_SP1 : STD_LOGIC;
71 SIGNAL data_shaping_R0 : STD_LOGIC;
71 SIGNAL data_shaping_R0 : STD_LOGIC;
72 SIGNAL data_shaping_R1 : STD_LOGIC;
72 SIGNAL data_shaping_R1 : STD_LOGIC;
73 --
73 --
74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 --
77 --
78 SIGNAL sample_f0_val : STD_LOGIC;
78 SIGNAL sample_f0_val : STD_LOGIC;
79 SIGNAL sample_f1_val : STD_LOGIC;
79 SIGNAL sample_f1_val : STD_LOGIC;
80 SIGNAL sample_f2_val : STD_LOGIC;
80 SIGNAL sample_f2_val : STD_LOGIC;
81 SIGNAL sample_f3_val : STD_LOGIC;
81 SIGNAL sample_f3_val : STD_LOGIC;
82 --
82 --
83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 --
87 --
88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91
91
92 -- SM
92 -- SM
93 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
93 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 SIGNAL ready_matrix_f1 : STD_LOGIC;
95 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 SIGNAL ready_matrix_f2 : STD_LOGIC;
96 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
97 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
98 SIGNAL error_bad_component_error : STD_LOGIC;
98 SIGNAL error_bad_component_error : STD_LOGIC;
99 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
101 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
101 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
104 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
104 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
105 SIGNAL status_error_bad_component_error : STD_LOGIC;
105 SIGNAL status_error_bad_component_error : STD_LOGIC;
106 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
106 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
107 SIGNAL config_active_interruption_onError : STD_LOGIC;
107 SIGNAL config_active_interruption_onError : STD_LOGIC;
108 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112
112
113 -- WFP
113 -- WFP
114 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
114 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
118 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
119 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
119 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
120 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
120 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
121 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
121 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
122 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
122 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
123 SIGNAL enable_f0 : STD_LOGIC;
123 SIGNAL enable_f0 : STD_LOGIC;
124 SIGNAL enable_f1 : STD_LOGIC;
124 SIGNAL enable_f1 : STD_LOGIC;
125 SIGNAL enable_f2 : STD_LOGIC;
125 SIGNAL enable_f2 : STD_LOGIC;
126 SIGNAL enable_f3 : STD_LOGIC;
126 SIGNAL enable_f3 : STD_LOGIC;
127 SIGNAL burst_f0 : STD_LOGIC;
127 SIGNAL burst_f0 : STD_LOGIC;
128 SIGNAL burst_f1 : STD_LOGIC;
128 SIGNAL burst_f1 : STD_LOGIC;
129 SIGNAL burst_f2 : STD_LOGIC;
129 SIGNAL burst_f2 : STD_LOGIC;
130 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
134
134
135 --
135 --
136 SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0);
136 SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0);
137 SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
137 SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
138 SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
138 SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141
141
142 SIGNAL val_f0_wfp : STD_LOGIC;
142 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 SIGNAL val_f1_wfp : STD_LOGIC;
143 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 SIGNAL val_f2_wfp : STD_LOGIC;
144 -- SIGNAL val_f2_wfp : STD_LOGIC;
145 SIGNAL val_f3_wfp : STD_LOGIC;
145 -- SIGNAL val_f3_wfp : STD_LOGIC;
146 BEGIN
146 BEGIN
147
147
148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
149 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
149 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
150
150
151 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
151 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
152 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
152 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
153 END GENERATE all_channel;
153 END GENERATE all_channel;
154
154
155 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
156 lpp_lfr_filter_1 : lpp_lfr_filter
156 lpp_lfr_filter_1 : lpp_lfr_filter
157 GENERIC MAP (
157 GENERIC MAP (
158 Mem_use => Mem_use)
158 Mem_use => Mem_use)
159 PORT MAP (
159 PORT MAP (
160 sample => sample_s,
160 sample => sample_s,
161 sample_val => sample_val,
161 sample_val => sample_val,
162 clk => clk,
162 clk => clk,
163 rstn => rstn,
163 rstn => rstn,
164 data_shaping_SP0 => data_shaping_SP0,
164 data_shaping_SP0 => data_shaping_SP0,
165 data_shaping_SP1 => data_shaping_SP1,
165 data_shaping_SP1 => data_shaping_SP1,
166 data_shaping_R0 => data_shaping_R0,
166 data_shaping_R0 => data_shaping_R0,
167 data_shaping_R1 => data_shaping_R1,
167 data_shaping_R1 => data_shaping_R1,
168 sample_f0_val => sample_f0_val,
168 sample_f0_val => sample_f0_val,
169 sample_f1_val => sample_f1_val,
169 sample_f1_val => sample_f1_val,
170 sample_f2_val => sample_f2_val,
170 sample_f2_val => sample_f2_val,
171 sample_f3_val => sample_f3_val,
171 sample_f3_val => sample_f3_val,
172 sample_f0_wdata => sample_f0_data,
172 sample_f0_wdata => sample_f0_data,
173 sample_f1_wdata => sample_f1_data,
173 sample_f1_wdata => sample_f1_data,
174 sample_f2_wdata => sample_f2_data,
174 sample_f2_wdata => sample_f2_data,
175 sample_f3_wdata => sample_f3_data);
175 sample_f3_wdata => sample_f3_data);
176
176
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178 lpp_top_apbreg_1 : lpp_lfr_apbreg
178 lpp_top_apbreg_1 : lpp_lfr_apbreg
179 GENERIC MAP (
179 GENERIC MAP (
180 nb_burst_available_size => nb_burst_available_size,
180 nb_burst_available_size => nb_burst_available_size,
181 nb_snapshot_param_size => nb_snapshot_param_size,
181 nb_snapshot_param_size => nb_snapshot_param_size,
182 delta_snapshot_size => delta_snapshot_size,
182 delta_snapshot_size => delta_snapshot_size,
183 delta_f2_f0_size => delta_f2_f0_size,
183 delta_f2_f0_size => delta_f2_f0_size,
184 delta_f2_f1_size => delta_f2_f1_size,
184 delta_f2_f1_size => delta_f2_f1_size,
185 pindex => pindex,
185 pindex => pindex,
186 paddr => paddr,
186 paddr => paddr,
187 pmask => pmask,
187 pmask => pmask,
188 pirq_ms => pirq_ms,
188 pirq_ms => pirq_ms,
189 pirq_wfp => pirq_wfp)
189 pirq_wfp => pirq_wfp)
190 PORT MAP (
190 PORT MAP (
191 HCLK => clk,
191 HCLK => clk,
192 HRESETn => rstn,
192 HRESETn => rstn,
193 apbi => apbi,
193 apbi => apbi,
194 apbo => apbo,
194 apbo => apbo,
195
195
196 ready_matrix_f0_0 => ready_matrix_f0_0,
196 ready_matrix_f0_0 => ready_matrix_f0_0,
197 ready_matrix_f0_1 => ready_matrix_f0_1,
197 ready_matrix_f0_1 => ready_matrix_f0_1,
198 ready_matrix_f1 => ready_matrix_f1,
198 ready_matrix_f1 => ready_matrix_f1,
199 ready_matrix_f2 => ready_matrix_f2,
199 ready_matrix_f2 => ready_matrix_f2,
200 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
200 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
201 error_bad_component_error => error_bad_component_error,
201 error_bad_component_error => error_bad_component_error,
202 debug_reg => debug_reg,
202 debug_reg => debug_reg,
203 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
203 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
204 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
204 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
205 status_ready_matrix_f1 => status_ready_matrix_f1,
205 status_ready_matrix_f1 => status_ready_matrix_f1,
206 status_ready_matrix_f2 => status_ready_matrix_f2,
206 status_ready_matrix_f2 => status_ready_matrix_f2,
207 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
207 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
208 status_error_bad_component_error => status_error_bad_component_error,
208 status_error_bad_component_error => status_error_bad_component_error,
209 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
209 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
210 config_active_interruption_onError => config_active_interruption_onError,
210 config_active_interruption_onError => config_active_interruption_onError,
211 addr_matrix_f0_0 => addr_matrix_f0_0,
211 addr_matrix_f0_0 => addr_matrix_f0_0,
212 addr_matrix_f0_1 => addr_matrix_f0_1,
212 addr_matrix_f0_1 => addr_matrix_f0_1,
213 addr_matrix_f1 => addr_matrix_f1,
213 addr_matrix_f1 => addr_matrix_f1,
214 addr_matrix_f2 => addr_matrix_f2,
214 addr_matrix_f2 => addr_matrix_f2,
215
215
216 status_full => status_full,
216 status_full => status_full,
217 status_full_ack => status_full_ack,
217 status_full_ack => status_full_ack,
218 status_full_err => status_full_err,
218 status_full_err => status_full_err,
219 status_new_err => status_new_err,
219 status_new_err => status_new_err,
220 data_shaping_BW => data_shaping_BW,
220 data_shaping_BW => data_shaping_BW,
221 data_shaping_SP0 => data_shaping_SP0,
221 data_shaping_SP0 => data_shaping_SP0,
222 data_shaping_SP1 => data_shaping_SP1,
222 data_shaping_SP1 => data_shaping_SP1,
223 data_shaping_R0 => data_shaping_R0,
223 data_shaping_R0 => data_shaping_R0,
224 data_shaping_R1 => data_shaping_R1,
224 data_shaping_R1 => data_shaping_R1,
225 delta_snapshot => delta_snapshot,
225 delta_snapshot => delta_snapshot,
226 delta_f2_f1 => delta_f2_f1,
226 delta_f2_f1 => delta_f2_f1,
227 delta_f2_f0 => delta_f2_f0,
227 delta_f2_f0 => delta_f2_f0,
228 nb_burst_available => nb_burst_available,
228 nb_burst_available => nb_burst_available,
229 nb_snapshot_param => nb_snapshot_param,
229 nb_snapshot_param => nb_snapshot_param,
230 enable_f0 => enable_f0,
230 enable_f0 => enable_f0,
231 enable_f1 => enable_f1,
231 enable_f1 => enable_f1,
232 enable_f2 => enable_f2,
232 enable_f2 => enable_f2,
233 enable_f3 => enable_f3,
233 enable_f3 => enable_f3,
234 burst_f0 => burst_f0,
234 burst_f0 => burst_f0,
235 burst_f1 => burst_f1,
235 burst_f1 => burst_f1,
236 burst_f2 => burst_f2,
236 burst_f2 => burst_f2,
237 addr_data_f0 => addr_data_f0,
237 addr_data_f0 => addr_data_f0,
238 addr_data_f1 => addr_data_f1,
238 addr_data_f1 => addr_data_f1,
239 addr_data_f2 => addr_data_f2,
239 addr_data_f2 => addr_data_f2,
240 addr_data_f3 => addr_data_f3);
240 addr_data_f3 => addr_data_f3);
241
241
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 lpp_waveform_1: lpp_waveform
243 lpp_waveform_1: lpp_waveform
244 GENERIC MAP (
244 GENERIC MAP (
245 hindex => hindex_wfp,
245 hindex => hindex_wfp,
246 tech => inferred,
246 tech => inferred,
247 data_size => 160,
247 data_size => 160,
248 nb_burst_available_size => nb_burst_available_size,
248 nb_burst_available_size => nb_burst_available_size,
249 nb_snapshot_param_size => nb_snapshot_param_size,
249 nb_snapshot_param_size => nb_snapshot_param_size,
250 delta_snapshot_size => delta_snapshot_size,
250 delta_snapshot_size => delta_snapshot_size,
251 delta_f2_f0_size => delta_f2_f0_size,
251 delta_f2_f0_size => delta_f2_f0_size,
252 delta_f2_f1_size => delta_f2_f1_size)
252 delta_f2_f1_size => delta_f2_f1_size)
253 PORT MAP (
253 PORT MAP (
254 clk => clk,
254 clk => clk,
255 rstn => rstn,
255 rstn => rstn,
256 AHB_Master_In => ahbi_wfp,
256 AHB_Master_In => ahbi_wfp,
257 AHB_Master_Out => ahbo_wfp,
257 AHB_Master_Out => ahbo_wfp,
258 coarse_time_0 => coarse_time_0,
258 coarse_time_0 => coarse_time_0,
259
259
260 delta_snapshot => delta_snapshot,
260 delta_snapshot => delta_snapshot,
261 delta_f2_f1 => delta_f2_f1,
261 delta_f2_f1 => delta_f2_f1,
262 delta_f2_f0 => delta_f2_f0,
262 delta_f2_f0 => delta_f2_f0,
263 enable_f0 => enable_f0,
263 enable_f0 => enable_f0,
264 enable_f1 => enable_f1,
264 enable_f1 => enable_f1,
265 enable_f2 => enable_f2,
265 enable_f2 => enable_f2,
266 enable_f3 => enable_f3,
266 enable_f3 => enable_f3,
267 burst_f0 => burst_f0,
267 burst_f0 => burst_f0,
268 burst_f1 => burst_f1,
268 burst_f1 => burst_f1,
269 burst_f2 => burst_f2,
269 burst_f2 => burst_f2,
270 nb_burst_available => nb_burst_available,
270 nb_burst_available => nb_burst_available,
271 nb_snapshot_param => nb_snapshot_param,
271 nb_snapshot_param => nb_snapshot_param,
272 status_full => status_full,
272 status_full => status_full,
273 status_full_ack => status_full_ack,
273 status_full_ack => status_full_ack,
274 status_full_err => status_full_err,
274 status_full_err => status_full_err,
275 status_new_err => status_new_err,
275 status_new_err => status_new_err,
276 addr_data_f0 => addr_data_f0,
276 addr_data_f0 => addr_data_f0,
277 addr_data_f1 => addr_data_f1,
277 addr_data_f1 => addr_data_f1,
278 addr_data_f2 => addr_data_f2,
278 addr_data_f2 => addr_data_f2,
279 addr_data_f3 => addr_data_f3,
279 addr_data_f3 => addr_data_f3,
280
280
281 data_f0_in => data_f0_wfp,
281 data_f0_in => data_f0_wfp,
282 data_f1_in => data_f1_wfp,
282 data_f1_in => data_f1_wfp,
283 data_f2_in => data_f2_wfp,
283 data_f2_in => data_f2_wfp,
284 data_f3_in => data_f3_wfp,
284 data_f3_in => data_f3_wfp,
285 data_f0_in_valid => sample_f0_val,
285 data_f0_in_valid => sample_f0_val,
286 data_f1_in_valid => sample_f1_val,
286 data_f1_in_valid => sample_f1_val,
287 data_f2_in_valid => sample_f2_val,
287 data_f2_in_valid => sample_f2_val,
288 data_f3_in_valid => sample_f3_val);
288 data_f3_in_valid => sample_f3_val);
289
289
290 time_info <= (others => '0');
291
290 data_f0_wfp <= sample_f0_data & time_info;
292 data_f0_wfp <= sample_f0_data & time_info;
291 data_f1_wfp <= sample_f1_data & time_info;
293 data_f1_wfp <= sample_f1_data & time_info;
292 data_f2_wfp <= sample_f2_data & time_info;
294 data_f2_wfp <= sample_f2_data & time_info;
293 data_f3_wfp <= sample_f3_data & time_info;
295 data_f3_wfp <= sample_f3_data & time_info;
294
296
295 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
296 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
298 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
297 NOT(sample_f0_val) & NOT(sample_f0_val) ;
299 NOT(sample_f0_val) & NOT(sample_f0_val) ;
298 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
300 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
299 NOT(sample_f1_val) & NOT(sample_f1_val) ;
301 NOT(sample_f1_val) & NOT(sample_f1_val) ;
300 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
302 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
301 NOT(sample_f3_val) & NOT(sample_f3_val) ;
303 NOT(sample_f3_val) & NOT(sample_f3_val) ;
302
304
303 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
305 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
304 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
306 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
305 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
307 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
306 -----------------------------------------------------------------------------
308 -----------------------------------------------------------------------------
307 lpp_lfr_ms_1: lpp_lfr_ms
309 lpp_lfr_ms_1: lpp_lfr_ms
308 GENERIC MAP (
310 GENERIC MAP (
309 hindex => hindex_ms)
311 hindex => hindex_ms)
310 PORT MAP (
312 PORT MAP (
311 clk => clk,
313 clk => clk,
312 rstn => rstn,
314 rstn => rstn,
313 sample_f0_wen => sample_f0_wen,
315 sample_f0_wen => sample_f0_wen,
314 sample_f0_wdata => sample_f0_wdata,
316 sample_f0_wdata => sample_f0_wdata,
315 sample_f1_wen => sample_f1_wen,
317 sample_f1_wen => sample_f1_wen,
316 sample_f1_wdata => sample_f1_wdata,
318 sample_f1_wdata => sample_f1_wdata,
317 sample_f3_wen => sample_f3_wen,
319 sample_f3_wen => sample_f3_wen,
318 sample_f3_wdata => sample_f3_wdata,
320 sample_f3_wdata => sample_f3_wdata,
319 AHB_Master_In => ahbi_ms,
321 AHB_Master_In => ahbi_ms,
320 AHB_Master_Out => ahbo_ms,
322 AHB_Master_Out => ahbo_ms,
321
323
322 ready_matrix_f0_0 => ready_matrix_f0_0,
324 ready_matrix_f0_0 => ready_matrix_f0_0,
323 ready_matrix_f0_1 => ready_matrix_f0_1,
325 ready_matrix_f0_1 => ready_matrix_f0_1,
324 ready_matrix_f1 => ready_matrix_f1,
326 ready_matrix_f1 => ready_matrix_f1,
325 ready_matrix_f2 => ready_matrix_f2,
327 ready_matrix_f2 => ready_matrix_f2,
326 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
327 error_bad_component_error => error_bad_component_error,
329 error_bad_component_error => error_bad_component_error,
328 debug_reg => debug_reg,
330 debug_reg => debug_reg,
329 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
330 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
331 status_ready_matrix_f1 => status_ready_matrix_f1,
333 status_ready_matrix_f1 => status_ready_matrix_f1,
332 status_ready_matrix_f2 => status_ready_matrix_f2,
334 status_ready_matrix_f2 => status_ready_matrix_f2,
333 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
334 status_error_bad_component_error => status_error_bad_component_error,
336 status_error_bad_component_error => status_error_bad_component_error,
335 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
336 config_active_interruption_onError => config_active_interruption_onError,
338 config_active_interruption_onError => config_active_interruption_onError,
337 addr_matrix_f0_0 => addr_matrix_f0_0,
339 addr_matrix_f0_0 => addr_matrix_f0_0,
338 addr_matrix_f0_1 => addr_matrix_f0_1,
340 addr_matrix_f0_1 => addr_matrix_f0_1,
339 addr_matrix_f1 => addr_matrix_f1,
341 addr_matrix_f1 => addr_matrix_f1,
340 addr_matrix_f2 => addr_matrix_f2);
342 addr_matrix_f2 => addr_matrix_f2);
341
343
342 END beh; No newline at end of file
344 END beh;
Show file before | Show file after | Hide comments
@@ -1,385 +1,385
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11
11
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 LIBRARY grlib;
15 LIBRARY grlib;
16 USE grlib.amba.ALL;
16 USE grlib.amba.ALL;
17 USE grlib.stdlib.ALL;
17 USE grlib.stdlib.ALL;
18 USE grlib.devices.ALL;
18 USE grlib.devices.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
20
20
21 ENTITY lpp_lfr_filter IS
21 ENTITY lpp_lfr_filter IS
22 GENERIC(
22 GENERIC(
23 Mem_use : INTEGER := use_RAM
23 Mem_use : INTEGER := use_RAM
24 );
24 );
25 PORT (
25 PORT (
26 sample : IN Samples(7 DOWNTO 0);
26 sample : IN Samples(7 DOWNTO 0);
27 sample_val : IN STD_LOGIC;
27 sample_val : IN STD_LOGIC;
28 --
28 --
29 clk : IN STD_LOGIC;
29 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
31 --
31 --
32 data_shaping_SP0 : IN STD_LOGIC;
32 data_shaping_SP0 : IN STD_LOGIC;
33 data_shaping_SP1 : IN STD_LOGIC;
33 data_shaping_SP1 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
36 --
36 --
37 sample_f0_val : OUT STD_LOGIC;
37 sample_f0_val : OUT STD_LOGIC;
38 sample_f1_val : OUT STD_LOGIC;
38 sample_f1_val : OUT STD_LOGIC;
39 sample_f2_val : OUT STD_LOGIC;
39 sample_f2_val : OUT STD_LOGIC;
40 sample_f3_val : OUT STD_LOGIC;
40 sample_f3_val : OUT STD_LOGIC;
41 --
41 --
42 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
42 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
43 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
43 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
44 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
44 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
46 );
46 );
47 END lpp_lfr_filter;
47 END lpp_lfr_filter;
48
48
49 ARCHITECTURE tb OF lpp_lfr_filter IS
49 ARCHITECTURE tb OF lpp_lfr_filter IS
50
50
51 COMPONENT Downsampling
51 COMPONENT Downsampling
52 GENERIC (
52 GENERIC (
53 ChanelCount : INTEGER;
53 ChanelCount : INTEGER;
54 SampleSize : INTEGER;
54 SampleSize : INTEGER;
55 DivideParam : INTEGER);
55 DivideParam : INTEGER);
56 PORT (
56 PORT (
57 clk : IN STD_LOGIC;
57 clk : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
59 sample_in_val : IN STD_LOGIC;
59 sample_in_val : IN STD_LOGIC;
60 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
60 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
61 sample_out_val : OUT STD_LOGIC;
61 sample_out_val : OUT STD_LOGIC;
62 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
62 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
63 END COMPONENT;
63 END COMPONENT;
64
64
65 -----------------------------------------------------------------------------
65 -----------------------------------------------------------------------------
66 CONSTANT ChanelCount : INTEGER := 8;
66 CONSTANT ChanelCount : INTEGER := 8;
67
67
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 SIGNAL sample_val_delay : STD_LOGIC;
69 SIGNAL sample_val_delay : STD_LOGIC;
70 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
71 CONSTANT Coef_SZ : INTEGER := 9;
71 CONSTANT Coef_SZ : INTEGER := 9;
72 CONSTANT CoefCntPerCel : INTEGER := 6;
72 CONSTANT CoefCntPerCel : INTEGER := 6;
73 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT CoefPerCel : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
75
75
76 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 --
80 --
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
83 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
84 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
84 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
85 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
86 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
87 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
87 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
88 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
88 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
89 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
89 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
90 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
90 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
91 -----------------------------------------------------------------------------
91 -----------------------------------------------------------------------------
92 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
92 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
93 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
93 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
94 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
95 -- SIGNAL sample_f0_val : STD_LOGIC;
95 -- SIGNAL sample_f0_val : STD_LOGIC;
96 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
96 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
97 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
97 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
98 --
98 --
99 -- SIGNAL sample_f1_val : STD_LOGIC;
99 -- SIGNAL sample_f1_val : STD_LOGIC;
100 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
100 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
101 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
101 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
102 --
102 --
103 -- SIGNAL sample_f2_val : STD_LOGIC;
103 -- SIGNAL sample_f2_val : STD_LOGIC;
104 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
104 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
105 --
105 --
106 -- SIGNAL sample_f3_val : STD_LOGIC;
106 -- SIGNAL sample_f3_val : STD_LOGIC;
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
110 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115
115
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
120
121 SIGNAL sample_f0_val_s : STD_LOGIC;
121 SIGNAL sample_f0_val_s : STD_LOGIC;
122 SIGNAL sample_f1_val_s : STD_LOGIC;
122 SIGNAL sample_f1_val_s : STD_LOGIC;
123 BEGIN
123 BEGIN
124
124
125 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 PROCESS (clk, rstn)
126 PROCESS (clk, rstn)
127 BEGIN -- PROCESS
127 BEGIN -- PROCESS
128 IF rstn = '0' THEN -- asynchronous reset (active low)
128 IF rstn = '0' THEN -- asynchronous reset (active low)
129 sample_val_delay <= '0';
129 sample_val_delay <= '0';
130 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
130 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
131 sample_val_delay <= sample_val;
131 sample_val_delay <= sample_val;
132 END IF;
132 END IF;
133 END PROCESS;
133 END PROCESS;
134
134
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
136 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
137 SampleLoop : FOR j IN 0 TO 15 GENERATE
137 SampleLoop : FOR j IN 0 TO 15 GENERATE
138 sample_filter_in(i, j) <= sample(i)(j);
138 sample_filter_in(i, j) <= sample(i)(j);
139 END GENERATE;
139 END GENERATE;
140
140
141 sample_filter_in(i, 16) <= sample(i)(15);
141 sample_filter_in(i, 16) <= sample(i)(15);
142 sample_filter_in(i, 17) <= sample(i)(15);
142 sample_filter_in(i, 17) <= sample(i)(15);
143 END GENERATE;
143 END GENERATE;
144
144
145 coefs_v2 <= CoefsInitValCst_v2;
145 coefs_v2 <= CoefsInitValCst_v2;
146
146
147 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
147 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
148 GENERIC MAP (
148 GENERIC MAP (
149 tech => 0,
149 tech => 0,
150 Mem_use => Mem_use, -- use_RAM
150 Mem_use => Mem_use, -- use_RAM
151 Sample_SZ => 18,
151 Sample_SZ => 18,
152 Coef_SZ => Coef_SZ,
152 Coef_SZ => Coef_SZ,
153 Coef_Nb => 25,
153 Coef_Nb => 25,
154 Coef_sel_SZ => 5,
154 Coef_sel_SZ => 5,
155 Cels_count => Cels_count,
155 Cels_count => Cels_count,
156 ChanelsCount => ChanelCount)
156 ChanelsCount => ChanelCount)
157 PORT MAP (
157 PORT MAP (
158 rstn => rstn,
158 rstn => rstn,
159 clk => clk,
159 clk => clk,
160 virg_pos => 7,
160 virg_pos => 7,
161 coefs => coefs_v2,
161 coefs => coefs_v2,
162 sample_in_val => sample_val_delay,
162 sample_in_val => sample_val_delay,
163 sample_in => sample_filter_in,
163 sample_in => sample_filter_in,
164 sample_out_val => sample_filter_v2_out_val,
164 sample_out_val => sample_filter_v2_out_val,
165 sample_out => sample_filter_v2_out);
165 sample_out => sample_filter_v2_out);
166
166
167 -----------------------------------------------------------------------------
167 -----------------------------------------------------------------------------
168 -- DATA_SHAPING
168 -- DATA_SHAPING
169 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
170 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
170 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
171 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
171 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
172 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
172 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
173 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
173 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
174 END GENERATE all_data_shaping_in_loop;
174 END GENERATE all_data_shaping_in_loop;
175
175
176 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
176 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
177 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
177 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
178
178
179 PROCESS (clk, rstn)
179 PROCESS (clk, rstn)
180 BEGIN -- PROCESS
180 BEGIN -- PROCESS
181 IF rstn = '0' THEN -- asynchronous reset (active low)
181 IF rstn = '0' THEN -- asynchronous reset (active low)
182 sample_data_shaping_out_val <= '0';
182 sample_data_shaping_out_val <= '0';
183 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
183 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
184 sample_data_shaping_out_val <= sample_filter_v2_out_val;
184 sample_data_shaping_out_val <= sample_filter_v2_out_val;
185 END IF;
185 END IF;
186 END PROCESS;
186 END PROCESS;
187
187
188 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
188 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
189 PROCESS (clk, rstn)
189 PROCESS (clk, rstn)
190 BEGIN
190 BEGIN
191 IF rstn = '0' THEN
191 IF rstn = '0' THEN
192 sample_data_shaping_out(0, j) <= '0';
192 sample_data_shaping_out(0, j) <= '0';
193 sample_data_shaping_out(1, j) <= '0';
193 sample_data_shaping_out(1, j) <= '0';
194 sample_data_shaping_out(2, j) <= '0';
194 sample_data_shaping_out(2, j) <= '0';
195 sample_data_shaping_out(3, j) <= '0';
195 sample_data_shaping_out(3, j) <= '0';
196 sample_data_shaping_out(4, j) <= '0';
196 sample_data_shaping_out(4, j) <= '0';
197 sample_data_shaping_out(5, j) <= '0';
197 sample_data_shaping_out(5, j) <= '0';
198 sample_data_shaping_out(6, j) <= '0';
198 sample_data_shaping_out(6, j) <= '0';
199 sample_data_shaping_out(7, j) <= '0';
199 sample_data_shaping_out(7, j) <= '0';
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
201 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
202 IF data_shaping_SP0 = '1' THEN
202 IF data_shaping_SP0 = '1' THEN
203 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
203 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
204 ELSE
204 ELSE
205 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
205 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
206 END IF;
206 END IF;
207 IF data_shaping_SP1 = '1' THEN
207 IF data_shaping_SP1 = '1' THEN
208 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
208 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
209 ELSE
209 ELSE
210 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
210 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
211 END IF;
211 END IF;
212 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
212 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
213 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
213 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
214 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
214 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
215 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
215 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
216 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
216 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
217 END IF;
217 END IF;
218 END PROCESS;
218 END PROCESS;
219 END GENERATE;
219 END GENERATE;
220
220
221 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
221 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
222 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
222 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
223 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
223 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
224 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
224 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
225 END GENERATE;
225 END GENERATE;
226 END GENERATE;
226 END GENERATE;
227 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
228 -- F0 -- @24.576 kHz
228 -- F0 -- @24.576 kHz
229 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
230 Downsampling_f0 : Downsampling
230 Downsampling_f0 : Downsampling
231 GENERIC MAP (
231 GENERIC MAP (
232 ChanelCount => 8,
232 ChanelCount => 8,
233 SampleSize => 16,
233 SampleSize => 16,
234 DivideParam => 4)
234 DivideParam => 4)
235 PORT MAP (
235 PORT MAP (
236 clk => clk,
236 clk => clk,
237 rstn => rstn,
237 rstn => rstn,
238 sample_in_val => sample_filter_v2_out_val_s,
238 sample_in_val => sample_filter_v2_out_val_s,
239 sample_in => sample_filter_v2_out_s,
239 sample_in => sample_filter_v2_out_s,
240 sample_out_val => sample_f0_val_s,
240 sample_out_val => sample_f0_val_s,
241 sample_out => sample_f0);
241 sample_out => sample_f0);
242
242
243 sample_f0_val <= sample_f0_val_s;
243 sample_f0_val <= sample_f0_val_s;
244
244
245 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
245 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
246 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
246 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
247 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
247 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
248 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
248 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
249 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
249 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
250 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
250 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
251 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
251 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
252 END GENERATE all_bit_sample_f0;
252 END GENERATE all_bit_sample_f0;
253
253
254 --sample_f0_wen <= NOT(sample_f0_val) &
254 --sample_f0_wen <= NOT(sample_f0_val) &
255 -- NOT(sample_f0_val) &
255 -- NOT(sample_f0_val) &
256 -- NOT(sample_f0_val) &
256 -- NOT(sample_f0_val) &
257 -- NOT(sample_f0_val) &
257 -- NOT(sample_f0_val) &
258 -- NOT(sample_f0_val) &
258 -- NOT(sample_f0_val) &
259 -- NOT(sample_f0_val);
259 -- NOT(sample_f0_val);
260
260
261 -----------------------------------------------------------------------------
261 -----------------------------------------------------------------------------
262 -- F1 -- @4096 Hz
262 -- F1 -- @4096 Hz
263 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
264 Downsampling_f1 : Downsampling
264 Downsampling_f1 : Downsampling
265 GENERIC MAP (
265 GENERIC MAP (
266 ChanelCount => 8,
266 ChanelCount => 8,
267 SampleSize => 16,
267 SampleSize => 16,
268 DivideParam => 6)
268 DivideParam => 6)
269 PORT MAP (
269 PORT MAP (
270 clk => clk,
270 clk => clk,
271 rstn => rstn,
271 rstn => rstn,
272 sample_in_val => sample_f0_val_s ,
272 sample_in_val => sample_f0_val_s ,
273 sample_in => sample_f0,
273 sample_in => sample_f0,
274 sample_out_val => sample_f1_val_s,
274 sample_out_val => sample_f1_val_s,
275 sample_out => sample_f1);
275 sample_out => sample_f1);
276
276
277 sample_f1_val <= sample_f1_val_s;
277 sample_f1_val <= sample_f1_val_s;
278
278
279 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
279 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
280 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
280 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
281 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
281 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
282 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
282 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
283 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
283 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
284 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
284 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
285 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
285 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
286 END GENERATE all_bit_sample_f1;
286 END GENERATE all_bit_sample_f1;
287
287
288 --sample_f1_wen <= NOT(sample_f1_val) &
288 --sample_f1_wen <= NOT(sample_f1_val) &
289 -- NOT(sample_f1_val) &
289 -- NOT(sample_f1_val) &
290 -- NOT(sample_f1_val) &
290 -- NOT(sample_f1_val) &
291 -- NOT(sample_f1_val) &
291 -- NOT(sample_f1_val) &
292 -- NOT(sample_f1_val) &
292 -- NOT(sample_f1_val) &
293 -- NOT(sample_f1_val);
293 -- NOT(sample_f1_val);
294
294
295 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
296 -- F2 -- @256 Hz
296 -- F2 -- @256 Hz
297 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
298 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
298 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
299 sample_f0_s(0, I) <= sample_f0(0, I); -- V
299 sample_f0_s(0, I) <= sample_f0(0, I); -- V
300 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
300 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
301 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
301 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
302 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
302 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
303 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
303 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
304 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
304 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
305 END GENERATE all_bit_sample_f0_s;
305 END GENERATE all_bit_sample_f0_s;
306
306
307 Downsampling_f2 : Downsampling
307 Downsampling_f2 : Downsampling
308 GENERIC MAP (
308 GENERIC MAP (
309 ChanelCount => 6,
309 ChanelCount => 6,
310 SampleSize => 16,
310 SampleSize => 16,
311 DivideParam => 96)
311 DivideParam => 96)
312 PORT MAP (
312 PORT MAP (
313 clk => clk,
313 clk => clk,
314 rstn => rstn,
314 rstn => rstn,
315 sample_in_val => sample_f0_val_s ,
315 sample_in_val => sample_f0_val_s ,
316 sample_in => sample_f0_s,
316 sample_in => sample_f0_s,
317 sample_out_val => sample_f2_val,
317 sample_out_val => sample_f2_val,
318 sample_out => sample_f2);
318 sample_out => sample_f2);
319
319
320 --sample_f2_wen <= NOT(sample_f2_val) &
320 --sample_f2_wen <= NOT(sample_f2_val) &
321 -- NOT(sample_f2_val) &
321 -- NOT(sample_f2_val) &
322 -- NOT(sample_f2_val) &
322 -- NOT(sample_f2_val) &
323 -- NOT(sample_f2_val) &
323 -- NOT(sample_f2_val) &
324 -- NOT(sample_f2_val) &
324 -- NOT(sample_f2_val) &
325 -- NOT(sample_f2_val);
325 -- NOT(sample_f2_val);
326
326
327 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
327 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
328 sample_f2_wdata_s(I) <= sample_f2(0, I);
328 sample_f2_wdata_s(I) <= sample_f2(0, I);
329 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
329 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
330 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
330 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
331 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
331 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
332 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
332 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
333 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
333 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
334 END GENERATE all_bit_sample_f2;
334 END GENERATE all_bit_sample_f2;
335
335
336 -----------------------------------------------------------------------------
336 -----------------------------------------------------------------------------
337 -- F3 -- @16 Hz
337 -- F3 -- @16 Hz
338 -----------------------------------------------------------------------------
338 -----------------------------------------------------------------------------
339 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
339 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
340 sample_f1_s(0, I) <= sample_f1(0, I); -- V
340 sample_f1_s(0, I) <= sample_f1(0, I); -- V
341 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
341 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
342 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
342 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
343 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
343 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
344 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
344 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
345 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
345 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
346 END GENERATE all_bit_sample_f1_s;
346 END GENERATE all_bit_sample_f1_s;
347
347
348 Downsampling_f3 : Downsampling
348 Downsampling_f3 : Downsampling
349 GENERIC MAP (
349 GENERIC MAP (
350 ChanelCount => 6,
350 ChanelCount => 6,
351 SampleSize => 16,
351 SampleSize => 16,
352 DivideParam => 256)
352 DivideParam => 256)
353 PORT MAP (
353 PORT MAP (
354 clk => clk,
354 clk => clk,
355 rstn => rstn,
355 rstn => rstn,
356 sample_in_val => sample_f1_val_s ,
356 sample_in_val => sample_f1_val_s ,
357 sample_in => sample_f1_s,
357 sample_in => sample_f1_s,
358 sample_out_val => sample_f3_val,
358 sample_out_val => sample_f3_val,
359 sample_out => sample_f3);
359 sample_out => sample_f3);
360
360
361 --sample_f3_wen <= (NOT sample_f3_val) &
361 --sample_f3_wen <= (NOT sample_f3_val) &
362 -- (NOT sample_f3_val) &
362 -- (NOT sample_f3_val) &
363 -- (NOT sample_f3_val) &
363 -- (NOT sample_f3_val) &
364 -- (NOT sample_f3_val) &
364 -- (NOT sample_f3_val) &
365 -- (NOT sample_f3_val) &
365 -- (NOT sample_f3_val) &
366 -- (NOT sample_f3_val);
366 -- (NOT sample_f3_val);
367
367
368 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
368 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
369 sample_f3_wdata_s(I) <= sample_f3(0, I);
369 sample_f3_wdata_s(I) <= sample_f3(0, I);
370 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
370 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
371 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
371 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
372 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
372 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
373 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
373 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
374 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
374 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
375 END GENERATE all_bit_sample_f3;
375 END GENERATE all_bit_sample_f3;
376
376
377 -----------------------------------------------------------------------------
377 -----------------------------------------------------------------------------
378 --
378 --
379 -----------------------------------------------------------------------------
379 -----------------------------------------------------------------------------
380 sample_f0_wdata <= sample_f0_wdata_s;
380 sample_f0_wdata <= sample_f0_wdata_s;
381 sample_f1_wdata <= sample_f1_wdata_s;
381 sample_f1_wdata <= sample_f1_wdata_s;
382 sample_f2_wdata <= sample_f2_wdata_s;
382 sample_f2_wdata <= sample_f2_wdata_s;
383 sample_f3_wdata <= sample_f3_wdata_s;
383 sample_f3_wdata <= sample_f3_wdata_s;
384
384
385 END tb; No newline at end of file
385 END tb;
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@@ -1,346 +1,346
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20
20
21 LIBRARY grlib;
21 LIBRARY grlib;
22 USE grlib.amba.ALL;
22 USE grlib.amba.ALL;
23 USE grlib.stdlib.ALL;
23 USE grlib.stdlib.ALL;
24 USE grlib.devices.ALL;
24 USE grlib.devices.ALL;
25 USE GRLIB.DMA2AHB_Package.ALL;
25 USE GRLIB.DMA2AHB_Package.ALL;
26
26
27
27
28 ENTITY lpp_lfr_ms IS
28 ENTITY lpp_lfr_ms IS
29 GENERIC (
29 GENERIC (
30 hindex : INTEGER := 2
30 hindex : INTEGER := 2
31 );
31 );
32 PORT (
32 PORT (
33 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35
35
36 ---------------------------------------------------------------------------
36 ---------------------------------------------------------------------------
37 -- DATA INPUT
37 -- DATA INPUT
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 --
39 --
40 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
41 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 --
42 --
43 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 --
45 --
46 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
47 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48
48
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 -- DMA
50 -- DMA
51 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
52
52
53 -- AMBA AHB Master Interface
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
56
57 -- Reg out
57 -- Reg out
58 ready_matrix_f0_0 : OUT STD_LOGIC;
58 ready_matrix_f0_0 : OUT STD_LOGIC;
59 ready_matrix_f0_1 : OUT STD_LOGIC;
59 ready_matrix_f0_1 : OUT STD_LOGIC;
60 ready_matrix_f1 : OUT STD_LOGIC;
60 ready_matrix_f1 : OUT STD_LOGIC;
61 ready_matrix_f2 : OUT STD_LOGIC;
61 ready_matrix_f2 : OUT STD_LOGIC;
62 error_anticipating_empty_fifo : OUT STD_LOGIC;
62 error_anticipating_empty_fifo : OUT STD_LOGIC;
63 error_bad_component_error : OUT STD_LOGIC;
63 error_bad_component_error : OUT STD_LOGIC;
64 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65
65
66 -- Reg In
66 -- Reg In
67 status_ready_matrix_f0_0 :IN STD_LOGIC;
67 status_ready_matrix_f0_0 :IN STD_LOGIC;
68 status_ready_matrix_f0_1 :IN STD_LOGIC;
68 status_ready_matrix_f0_1 :IN STD_LOGIC;
69 status_ready_matrix_f1 :IN STD_LOGIC;
69 status_ready_matrix_f1 :IN STD_LOGIC;
70 status_ready_matrix_f2 :IN STD_LOGIC;
70 status_ready_matrix_f2 :IN STD_LOGIC;
71 status_error_anticipating_empty_fifo :IN STD_LOGIC;
71 status_error_anticipating_empty_fifo :IN STD_LOGIC;
72 status_error_bad_component_error :IN STD_LOGIC;
72 status_error_bad_component_error :IN STD_LOGIC;
73
73
74 config_active_interruption_onNewMatrix : IN STD_LOGIC;
74 config_active_interruption_onNewMatrix : IN STD_LOGIC;
75 config_active_interruption_onError : IN STD_LOGIC;
75 config_active_interruption_onError : IN STD_LOGIC;
76 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
79 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
80 );
80 );
81 END;
81 END;
82
82
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
84 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
85 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
88 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
89 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
89 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
90 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
90 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
91
91
92 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
93 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
93 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
94 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
95 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
96 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
96 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
97
97
98 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
99 SIGNAL FFT_Load : STD_LOGIC;
99 SIGNAL FFT_Load : STD_LOGIC;
100 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
103 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
104
104
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL SM_FlagError : STD_LOGIC;
110 SIGNAL SM_FlagError : STD_LOGIC;
111 SIGNAL SM_Pong : STD_LOGIC;
111 SIGNAL SM_Pong : STD_LOGIC;
112 SIGNAL SM_Wen : STD_LOGIC;
112 SIGNAL SM_Wen : STD_LOGIC;
113 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
117 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
122 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
123
123
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL Head_Empty : STD_LOGIC;
127 SIGNAL Head_Empty : STD_LOGIC;
128 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL Head_Valid : STD_LOGIC;
129 SIGNAL Head_Valid : STD_LOGIC;
130 SIGNAL Head_Val : STD_LOGIC;
130 SIGNAL Head_Val : STD_LOGIC;
131
131
132 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
133 SIGNAL DMA_Read : STD_LOGIC;
133 SIGNAL DMA_Read : STD_LOGIC;
134 SIGNAL DMA_ack : STD_LOGIC;
134 SIGNAL DMA_ack : STD_LOGIC;
135
135
136 BEGIN
136 BEGIN
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 Memf0: lppFIFOxN
139 Memf0: lppFIFOxN
140 GENERIC MAP (
140 GENERIC MAP (
141 tech => 0, Mem_use => use_RAM, Data_sz => 16,
141 tech => 0, Mem_use => use_RAM, Data_sz => 16,
142 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
142 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
143 PORT MAP (
143 PORT MAP (
144 rst => rstn, wclk => clk, rclk => clk,
144 rst => rstn, wclk => clk, rclk => clk,
145 ReUse => (OTHERS => '0'),
145 ReUse => (OTHERS => '0'),
146 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
146 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
147 wdata => sample_f0_wdata, rdata => FifoF0_Data,
147 wdata => sample_f0_wdata, rdata => FifoF0_Data,
148 full => OPEN, empty => FifoF0_Empty);
148 full => OPEN, empty => FifoF0_Empty);
149
149
150 Memf1: lppFIFOxN
150 Memf1: lppFIFOxN
151 GENERIC MAP (
151 GENERIC MAP (
152 tech => 0, Mem_use => use_RAM, Data_sz => 16,
152 tech => 0, Mem_use => use_RAM, Data_sz => 16,
153 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
153 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
154 PORT MAP (
154 PORT MAP (
155 rst => rstn, wclk => clk, rclk => clk,
155 rst => rstn, wclk => clk, rclk => clk,
156 ReUse => (OTHERS => '0'),
156 ReUse => (OTHERS => '0'),
157 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
157 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
158 wdata => sample_f1_wdata, rdata => FifoF1_Data,
158 wdata => sample_f1_wdata, rdata => FifoF1_Data,
159 full => OPEN, empty => FifoF1_Empty);
159 full => OPEN, empty => FifoF1_Empty);
160
160
161
161
162 Memf2: lppFIFOxN
162 Memf2: lppFIFOxN
163 GENERIC MAP (
163 GENERIC MAP (
164 tech => 0, Mem_use => use_RAM, Data_sz => 16,
164 tech => 0, Mem_use => use_RAM, Data_sz => 16,
165 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
165 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
166 PORT MAP (
166 PORT MAP (
167 rst => rstn, wclk => clk, rclk => clk,
167 rst => rstn, wclk => clk, rclk => clk,
168 ReUse => (OTHERS => '0'),
168 ReUse => (OTHERS => '0'),
169 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
169 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
170 wdata => sample_f3_wdata, rdata => FifoF3_Data,
170 wdata => sample_f3_wdata, rdata => FifoF3_Data,
171 full => OPEN, empty => FifoF3_Empty);
171 full => OPEN, empty => FifoF3_Empty);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173
173
174
174
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176 DMUX0 : DEMUX
176 DMUX0 : DEMUX
177 GENERIC MAP (
177 GENERIC MAP (
178 Data_sz => 16)
178 Data_sz => 16)
179 PORT MAP (
179 PORT MAP (
180 clk => clk,
180 clk => clk,
181 rstn => rstn,
181 rstn => rstn,
182 Read => FFT_Read,
182 Read => FFT_Read,
183 Load => FFT_Load,
183 Load => FFT_Load,
184 EmptyF0 => FifoF0_Empty,
184 EmptyF0 => FifoF0_Empty,
185 EmptyF1 => FifoF1_Empty,
185 EmptyF1 => FifoF1_Empty,
186 EmptyF2 => FifoF3_Empty,
186 EmptyF2 => FifoF3_Empty,
187 DataF0 => FifoF0_Data,
187 DataF0 => FifoF0_Data,
188 DataF1 => FifoF1_Data,
188 DataF1 => FifoF1_Data,
189 DataF2 => FifoF3_Data,
189 DataF2 => FifoF3_Data,
190 WorkFreq => DMUX_WorkFreq,
190 WorkFreq => DMUX_WorkFreq,
191 Read_DEMUX => DMUX_Read,
191 Read_DEMUX => DMUX_Read,
192 Empty => DMUX_Empty,
192 Empty => DMUX_Empty,
193 Data => DMUX_Data);
193 Data => DMUX_Data);
194 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
195
195
196
196
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198 FFT0: FFT
198 FFT0: FFT
199 GENERIC MAP (
199 GENERIC MAP (
200 Data_sz => 16,
200 Data_sz => 16,
201 NbData => 256)
201 NbData => 256)
202 PORT MAP (
202 PORT MAP (
203 clkm => clk,
203 clkm => clk,
204 rstn => rstn,
204 rstn => rstn,
205 FifoIN_Empty => DMUX_Empty,
205 FifoIN_Empty => DMUX_Empty,
206 FifoIN_Data => DMUX_Data,
206 FifoIN_Data => DMUX_Data,
207 FifoOUT_Full => FifoINT_Full,
207 FifoOUT_Full => FifoINT_Full,
208 Load => FFT_Load,
208 Load => FFT_Load,
209 Read => FFT_Read,
209 Read => FFT_Read,
210 Write => FFT_Write,
210 Write => FFT_Write,
211 ReUse => FFT_ReUse,
211 ReUse => FFT_ReUse,
212 Data => FFT_Data);
212 Data => FFT_Data);
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214
214
215
215
216 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
217 MemInt : lppFIFOxN
217 MemInt : lppFIFOxN
218 GENERIC MAP (
218 GENERIC MAP (
219 tech => 0,
219 tech => 0,
220 Mem_use => use_RAM,
220 Mem_use => use_RAM,
221 Data_sz => 16,
221 Data_sz => 16,
222 Addr_sz => 8,
222 Addr_sz => 8,
223 FifoCnt => 5,
223 FifoCnt => 5,
224 Enable_ReUse => '1')
224 Enable_ReUse => '1')
225 PORT MAP (
225 PORT MAP (
226 rst => rstn,
226 rst => rstn,
227 wclk => clk,
227 wclk => clk,
228 rclk => clk,
228 rclk => clk,
229 ReUse => SM_ReUse,
229 ReUse => SM_ReUse,
230 wen => FFT_Write,
230 wen => FFT_Write,
231 ren => SM_Read,
231 ren => SM_Read,
232 wdata => FFT_Data,
232 wdata => FFT_Data,
233 rdata => FifoINT_Data,
233 rdata => FifoINT_Data,
234 full => FifoINT_Full,
234 full => FifoINT_Full,
235 empty => OPEN);
235 empty => OPEN);
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237
237
238 -----------------------------------------------------------------------------
238 -----------------------------------------------------------------------------
239 SM0 : MatriceSpectrale
239 SM0 : MatriceSpectrale
240 GENERIC MAP (
240 GENERIC MAP (
241 Input_SZ => 16,
241 Input_SZ => 16,
242 Result_SZ => 32)
242 Result_SZ => 32)
243 PORT MAP (
243 PORT MAP (
244 clkm => clk,
244 clkm => clk,
245 rstn => rstn,
245 rstn => rstn,
246 FifoIN_Full => FifoINT_Full,
246 FifoIN_Full => FifoINT_Full,
247 SetReUse => FFT_ReUse,
247 SetReUse => FFT_ReUse,
248 Valid => Head_Valid,
248 Valid => Head_Valid,
249 Data_IN => FifoINT_Data,
249 Data_IN => FifoINT_Data,
250 ACQ => DMA_ack,
250 ACQ => DMA_ack,
251 SM_Write => SM_Wen,
251 SM_Write => SM_Wen,
252 FlagError => SM_FlagError,
252 FlagError => SM_FlagError,
253 Pong => SM_Pong,
253 Pong => SM_Pong,
254 Statu => SM_Param,
254 Statu => SM_Param,
255 Write => SM_Write,
255 Write => SM_Write,
256 Read => SM_Read,
256 Read => SM_Read,
257 ReUse => SM_ReUse,
257 ReUse => SM_ReUse,
258 Data_OUT => SM_Data);
258 Data_OUT => SM_Data);
259 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
260
260
261 -----------------------------------------------------------------------------
261 -----------------------------------------------------------------------------
262 MemOut : lppFIFOxN
262 MemOut : lppFIFOxN
263 GENERIC MAP (
263 GENERIC MAP (
264 tech => 0,
264 tech => 0,
265 Mem_use => use_RAM,
265 Mem_use => use_RAM,
266 Data_sz => 32,
266 Data_sz => 32,
267 Addr_sz => 8,
267 Addr_sz => 8,
268 FifoCnt => 2,
268 FifoCnt => 2,
269 Enable_ReUse => '0')
269 Enable_ReUse => '0')
270 PORT MAP (
270 PORT MAP (
271 rst => rstn,
271 rst => rstn,
272 wclk => clk,
272 wclk => clk,
273 rclk => clk,
273 rclk => clk,
274 ReUse => (OTHERS => '0'),
274 ReUse => (OTHERS => '0'),
275 wen => SM_Write,
275 wen => SM_Write,
276 ren => Head_Read,
276 ren => Head_Read,
277 wdata => SM_Data,
277 wdata => SM_Data,
278 rdata => FifoOUT_Data,
278 rdata => FifoOUT_Data,
279 full => FifoOUT_Full,
279 full => FifoOUT_Full,
280 empty => FifoOUT_Empty);
280 empty => FifoOUT_Empty);
281 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
282
282
283 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
284 Head0 : HeaderBuilder
284 Head0 : HeaderBuilder
285 GENERIC MAP (
285 GENERIC MAP (
286 Data_sz => 32)
286 Data_sz => 32)
287 PORT MAP (
287 PORT MAP (
288 clkm => clk,
288 clkm => clk,
289 rstn => rstn,
289 rstn => rstn,
290 pong => SM_Pong,
290 pong => SM_Pong,
291 Statu => SM_Param,
291 Statu => SM_Param,
292 Matrix_Type => DMUX_WorkFreq,
292 Matrix_Type => DMUX_WorkFreq,
293 Matrix_Write => SM_Wen,
293 Matrix_Write => SM_Wen,
294 Valid => Head_Valid,
294 Valid => Head_Valid,
295 dataIN => FifoOUT_Data,
295 dataIN => FifoOUT_Data,
296 emptyIN => FifoOUT_Empty,
296 emptyIN => FifoOUT_Empty,
297 RenOUT => Head_Read,
297 RenOUT => Head_Read,
298 dataOUT => Head_Data,
298 dataOUT => Head_Data,
299 emptyOUT => Head_Empty,
299 emptyOUT => Head_Empty,
300 RenIN => DMA_Read,
300 RenIN => DMA_Read,
301 header => Head_Header,
301 header => Head_Header,
302 header_val => Head_Val,
302 header_val => Head_Val,
303 header_ack => DMA_ack );
303 header_ack => DMA_ack );
304 -----------------------------------------------------------------------------
304 -----------------------------------------------------------------------------
305
305
306 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
307 lpp_dma_ip_1: lpp_dma_ip
307 lpp_dma_ip_1: lpp_dma_ip
308 GENERIC MAP (
308 GENERIC MAP (
309 tech => 0,
309 tech => 0,
310 hindex => hindex)
310 hindex => hindex)
311 PORT MAP (
311 PORT MAP (
312 HCLK => clk,
312 HCLK => clk,
313 HRESETn => rstn,
313 HRESETn => rstn,
314 AHB_Master_In => AHB_Master_In,
314 AHB_Master_In => AHB_Master_In,
315 AHB_Master_Out => AHB_Master_Out,
315 AHB_Master_Out => AHB_Master_Out,
316
316
317 fifo_data => Head_Data,
317 fifo_data => Head_Data,
318 fifo_empty => Head_Empty,
318 fifo_empty => Head_Empty,
319 fifo_ren => DMA_Read,
319 fifo_ren => DMA_Read,
320
320
321 header => Head_Header,
321 header => Head_Header,
322 header_val => Head_Val,
322 header_val => Head_Val,
323 header_ack => DMA_ack,
323 header_ack => DMA_ack,
324
324
325 ready_matrix_f0_0 => ready_matrix_f0_0,
325 ready_matrix_f0_0 => ready_matrix_f0_0,
326 ready_matrix_f0_1 => ready_matrix_f0_1,
326 ready_matrix_f0_1 => ready_matrix_f0_1,
327 ready_matrix_f1 => ready_matrix_f1,
327 ready_matrix_f1 => ready_matrix_f1,
328 ready_matrix_f2 => ready_matrix_f2,
328 ready_matrix_f2 => ready_matrix_f2,
329 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
329 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
330 error_bad_component_error => error_bad_component_error,
330 error_bad_component_error => error_bad_component_error,
331 debug_reg => debug_reg,
331 debug_reg => debug_reg,
332 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
332 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
333 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
333 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
334 status_ready_matrix_f1 => status_ready_matrix_f1,
334 status_ready_matrix_f1 => status_ready_matrix_f1,
335 status_ready_matrix_f2 => status_ready_matrix_f2,
335 status_ready_matrix_f2 => status_ready_matrix_f2,
336 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
336 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
337 status_error_bad_component_error => status_error_bad_component_error,
337 status_error_bad_component_error => status_error_bad_component_error,
338 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
338 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
339 config_active_interruption_onError => config_active_interruption_onError,
339 config_active_interruption_onError => config_active_interruption_onError,
340 addr_matrix_f0_0 => addr_matrix_f0_0,
340 addr_matrix_f0_0 => addr_matrix_f0_0,
341 addr_matrix_f0_1 => addr_matrix_f0_1,
341 addr_matrix_f0_1 => addr_matrix_f0_1,
342 addr_matrix_f1 => addr_matrix_f1,
342 addr_matrix_f1 => addr_matrix_f1,
343 addr_matrix_f2 => addr_matrix_f2);
343 addr_matrix_f2 => addr_matrix_f2);
344 -----------------------------------------------------------------------------
344 -----------------------------------------------------------------------------
345
345
346 END Behavioral; No newline at end of file
346 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,168 +1,196
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 hindex : INTEGER);
19 hindex : INTEGER);
20 PORT (
20 PORT (
21 clk : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 AHB_Master_In : IN AHB_Mst_In_Type;
29 AHB_Master_In : IN AHB_Mst_In_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 END COMPONENT;
50 END COMPONENT;
51
51
52 COMPONENT lpp_lfr_filter
52 COMPONENT lpp_lfr_filter
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER);
54 Mem_use : INTEGER);
55 PORT (
55 PORT (
56 sample : IN Samples(7 DOWNTO 0);
56 sample : IN Samples(7 DOWNTO 0);
57 sample_val : IN STD_LOGIC;
57 sample_val : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_burst_available_size : INTEGER;
77 nb_burst_available_size : INTEGER;
78 nb_snapshot_param_size : INTEGER;
78 nb_snapshot_param_size : INTEGER;
79 delta_snapshot_size : INTEGER;
79 delta_snapshot_size : INTEGER;
80 delta_f2_f0_size : INTEGER;
80 delta_f2_f0_size : INTEGER;
81 delta_f2_f1_size : INTEGER;
81 delta_f2_f1_size : INTEGER;
82 pindex : INTEGER;
82 pindex : INTEGER;
83 paddr : INTEGER;
83 paddr : INTEGER;
84 pmask : INTEGER;
84 pmask : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
86 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
87 hindex_wfp : INTEGER;
87 hindex_wfp : INTEGER;
88 hindex_ms : INTEGER);
88 hindex_ms : INTEGER);
89 PORT (
89 PORT (
90 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
91 rstn : IN STD_LOGIC;
91 rstn : IN STD_LOGIC;
92 sample_B : IN Samples14v(2 DOWNTO 0);
92 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_E : IN Samples14v(4 DOWNTO 0);
93 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_val : IN STD_LOGIC;
94 sample_val : IN STD_LOGIC;
95 apbi : IN apb_slv_in_type;
95 apbi : IN apb_slv_in_type;
96 apbo : OUT apb_slv_out_type;
96 apbo : OUT apb_slv_out_type;
97 ahbi_wfp : IN AHB_Mst_In_Type;
97 ahbi_wfp : IN AHB_Mst_In_Type;
98 ahbo_wfp : OUT AHB_Mst_Out_Type;
98 ahbo_wfp : OUT AHB_Mst_Out_Type;
99 ahbi_ms : IN AHB_Mst_In_Type;
99 ahbi_ms : IN AHB_Mst_In_Type;
100 ahbo_ms : OUT AHB_Mst_Out_Type;
100 ahbo_ms : OUT AHB_Mst_Out_Type;
101 coarse_time_0 : IN STD_LOGIC;
101 coarse_time_0 : IN STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC);
102 data_shaping_BW : OUT STD_LOGIC);
103 END COMPONENT;
103 END COMPONENT;
104
104
105 COMPONENT lpp_lfr_apbreg
105 COMPONENT lpp_lfr_apbreg
106 GENERIC (
106 GENERIC (
107 nb_burst_available_size : INTEGER;
107 nb_burst_available_size : INTEGER;
108 nb_snapshot_param_size : INTEGER;
108 nb_snapshot_param_size : INTEGER;
109 delta_snapshot_size : INTEGER;
109 delta_snapshot_size : INTEGER;
110 delta_f2_f0_size : INTEGER;
110 delta_f2_f0_size : INTEGER;
111 delta_f2_f1_size : INTEGER;
111 delta_f2_f1_size : INTEGER;
112 pindex : INTEGER;
112 pindex : INTEGER;
113 paddr : INTEGER;
113 paddr : INTEGER;
114 pmask : INTEGER;
114 pmask : INTEGER;
115 pirq_ms : INTEGER;
115 pirq_ms : INTEGER;
116 pirq_wfp : INTEGER);
116 pirq_wfp : INTEGER);
117 PORT (
117 PORT (
118 HCLK : IN STD_ULOGIC;
118 HCLK : IN STD_ULOGIC;
119 HRESETn : IN STD_ULOGIC;
119 HRESETn : IN STD_ULOGIC;
120 apbi : IN apb_slv_in_type;
120 apbi : IN apb_slv_in_type;
121 apbo : OUT apb_slv_out_type;
121 apbo : OUT apb_slv_out_type;
122 ready_matrix_f0_0 : IN STD_LOGIC;
122 ready_matrix_f0_0 : IN STD_LOGIC;
123 ready_matrix_f0_1 : IN STD_LOGIC;
123 ready_matrix_f0_1 : IN STD_LOGIC;
124 ready_matrix_f1 : IN STD_LOGIC;
124 ready_matrix_f1 : IN STD_LOGIC;
125 ready_matrix_f2 : IN STD_LOGIC;
125 ready_matrix_f2 : IN STD_LOGIC;
126 error_anticipating_empty_fifo : IN STD_LOGIC;
126 error_anticipating_empty_fifo : IN STD_LOGIC;
127 error_bad_component_error : IN STD_LOGIC;
127 error_bad_component_error : IN STD_LOGIC;
128 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 status_ready_matrix_f0_0 : OUT STD_LOGIC;
129 status_ready_matrix_f0_0 : OUT STD_LOGIC;
130 status_ready_matrix_f0_1 : OUT STD_LOGIC;
130 status_ready_matrix_f0_1 : OUT STD_LOGIC;
131 status_ready_matrix_f1 : OUT STD_LOGIC;
131 status_ready_matrix_f1 : OUT STD_LOGIC;
132 status_ready_matrix_f2 : OUT STD_LOGIC;
132 status_ready_matrix_f2 : OUT STD_LOGIC;
133 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
133 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
134 status_error_bad_component_error : OUT STD_LOGIC;
134 status_error_bad_component_error : OUT STD_LOGIC;
135 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
135 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
136 config_active_interruption_onError : OUT STD_LOGIC;
136 config_active_interruption_onError : OUT STD_LOGIC;
137 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
137 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
141 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
142 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
142 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
143 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
143 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
145 data_shaping_BW : OUT STD_LOGIC;
145 data_shaping_BW : OUT STD_LOGIC;
146 data_shaping_SP0 : OUT STD_LOGIC;
146 data_shaping_SP0 : OUT STD_LOGIC;
147 data_shaping_SP1 : OUT STD_LOGIC;
147 data_shaping_SP1 : OUT STD_LOGIC;
148 data_shaping_R0 : OUT STD_LOGIC;
148 data_shaping_R0 : OUT STD_LOGIC;
149 data_shaping_R1 : OUT STD_LOGIC;
149 data_shaping_R1 : OUT STD_LOGIC;
150 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
150 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
151 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
151 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
152 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
152 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
153 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
153 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
154 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
154 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
155 enable_f0 : OUT STD_LOGIC;
155 enable_f0 : OUT STD_LOGIC;
156 enable_f1 : OUT STD_LOGIC;
156 enable_f1 : OUT STD_LOGIC;
157 enable_f2 : OUT STD_LOGIC;
157 enable_f2 : OUT STD_LOGIC;
158 enable_f3 : OUT STD_LOGIC;
158 enable_f3 : OUT STD_LOGIC;
159 burst_f0 : OUT STD_LOGIC;
159 burst_f0 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
162 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
165 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
166 END COMPONENT;
166 END COMPONENT;
167
168 COMPONENT lpp_top_ms
169 GENERIC (
170 Mem_use : INTEGER;
171 nb_burst_available_size : INTEGER;
172 nb_snapshot_param_size : INTEGER;
173 delta_snapshot_size : INTEGER;
174 delta_f2_f0_size : INTEGER;
175 delta_f2_f1_size : INTEGER;
176 pindex : INTEGER;
177 paddr : INTEGER;
178 pmask : INTEGER;
179 pirq_ms : INTEGER;
180 pirq_wfp : INTEGER;
181 hindex_wfp : INTEGER;
182 hindex_ms : INTEGER);
183 PORT (
184 clk : IN STD_LOGIC;
185 rstn : IN STD_LOGIC;
186 sample_B : IN Samples14v(2 DOWNTO 0);
187 sample_E : IN Samples14v(4 DOWNTO 0);
188 sample_val : IN STD_LOGIC;
189 apbi : IN apb_slv_in_type;
190 apbo : OUT apb_slv_out_type;
191 ahbi_ms : IN AHB_Mst_In_Type;
192 ahbo_ms : OUT AHB_Mst_Out_Type;
193 data_shaping_BW : OUT STD_LOGIC);
194 END COMPONENT;
167
195
168 END lpp_lfr_pkg;
196 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,13 +1,14
1 lpp_top_lfr_pkg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
3 lpp_top_apbreg.vhd
3 lpp_top_apbreg.vhd
4 lpp_top_acq.vhd
4 lpp_top_acq.vhd
5 lpp_top_lfr_wf_picker.vhd
5 lpp_top_lfr_wf_picker.vhd
6 lpp_top_lfr_wf_picker_ip.vhd
6 lpp_top_lfr_wf_picker_ip.vhd
7 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
7 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
8 top_lfr_wf_picker.vhd
8 top_lfr_wf_picker.vhd
9 lpp_lfr_apbreg.vhd
9 lpp_lfr_apbreg.vhd
10 top_wf_picker.vhd
10 top_wf_picker.vhd
11 lpp_lfr_filter.vhd
11 lpp_lfr_filter.vhd
12 lpp_lfr_ms.vhd
12 lpp_lfr_ms.vhd
13 lpp_top_ms.vhd
13 lpp_lfr.vhd
14 lpp_lfr.vhd
Show file before | Show file after | Hide comments
@@ -1,265 +1,272
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY grlib;
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
7 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
8 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
10
10
11 LIBRARY lpp;
11 LIBRARY lpp;
12 USE lpp.lpp_waveform_pkg.ALL;
12 USE lpp.lpp_waveform_pkg.ALL;
13
13
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 ENTITY lpp_waveform IS
17 ENTITY lpp_waveform IS
18
18
19 GENERIC (
19 GENERIC (
20 hindex : INTEGER := 2;
20 hindex : INTEGER := 2;
21 tech : INTEGER := inferred;
21 tech : INTEGER := inferred;
22 data_size : INTEGER := 160;
22 data_size : INTEGER := 160;
23 nb_burst_available_size : INTEGER := 11;
23 nb_burst_available_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
25 delta_snapshot_size : INTEGER := 16;
25 delta_snapshot_size : INTEGER := 16;
26 delta_f2_f0_size : INTEGER := 10;
26 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f1_size : INTEGER := 10);
27 delta_f2_f1_size : INTEGER := 10);
28
28
29 PORT (
29 PORT (
30 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32
32
33 -- AMBA AHB Master Interface
33 -- AMBA AHB Master Interface
34 AHB_Master_In : IN AHB_Mst_In_Type;
34 AHB_Master_In : IN AHB_Mst_In_Type;
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
36
36
37 coarse_time_0 : IN STD_LOGIC;
37 coarse_time_0 : IN STD_LOGIC;
38
38
39 --config
39 --config
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
43
43
44 enable_f0 : IN STD_LOGIC;
44 enable_f0 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
48
48
49 burst_f0 : IN STD_LOGIC;
49 burst_f0 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
52
52
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63
63
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
68
68
69 data_f0_in_valid : IN STD_LOGIC;
69 data_f0_in_valid : IN STD_LOGIC;
70 data_f1_in_valid : IN STD_LOGIC;
70 data_f1_in_valid : IN STD_LOGIC;
71 data_f2_in_valid : IN STD_LOGIC;
71 data_f2_in_valid : IN STD_LOGIC;
72 data_f3_in_valid : IN STD_LOGIC
72 data_f3_in_valid : IN STD_LOGIC
73 );
73 );
74
74
75 END lpp_waveform;
75 END lpp_waveform;
76
76
77 ARCHITECTURE beh OF lpp_waveform IS
77 ARCHITECTURE beh OF lpp_waveform IS
78 SIGNAL start_snapshot_f0 : STD_LOGIC;
78 SIGNAL start_snapshot_f0 : STD_LOGIC;
79 SIGNAL start_snapshot_f1 : STD_LOGIC;
79 SIGNAL start_snapshot_f1 : STD_LOGIC;
80 SIGNAL start_snapshot_f2 : STD_LOGIC;
80 SIGNAL start_snapshot_f2 : STD_LOGIC;
81
81
82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86
86
87 SIGNAL data_f0_out_valid : STD_LOGIC;
87 SIGNAL data_f0_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
92
92
93 --
93 --
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --
103 --
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
106
108
107 BEGIN -- beh
109 BEGIN -- beh
108
110
109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
111 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
110 GENERIC MAP (
112 GENERIC MAP (
111 delta_snapshot_size => delta_snapshot_size,
113 delta_snapshot_size => delta_snapshot_size,
112 delta_f2_f0_size => delta_f2_f0_size,
114 delta_f2_f0_size => delta_f2_f0_size,
113 delta_f2_f1_size => delta_f2_f1_size)
115 delta_f2_f1_size => delta_f2_f1_size)
114 PORT MAP (
116 PORT MAP (
115 clk => clk,
117 clk => clk,
116 rstn => rstn,
118 rstn => rstn,
117 delta_snapshot => delta_snapshot,
119 delta_snapshot => delta_snapshot,
118 delta_f2_f1 => delta_f2_f1,
120 delta_f2_f1 => delta_f2_f1,
119 delta_f2_f0 => delta_f2_f0,
121 delta_f2_f0 => delta_f2_f0,
120 coarse_time_0 => coarse_time_0,
122 coarse_time_0 => coarse_time_0,
121 data_f0_in_valid => data_f0_in_valid,
123 data_f0_in_valid => data_f0_in_valid,
122 data_f2_in_valid => data_f2_in_valid,
124 data_f2_in_valid => data_f2_in_valid,
123 start_snapshot_f0 => start_snapshot_f0,
125 start_snapshot_f0 => start_snapshot_f0,
124 start_snapshot_f1 => start_snapshot_f1,
126 start_snapshot_f1 => start_snapshot_f1,
125 start_snapshot_f2 => start_snapshot_f2);
127 start_snapshot_f2 => start_snapshot_f2);
126
128
127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
129 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
128 GENERIC MAP (
130 GENERIC MAP (
129 data_size => data_size,
131 data_size => data_size,
130 nb_snapshot_param_size => nb_snapshot_param_size)
132 nb_snapshot_param_size => nb_snapshot_param_size)
131 PORT MAP (
133 PORT MAP (
132 clk => clk,
134 clk => clk,
133 rstn => rstn,
135 rstn => rstn,
134 enable => enable_f0,
136 enable => enable_f0,
135 burst_enable => burst_f0,
137 burst_enable => burst_f0,
136 nb_snapshot_param => nb_snapshot_param,
138 nb_snapshot_param => nb_snapshot_param,
137 start_snapshot => start_snapshot_f0,
139 start_snapshot => start_snapshot_f0,
138 data_in => data_f0_in,
140 data_in => data_f0_in,
139 data_in_valid => data_f0_in_valid,
141 data_in_valid => data_f0_in_valid,
140 data_out => data_f0_out,
142 data_out => data_f0_out,
141 data_out_valid => data_f0_out_valid);
143 data_out_valid => data_f0_out_valid);
142
144
143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
145 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
144
146
145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
147 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
146 GENERIC MAP (
148 GENERIC MAP (
147 data_size => data_size,
149 data_size => data_size,
148 nb_snapshot_param_size => nb_snapshot_param_size+1)
150 nb_snapshot_param_size => nb_snapshot_param_size+1)
149 PORT MAP (
151 PORT MAP (
150 clk => clk,
152 clk => clk,
151 rstn => rstn,
153 rstn => rstn,
152 enable => enable_f1,
154 enable => enable_f1,
153 burst_enable => burst_f1,
155 burst_enable => burst_f1,
154 nb_snapshot_param => nb_snapshot_param_more_one,
156 nb_snapshot_param => nb_snapshot_param_more_one,
155 start_snapshot => start_snapshot_f1,
157 start_snapshot => start_snapshot_f1,
156 data_in => data_f1_in,
158 data_in => data_f1_in,
157 data_in_valid => data_f1_in_valid,
159 data_in_valid => data_f1_in_valid,
158 data_out => data_f1_out,
160 data_out => data_f1_out,
159 data_out_valid => data_f1_out_valid);
161 data_out_valid => data_f1_out_valid);
160
162
161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
163 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
162 GENERIC MAP (
164 GENERIC MAP (
163 data_size => data_size,
165 data_size => data_size,
164 nb_snapshot_param_size => nb_snapshot_param_size+1)
166 nb_snapshot_param_size => nb_snapshot_param_size+1)
165 PORT MAP (
167 PORT MAP (
166 clk => clk,
168 clk => clk,
167 rstn => rstn,
169 rstn => rstn,
168 enable => enable_f2,
170 enable => enable_f2,
169 burst_enable => burst_f2,
171 burst_enable => burst_f2,
170 nb_snapshot_param => nb_snapshot_param_more_one,
172 nb_snapshot_param => nb_snapshot_param_more_one,
171 start_snapshot => start_snapshot_f2,
173 start_snapshot => start_snapshot_f2,
172 data_in => data_f2_in,
174 data_in => data_f2_in,
173 data_in_valid => data_f2_in_valid,
175 data_in_valid => data_f2_in_valid,
174 data_out => data_f2_out,
176 data_out => data_f2_out,
175 data_out_valid => data_f2_out_valid);
177 data_out_valid => data_f2_out_valid);
176
178
177 lpp_waveform_burst_f3: lpp_waveform_burst
179 lpp_waveform_burst_f3: lpp_waveform_burst
178 GENERIC MAP (
180 GENERIC MAP (
179 data_size => data_size)
181 data_size => data_size)
180 PORT MAP (
182 PORT MAP (
181 clk => clk,
183 clk => clk,
182 rstn => rstn,
184 rstn => rstn,
183 enable => enable_f3,
185 enable => enable_f3,
184 data_in => data_f3_in,
186 data_in => data_f3_in,
185 data_in_valid => data_f3_in_valid,
187 data_in_valid => data_f3_in_valid,
186 data_out => data_f3_out,
188 data_out => data_f3_out,
187 data_out_valid => data_f3_out_valid);
189 data_out_valid => data_f3_out_valid);
188
190
189
191
190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
192 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
191
193
192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
194 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
195 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
194 PORT MAP (
196 PORT MAP (
195 HCLK => clk,
197 HCLK => clk,
196 HRESETn => rstn,
198 HRESETn => rstn,
197 valid_in => valid_in(I),
199 valid_in => valid_in(I),
198 ack_in => valid_ack(I),
200 ack_in => valid_ack(I),
199 valid_out => valid_out(I),
201 valid_out => valid_out(I),
200 error => status_new_err(I));
202 error => status_new_err(I));
201 END GENERATE all_input_valid;
203 END GENERATE all_input_valid;
202
204
203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
205 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
204 GENERIC MAP (tech => tech)
206 GENERIC MAP (tech => tech)
205 PORT MAP (
207 PORT MAP (
206 clk => clk,
208 clk => clk,
207 rstn => rstn,
209 rstn => rstn,
208 data_f0_valid => valid_out(0),
210 data_f0_valid => valid_out(0),
209 data_f1_valid => valid_out(1),
211 data_f1_valid => valid_out(1),
210 data_f2_valid => valid_out(2),
212 data_f2_valid => valid_out(2),
211 data_f3_valid => valid_out(3),
213 data_f3_valid => valid_out(3),
212
214
213 data_valid_ack => valid_ack,
215 data_valid_ack => valid_ack,
214
216
215 data_f0 => data_f0_out,
217 data_f0 => data_f0_out,
216 data_f1 => data_f1_out,
218 data_f1 => data_f1_out,
217 data_f2 => data_f2_out,
219 data_f2 => data_f2_out,
218 data_f3 => data_f3_out,
220 data_f3 => data_f3_out,
219
221
220 ready => ready_arb,
222 ready => ready_arb,
221 time_wen => time_wen,
223 time_wen => time_wen,
222 data_wen => data_wen,
224 data_wen => data_wen,
223 data => wdata);
225 data => wdata);
224
226
225 ready_arb <= NOT ready;
227 ready_arb <= NOT data_ready;
226
228
227 lpp_waveform_fifo_1: lpp_waveform_fifo
229 lpp_waveform_fifo_1: lpp_waveform_fifo
228 GENERIC MAP (tech => tech)
230 GENERIC MAP (tech => tech)
229 PORT MAP (
231 PORT MAP (
230 clk => clk,
232 clk => clk,
231 rstn => rstn,
233 rstn => rstn,
232 ready => ready,
234 time_ready => time_ready,
235 data_ready => data_ready,
233 time_ren => time_ren, -- todo
236 time_ren => time_ren, -- todo
234 data_ren => data_ren, -- todo
237 data_ren => data_ren, -- todo
235 rdata => rdata, -- todo
238 rdata => rdata, -- todo
236
239
237 time_wen => time_wen,
240 time_wen => time_wen,
238 data_wen => data_wen,
241 data_wen => data_wen,
239 wdata => wdata);
242 wdata => wdata);
240
243
244 enable <= enable_f3 & enable_f2 & enable_f1 & enable_f0;
245
241 pp_waveform_dma_1: lpp_waveform_dma
246 pp_waveform_dma_1: lpp_waveform_dma
242 GENERIC MAP (
247 GENERIC MAP (
243 data_size => data_size,
248 data_size => data_size,
244 tech => tech,
249 tech => tech,
245 hindex => hindex,
250 hindex => hindex,
246 nb_burst_available_size => nb_burst_available_size)
251 nb_burst_available_size => nb_burst_available_size)
247 PORT MAP (
252 PORT MAP (
248 HCLK => clk,
253 HCLK => clk,
249 HRESETn => rstn,
254 HRESETn => rstn,
250 AHB_Master_In => AHB_Master_In,
255 AHB_Master_In => AHB_Master_In,
251 AHB_Master_Out => AHB_Master_Out,
256 AHB_Master_Out => AHB_Master_Out,
252 data_ready => ready,
257 enable => enable, -- todo
258 time_ready => time_ready, -- todo
259 data_ready => data_ready,
253 data => rdata,
260 data => rdata,
254 data_data_ren => data_ren,
261 data_data_ren => data_ren,
255 data_time_ren => time_ren,
262 data_time_ren => time_ren,
256 nb_burst_available => nb_burst_available,
263 nb_burst_available => nb_burst_available,
257 status_full => status_full,
264 status_full => status_full,
258 status_full_ack => status_full_ack,
265 status_full_ack => status_full_ack,
259 status_full_err => status_full_err,
266 status_full_err => status_full_err,
260 addr_data_f0 => addr_data_f0,
267 addr_data_f0 => addr_data_f0,
261 addr_data_f1 => addr_data_f1,
268 addr_data_f1 => addr_data_f1,
262 addr_data_f2 => addr_data_f2,
269 addr_data_f2 => addr_data_f2,
263 addr_data_f3 => addr_data_f3);
270 addr_data_f3 => addr_data_f3);
264
271
265 END beh;
272 END beh;
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@@ -1,326 +1,372
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_waveform_dma IS
45 ENTITY lpp_waveform_dma IS
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER := 160;
47 data_size : INTEGER := 160;
48 tech : INTEGER := inferred;
48 tech : INTEGER := inferred;
49 hindex : INTEGER := 2;
49 hindex : INTEGER := 2;
50 nb_burst_available_size : INTEGER := 11
50 nb_burst_available_size : INTEGER := 11
51 );
51 );
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
60 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
65 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
64 -- Reg
66 -- Reg
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
67 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
69 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
70 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
71 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
75 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
74 );
76 );
75 END;
77 END;
76
78
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
79 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
78 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
79 SIGNAL DMAIn : DMA_In_Type;
81 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
82 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
84 TYPE state_DMAWriteBurst IS (IDLE,TRASH_FIFO_TIME,TRASH_FIFO_DATA,
83 SEND_TIME_0, WAIT_TIME_0,
85 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
86 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
87 SEND_5_TIME,
86 SEND_DATA, WAIT_DATA);
88 SEND_DATA, WAIT_DATA);
87 SIGNAL state : state_DMAWriteBurst ;
89 SIGNAL state : state_DMAWriteBurst ;
88 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
89 -- CONTROL
91 -- CONTROL
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL sel_data_ss : STD_LOGIC;
94 SIGNAL sel_time_s : STD_LOGIC;
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
95 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
96 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
97 SIGNAL time_select : STD_LOGIC;
98 SIGNAL enable_sel : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
99 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
101 SIGNAL time_already_send_s : STD_LOGIC;
97 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
98 -- SEND TIME MODULE
103 -- SEND TIME MODULE
99 SIGNAL time_dmai : DMA_In_Type;
104 SIGNAL time_dmai : DMA_In_Type;
100 SIGNAL time_send : STD_LOGIC;
105 SIGNAL time_send : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
106 SIGNAL time_send_ok : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
107 SIGNAL time_send_ko : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
108 SIGNAL time_fifo_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
109 SIGNAL time_ren : STD_LOGIC;
105 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
106 -- SEND DATA MODULE
111 -- SEND DATA MODULE
107 SIGNAL data_dmai : DMA_In_Type;
112 SIGNAL data_dmai : DMA_In_Type;
108 SIGNAL data_send : STD_LOGIC;
113 SIGNAL data_send : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
114 SIGNAL data_send_ok : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
115 SIGNAL data_send_ko : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
116 SIGNAL data_fifo_ren : STD_LOGIC;
117 SIGNAL trash_fifo_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
118 SIGNAL data_ren : STD_LOGIC;
113 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
114 -- SELECT ADDRESS
120 -- SELECT ADDRESS
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
122 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
123 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
124 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
126 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
127 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
122 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
123 SIGNAL send_16_3_time : STD_LOGIC;
129 SIGNAL send_16_3_time : STD_LOGIC;
124 SIGNAL count_send_time : INTEGER;
130 SIGNAL count_send_time : INTEGER;
125 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
126 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
132 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
127 BEGIN
133 BEGIN
128
134
129 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
130 -- DMA to AHB interface
136 -- DMA to AHB interface
131 DMA2AHB_1 : DMA2AHB
137 DMA2AHB_1 : DMA2AHB
132 GENERIC MAP (
138 GENERIC MAP (
133 hindex => hindex,
139 hindex => hindex,
134 vendorid => VENDOR_LPP,
140 vendorid => VENDOR_LPP,
135 deviceid => 10,
141 deviceid => 10,
136 version => 0,
142 version => 0,
137 syncrst => 1,
143 syncrst => 1,
138 boundary => 1) -- FIX 11/01/2013
144 boundary => 1) -- FIX 11/01/2013
139 PORT MAP (
145 PORT MAP (
140 HCLK => HCLK,
146 HCLK => HCLK,
141 HRESETn => HRESETn,
147 HRESETn => HRESETn,
142 DMAIn => DMAIn,
148 DMAIn => DMAIn,
143 DMAOut => DMAOut,
149 DMAOut => DMAOut,
144 AHBIn => AHB_Master_In,
150 AHBIn => AHB_Master_In,
145 AHBOut => AHB_Master_Out);
151 AHBOut => AHB_Master_Out);
146 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
147
153
148 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
149 -- This module memorises when the Times info are write. When FSM send
155 -- This module memorises when the Times info are write. When FSM send
150 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
156 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
151 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
157 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
152 PROCESS (HCLK, HRESETn)
158 PROCESS (HCLK, HRESETn)
153 BEGIN -- PROCESS
159 BEGIN -- PROCESS
154 IF HRESETn = '0' THEN -- asynchronous reset (active low)
160 IF HRESETn = '0' THEN -- asynchronous reset (active low)
155 time_already_send(I) <= '0';
161 time_already_send(I) <= '0';
156 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
162 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
157 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
163 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
158 time_already_send(I) <= '1';
164 time_already_send(I) <= '1';
159 ELSIF status_full_ack(I) = '1' THEN
165 ELSIF status_full_ack(I) = '1' THEN
160 time_already_send(I) <= '0';
166 time_already_send(I) <= '0';
161 END IF;
167 END IF;
162 END IF;
168 END IF;
163 END PROCESS;
169 END PROCESS;
164 END GENERATE all_time_write;
170 END GENERATE all_time_write;
165
171
166
172
167
173
168 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
169 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
175 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
170 "01" WHEN data_ready(1) = '1' ELSE
176 "01" WHEN data_ready(1) = '1' ELSE
171 "10" WHEN data_ready(2) = '1' ELSE
177 "10" WHEN data_ready(2) = '1' ELSE
172 "11";
178 "11";
179
180 sel_data_ss <= data_ready(0) WHEN sel_data = "00" ELSE
181 data_ready(1) WHEN sel_data = "01" ELSE
182 data_ready(2) WHEN sel_data = "10" ELSE
183 data_ready(3);
184
185 sel_time_s <= time_ready(0) WHEN sel_data = "00" ELSE
186 time_ready(1) WHEN sel_data = "01" ELSE
187 time_ready(2) WHEN sel_data = "10" ELSE
188 time_ready(3);
189
190 enable_sel <= enable(0) WHEN sel_data = "00" ELSE
191 enable(1) WHEN sel_data = "01" ELSE
192 enable(2) WHEN sel_data = "10" ELSE
193 enable(3);
173
194
174 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
195 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
175 time_already_send(1) WHEN data_ready(1) = '1' ELSE
196 time_already_send(1) WHEN data_ready(1) = '1' ELSE
176 time_already_send(2) WHEN data_ready(2) = '1' ELSE
197 time_already_send(2) WHEN data_ready(2) = '1' ELSE
177 time_already_send(3);
198 time_already_send(3);
178
199
179 -- DMA control
200 -- DMA control
180 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
201 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
181 BEGIN -- PROCESS DMAWriteBurst_p
202 BEGIN -- PROCESS DMAWriteBurst_p
182 IF HRESETn = '0' THEN
203 IF HRESETn = '0' THEN
183 state <= IDLE;
204 state <= IDLE;
184
205
185 sel_data <= "00";
206 sel_data <= "00";
186 update <= "00";
207 update <= "00";
187 time_select <= '0';
208 time_select <= '0';
188 time_fifo_ren <= '1';
209 time_fifo_ren <= '1';
210 trash_fifo_ren <= '1';
189 data_send <= '0';
211 data_send <= '0';
190 time_send <= '0';
212 time_send <= '0';
191 time_write <= '0';
213 time_write <= '0';
192
214
193 count_send_time <= 0;
215 count_send_time <= 0;
194 ELSIF HCLK'EVENT AND HCLK = '1' THEN
216 ELSIF HCLK'EVENT AND HCLK = '1' THEN
195
217
196 CASE state IS
218 CASE state IS
197 WHEN IDLE =>
219 WHEN IDLE =>
198 count_send_time <= 0;
220 count_send_time <= 0;
199 sel_data <= "00";
221 sel_data <= "00";
200 update <= "00";
222 update <= "00";
201 time_select <= '0';
223 time_select <= '0';
202 time_fifo_ren <= '1';
224 time_fifo_ren <= '1';
203 data_send <= '0';
225 data_send <= '0';
204 time_send <= '0';
226 time_send <= '0';
205 time_write <= '0';
227 time_write <= '0';
206
228 trash_fifo_ren <= '1';
207 IF data_ready = "0000" THEN
229 IF data_ready = "0000" THEN
208 state <= IDLE;
230 state <= IDLE;
209 ELSE
231 ELSE
210 sel_data <= sel_data_s;
232 sel_data <= sel_data_s;
211 state <= SEND_5_TIME;
233 IF enable_sel = '1' THEN
234 state <= SEND_5_TIME;
235 ELSE
236 state <= TRASH_FIFO_TIME;
237 END IF;
238
212 END IF;
239 END IF;
213
240
241 WHEN TRASH_FIFO_TIME =>
242 time_select <= '1';
243 time_fifo_ren <= '0';
244 IF sel_time_s = '1' THEN
245 time_fifo_ren <= '1';
246 state <= TRASH_FIFO_DATA;
247 END IF;
248
249
250 WHEN TRASH_FIFO_DATA =>
251 time_select <= '1';
252 trash_fifo_ren <= '0';
253 IF sel_data_ss = '1' THEN
254 trash_fifo_ren <= '1';
255 state <= IDLE;
256 END IF;
257
258
214 WHEN SEND_5_TIME =>
259 WHEN SEND_5_TIME =>
215 update <= "00";
260 update <= "00";
216 time_select <= '1';
261 time_select <= '1';
217 time_fifo_ren <= '0';
262 time_fifo_ren <= '0';
218 count_send_time <= count_send_time + 1;
263 count_send_time <= count_send_time + 1;
219 IF count_send_time = 10 THEN
264 IF count_send_time = 10 THEN
220 state <= SEND_DATA;
265 state <= SEND_DATA;
221 END IF;
266 END IF;
222
267
223 WHEN SEND_DATA =>
268 WHEN SEND_DATA =>
224 time_fifo_ren <= '1';
269 time_fifo_ren <= '1';
225 time_write <= '0';
270 time_write <= '0';
226 time_send <= '0';
271 time_send <= '0';
227
272
228 time_select <= '0';
273 time_select <= '0';
229 data_send <= '1';
274 data_send <= '1';
230 update <= "00";
275 update <= "00";
231 state <= WAIT_DATA;
276 state <= WAIT_DATA;
232
277
233 WHEN WAIT_DATA =>
278 WHEN WAIT_DATA =>
234 data_send <= '0';
279 data_send <= '0';
235
280
236 IF data_send_ok = '1' OR data_send_ko = '1' THEN
281 IF data_send_ok = '1' OR data_send_ko = '1' THEN
237 state <= IDLE;
282 state <= IDLE;
238 update <= "10";
283 update <= "10";
239 END IF;
284 END IF;
240
285
241 WHEN OTHERS => NULL;
286 WHEN OTHERS => NULL;
242 END CASE;
287 END CASE;
243
288
244 END IF;
289 END IF;
245 END PROCESS DMAWriteFSM_p;
290 END PROCESS DMAWriteFSM_p;
246 -----------------------------------------------------------------------------
291 -----------------------------------------------------------------------------
247
292
248
293
249
294
250 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
251 -- SEND 1 word by DMA
296 -- SEND 1 word by DMA
252 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
253 lpp_dma_send_1word_1 : lpp_dma_send_1word
298 lpp_dma_send_1word_1 : lpp_dma_send_1word
254 PORT MAP (
299 PORT MAP (
255 HCLK => HCLK,
300 HCLK => HCLK,
256 HRESETn => HRESETn,
301 HRESETn => HRESETn,
257 DMAIn => time_dmai,
302 DMAIn => time_dmai,
258 DMAOut => DMAOut,
303 DMAOut => DMAOut,
259
304
260 send => time_send,
305 send => time_send,
261 address => data_address,
306 address => data_address,
262 data => data,
307 data => data,
263 send_ok => time_send_ok,
308 send_ok => time_send_ok,
264 send_ko => time_send_ko
309 send_ko => time_send_ko
265 );
310 );
266
311
267 -----------------------------------------------------------------------------
312 -----------------------------------------------------------------------------
268 -- SEND 16 word by DMA (in burst mode)
313 -- SEND 16 word by DMA (in burst mode)
269 -----------------------------------------------------------------------------
314 -----------------------------------------------------------------------------
270 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
315 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
271
316
272 lpp_dma_send_16word_1 : lpp_dma_send_16word
317 lpp_dma_send_16word_1 : lpp_dma_send_16word
273 PORT MAP (
318 PORT MAP (
274 HCLK => HCLK,
319 HCLK => HCLK,
275 HRESETn => HRESETn,
320 HRESETn => HRESETn,
276 DMAIn => data_dmai,
321 DMAIn => data_dmai,
277 DMAOut => DMAOut,
322 DMAOut => DMAOut,
278
323
279 send => data_send,
324 send => data_send,
280 address => data_address,
325 address => data_address,
281 data => data_2_halfword,
326 data => data_2_halfword,
282 ren => data_fifo_ren,
327 ren => data_fifo_ren,
283 send_ok => data_send_ok,
328 send_ok => data_send_ok,
284 send_ko => data_send_ko);
329 send_ko => data_send_ko);
285
330
286 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
331 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
287 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
332 data_ren <= trash_fifo_ren WHEN time_select = '1' ELSE data_fifo_ren;
288 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
333 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
289
334
290 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
335 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
291 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
336 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
292 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
337 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
293 END GENERATE all_data_ren;
338 END GENERATE all_data_ren;
294
339
295 -----------------------------------------------------------------------------
340 -----------------------------------------------------------------------------
296 -- SELECT ADDRESS
341 -- SELECT ADDRESS
297 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
342 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
298
343
299 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
344 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
300
345
301 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
346 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
302
347
303 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
348 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
304 GENERIC MAP (
349 GENERIC MAP (
305 nb_burst_available_size => nb_burst_available_size)
350 nb_burst_available_size => nb_burst_available_size)
306 PORT MAP (
351 PORT MAP (
307 HCLK => HCLK,
352 HCLK => HCLK,
308 HRESETn => HRESETn,
353 HRESETn => HRESETn,
354 enable => enable(I),
309 update => update_and_sel((2*I)+1 DOWNTO 2*I),
355 update => update_and_sel((2*I)+1 DOWNTO 2*I),
310 nb_burst_available => nb_burst_available,
356 nb_burst_available => nb_burst_available,
311 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
357 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
312 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
358 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
313 status_full => status_full(I),
359 status_full => status_full(I),
314 status_full_ack => status_full_ack(I),
360 status_full_ack => status_full_ack(I),
315 status_full_err => status_full_err(I));
361 status_full_err => status_full_err(I));
316
362
317 END GENERATE gen_select_address;
363 END GENERATE gen_select_address;
318
364
319 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
365 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
320 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
366 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
321 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
367 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
322 addr_data_vector(32*3+31 DOWNTO 32*3);
368 addr_data_vector(32*3+31 DOWNTO 32*3);
323 -----------------------------------------------------------------------------
369 -----------------------------------------------------------------------------
324
370
325
371
326 END Behavioral;
372 END Behavioral; No newline at end of file
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@@ -1,132 +1,137
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26
26
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30
30
31
31
32 ENTITY lpp_waveform_dma_selectaddress IS
32 ENTITY lpp_waveform_dma_selectaddress IS
33 GENERIC (
33 GENERIC (
34 nb_burst_available_size : INTEGER := 11
34 nb_burst_available_size : INTEGER := 11
35 );
35 );
36 PORT (
36 PORT (
37 HCLK : IN STD_ULOGIC;
37 HCLK : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
39
39
40 enable : IN STD_LOGIC;
40 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41
42
42 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
43 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
43 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
44 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
44
45
45 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46
47
47 status_full : OUT STD_LOGIC;
48 status_full : OUT STD_LOGIC;
48 status_full_ack : IN STD_LOGIC;
49 status_full_ack : IN STD_LOGIC;
49 status_full_err : OUT STD_LOGIC
50 status_full_err : OUT STD_LOGIC
50 );
51 );
51 END;
52 END;
52
53
53 ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS
54 ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS
54 TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED);
55 TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED);
55 SIGNAL state : state_fsm_select_data;
56 SIGNAL state : state_fsm_select_data;
56
57
57 SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
59 SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
59 SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
60 SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
60
61
61 SIGNAL update_s : STD_LOGIC;
62 SIGNAL update_s : STD_LOGIC;
62 SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0);
63 SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0);
63 BEGIN
64 BEGIN
64
65
65 update_s <= update(0) OR update(1);
66 update_s <= update(0) OR update(1);
66
67
67 addr_data <= address;
68 addr_data <= address;
68 nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1);
69 nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1);
69
70
70 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
71 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
71 BEGIN
72 BEGIN
72 IF HRESETn = '0' THEN
73 IF HRESETn = '0' THEN
73 state <= IDLE;
74 state <= IDLE;
74 address <= (OTHERS => '0');
75 address <= (OTHERS => '0');
75 nb_send <= (OTHERS => '0');
76 nb_send <= (OTHERS => '0');
76 status_full <= '0';
77 status_full <= '0';
77 status_full_err <= '0';
78 status_full_err <= '0';
78 update_r <= "00";
79 update_r <= "00";
79 ELSIF HCLK'EVENT AND HCLK = '1' THEN
80 ELSIF HCLK'EVENT AND HCLK = '1' THEN
80 update_r <= update;
81 update_r <= update;
81 CASE state IS
82 CASE state IS
82 WHEN IDLE =>
83 WHEN IDLE =>
83 IF update_s = '1' THEN
84 IF enable = '0' THEN
85 state <= UPDATED;
86 elsIF update_s = '1' THEN
84 state <= ADD;
87 state <= ADD;
85 END IF;
88 END IF;
86
89
87 WHEN ADD =>
90 WHEN ADD =>
88 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
91 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
89 state <= IDLE;
92 state <= IDLE;
90 IF update_r = "10" THEN
93 IF update_r = "10" THEN
91 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
94 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
92 nb_send <= nb_send_next;
95 nb_send <= nb_send_next;
93 ELSIF update_r = "01" THEN
96 ELSIF update_r = "01" THEN
94 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
97 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
95 END IF;
98 END IF;
96 ELSE
99 ELSE
97 state <= FULL;
100 state <= FULL;
98 nb_send <= (OTHERS => '0');
101 nb_send <= (OTHERS => '0');
99 status_full <= '1';
102 status_full <= '1';
100 END IF;
103 END IF;
101
104
102 WHEN FULL =>
105 WHEN FULL =>
103 status_full <= '0';
106 status_full <= '0';
104 IF status_full_ack = '1' THEN
107 IF status_full_ack = '1' THEN
105 IF update_s = '1' THEN
108 IF update_s = '1' THEN
106 status_full_err <= '1';
109 status_full_err <= '1';
107 END IF;
110 END IF;
108 state <= UPDATED;
111 state <= UPDATED;
109 ELSE
112 ELSE
110 IF update_s = '1' THEN
113 IF update_s = '1' THEN
111 status_full_err <= '1';
114 status_full_err <= '1';
112 state <= ERR;
115 state <= ERR;
113 END IF;
116 END IF;
114 END IF;
117 END IF;
115
118
116 WHEN ERR =>
119 WHEN ERR =>
117 status_full_err <= '0';
120 status_full_err <= '0';
118 IF status_full_ack = '1' THEN
121 IF status_full_ack = '1' THEN
119 state <= UPDATED;
122 state <= UPDATED;
120 END IF;
123 END IF;
121
124
122 WHEN UPDATED =>
125 WHEN UPDATED =>
123 status_full_err <= '0';
126 status_full_err <= '0';
124 state <= IDLE;
125 address <= addr_data_reg;
127 address <= addr_data_reg;
128 IF enable = '1' THEN
129 state <= IDLE;
130 END IF;
126
131
127 WHEN OTHERS => NULL;
132 WHEN OTHERS => NULL;
128 END CASE;
133 END CASE;
129 END IF;
134 END IF;
130 END PROCESS FSM_SELECT_ADDRESS;
135 END PROCESS FSM_SELECT_ADDRESS;
131
136
132 END Behavioral;
137 END Behavioral;
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@@ -1,176 +1,177
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
29
30 LIBRARY techmap;
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
31 USE techmap.gencomp.ALL;
32
32
33 ENTITY lpp_waveform_fifo IS
33 ENTITY lpp_waveform_fifo IS
34 GENERIC(
34 GENERIC(
35 tech : INTEGER := 0
35 tech : INTEGER := 0
36 );
36 );
37 PORT(
37 PORT(
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
42 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
43 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
43
44
44 ---------------------------------------------------------------------------
45 ---------------------------------------------------------------------------
45 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
47 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
47
48
48 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49
50
50 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
51 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53
54
54 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 );
56 );
56 END ENTITY;
57 END ENTITY;
57
58
58
59
59 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
60 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
60
61
61
62
62 SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
63 SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
63 SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
64 SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
64 SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
66 SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
66
67
67 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
68 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
68 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
69 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
69 SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
70 SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
70 SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
71 SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
71
72
72 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
73 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
73 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
74 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
74 SIGNAL ren : STD_LOGIC;
75 SIGNAL ren : STD_LOGIC;
75 SIGNAL wen : STD_LOGIC;
76 SIGNAL wen : STD_LOGIC;
76
77
77 BEGIN
78 BEGIN
78
79
79 SRAM : syncram_2p
80 SRAM : syncram_2p
80 GENERIC MAP(tech, 7, 32)
81 GENERIC MAP(tech, 7, 32)
81 PORT MAP(clk, ren, data_addr_r, rdata,
82 PORT MAP(clk, ren, data_addr_r, rdata,
82 clk, wen, data_addr_w, wdata);
83 clk, wen, data_addr_w, wdata);
83
84
84
85
85 ren <= time_mem_ren(3) OR data_mem_ren(3) OR
86 ren <= time_mem_ren(3) OR data_mem_ren(3) OR
86 time_mem_ren(2) OR data_mem_ren(2) OR
87 time_mem_ren(2) OR data_mem_ren(2) OR
87 time_mem_ren(1) OR data_mem_ren(1) OR
88 time_mem_ren(1) OR data_mem_ren(1) OR
88 time_mem_ren(0) OR data_mem_ren(0);
89 time_mem_ren(0) OR data_mem_ren(0);
89
90
90 wen <= time_mem_wen(3) OR data_mem_wen(3) OR
91 wen <= time_mem_wen(3) OR data_mem_wen(3) OR
91 time_mem_wen(2) OR data_mem_wen(2) OR
92 time_mem_wen(2) OR data_mem_wen(2) OR
92 time_mem_wen(1) OR data_mem_wen(1) OR
93 time_mem_wen(1) OR data_mem_wen(1) OR
93 time_mem_wen(0) OR data_mem_wen(0);
94 time_mem_wen(0) OR data_mem_wen(0);
94
95
95 data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE
96 data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE
96 time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE
97 time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE
97 time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE
98 time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE
98 time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE
99 time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE
99 data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
100 data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
100 data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
101 data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
101 data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
102 data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
102 data_mem_addr_r(3);
103 data_mem_addr_r(3);
103
104
104 data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE
105 data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE
105 time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE
106 time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE
106 time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE
107 time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE
107 time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE
108 time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE
108 data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
109 data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
109 data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
110 data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
110 data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
111 data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
111 data_mem_addr_w(3);
112 data_mem_addr_w(3);
112
113
113 gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE
114 gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE
114 lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl
115 lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl
115 GENERIC MAP (
116 GENERIC MAP (
116 offset => 32*I + 20,
117 offset => 32*I + 20,
117 length => 10,
118 length => 10,
118 enable_ready => '0')
119 enable_ready => '1')
119 PORT MAP (
120 PORT MAP (
120 clk => clk,
121 clk => clk,
121 rstn => rstn,
122 rstn => rstn,
122 ren => time_ren(I),
123 ren => time_ren(I),
123 wen => time_wen(I),
124 wen => time_wen(I),
124 mem_re => time_mem_ren(I),
125 mem_re => time_mem_ren(I),
125 mem_we => time_mem_wen(I),
126 mem_we => time_mem_wen(I),
126 mem_addr_ren => time_mem_addr_r(I),
127 mem_addr_ren => time_mem_addr_r(I),
127 mem_addr_wen => time_mem_addr_w(I),
128 mem_addr_wen => time_mem_addr_w(I),
128 ready => OPEN);
129 ready => time_ready(I));
129 END GENERATE gen_fifo_ctrl_time;
130 END GENERATE gen_fifo_ctrl_time;
130
131
131 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
132 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
132 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
133 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
133 GENERIC MAP (
134 GENERIC MAP (
134 offset => 32*I,
135 offset => 32*I,
135 length => 20,
136 length => 20,
136 enable_ready => '1')
137 enable_ready => '1')
137 PORT MAP (
138 PORT MAP (
138 clk => clk,
139 clk => clk,
139 rstn => rstn,
140 rstn => rstn,
140 ren => data_ren(I),
141 ren => data_ren(I),
141 wen => data_wen(I),
142 wen => data_wen(I),
142 mem_re => data_mem_ren(I),
143 mem_re => data_mem_ren(I),
143 mem_we => data_mem_wen(I),
144 mem_we => data_mem_wen(I),
144 mem_addr_ren => data_mem_addr_r(I),
145 mem_addr_ren => data_mem_addr_r(I),
145 mem_addr_wen => data_mem_addr_w(I),
146 mem_addr_wen => data_mem_addr_w(I),
146 ready => ready(I));
147 ready => data_ready(I));
147 END GENERATE gen_fifo_ctrl_data;
148 END GENERATE gen_fifo_ctrl_data;
148
149
149
150
150 END ARCHITECTURE;
151 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
29
30 LIBRARY techmap;
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
31 USE techmap.gencomp.ALL;
32
32
33 ENTITY lpp_waveform_fifo_ctrl IS
33 ENTITY lpp_waveform_fifo_ctrl IS
34 generic(
34 generic(
35 offset : INTEGER := 0;
35 offset : INTEGER := 0;
36 length : INTEGER := 20;
36 length : INTEGER := 20;
37 enable_ready : STD_LOGIC := '1'
37 enable_ready : STD_LOGIC := '1'
38 );
38 );
39 PORT(
39 PORT(
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42
42
43 ren : IN STD_LOGIC;
43 ren : IN STD_LOGIC;
44 wen : IN STD_LOGIC;
44 wen : IN STD_LOGIC;
45
45
46 mem_re : OUT STD_LOGIC;
46 mem_re : OUT STD_LOGIC;
47 mem_we : OUT STD_LOGIC;
47 mem_we : OUT STD_LOGIC;
48
48
49 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
49 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
50 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
50 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
51
51
52 ready : OUT STD_LOGIC
52 ready : OUT STD_LOGIC
53 );
53 );
54 END ENTITY;
54 END ENTITY;
55
55
56
56
57 ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS
57 ARCHITECTURE ar_lpp_waveform_fifo_ctrl OF lpp_waveform_fifo_ctrl IS
58
58
59 SIGNAL sFull : STD_LOGIC;
59 SIGNAL sFull : STD_LOGIC;
60 SIGNAL sFull_s : STD_LOGIC;
60 SIGNAL sFull_s : STD_LOGIC;
61 SIGNAL sEmpty_s : STD_LOGIC;
61 SIGNAL sEmpty_s : STD_LOGIC;
62
62
63 SIGNAL sEmpty : STD_LOGIC;
63 SIGNAL sEmpty : STD_LOGIC;
64 SIGNAL sREN : STD_LOGIC;
64 SIGNAL sREN : STD_LOGIC;
65 SIGNAL sWEN : STD_LOGIC;
65 SIGNAL sWEN : STD_LOGIC;
66 SIGNAL sRE : STD_LOGIC;
66 SIGNAL sRE : STD_LOGIC;
67 SIGNAL sWE : STD_LOGIC;
67 SIGNAL sWE : STD_LOGIC;
68
68
69 SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0;
69 SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0;
70 SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0;
70 SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0;
71 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
71 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
72 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
72 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
73
73
74 BEGIN
74 BEGIN
75 mem_re <= sRE;
75 mem_re <= sRE;
76 mem_we <= sWE;
76 mem_we <= sWE;
77 --=============================
77 --=============================
78 -- Read section
78 -- Read section
79 --=============================
79 --=============================
80 sREN <= REN OR sEmpty;
80 sREN <= REN OR sEmpty;
81 sRE <= NOT sREN;
81 sRE <= NOT sREN;
82
82
83 sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
83 sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
84 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
84 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
85 '0';
85 '0';
86
86
87 Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ;
87 Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ;
88
88
89 PROCESS (clk, rstn)
89 PROCESS (clk, rstn)
90 BEGIN
90 BEGIN
91 IF(rstn = '0')then
91 IF(rstn = '0')then
92 Raddr_vect <= 0;
92 Raddr_vect <= 0;
93 sempty <= '1';
93 sempty <= '1';
94 ELSIF(clk'EVENT AND clk = '1')then
94 ELSIF(clk'EVENT AND clk = '1')then
95 sEmpty <= sempty_s;
95 sEmpty <= sempty_s;
96
96
97 IF(sREN = '0' and sempty = '0')then
97 IF(sREN = '0' and sempty = '0')then
98 Raddr_vect <= Raddr_vect_s;
98 Raddr_vect <= Raddr_vect_s;
99 END IF;
99 END IF;
100
100
101 END IF;
101 END IF;
102 END PROCESS;
102 END PROCESS;
103
103
104 --=============================
104 --=============================
105 -- Write section
105 -- Write section
106 --=============================
106 --=============================
107 sWEN <= WEN OR sFull;
107 sWEN <= WEN OR sFull;
108 sWE <= NOT sWEN;
108 sWE <= NOT sWEN;
109
109
110 sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
110 sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
111 '1' WHEN sFull = '1' AND REN = '1' ELSE
111 '1' WHEN sFull = '1' AND REN = '1' ELSE
112 '0';
112 '0';
113
113
114 Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ;
114 Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ;
115
115
116 PROCESS (clk, rstn)
116 PROCESS (clk, rstn)
117 BEGIN
117 BEGIN
118 IF(rstn = '0')then
118 IF(rstn = '0')then
119 Waddr_vect <= 0;
119 Waddr_vect <= 0;
120 sfull <= '0';
120 sfull <= '0';
121 ELSIF(clk'EVENT AND clk = '1')then
121 ELSIF(clk'EVENT AND clk = '1')then
122 sfull <= sfull_s;
122 sfull <= sfull_s;
123
123
124 IF(sWEN = '0' and sfull = '0')THEN
124 IF(sWEN = '0' and sfull = '0')THEN
125 Waddr_vect <= Waddr_vect_s;
125 Waddr_vect <= Waddr_vect_s;
126 END IF;
126 END IF;
127
127
128 END IF;
128 END IF;
129 END PROCESS;
129 END PROCESS;
130
130
131
131
132 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
132 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
133 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
133 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
134
134
135 ready_gen: IF enable_ready = '1' GENERATE
135 ready_gen: IF enable_ready = '1' GENERATE
136 ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
136 ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
137 '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
137 '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
138 '0';
138 '0';
139 END GENERATE ready_gen;
139 END GENERATE ready_gen;
140
140
141 ready_not_gen: IF enable_ready = '0' GENERATE
141 ready_not_gen: IF enable_ready = '0' GENERATE
142 ready <= '0';
142 ready <= '0';
143 END GENERATE ready_not_gen;
143 END GENERATE ready_not_gen;
144
144
145 END ARCHITECTURE;
145 END ARCHITECTURE;
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1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
6 USE grlib.stdlib.ALL;
7 USE grlib.devices.ALL;
7 USE grlib.devices.ALL;
8 USE GRLIB.DMA2AHB_Package.ALL;
8 USE GRLIB.DMA2AHB_Package.ALL;
9
9
10 LIBRARY techmap;
10 LIBRARY techmap;
11 USE techmap.gencomp.ALL;
11 USE techmap.gencomp.ALL;
12
12
13 PACKAGE lpp_waveform_pkg IS
13 PACKAGE lpp_waveform_pkg IS
14
14
15 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
15 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
16
16
17 COMPONENT lpp_waveform_snapshot
17 COMPONENT lpp_waveform_snapshot
18 GENERIC (
18 GENERIC (
19 data_size : INTEGER;
19 data_size : INTEGER;
20 nb_snapshot_param_size : INTEGER);
20 nb_snapshot_param_size : INTEGER);
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 enable : IN STD_LOGIC;
24 enable : IN STD_LOGIC;
25 burst_enable : IN STD_LOGIC;
25 burst_enable : IN STD_LOGIC;
26 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
26 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
27 start_snapshot : IN STD_LOGIC;
27 start_snapshot : IN STD_LOGIC;
28 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
28 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
29 data_in_valid : IN STD_LOGIC;
29 data_in_valid : IN STD_LOGIC;
30 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
30 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
31 data_out_valid : OUT STD_LOGIC);
31 data_out_valid : OUT STD_LOGIC);
32 END COMPONENT;
32 END COMPONENT;
33
33
34 COMPONENT lpp_waveform_burst
34 COMPONENT lpp_waveform_burst
35 GENERIC (
35 GENERIC (
36 data_size : INTEGER);
36 data_size : INTEGER);
37 PORT (
37 PORT (
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 enable : IN STD_LOGIC;
40 enable : IN STD_LOGIC;
41 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
41 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
42 data_in_valid : IN STD_LOGIC;
43 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
43 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
44 data_out_valid : OUT STD_LOGIC);
44 data_out_valid : OUT STD_LOGIC);
45 END COMPONENT;
45 END COMPONENT;
46
46
47 COMPONENT lpp_waveform_snapshot_controler
47 COMPONENT lpp_waveform_snapshot_controler
48 GENERIC (
48 GENERIC (
49 delta_snapshot_size : INTEGER;
49 delta_snapshot_size : INTEGER;
50 delta_f2_f0_size : INTEGER;
50 delta_f2_f0_size : INTEGER;
51 delta_f2_f1_size : INTEGER);
51 delta_f2_f1_size : INTEGER);
52 PORT (
52 PORT (
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
55 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
56 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
56 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
57 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
57 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
58 coarse_time_0 : IN STD_LOGIC;
58 coarse_time_0 : IN STD_LOGIC;
59 data_f0_in_valid : IN STD_LOGIC;
59 data_f0_in_valid : IN STD_LOGIC;
60 data_f2_in_valid : IN STD_LOGIC;
60 data_f2_in_valid : IN STD_LOGIC;
61 start_snapshot_f0 : OUT STD_LOGIC;
61 start_snapshot_f0 : OUT STD_LOGIC;
62 start_snapshot_f1 : OUT STD_LOGIC;
62 start_snapshot_f1 : OUT STD_LOGIC;
63 start_snapshot_f2 : OUT STD_LOGIC);
63 start_snapshot_f2 : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66
66
67
67
68 COMPONENT lpp_waveform
68 COMPONENT lpp_waveform
69 GENERIC (
69 GENERIC (
70 hindex : INTEGER;
70 hindex : INTEGER;
71 tech : INTEGER;
71 tech : INTEGER;
72 data_size : INTEGER;
72 data_size : INTEGER;
73 nb_burst_available_size : INTEGER;
73 nb_burst_available_size : INTEGER;
74 nb_snapshot_param_size : INTEGER;
74 nb_snapshot_param_size : INTEGER;
75 delta_snapshot_size : INTEGER;
75 delta_snapshot_size : INTEGER;
76 delta_f2_f0_size : INTEGER;
76 delta_f2_f0_size : INTEGER;
77 delta_f2_f1_size : INTEGER);
77 delta_f2_f1_size : INTEGER);
78 PORT (
78 PORT (
79 clk : IN STD_LOGIC;
79 clk : IN STD_LOGIC;
80 rstn : IN STD_LOGIC;
80 rstn : IN STD_LOGIC;
81 AHB_Master_In : IN AHB_Mst_In_Type;
81 AHB_Master_In : IN AHB_Mst_In_Type;
82 AHB_Master_Out : OUT AHB_Mst_Out_Type;
82 AHB_Master_Out : OUT AHB_Mst_Out_Type;
83 coarse_time_0 : IN STD_LOGIC;
83 coarse_time_0 : IN STD_LOGIC;
84 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
84 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
85 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
85 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
86 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
86 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
87 enable_f0 : IN STD_LOGIC;
87 enable_f0 : IN STD_LOGIC;
88 enable_f1 : IN STD_LOGIC;
88 enable_f1 : IN STD_LOGIC;
89 enable_f2 : IN STD_LOGIC;
89 enable_f2 : IN STD_LOGIC;
90 enable_f3 : IN STD_LOGIC;
90 enable_f3 : IN STD_LOGIC;
91 burst_f0 : IN STD_LOGIC;
91 burst_f0 : IN STD_LOGIC;
92 burst_f1 : IN STD_LOGIC;
92 burst_f1 : IN STD_LOGIC;
93 burst_f2 : IN STD_LOGIC;
93 burst_f2 : IN STD_LOGIC;
94 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
94 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
95 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
95 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
96 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
98 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
108 data_f0_in_valid : IN STD_LOGIC;
108 data_f0_in_valid : IN STD_LOGIC;
109 data_f1_in_valid : IN STD_LOGIC;
109 data_f1_in_valid : IN STD_LOGIC;
110 data_f2_in_valid : IN STD_LOGIC;
110 data_f2_in_valid : IN STD_LOGIC;
111 data_f3_in_valid : IN STD_LOGIC);
111 data_f3_in_valid : IN STD_LOGIC);
112 END COMPONENT;
112 END COMPONENT;
113
113
114 COMPONENT lpp_waveform_dma_send_Nword
114 COMPONENT lpp_waveform_dma_send_Nword
115 PORT (
115 PORT (
116 HCLK : IN STD_ULOGIC;
116 HCLK : IN STD_ULOGIC;
117 HRESETn : IN STD_ULOGIC;
117 HRESETn : IN STD_ULOGIC;
118 DMAIn : OUT DMA_In_Type;
118 DMAIn : OUT DMA_In_Type;
119 DMAOut : IN DMA_OUt_Type;
119 DMAOut : IN DMA_OUt_Type;
120 Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
120 Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
121 send : IN STD_LOGIC;
121 send : IN STD_LOGIC;
122 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 ren : OUT STD_LOGIC;
124 ren : OUT STD_LOGIC;
125 send_ok : OUT STD_LOGIC;
125 send_ok : OUT STD_LOGIC;
126 send_ko : OUT STD_LOGIC);
126 send_ko : OUT STD_LOGIC);
127 END COMPONENT;
127 END COMPONENT;
128
128
129 COMPONENT lpp_waveform_dma_selectaddress
129 COMPONENT lpp_waveform_dma_selectaddress
130 GENERIC (
130 GENERIC (
131 nb_burst_available_size : INTEGER);
131 nb_burst_available_size : INTEGER);
132 PORT (
132 PORT (
133 HCLK : IN STD_ULOGIC;
133 HCLK : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
135 enable : IN STD_LOGIC;
135 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
136 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
136 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
137 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
137 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 status_full : OUT STD_LOGIC;
140 status_full : OUT STD_LOGIC;
140 status_full_ack : IN STD_LOGIC;
141 status_full_ack : IN STD_LOGIC;
141 status_full_err : OUT STD_LOGIC);
142 status_full_err : OUT STD_LOGIC);
142 END COMPONENT;
143 END COMPONENT;
143
144
144 COMPONENT lpp_waveform_dma_gen_valid
145 COMPONENT lpp_waveform_dma_gen_valid
145 PORT (
146 PORT (
146 HCLK : IN STD_LOGIC;
147 HCLK : IN STD_LOGIC;
147 HRESETn : IN STD_LOGIC;
148 HRESETn : IN STD_LOGIC;
148 valid_in : IN STD_LOGIC;
149 valid_in : IN STD_LOGIC;
149 ack_in : IN STD_LOGIC;
150 ack_in : IN STD_LOGIC;
150 valid_out : OUT STD_LOGIC;
151 valid_out : OUT STD_LOGIC;
151 error : OUT STD_LOGIC);
152 error : OUT STD_LOGIC);
152 END COMPONENT;
153 END COMPONENT;
153
154
154 COMPONENT lpp_waveform_dma
155 COMPONENT lpp_waveform_dma
155 GENERIC (
156 GENERIC (
156 data_size : INTEGER;
157 data_size : INTEGER;
157 tech : INTEGER;
158 tech : INTEGER;
158 hindex : INTEGER;
159 hindex : INTEGER;
159 nb_burst_available_size : INTEGER);
160 nb_burst_available_size : INTEGER);
160 PORT (
161 PORT (
161 HCLK : IN STD_ULOGIC;
162 HCLK : IN STD_ULOGIC;
162 HRESETn : IN STD_ULOGIC;
163 HRESETn : IN STD_ULOGIC;
163 AHB_Master_In : IN AHB_Mst_In_Type;
164 AHB_Master_In : IN AHB_Mst_In_Type;
164 AHB_Master_Out : OUT AHB_Mst_Out_Type;
165 AHB_Master_Out : OUT AHB_Mst_Out_Type;
166 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
167 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
165 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
168 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
166 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
170 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
168 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
171 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
169 --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
171 --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 --data_f0_in_valid : IN STD_LOGIC;
176 --data_f0_in_valid : IN STD_LOGIC;
174 --data_f1_in_valid : IN STD_LOGIC;
177 --data_f1_in_valid : IN STD_LOGIC;
175 --data_f2_in_valid : IN STD_LOGIC;
178 --data_f2_in_valid : IN STD_LOGIC;
176 --data_f3_in_valid : IN STD_LOGIC;
179 --data_f3_in_valid : IN STD_LOGIC;
177 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
180 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
178 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
181 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
182 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
180 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
183 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
181 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
184 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
182 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
187 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
188 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
186 END COMPONENT;
189 END COMPONENT;
187
190
188 COMPONENT lpp_waveform_fifo_ctrl
191 COMPONENT lpp_waveform_fifo_ctrl
189 GENERIC (
192 GENERIC (
190 offset : INTEGER;
193 offset : INTEGER;
191 length : INTEGER;
194 length : INTEGER;
192 enable_ready : STD_LOGIC);
195 enable_ready : STD_LOGIC);
193 PORT (
196 PORT (
194 clk : IN STD_LOGIC;
197 clk : IN STD_LOGIC;
195 rstn : IN STD_LOGIC;
198 rstn : IN STD_LOGIC;
196 ren : IN STD_LOGIC;
199 ren : IN STD_LOGIC;
197 wen : IN STD_LOGIC;
200 wen : IN STD_LOGIC;
198 mem_re : OUT STD_LOGIC;
201 mem_re : OUT STD_LOGIC;
199 mem_we : OUT STD_LOGIC;
202 mem_we : OUT STD_LOGIC;
200 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
203 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
201 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
204 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
202 ready : OUT STD_LOGIC);
205 ready : OUT STD_LOGIC);
203 END COMPONENT;
206 END COMPONENT;
204
207
205 COMPONENT lpp_waveform_fifo_arbiter
208 COMPONENT lpp_waveform_fifo_arbiter
206 GENERIC (
209 GENERIC (
207 tech : INTEGER);
210 tech : INTEGER);
208 PORT (
211 PORT (
209 clk : IN STD_LOGIC;
212 clk : IN STD_LOGIC;
210 rstn : IN STD_LOGIC;
213 rstn : IN STD_LOGIC;
211 data_f0_valid : IN STD_LOGIC;
214 data_f0_valid : IN STD_LOGIC;
212 data_f1_valid : IN STD_LOGIC;
215 data_f1_valid : IN STD_LOGIC;
213 data_f2_valid : IN STD_LOGIC;
216 data_f2_valid : IN STD_LOGIC;
214 data_f3_valid : IN STD_LOGIC;
217 data_f3_valid : IN STD_LOGIC;
215 data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
218 data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
216 data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
219 data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
217 data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
220 data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
218 data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
221 data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
219 data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
222 data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
220 ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
223 ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
221 time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
224 time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
222 data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
225 data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
223 data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
226 data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
224 END COMPONENT;
227 END COMPONENT;
225
228
226 COMPONENT lpp_waveform_fifo
229 COMPONENT lpp_waveform_fifo
227 GENERIC (
230 GENERIC (
228 tech : INTEGER);
231 tech : INTEGER);
229 PORT (
232 PORT (
230 clk : IN STD_LOGIC;
233 clk : IN STD_LOGIC;
231 rstn : IN STD_LOGIC;
234 rstn : IN STD_LOGIC;
232 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
235 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
236 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
237 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
238 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
235 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
236 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
237 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
241 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
238 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
242 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
239 END COMPONENT;
243 END COMPONENT;
240
244
241
245
242
246
243 END lpp_waveform_pkg;
247 END lpp_waveform_pkg;
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