diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt --- a/lib/lpp/dsp/iir_filter/vhdlsyn.txt +++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt @@ -2,6 +2,7 @@ iir_filter.vhd FILTERcfg.vhd RAM.vhd RAM_CEL.vhd +RAM_CEL_N.vhd RAM_CTRLR_v2.vhd IIR_CEL_CTRLR_v2_CONTROL.vhd IIR_CEL_CTRLR_v2_DATAFLOW.vhd diff --git a/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd b/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY lpp; +USE lpp.general_purpose.ALL; + +ENTITY SYNC_VALID_BIT IS + GENERIC ( + NB_FF_OF_SYNC : INTEGER := 2); + PORT ( + clk_in : IN STD_LOGIC; + clk_out : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); +END SYNC_VALID_BIT; + +ARCHITECTURE beh OF SYNC_VALID_BIT IS + SIGNAL s_1 : STD_LOGIC; + SIGNAL s_2 : STD_LOGIC; +BEGIN -- beh + + lpp_front_to_level_1: lpp_front_to_level + PORT MAP ( + clk => clk_in, + rstn => rstn, + sin => sin, + sout => s_1); + + SYNC_FF_1: SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => NB_FF_OF_SYNC) + PORT MAP ( + clk => clk_out, + rstn => rstn, + A => s_1, + A_sync => s_2); + + lpp_front_detection_1: lpp_front_detection + PORT MAP ( + clk => clk_out, + rstn => rstn, + sin => s_2, + sout => sout); + +END beh; diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -269,4 +269,31 @@ Constant ctrl_CLRMAC : std_logic_vector( A_sync : OUT STD_LOGIC); END COMPONENT; + COMPONENT lpp_front_to_level + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_front_detection + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT SYNC_VALID_BIT + GENERIC ( + NB_FF_OF_SYNC : INTEGER); + PORT ( + clk_in : IN STD_LOGIC; + clk_out : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + END COMPONENT; + END; diff --git a/lib/lpp/general_purpose/lpp_front_detection.vhd b/lib/lpp/general_purpose/lpp_front_detection.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/lpp_front_detection.vhd @@ -0,0 +1,59 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY lpp_front_detection IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + +END lpp_front_detection; + +ARCHITECTURE beh OF lpp_front_detection IS + + SIGNAL reg : STD_LOGIC; + SIGNAL sout_reg : STD_LOGIC; + +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + reg <= '0'; + sout_reg <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + reg <= sin; + IF sin = NOT reg THEN + sout_reg <= '1'; + ELSE + sout_reg <= '0'; + END IF; + END IF; + END PROCESS; + + sout <= sout_reg; + +END beh; diff --git a/lib/lpp/general_purpose/lpp_front_to_level.vhd b/lib/lpp/general_purpose/lpp_front_to_level.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/general_purpose/lpp_front_to_level.vhd @@ -0,0 +1,57 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY lpp_front_to_level IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + +END lpp_front_to_level; + +ARCHITECTURE beh OF lpp_front_to_level IS + + SIGNAL reg : STD_LOGIC; + + SIGNAL sout_reg : STD_LOGIC; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + reg <= '0'; + sout_reg <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + reg <= sin; + IF sin = '1' AND reg = '0' THEN + sout_reg <= NOT sout_reg; + END IF; + END IF; + END PROCESS; + + sout <= sout_reg; + +END beh; diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -16,3 +16,7 @@ REG.vhd SYNC_FF.vhd Shifter.vhd TwoComplementer.vhd +lpp_front_to_level.vhd +lpp_front_detection.vhd +SYNC_VALID_BIT.vhd + diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -26,29 +26,28 @@ USE grlib.stdlib.ALL; USE grlib.devices.ALL; LIBRARY lpp; USE lpp.apb_devices_list.ALL; +USE lpp.general_purpose.ALL; USE lpp.lpp_lfr_time_management.ALL; ENTITY apb_lfr_time_management IS GENERIC( - pindex : INTEGER := 0; --! APB slave index - paddr : INTEGER := 0; --! ADDR field of the APB BAR - pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR - pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used - masterclk : INTEGER := 25000000; --! master clock in Hz - timeclk : INTEGER := 49152000; --! other clock in Hz - finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used ); PORT ( - clk25MHz : IN STD_LOGIC; --! Clock - clk49_152MHz : IN STD_LOGIC; --! secondary clock - resetn : IN STD_LOGIC; --! Reset - grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : IN apb_slv_in_type; --! APB slave input signals - apbo : OUT apb_slv_out_type; --! APB slave output signals - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time - fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time ); END apb_lfr_time_management; @@ -56,91 +55,83 @@ END apb_lfr_time_management; ARCHITECTURE Behavioral OF apb_lfr_time_management IS CONSTANT REVISION : INTEGER := 1; - ---! the following types are defined in the grlib amba package ---! subtype amba_config_word is std_logic_vector(31 downto 0); ---! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; CONSTANT pconfig : apb_config_type := ( ---! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); + 1 => apb_iobar(paddr, pmask) + ); TYPE apb_lfr_time_management_Reg IS RECORD ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); END RECORD; - SIGNAL r : apb_lfr_time_management_Reg; - SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL force_tick : STD_LOGIC; - SIGNAL previous_force_tick : STD_LOGIC; - SIGNAL soft_tick : STD_LOGIC; --- SIGNAL reset_next_commutation : STD_LOGIC; - + SIGNAL r : apb_lfr_time_management_Reg; + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL force_tick : STD_LOGIC; + SIGNAL previous_force_tick : STD_LOGIC; + SIGNAL soft_tick : STD_LOGIC; + SIGNAL irq1 : STD_LOGIC; SIGNAL irq2 : STD_LOGIC; -BEGIN + SIGNAL coarsetime_reg_updated : STD_LOGIC; + SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - lfrtimemanagement0 : lfr_time_management - GENERIC MAP( - masterclk => masterclk, - timeclk => timeclk, - finetimeclk => finetimeclk, - nb_clk_div_ticks => 1) - PORT MAP( - master_clock => clk25MHz, - time_clock => clk49_152MHz, - resetn => resetn, - grspw_tick => grspw_tick, - soft_tick => soft_tick, - coarse_time_load => r.coarse_time_load, - coarse_time => r.coarse_time, - fine_time => r.fine_time, - next_commutation => r.next_commutation, --- reset_next_commutation => reset_next_commutation, - irq1 => irq1,--apbo.pirq(pirq), - irq2 => irq2);--apbo.pirq(pirq+1)); + SIGNAL coarse_time_new : STD_LOGIC; + SIGNAL coarse_time_new_49 : STD_LOGIC; + SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL fine_time_new : STD_LOGIC; + SIGNAL fine_time_new_temp : STD_LOGIC; + SIGNAL fine_time_new_49 : STD_LOGIC; + SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL tick : STD_LOGIC; + SIGNAL new_timecode : STD_LOGIC; + SIGNAL new_coarsetime : STD_LOGIC; + +BEGIN + ----------------------------------------------------------------------------- + -- TODO + -- IRQ 1 & 2 + ----------------------------------------------------------------------------- + irq2 <= '0'; + irq1 <= '0'; - --apbo.pirq <= (OTHERS => '0'); + + --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE + --irq1_gen : IF I = pirq GENERATE + apbo.pirq(pirq) <= irq1; + --END GENERATE irq1_gen; + --irq2_gen : IF I = pirq+1 GENERATE + apbo.pirq(pirq+1) <= irq2; + -- END GENERATE irq2_gen; + -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE + -- apbo.pirq(I) <= '0'; + -- END GENERATE others_irq; + --END GENERATE all_irq_gen; - all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE - irq1_gen: IF I = pirq GENERATE - apbo.pirq(I) <= irq1; - END GENERATE irq1_gen; - irq2_gen: IF I = pirq+1 GENERATE - apbo.pirq(I) <= irq2; - END GENERATE irq2_gen; - others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE - apbo.pirq(I) <= '0'; - END GENERATE others_irq; - END GENERATE all_irq_gen; - - --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE - --END GENERATE all_irq_sig; - - PROCESS(resetn, clk25MHz)--, reset_next_commutation) + PROCESS(resetn, clk25MHz) BEGIN IF resetn = '0' THEN - Rdata <= (OTHERS => '0'); + Rdata <= (OTHERS => '0'); r.coarse_time_load <= x"80000000"; r.ctrl <= x"00000000"; - r.next_commutation <= x"ffffffff"; force_tick <= '0'; previous_force_tick <= '0'; soft_tick <= '0'; - --ELSIF reset_next_commutation = '1' THEN - -- r.next_commutation <= x"ffffffff"; + coarsetime_reg_updated <= '0'; ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN + coarsetime_reg_updated <= '0'; + force_tick <= r.ctrl(0); previous_force_tick <= force_tick; - force_tick <= r.ctrl(0); IF (previous_force_tick = '0') AND (force_tick = '1') THEN soft_tick <= '1'; ELSE @@ -154,10 +145,8 @@ BEGIN r.ctrl <= apbi.pwdata(31 DOWNTO 0); WHEN "000001" => r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); - WHEN "000100" => - r.next_commutation <= apbi.pwdata(31 DOWNTO 0); + coarsetime_reg_updated <= '1'; WHEN OTHERS => - r.coarse_time_load <= x"00000000"; END CASE; ELSIF r.ctrl(0) = '1' THEN r.ctrl(0) <= '0'; @@ -167,30 +156,14 @@ BEGIN IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN CASE apbi.paddr(7 DOWNTO 2) IS WHEN "000000" => - Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0); + Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0); WHEN "000001" => - Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0); + Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); WHEN "000010" => - Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0); + Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); WHEN "000011" => - Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0); - WHEN "000100" => - Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24); - Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16); - Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8); - Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0); + Rdata(31 DOWNTO 16) <= (OTHERS => '0'); + Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); WHEN OTHERS => Rdata(31 DOWNTO 0) <= x"00000000"; END CASE; @@ -199,10 +172,115 @@ BEGIN END IF; END PROCESS; - apbo.prdata <= Rdata ;--WHEN apbi.penable = '1'; + apbo.prdata <= Rdata; + apbo.pconfig <= pconfig; + apbo.pindex <= pindex; + coarse_time <= r.coarse_time; fine_time <= r.fine_time; - apbo.pconfig <= pconfig; - apbo.pindex <= pindex; + ----------------------------------------------------------------------------- + + coarsetime_reg <= r.coarse_time_load; + r.coarse_time <= coarse_time_s; + r.fine_time <= fine_time_s; + ----------------------------------------------------------------------------- + -- IN coarsetime_reg_updated + -- IN coarsetime_reg + + -- OUT coarse_time_s -- ok + -- OUT fine_time_s -- ok + ----------------------------------------------------------------------------- + + tick <= grspw_tick OR soft_tick; + + SYNC_VALID_BIT_1 : SYNC_VALID_BIT + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk25MHz, + clk_out => clk49_152MHz, + rstn => resetn, + sin => tick, + sout => new_timecode); + + SYNC_VALID_BIT_2 : SYNC_VALID_BIT + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk25MHz, + clk_out => clk49_152MHz, + rstn => resetn, + sin => coarsetime_reg_updated, + sout => new_coarsetime); + + --SYNC_VALID_BIT_3 : SYNC_VALID_BIT + -- GENERIC MAP ( + -- NB_FF_OF_SYNC => 2) + -- PORT MAP ( + -- clk_in => clk49_152MHz, + -- clk_out => clk25MHz, + -- rstn => resetn, + -- sin => 9, + -- sout => ); + + SYNC_FF_1: SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk25MHz, + rstn => resetn, + A => fine_time_new_49, + A_sync => fine_time_new_temp); + + lpp_front_detection_1: lpp_front_detection + PORT MAP ( + clk => clk25MHz, + rstn => resetn, + sin => fine_time_new_temp, + sout => fine_time_new); + + SYNC_VALID_BIT_4 : SYNC_VALID_BIT + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk49_152MHz, + clk_out => clk25MHz, + rstn => resetn, + sin => coarse_time_new_49, + sout => coarse_time_new); + + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + fine_time_s <= (OTHERS => '0'); + coarse_time_s <= (OTHERS => '0'); + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge + IF fine_time_new = '1' THEN + fine_time_s <= fine_time_49; + END IF; + IF coarse_time_new = '1' THEN + coarse_time_s <= coarse_time_49; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- LFR_TIME_MANAGMENT + ----------------------------------------------------------------------------- + lfr_time_management_1 : lfr_time_management + GENERIC MAP ( + nb_time_code_missing_limit => 60) + PORT MAP ( + clk => clk49_152MHz, + rstn => resetn, + + new_timecode => new_timecode, + new_coarsetime => new_coarsetime, + coarsetime_reg => coarsetime_reg, + + fine_time => fine_time_49, + fine_time_new => fine_time_new_49, + coarse_time => coarse_time_49, + coarse_time_new => coarse_time_new_49); END Behavioral; diff --git a/lib/lpp/lfr_time_management/lfr_time_management.vhd b/lib/lpp/lfr_time_management/lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lfr_time_management.vhd @@ -21,247 +21,83 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; LIBRARY lpp; -USE lpp.general_purpose.Clk_divider; +USE lpp.lpp_lfr_time_management.ALL; ENTITY lfr_time_management IS GENERIC ( - masterclk : INTEGER := 25000000; -- master clock in Hz - timeclk : INTEGER := 49152000; -- 2nd clock in Hz - finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter - nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state + nb_time_code_missing_limit : INTEGER := 60 ); PORT ( - master_clock : IN STD_LOGIC; --! Clock -- 25MHz - time_clock : IN STD_LOGIC; --! 2nd Clock -- 49MHz - resetn : IN STD_LOGIC; --! Reset - grspw_tick : IN STD_LOGIC; - soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value -- 25MHz - coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz - fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz - next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz --- reset_next_commutation : OUT STD_LOGIC; - irq1 : OUT STD_LOGIC; -- 25MHz - irq2 : OUT STD_LOGIC -- 25MHz + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + new_timecode : IN STD_LOGIC; -- transition signal information + new_coarsetime : IN STD_LOGIC; -- transition signal information + coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fine_time_new : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_new : OUT STD_LOGIC ); END lfr_time_management; ARCHITECTURE Behavioral OF lfr_time_management IS - SIGNAL resetn_clk_div : STD_LOGIC; - SIGNAL clk_div : STD_LOGIC; --- - SIGNAL flag : STD_LOGIC; - SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL cpt : INTEGER RANGE 0 TO 100000; - SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000; --- - SIGNAL sirq1 : STD_LOGIC; - SIGNAL sirq2 : STD_LOGIC; - SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000; - SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL p_clk_div : STD_LOGIC; --- - TYPE state_type IS (auto, slave); - SIGNAL state : state_type; - TYPE timer_type IS (idle, engaged); - SIGNAL commutation_timer : timer_type; + SIGNAL counter_clear : STD_LOGIC; + SIGNAL counter_full : STD_LOGIC; + SIGNAL nb_time_code_missing : INTEGER; + SIGNAL coarse_time_s : INTEGER; + BEGIN - ---******************************************* --- COMMUTATION TIMER AND INTERRUPT GENERATION - PROCESS(master_clock, resetn) - BEGIN + + lpp_counter_1 : lpp_counter + GENERIC MAP ( + nb_wait_period => 750, + nb_bit_of_data => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + clear => counter_clear, + full => counter_full, + data => fine_time, + new_data => fine_time_new); - IF resetn = '0' THEN - commutation_timer <= idle; - cpt_next_commutation <= 0; - sirq1 <= '0'; - sirq2 <= '0'; - latched_next_commutation <= x"ffffffff"; - p_next_commutation <= (others => '0'); - p_clk_div <= '0'; - ELSIF master_clock'EVENT AND master_clock = '1' THEN - - CASE commutation_timer IS - - WHEN idle => - sirq1 <= '0'; - sirq2 <= '0'; - IF s_coarse_time = latched_next_commutation THEN - commutation_timer <= engaged; -- transition to state "engaged" - sirq1 <= '1'; -- start the pulse on sirq1 - latched_next_commutation <= x"ffffffff"; - ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed - latched_next_commutation <= next_commutation; -- latch the value + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + nb_time_code_missing <= 0; + counter_clear <= '0'; + coarse_time_s <= 0; + coarse_time_new <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF new_timecode = '1' THEN + coarse_time_new <= '1'; + IF new_coarsetime = '1' THEN + coarse_time_s <= to_integer(unsigned(coarsetime_reg)); + ELSE + coarse_time_s <= coarse_time_s + 1; + END IF; + nb_time_code_missing <= 0; + counter_clear <= '1'; + ELSE + coarse_time_new <= '0'; + counter_clear <= '0'; + IF counter_full = '1' THEN + coarse_time_new <= '1'; + coarse_time_s <= coarse_time_s + 1; + IF nb_time_code_missing = nb_time_code_missing_limit THEN + nb_time_code_missing <= nb_time_code_missing_limit; ELSE - commutation_timer <= idle; + nb_time_code_missing <= nb_time_code_missing + 1; END IF; - - WHEN engaged => - sirq1 <= '0'; -- stop the pulse on sirq1 - IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge - IF cpt_next_commutation = 65536 THEN - cpt_next_commutation <= 0; - commutation_timer <= idle; - sirq2 <= '1'; -- start the pulse on sirq2 - ELSE - cpt_next_commutation <= cpt_next_commutation + 1; - END IF; - END IF; - - WHEN OTHERS => - commutation_timer <= idle; - - END CASE; - - p_next_commutation <= next_commutation; - p_clk_div <= clk_div; - + END IF; + END IF; END IF; - END PROCESS; - irq1 <= sirq1; - irq2 <= sirq2; --- reset_next_commutation <= '0'; - --- ---******************************************* - ---********************** --- synchronization stage - PROCESS(master_clock, resetn) -- resynchronisation with clk - BEGIN - - IF resetn = '0' THEN - coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset - - ELSIF master_clock'EVENT AND master_clock = '1' THEN - coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk - END IF; - - END PROCESS; --- ---********************** - - - -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC - PROCESS(clk_div, resetn) -- JC - BEGIN - - IF resetn = '0' THEN - flag <= '0'; - cpt <= 0; - secondary_cpt <= 0; - s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset - previous_coarse_time_load <= x"80000000"; - state <= auto; - - --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN - -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode - -- -- s_coarse_time <= coarse_time_load; - -- -- flag <= '0'; - -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously - -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); - -- --END IF; - - -- cpt <= 0; - -- secondary_cpt <= 0; - -- state <= slave; - - ELSIF clk_div'EVENT AND clk_div = '1' THEN - - CASE state IS - - WHEN auto => - IF grspw_tick = '1' OR soft_tick = '1' THEN - IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode - s_coarse_time <= coarse_time_load; - ELSE -- if coarse_time_load has not changed, increment the value autonomously - s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); - END IF; - flag <= '0'; - cpt <= 0; - secondary_cpt <= 0; - state <= slave; - ELSE - IF cpt = 65535 THEN - IF flag = '1' THEN - s_coarse_time <= coarse_time_load; - flag <= '0'; - ELSE - s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); - END IF; - cpt <= 0; - secondary_cpt <= secondary_cpt + 1; - ELSE - cpt <= cpt + 1; - END IF; - END IF; - - WHEN slave => - IF grspw_tick = '1' OR soft_tick = '1' THEN - IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode - s_coarse_time <= coarse_time_load; - ELSE -- if coarse_time_load has not changed, increment the value autonomously - s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); - END IF; - flag <= '0'; - cpt <= 0; - secondary_cpt <= 0; - state <= slave; - ELSE - IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us - state <= auto; -- commutation to AUTO state - IF flag = '1' THEN - s_coarse_time <= coarse_time_load; - flag <= '0'; - ELSE - s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); - END IF; - cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks - secondary_cpt <= secondary_cpt + 1; - ELSE - cpt <= cpt + 1; - END IF; - END IF; - - WHEN OTHERS => - state <= auto; - - END CASE; - - IF secondary_cpt > 60 THEN - s_coarse_time(31) <= '1'; - END IF; - - IF NOT(previous_coarse_time_load = coarse_time_load) THEN - flag <= '1'; - END IF; - - previous_coarse_time_load <= coarse_time_load; - - END IF; - - END PROCESS; - - fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32)); - --- resetn grspw_tick soft_tick resetn_clk_div --- 0 0 0 0 --- 0 0 1 0 --- 0 1 0 0 --- 0 1 1 0 --- 1 0 0 1 --- 1 0 1 0 --- 1 1 0 0 --- 1 1 1 0 - resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0'; - Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz - GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div); - + coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31)); + coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0'; + END Behavioral; diff --git a/lib/lpp/lfr_time_management/lpp_counter.vhd b/lib/lpp/lfr_time_management/lpp_counter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lfr_time_management/lpp_counter.vhd @@ -0,0 +1,65 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY lpp_counter IS + + GENERIC ( + nb_wait_period : INTEGER := 750; + nb_bit_of_data : INTEGER := 16 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + clear : IN STD_LOGIC; + full : OUT STD_LOGIC; + data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0); + new_data : OUT STD_LOGIC + ); + +END lpp_counter; + +ARCHITECTURE beh OF lpp_counter IS + + SIGNAL counter_wait : INTEGER; + SIGNAL counter_data : INTEGER; + + SIGNAL new_data_s : STD_LOGIC; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + counter_wait <= 0; + counter_data <= 0; + full <= '0'; + new_data_s <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF clear = '1' THEN + counter_wait <= 0; + counter_data <= 0; + full <= '0'; + new_data_s <= NOT new_data_s; + ELSE + IF counter_wait = nb_wait_period-1 THEN + counter_wait <= 0; + new_data_s <= NOT new_data_s; + IF counter_data = (2**nb_bit_of_data)-1 THEN + full <= '1'; + counter_data <= 0; + ELSE + full <= '0'; + counter_data <= counter_data +1; + END IF; + ELSE + full <= '0'; + counter_wait <= counter_wait +1; + END IF; + END IF; + END IF; + END PROCESS; + + data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data)); + new_data <= new_data_s; + +END beh; diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd @@ -17,67 +17,68 @@ -- Additional Comments: -- ---------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; -package lpp_lfr_time_management is +PACKAGE lpp_lfr_time_management IS --*************************** -- APB_LFR_TIME_MANAGEMENT -component apb_lfr_time_management is + COMPONENT apb_lfr_time_management IS - generic( - pindex : integer := 0; --! APB slave index - paddr : integer := 0; --! ADDR field of the APB BAR - pmask : integer := 16#fff#; --! MASK field of the APB BAR - pirq : integer := 0; --! 2 consecutive IRQ lines are used - masterclk : integer := 25000000; --! master clock in Hz - timeclk : integer := 49152000; --! other clock in Hz - finetimeclk : integer := 65536 --! divided clock used for the fine time counter - ); + GENERIC( + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0 + ); - Port ( - clk25MHz : in STD_LOGIC; --! Clock - clk49_152MHz : in STD_LOGIC; --! secondary clock - resetn : in STD_LOGIC; --! Reset - grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : in apb_slv_in_type; --! APB slave input signals - apbo : out apb_slv_out_type; --! APB slave output signals - coarse_time : out std_logic_vector(31 downto 0); --! coarse time - fine_time : out std_logic_vector(31 downto 0) --! fine time - ); + PORT ( + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time + ); -end component; + END COMPONENT; -component lfr_time_management is + COMPONENT lfr_time_management + GENERIC ( + nb_time_code_missing_limit : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + new_timecode : IN STD_LOGIC; + new_coarsetime : IN STD_LOGIC; + coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fine_time_new : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_new : OUT STD_LOGIC + ); + END COMPONENT; - generic ( - masterclk : integer := 25000000; -- master clock in Hz - timeclk : integer := 49152000; -- 2nd clock in Hz - finetimeclk : integer := 65536; -- divided clock used for the fine time counter - nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state - ); - Port ( - master_clock : in std_logic; --! Clock - time_clock : in std_logic; --! 2nd Clock - resetn : in std_logic; --! Reset - grspw_tick : in std_logic; - soft_tick : in std_logic; --! soft tick, load the coarse_time value - coarse_time_load : in std_logic_vector(31 downto 0); - coarse_time : out std_logic_vector(31 downto 0); - fine_time : out std_logic_vector(31 downto 0); - next_commutation : in std_logic_vector(31 downto 0); --- reset_next_commutation: out std_logic; - irq1 : out std_logic; - irq2 : out std_logic - ); - -end component; + COMPONENT lpp_counter + GENERIC ( + nb_wait_period : INTEGER; + nb_bit_of_data : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + clear : IN STD_LOGIC; + full : OUT STD_LOGIC; + data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0); + new_data : OUT STD_LOGIC ); + END COMPONENT; -end lpp_lfr_time_management; +END lpp_lfr_time_management; diff --git a/lib/lpp/lfr_time_management/vhdlsyn.txt b/lib/lpp/lfr_time_management/vhdlsyn.txt --- a/lib/lpp/lfr_time_management/vhdlsyn.txt +++ b/lib/lpp/lfr_time_management/vhdlsyn.txt @@ -1,3 +1,4 @@ lpp_lfr_time_management.vhd +lpp_counter.vhd lfr_time_management.vhd apb_lfr_time_management.vhd diff --git a/lib/lpp/lpp_dma/lpp_dma_ip.vhd b/lib/lpp/lpp_dma/lpp_dma_ip.vhd --- a/lib/lpp/lpp_dma/lpp_dma_ip.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_ip.vhd @@ -110,17 +110,17 @@ ARCHITECTURE Behavioral OF lpp_dma_ip IS WAIT_DATA_ACK, CHECK_LENGTH ); - SIGNAL state : state_DMAWriteBurst := IDLE; + SIGNAL state : state_DMAWriteBurst;-- := IDLE; - SIGNAL nbSend : INTEGER; + -- SIGNAL nbSend : INTEGER; SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL header_check_ok : STD_LOGIC; SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL send_matrix : STD_LOGIC; - SIGNAL request : STD_LOGIC; - SIGNAL remaining_data_request : INTEGER; + -- SIGNAL request : STD_LOGIC; +-- SIGNAL remaining_data_request : INTEGER; SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- @@ -362,4 +362,4 @@ BEGIN DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai; fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren; -END Behavioral; +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/SSRAM_plugin.vhd b/lib/lpp/lpp_memory/SSRAM_plugin.vhd --- a/lib/lpp/lpp_memory/SSRAM_plugin.vhd +++ b/lib/lpp/lpp_memory/SSRAM_plugin.vhd @@ -104,7 +104,7 @@ BEGIN END IF; END PROCESS; ---nclk <= NOT clk; + --nclk <= NOT clk; ssram_clk_pad : outpad GENERIC MAP (tech => tech) PORT MAP (SSRAM_CLK, NOT clk); @@ -184,4 +184,4 @@ BEGIN ZZ_pad : outpad GENERIC MAP (tech => tech) PORT MAP (ZZ, '0'); -END ARCHITECTURE; +END ARCHITECTURE; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -139,10 +139,10 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ; - SIGNAL val_f0_wfp : STD_LOGIC; - SIGNAL val_f1_wfp : STD_LOGIC; - SIGNAL val_f2_wfp : STD_LOGIC; - SIGNAL val_f3_wfp : STD_LOGIC; + -- SIGNAL val_f0_wfp : STD_LOGIC; + -- SIGNAL val_f1_wfp : STD_LOGIC; + -- SIGNAL val_f2_wfp : STD_LOGIC; + -- SIGNAL val_f3_wfp : STD_LOGIC; BEGIN sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); @@ -287,6 +287,8 @@ BEGIN data_f2_in_valid => sample_f2_val, data_f3_in_valid => sample_f3_val); + time_info <= (others => '0'); + data_f0_wfp <= sample_f0_data & time_info; data_f1_wfp <= sample_f1_data & time_info; data_f2_wfp <= sample_f2_data & time_info; diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd @@ -73,10 +73,10 @@ ARCHITECTURE tb OF lpp_lfr_filter IS CONSTANT CoefPerCel : INTEGER := 5; CONSTANT Cels_count : INTEGER := 5; - SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); + --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); - SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); -- SIGNAL sample_filter_v2_out_val : STD_LOGIC; SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); @@ -107,10 +107,10 @@ ARCHITECTURE tb OF lpp_lfr_filter IS SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0); ----------------------------------------------------------------------------- - SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); - SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); + --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0'); ----------------------------------------------------------------------------- SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -1,346 +1,346 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_uart.ALL; -USE lpp.lpp_matrix.ALL; -USE lpp.lpp_delay.ALL; -USE lpp.lpp_fft.ALL; -USE lpp.fft_components.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.Filtercfg.ALL; -USE lpp.lpp_demux.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_Header.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - - -ENTITY lpp_lfr_ms IS - GENERIC ( - hindex : INTEGER := 2 - ); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - - --------------------------------------------------------------------------- - -- DATA INPUT - --------------------------------------------------------------------------- - -- - sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - -- - sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); - - --------------------------------------------------------------------------- - -- DMA - --------------------------------------------------------------------------- - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - -- Reg out - ready_matrix_f0_0 : OUT STD_LOGIC; - ready_matrix_f0_1 : OUT STD_LOGIC; - ready_matrix_f1 : OUT STD_LOGIC; - ready_matrix_f2 : OUT STD_LOGIC; - error_anticipating_empty_fifo : OUT STD_LOGIC; - error_bad_component_error : OUT STD_LOGIC; - debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - - -- Reg In - status_ready_matrix_f0_0 :IN STD_LOGIC; - status_ready_matrix_f0_1 :IN STD_LOGIC; - status_ready_matrix_f1 :IN STD_LOGIC; - status_ready_matrix_f2 :IN STD_LOGIC; - status_error_anticipating_empty_fifo :IN STD_LOGIC; - status_error_bad_component_error :IN STD_LOGIC; - - config_active_interruption_onNewMatrix : IN STD_LOGIC; - config_active_interruption_onError : IN STD_LOGIC; - addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_lfr_ms IS - ----------------------------------------------------------------------------- - SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); - SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL FFT_Load : STD_LOGIC; - SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL SM_FlagError : STD_LOGIC; - SIGNAL SM_Pong : STD_LOGIC; - SIGNAL SM_Wen : STD_LOGIC; - SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); - SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); - - ----------------------------------------------------------------------------- - SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL Head_Empty : STD_LOGIC; - SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL Head_Valid : STD_LOGIC; - SIGNAL Head_Val : STD_LOGIC; - - ----------------------------------------------------------------------------- - SIGNAL DMA_Read : STD_LOGIC; - SIGNAL DMA_ack : STD_LOGIC; - -BEGIN - - ----------------------------------------------------------------------------- - Memf0: lppFIFOxN - GENERIC MAP ( - tech => 0, Mem_use => use_RAM, Data_sz => 16, - Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP ( - rst => rstn, wclk => clk, rclk => clk, - ReUse => (OTHERS => '0'), - wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), - wdata => sample_f0_wdata, rdata => FifoF0_Data, - full => OPEN, empty => FifoF0_Empty); - - Memf1: lppFIFOxN - GENERIC MAP ( - tech => 0, Mem_use => use_RAM, Data_sz => 16, - Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP ( - rst => rstn, wclk => clk, rclk => clk, - ReUse => (OTHERS => '0'), - wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), - wdata => sample_f1_wdata, rdata => FifoF1_Data, - full => OPEN, empty => FifoF1_Empty); - - - Memf2: lppFIFOxN - GENERIC MAP ( - tech => 0, Mem_use => use_RAM, Data_sz => 16, - Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') - PORT MAP ( - rst => rstn, wclk => clk, rclk => clk, - ReUse => (OTHERS => '0'), - wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), - wdata => sample_f3_wdata, rdata => FifoF3_Data, - full => OPEN, empty => FifoF3_Empty); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - DMUX0 : DEMUX - GENERIC MAP ( - Data_sz => 16) - PORT MAP ( - clk => clk, - rstn => rstn, - Read => FFT_Read, - Load => FFT_Load, - EmptyF0 => FifoF0_Empty, - EmptyF1 => FifoF1_Empty, - EmptyF2 => FifoF3_Empty, - DataF0 => FifoF0_Data, - DataF1 => FifoF1_Data, - DataF2 => FifoF3_Data, - WorkFreq => DMUX_WorkFreq, - Read_DEMUX => DMUX_Read, - Empty => DMUX_Empty, - Data => DMUX_Data); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - FFT0: FFT - GENERIC MAP ( - Data_sz => 16, - NbData => 256) - PORT MAP ( - clkm => clk, - rstn => rstn, - FifoIN_Empty => DMUX_Empty, - FifoIN_Data => DMUX_Data, - FifoOUT_Full => FifoINT_Full, - Load => FFT_Load, - Read => FFT_Read, - Write => FFT_Write, - ReUse => FFT_ReUse, - Data => FFT_Data); - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - MemInt : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, - Data_sz => 16, - Addr_sz => 8, - FifoCnt => 5, - Enable_ReUse => '1') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => SM_ReUse, - wen => FFT_Write, - ren => SM_Read, - wdata => FFT_Data, - rdata => FifoINT_Data, - full => FifoINT_Full, - empty => OPEN); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - SM0 : MatriceSpectrale - GENERIC MAP ( - Input_SZ => 16, - Result_SZ => 32) - PORT MAP ( - clkm => clk, - rstn => rstn, - FifoIN_Full => FifoINT_Full, - SetReUse => FFT_ReUse, - Valid => Head_Valid, - Data_IN => FifoINT_Data, - ACQ => DMA_ack, - SM_Write => SM_Wen, - FlagError => SM_FlagError, - Pong => SM_Pong, - Statu => SM_Param, - Write => SM_Write, - Read => SM_Read, - ReUse => SM_ReUse, - Data_OUT => SM_Data); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - MemOut : lppFIFOxN - GENERIC MAP ( - tech => 0, - Mem_use => use_RAM, - Data_sz => 32, - Addr_sz => 8, - FifoCnt => 2, - Enable_ReUse => '0') - PORT MAP ( - rst => rstn, - wclk => clk, - rclk => clk, - ReUse => (OTHERS => '0'), - wen => SM_Write, - ren => Head_Read, - wdata => SM_Data, - rdata => FifoOUT_Data, - full => FifoOUT_Full, - empty => FifoOUT_Empty); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - Head0 : HeaderBuilder - GENERIC MAP ( - Data_sz => 32) - PORT MAP ( - clkm => clk, - rstn => rstn, - pong => SM_Pong, - Statu => SM_Param, - Matrix_Type => DMUX_WorkFreq, - Matrix_Write => SM_Wen, - Valid => Head_Valid, - dataIN => FifoOUT_Data, - emptyIN => FifoOUT_Empty, - RenOUT => Head_Read, - dataOUT => Head_Data, - emptyOUT => Head_Empty, - RenIN => DMA_Read, - header => Head_Header, - header_val => Head_Val, - header_ack => DMA_ack ); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - lpp_dma_ip_1: lpp_dma_ip - GENERIC MAP ( - tech => 0, - hindex => hindex) - PORT MAP ( - HCLK => clk, - HRESETn => rstn, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - - fifo_data => Head_Data, - fifo_empty => Head_Empty, - fifo_ren => DMA_Read, - - header => Head_Header, - header_val => Head_Val, - header_ack => DMA_ack, - - ready_matrix_f0_0 => ready_matrix_f0_0, - ready_matrix_f0_1 => ready_matrix_f0_1, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - error_anticipating_empty_fifo => error_anticipating_empty_fifo, - error_bad_component_error => error_bad_component_error, - debug_reg => debug_reg, - status_ready_matrix_f0_0 => status_ready_matrix_f0_0, - status_ready_matrix_f0_1 => status_ready_matrix_f0_1, - status_ready_matrix_f1 => status_ready_matrix_f1, - status_ready_matrix_f2 => status_ready_matrix_f2, - status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, - status_error_bad_component_error => status_error_bad_component_error, - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, - addr_matrix_f0_0 => addr_matrix_f0_0, - addr_matrix_f0_1 => addr_matrix_f0_1, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2); - ----------------------------------------------------------------------------- - +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.lpp_memory.ALL; +--USE lpp.lpp_uart.ALL; +USE lpp.lpp_matrix.ALL; +--USE lpp.lpp_delay.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.Filtercfg.ALL; +USE lpp.lpp_demux.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_Header.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + + +ENTITY lpp_lfr_ms IS + GENERIC ( + hindex : INTEGER := 2 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- DATA INPUT + --------------------------------------------------------------------------- + -- + sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + -- + sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- DMA + --------------------------------------------------------------------------- + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- Reg out + ready_matrix_f0_0 : OUT STD_LOGIC; + ready_matrix_f0_1 : OUT STD_LOGIC; + ready_matrix_f1 : OUT STD_LOGIC; + ready_matrix_f2 : OUT STD_LOGIC; + error_anticipating_empty_fifo : OUT STD_LOGIC; + error_bad_component_error : OUT STD_LOGIC; + debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- Reg In + status_ready_matrix_f0_0 :IN STD_LOGIC; + status_ready_matrix_f0_1 :IN STD_LOGIC; + status_ready_matrix_f1 :IN STD_LOGIC; + status_ready_matrix_f2 :IN STD_LOGIC; + status_error_anticipating_empty_fifo :IN STD_LOGIC; + status_error_bad_component_error :IN STD_LOGIC; + + config_active_interruption_onNewMatrix : IN STD_LOGIC; + config_active_interruption_onError : IN STD_LOGIC; + addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_lfr_ms IS + ----------------------------------------------------------------------------- + SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0); + SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FFT_Load : STD_LOGIC; + SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL SM_FlagError : STD_LOGIC; + SIGNAL SM_Pong : STD_LOGIC; + SIGNAL SM_Wen : STD_LOGIC; + SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL Head_Empty : STD_LOGIC; + SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL Head_Valid : STD_LOGIC; + SIGNAL Head_Val : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL DMA_Read : STD_LOGIC; + SIGNAL DMA_ack : STD_LOGIC; + +BEGIN + + ----------------------------------------------------------------------------- + Memf0: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => use_RAM, Data_sz => 16, + Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rst => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), + wdata => sample_f0_wdata, rdata => FifoF0_Data, + full => OPEN, empty => FifoF0_Empty); + + Memf1: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => use_RAM, Data_sz => 16, + Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rst => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), + wdata => sample_f1_wdata, rdata => FifoF1_Data, + full => OPEN, empty => FifoF1_Empty); + + + Memf2: lppFIFOxN + GENERIC MAP ( + tech => 0, Mem_use => use_RAM, Data_sz => 16, + Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') + PORT MAP ( + rst => rstn, wclk => clk, rclk => clk, + ReUse => (OTHERS => '0'), + wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), + wdata => sample_f3_wdata, rdata => FifoF3_Data, + full => OPEN, empty => FifoF3_Empty); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + DMUX0 : DEMUX + GENERIC MAP ( + Data_sz => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + Read => FFT_Read, + Load => FFT_Load, + EmptyF0 => FifoF0_Empty, + EmptyF1 => FifoF1_Empty, + EmptyF2 => FifoF3_Empty, + DataF0 => FifoF0_Data, + DataF1 => FifoF1_Data, + DataF2 => FifoF3_Data, + WorkFreq => DMUX_WorkFreq, + Read_DEMUX => DMUX_Read, + Empty => DMUX_Empty, + Data => DMUX_Data); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + FFT0: FFT + GENERIC MAP ( + Data_sz => 16, + NbData => 256) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Empty => DMUX_Empty, + FifoIN_Data => DMUX_Data, + FifoOUT_Full => FifoINT_Full, + Load => FFT_Load, + Read => FFT_Read, + Write => FFT_Write, + ReUse => FFT_ReUse, + Data => FFT_Data); + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + MemInt : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + Data_sz => 16, + Addr_sz => 8, + FifoCnt => 5, + Enable_ReUse => '1') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => SM_ReUse, + wen => FFT_Write, + ren => SM_Read, + wdata => FFT_Data, + rdata => FifoINT_Data, + full => FifoINT_Full, + empty => OPEN); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + SM0 : MatriceSpectrale + GENERIC MAP ( + Input_SZ => 16, + Result_SZ => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, + FifoIN_Full => FifoINT_Full, + SetReUse => FFT_ReUse, + Valid => Head_Valid, + Data_IN => FifoINT_Data, + ACQ => DMA_ack, + SM_Write => SM_Wen, + FlagError => SM_FlagError, + Pong => SM_Pong, + Statu => SM_Param, + Write => SM_Write, + Read => SM_Read, + ReUse => SM_ReUse, + Data_OUT => SM_Data); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + MemOut : lppFIFOxN + GENERIC MAP ( + tech => 0, + Mem_use => use_RAM, + Data_sz => 32, + Addr_sz => 8, + FifoCnt => 2, + Enable_ReUse => '0') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + wen => SM_Write, + ren => Head_Read, + wdata => SM_Data, + rdata => FifoOUT_Data, + full => FifoOUT_Full, + empty => FifoOUT_Empty); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + Head0 : HeaderBuilder + GENERIC MAP ( + Data_sz => 32) + PORT MAP ( + clkm => clk, + rstn => rstn, + pong => SM_Pong, + Statu => SM_Param, + Matrix_Type => DMUX_WorkFreq, + Matrix_Write => SM_Wen, + Valid => Head_Valid, + dataIN => FifoOUT_Data, + emptyIN => FifoOUT_Empty, + RenOUT => Head_Read, + dataOUT => Head_Data, + emptyOUT => Head_Empty, + RenIN => DMA_Read, + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack ); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + lpp_dma_ip_1: lpp_dma_ip + GENERIC MAP ( + tech => 0, + hindex => hindex) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + + fifo_data => Head_Data, + fifo_empty => Head_Empty, + fifo_ren => DMA_Read, + + header => Head_Header, + header_val => Head_Val, + header_ack => DMA_ack, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); + ----------------------------------------------------------------------------- + END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd @@ -164,5 +164,33 @@ PACKAGE lpp_lfr_pkg IS addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT; + + COMPONENT lpp_top_ms + GENERIC ( + Mem_use : INTEGER; + nb_burst_available_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_snapshot_size : INTEGER; + delta_f2_f0_size : INTEGER; + delta_f2_f1_size : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + hindex_wfp : INTEGER; + hindex_ms : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ahbi_ms : IN AHB_Mst_In_Type; + ahbo_ms : OUT AHB_Mst_Out_Type; + data_shaping_BW : OUT STD_LOGIC); + END COMPONENT; END lpp_lfr_pkg; diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -10,4 +10,5 @@ lpp_lfr_apbreg.vhd top_wf_picker.vhd lpp_lfr_filter.vhd lpp_lfr_ms.vhd +lpp_top_ms.vhd lpp_lfr.vhd diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd @@ -94,7 +94,8 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -103,6 +104,7 @@ ARCHITECTURE beh OF lpp_waveform IS SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN -- beh @@ -222,14 +224,15 @@ BEGIN -- beh data_wen => data_wen, data => wdata); - ready_arb <= NOT ready; + ready_arb <= NOT data_ready; lpp_waveform_fifo_1: lpp_waveform_fifo GENERIC MAP (tech => tech) PORT MAP ( clk => clk, rstn => rstn, - ready => ready, + time_ready => time_ready, + data_ready => data_ready, time_ren => time_ren, -- todo data_ren => data_ren, -- todo rdata => rdata, -- todo @@ -237,7 +240,9 @@ BEGIN -- beh time_wen => time_wen, data_wen => data_wen, wdata => wdata); - + + enable <= enable_f3 & enable_f2 & enable_f1 & enable_f0; + pp_waveform_dma_1: lpp_waveform_dma GENERIC MAP ( data_size => data_size, @@ -249,7 +254,9 @@ BEGIN -- beh HRESETn => rstn, AHB_Master_In => AHB_Master_In, AHB_Master_Out => AHB_Master_Out, - data_ready => ready, + enable => enable, -- todo + time_ready => time_ready, -- todo + data_ready => data_ready, data => rdata, data_data_ren => data_ren, data_time_ren => time_ren, diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -57,10 +57,12 @@ ENTITY lpp_waveform_dma IS AHB_Master_In : IN AHB_Mst_In_Type; AHB_Master_Out : OUT AHB_Mst_Out_Type; -- - data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Reg nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -79,7 +81,7 @@ ARCHITECTURE Behavioral OF lpp_waveform_ SIGNAL DMAIn : DMA_In_Type; SIGNAL DMAOut : DMA_OUt_Type; ----------------------------------------------------------------------------- - TYPE state_DMAWriteBurst IS (IDLE, + TYPE state_DMAWriteBurst IS (IDLE,TRASH_FIFO_TIME,TRASH_FIFO_DATA, SEND_TIME_0, WAIT_TIME_0, SEND_TIME_1, WAIT_TIME_1, SEND_5_TIME, @@ -88,9 +90,12 @@ ARCHITECTURE Behavioral OF lpp_waveform_ ----------------------------------------------------------------------------- -- CONTROL SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sel_data_ss : STD_LOGIC; + SIGNAL sel_time_s : STD_LOGIC; SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL time_select : STD_LOGIC; + SIGNAL enable_sel : STD_LOGIC; SIGNAL time_write : STD_LOGIC; SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL time_already_send_s : STD_LOGIC; @@ -109,6 +114,7 @@ ARCHITECTURE Behavioral OF lpp_waveform_ SIGNAL data_send_ok : STD_LOGIC; SIGNAL data_send_ko : STD_LOGIC; SIGNAL data_fifo_ren : STD_LOGIC; + SIGNAL trash_fifo_ren : STD_LOGIC; SIGNAL data_ren : STD_LOGIC; ----------------------------------------------------------------------------- -- SELECT ADDRESS @@ -170,6 +176,21 @@ BEGIN "01" WHEN data_ready(1) = '1' ELSE "10" WHEN data_ready(2) = '1' ELSE "11"; + + sel_data_ss <= data_ready(0) WHEN sel_data = "00" ELSE + data_ready(1) WHEN sel_data = "01" ELSE + data_ready(2) WHEN sel_data = "10" ELSE + data_ready(3); + + sel_time_s <= time_ready(0) WHEN sel_data = "00" ELSE + time_ready(1) WHEN sel_data = "01" ELSE + time_ready(2) WHEN sel_data = "10" ELSE + time_ready(3); + + enable_sel <= enable(0) WHEN sel_data = "00" ELSE + enable(1) WHEN sel_data = "01" ELSE + enable(2) WHEN sel_data = "10" ELSE + enable(3); time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE time_already_send(1) WHEN data_ready(1) = '1' ELSE @@ -186,6 +207,7 @@ BEGIN update <= "00"; time_select <= '0'; time_fifo_ren <= '1'; + trash_fifo_ren <= '1'; data_send <= '0'; time_send <= '0'; time_write <= '0'; @@ -203,14 +225,37 @@ BEGIN data_send <= '0'; time_send <= '0'; time_write <= '0'; - + trash_fifo_ren <= '1'; IF data_ready = "0000" THEN state <= IDLE; ELSE - sel_data <= sel_data_s; - state <= SEND_5_TIME; + sel_data <= sel_data_s; + IF enable_sel = '1' THEN + state <= SEND_5_TIME; + ELSE + state <= TRASH_FIFO_TIME; + END IF; + END IF; + WHEN TRASH_FIFO_TIME => + time_select <= '1'; + time_fifo_ren <= '0'; + IF sel_time_s = '1' THEN + time_fifo_ren <= '1'; + state <= TRASH_FIFO_DATA; + END IF; + + + WHEN TRASH_FIFO_DATA => + time_select <= '1'; + trash_fifo_ren <= '0'; + IF sel_data_ss = '1' THEN + trash_fifo_ren <= '1'; + state <= IDLE; + END IF; + + WHEN SEND_5_TIME => update <= "00"; time_select <= '1'; @@ -283,9 +328,9 @@ BEGIN send_ok => data_send_ok, send_ko => data_send_ko); - DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; - data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; - time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; + DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; + data_ren <= trash_fifo_ren WHEN time_select = '1' ELSE data_fifo_ren; + time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; @@ -306,6 +351,7 @@ BEGIN PORT MAP ( HCLK => HCLK, HRESETn => HRESETn, + enable => enable(I), update => update_and_sel((2*I)+1 DOWNTO 2*I), nb_burst_available => nb_burst_available, addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), @@ -323,4 +369,4 @@ BEGIN ----------------------------------------------------------------------------- -END Behavioral; +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd @@ -37,6 +37,7 @@ ENTITY lpp_waveform_dma_selectaddress IS HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; + enable : IN STD_LOGIC; update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); @@ -80,10 +81,12 @@ BEGIN update_r <= update; CASE state IS WHEN IDLE => - IF update_s = '1' THEN + IF enable = '0' THEN + state <= UPDATED; + elsIF update_s = '1' THEN state <= ADD; END IF; - + WHEN ADD => IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN state <= IDLE; @@ -121,8 +124,10 @@ BEGIN WHEN UPDATED => status_full_err <= '0'; - state <= IDLE; address <= addr_data_reg; + IF enable = '1' THEN + state <= IDLE; + END IF; WHEN OTHERS => NULL; END CASE; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo.vhd @@ -39,7 +39,8 @@ ENTITY lpp_waveform_fifo IS rstn : IN STD_LOGIC; --------------------------------------------------------------------------- - ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b + time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b + data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b --------------------------------------------------------------------------- time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -115,7 +116,7 @@ BEGIN GENERIC MAP ( offset => 32*I + 20, length => 10, - enable_ready => '0') + enable_ready => '1') PORT MAP ( clk => clk, rstn => rstn, @@ -125,7 +126,7 @@ BEGIN mem_we => time_mem_wen(I), mem_addr_ren => time_mem_addr_r(I), mem_addr_wen => time_mem_addr_w(I), - ready => OPEN); + ready => time_ready(I)); END GENERATE gen_fifo_ctrl_time; gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE @@ -143,7 +144,7 @@ BEGIN mem_we => data_mem_wen(I), mem_addr_ren => data_mem_addr_r(I), mem_addr_wen => data_mem_addr_w(I), - ready => ready(I)); + ready => data_ready(I)); END GENERATE gen_fifo_ctrl_data; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_ctrl.vhd @@ -133,7 +133,7 @@ BEGIN mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length)); ready_gen: IF enable_ready = '1' GENERATE - ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE + ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE '0'; END GENERATE ready_gen; diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd @@ -132,6 +132,7 @@ PACKAGE lpp_waveform_pkg IS PORT ( HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; + enable : IN STD_LOGIC; update : IN STD_LOGIC_VECTOR(1 DOWNTO 0); nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -162,6 +163,8 @@ PACKAGE lpp_waveform_pkg IS HRESETn : IN STD_ULOGIC; AHB_Master_In : IN AHB_Mst_In_Type; AHB_Master_Out : OUT AHB_Mst_Out_Type; + enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); @@ -229,7 +232,8 @@ PACKAGE lpp_waveform_pkg IS PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);