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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 LIBRARY lpp;
27 USE lpp.general_purpose.ALL;
28
29 ENTITY SYNC_VALID_BIT IS
30 GENERIC (
31 NB_FF_OF_SYNC : INTEGER := 2);
32 PORT (
33 clk_in : IN STD_LOGIC;
34 clk_out : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 sin : IN STD_LOGIC;
37 sout : OUT STD_LOGIC);
38 END SYNC_VALID_BIT;
39
40 ARCHITECTURE beh OF SYNC_VALID_BIT IS
41 SIGNAL s_1 : STD_LOGIC;
42 SIGNAL s_2 : STD_LOGIC;
43 BEGIN -- beh
44
45 lpp_front_to_level_1: lpp_front_to_level
46 PORT MAP (
47 clk => clk_in,
48 rstn => rstn,
49 sin => sin,
50 sout => s_1);
51
52 SYNC_FF_1: SYNC_FF
53 GENERIC MAP (
54 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
55 PORT MAP (
56 clk => clk_out,
57 rstn => rstn,
58 A => s_1,
59 A_sync => s_2);
60
61 lpp_front_detection_1: lpp_front_detection
62 PORT MAP (
63 clk => clk_out,
64 rstn => rstn,
65 sin => s_2,
66 sout => sout);
67
68 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_detection IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_detection;
34
35 ARCHITECTURE beh OF lpp_front_detection IS
36
37 SIGNAL reg : STD_LOGIC;
38 SIGNAL sout_reg : STD_LOGIC;
39
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = NOT reg THEN
50 sout_reg <= '1';
51 ELSE
52 sout_reg <= '0';
53 END IF;
54 END IF;
55 END PROCESS;
56
57 sout <= sout_reg;
58
59 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_to_level IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_to_level;
34
35 ARCHITECTURE beh OF lpp_front_to_level IS
36
37 SIGNAL reg : STD_LOGIC;
38
39 SIGNAL sout_reg : STD_LOGIC;
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = '1' AND reg = '0' THEN
50 sout_reg <= NOT sout_reg;
51 END IF;
52 END IF;
53 END PROCESS;
54
55 sout <= sout_reg;
56
57 END beh;
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY lpp_counter IS
6
7 GENERIC (
8 nb_wait_period : INTEGER := 750;
9 nb_bit_of_data : INTEGER := 16
10 );
11 PORT (
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 clear : IN STD_LOGIC;
15 full : OUT STD_LOGIC;
16 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
17 new_data : OUT STD_LOGIC
18 );
19
20 END lpp_counter;
21
22 ARCHITECTURE beh OF lpp_counter IS
23
24 SIGNAL counter_wait : INTEGER;
25 SIGNAL counter_data : INTEGER;
26
27 SIGNAL new_data_s : STD_LOGIC;
28 BEGIN -- beh
29
30 PROCESS (clk, rstn)
31 BEGIN -- PROCESS
32 IF rstn = '0' THEN -- asynchronous reset (active low)
33 counter_wait <= 0;
34 counter_data <= 0;
35 full <= '0';
36 new_data_s <= '0';
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
38 IF clear = '1' THEN
39 counter_wait <= 0;
40 counter_data <= 0;
41 full <= '0';
42 new_data_s <= NOT new_data_s;
43 ELSE
44 IF counter_wait = nb_wait_period-1 THEN
45 counter_wait <= 0;
46 new_data_s <= NOT new_data_s;
47 IF counter_data = (2**nb_bit_of_data)-1 THEN
48 full <= '1';
49 counter_data <= 0;
50 ELSE
51 full <= '0';
52 counter_data <= counter_data +1;
53 END IF;
54 ELSE
55 full <= '0';
56 counter_wait <= counter_wait +1;
57 END IF;
58 END IF;
59 END IF;
60 END PROCESS;
61
62 data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data));
63 new_data <= new_data_s;
64
65 END beh;
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@@ -2,6 +2,7 iir_filter.vhd
2 2 FILTERcfg.vhd
3 3 RAM.vhd
4 4 RAM_CEL.vhd
5 RAM_CEL_N.vhd
5 6 RAM_CTRLR_v2.vhd
6 7 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
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@@ -269,4 +269,31 Constant ctrl_CLRMAC : std_logic_vector(
269 269 A_sync : OUT STD_LOGIC);
270 270 END COMPONENT;
271 271
272 COMPONENT lpp_front_to_level
273 PORT (
274 clk : IN STD_LOGIC;
275 rstn : IN STD_LOGIC;
276 sin : IN STD_LOGIC;
277 sout : OUT STD_LOGIC);
278 END COMPONENT;
279
280 COMPONENT lpp_front_detection
281 PORT (
282 clk : IN STD_LOGIC;
283 rstn : IN STD_LOGIC;
284 sin : IN STD_LOGIC;
285 sout : OUT STD_LOGIC);
286 END COMPONENT;
287
288 COMPONENT SYNC_VALID_BIT
289 GENERIC (
290 NB_FF_OF_SYNC : INTEGER);
291 PORT (
292 clk_in : IN STD_LOGIC;
293 clk_out : IN STD_LOGIC;
294 rstn : IN STD_LOGIC;
295 sin : IN STD_LOGIC;
296 sout : OUT STD_LOGIC);
297 END COMPONENT;
298
272 299 END;
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@@ -16,3 +16,7 REG.vhd
16 16 SYNC_FF.vhd
17 17 Shifter.vhd
18 18 TwoComplementer.vhd
19 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
21 SYNC_VALID_BIT.vhd
22
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@@ -26,6 +26,7 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 30 USE lpp.lpp_lfr_time_management.ALL;
30 31
31 32 ENTITY apb_lfr_time_management IS
@@ -34,21 +35,19 ENTITY apb_lfr_time_management IS
34 35 pindex : INTEGER := 0; --! APB slave index
35 36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
38 pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used
41 39 );
42 40
43 41 PORT (
44 42 clk25MHz : IN STD_LOGIC; --! Clock
45 43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
46 44 resetn : IN STD_LOGIC; --! Reset
45
47 46 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 47 apbi : IN apb_slv_in_type; --! APB slave input signals
49 48 apbo : OUT apb_slv_out_type; --! APB slave output signals
50 49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52 51 );
53 52
54 53 END apb_lfr_time_management;
@@ -56,21 +55,16 END apb_lfr_time_management;
56 55 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57 56
58 57 CONSTANT REVISION : INTEGER := 1;
59
60 --! the following types are defined in the grlib amba package
61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 58 CONSTANT pconfig : apb_config_type := (
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 59 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
66 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask)
61 );
67 62
68 63 TYPE apb_lfr_time_management_Reg IS RECORD
69 64 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 65 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 66 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
74 68 END RECORD;
75 69
76 70 SIGNAL r : apb_lfr_time_management_Reg;
@@ -78,69 +72,66 ARCHITECTURE Behavioral OF apb_lfr_time_
78 72 SIGNAL force_tick : STD_LOGIC;
79 73 SIGNAL previous_force_tick : STD_LOGIC;
80 74 SIGNAL soft_tick : STD_LOGIC;
81 -- SIGNAL reset_next_commutation : STD_LOGIC;
82 75
83 76 SIGNAL irq1 : STD_LOGIC;
84 77 SIGNAL irq2 : STD_LOGIC;
85 78
86 BEGIN
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
81
82 SIGNAL coarse_time_new : STD_LOGIC;
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 SIGNAL fine_time_new : STD_LOGIC;
88 SIGNAL fine_time_new_temp : STD_LOGIC;
89 SIGNAL fine_time_new_49 : STD_LOGIC;
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 SIGNAL tick : STD_LOGIC;
93 SIGNAL new_timecode : STD_LOGIC;
94 SIGNAL new_coarsetime : STD_LOGIC;
87 95
88 lfrtimemanagement0 : lfr_time_management
89 GENERIC MAP(
90 masterclk => masterclk,
91 timeclk => timeclk,
92 finetimeclk => finetimeclk,
93 nb_clk_div_ticks => 1)
94 PORT MAP(
95 master_clock => clk25MHz,
96 time_clock => clk49_152MHz,
97 resetn => resetn,
98 grspw_tick => grspw_tick,
99 soft_tick => soft_tick,
100 coarse_time_load => r.coarse_time_load,
101 coarse_time => r.coarse_time,
102 fine_time => r.fine_time,
103 next_commutation => r.next_commutation,
104 -- reset_next_commutation => reset_next_commutation,
105 irq1 => irq1,--apbo.pirq(pirq),
106 irq2 => irq2);--apbo.pirq(pirq+1));
96 BEGIN
97 -----------------------------------------------------------------------------
98 -- TODO
99 -- IRQ 1 & 2
100 -----------------------------------------------------------------------------
101 irq2 <= '0';
102 irq1 <= '0';
103
107 104
108 --apbo.pirq <= (OTHERS => '0');
105 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
106 --irq1_gen : IF I = pirq GENERATE
107 apbo.pirq(pirq) <= irq1;
108 --END GENERATE irq1_gen;
109 --irq2_gen : IF I = pirq+1 GENERATE
110 apbo.pirq(pirq+1) <= irq2;
111 -- END GENERATE irq2_gen;
112 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
113 -- apbo.pirq(I) <= '0';
114 -- END GENERATE others_irq;
115 --END GENERATE all_irq_gen;
109 116
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
124
125 PROCESS(resetn, clk25MHz)--, reset_next_commutation)
117 PROCESS(resetn, clk25MHz)
126 118 BEGIN
127 119
128 120 IF resetn = '0' THEN
129 121 Rdata <= (OTHERS => '0');
130 122 r.coarse_time_load <= x"80000000";
131 123 r.ctrl <= x"00000000";
132 r.next_commutation <= x"ffffffff";
133 124 force_tick <= '0';
134 125 previous_force_tick <= '0';
135 126 soft_tick <= '0';
136 127
137 --ELSIF reset_next_commutation = '1' THEN
138 -- r.next_commutation <= x"ffffffff";
128 coarsetime_reg_updated <= '0';
139 129
140 130 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
131 coarsetime_reg_updated <= '0';
141 132
133 force_tick <= r.ctrl(0);
142 134 previous_force_tick <= force_tick;
143 force_tick <= r.ctrl(0);
144 135 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
145 136 soft_tick <= '1';
146 137 ELSE
@@ -154,10 +145,8 BEGIN
154 145 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
155 146 WHEN "000001" =>
156 147 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
157 WHEN "000100" =>
158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
148 coarsetime_reg_updated <= '1';
159 149 WHEN OTHERS =>
160 r.coarse_time_load <= x"00000000";
161 150 END CASE;
162 151 ELSIF r.ctrl(0) = '1' THEN
163 152 r.ctrl(0) <= '0';
@@ -167,30 +156,14 BEGIN
167 156 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
168 157 CASE apbi.paddr(7 DOWNTO 2) IS
169 158 WHEN "000000" =>
170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
159 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
174 160 WHEN "000001" =>
175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
161 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
179 162 WHEN "000010" =>
180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
163 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
184 164 WHEN "000011" =>
185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
189 WHEN "000100" =>
190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
165 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
166 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
194 167 WHEN OTHERS =>
195 168 Rdata(31 DOWNTO 0) <= x"00000000";
196 169 END CASE;
@@ -199,10 +172,115 BEGIN
199 172 END IF;
200 173 END PROCESS;
201 174
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
203 coarse_time <= r.coarse_time;
204 fine_time <= r.fine_time;
175 apbo.prdata <= Rdata;
205 176 apbo.pconfig <= pconfig;
206 177 apbo.pindex <= pindex;
207 178
179 coarse_time <= r.coarse_time;
180 fine_time <= r.fine_time;
181 -----------------------------------------------------------------------------
182
183 coarsetime_reg <= r.coarse_time_load;
184 r.coarse_time <= coarse_time_s;
185 r.fine_time <= fine_time_s;
186 -----------------------------------------------------------------------------
187 -- IN coarsetime_reg_updated
188 -- IN coarsetime_reg
189
190 -- OUT coarse_time_s -- ok
191 -- OUT fine_time_s -- ok
192 -----------------------------------------------------------------------------
193
194 tick <= grspw_tick OR soft_tick;
195
196 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
197 GENERIC MAP (
198 NB_FF_OF_SYNC => 2)
199 PORT MAP (
200 clk_in => clk25MHz,
201 clk_out => clk49_152MHz,
202 rstn => resetn,
203 sin => tick,
204 sout => new_timecode);
205
206 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
207 GENERIC MAP (
208 NB_FF_OF_SYNC => 2)
209 PORT MAP (
210 clk_in => clk25MHz,
211 clk_out => clk49_152MHz,
212 rstn => resetn,
213 sin => coarsetime_reg_updated,
214 sout => new_coarsetime);
215
216 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
217 -- GENERIC MAP (
218 -- NB_FF_OF_SYNC => 2)
219 -- PORT MAP (
220 -- clk_in => clk49_152MHz,
221 -- clk_out => clk25MHz,
222 -- rstn => resetn,
223 -- sin => 9,
224 -- sout => );
225
226 SYNC_FF_1: SYNC_FF
227 GENERIC MAP (
228 NB_FF_OF_SYNC => 2)
229 PORT MAP (
230 clk => clk25MHz,
231 rstn => resetn,
232 A => fine_time_new_49,
233 A_sync => fine_time_new_temp);
234
235 lpp_front_detection_1: lpp_front_detection
236 PORT MAP (
237 clk => clk25MHz,
238 rstn => resetn,
239 sin => fine_time_new_temp,
240 sout => fine_time_new);
241
242 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
243 GENERIC MAP (
244 NB_FF_OF_SYNC => 2)
245 PORT MAP (
246 clk_in => clk49_152MHz,
247 clk_out => clk25MHz,
248 rstn => resetn,
249 sin => coarse_time_new_49,
250 sout => coarse_time_new);
251
252 PROCESS (clk25MHz, resetn)
253 BEGIN -- PROCESS
254 IF resetn = '0' THEN -- asynchronous reset (active low)
255 fine_time_s <= (OTHERS => '0');
256 coarse_time_s <= (OTHERS => '0');
257 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
258 IF fine_time_new = '1' THEN
259 fine_time_s <= fine_time_49;
260 END IF;
261 IF coarse_time_new = '1' THEN
262 coarse_time_s <= coarse_time_49;
263 END IF;
264 END IF;
265 END PROCESS;
266
267 -----------------------------------------------------------------------------
268 -- LFR_TIME_MANAGMENT
269 -----------------------------------------------------------------------------
270 lfr_time_management_1 : lfr_time_management
271 GENERIC MAP (
272 nb_time_code_missing_limit => 60)
273 PORT MAP (
274 clk => clk49_152MHz,
275 rstn => resetn,
276
277 new_timecode => new_timecode,
278 new_coarsetime => new_coarsetime,
279 coarsetime_reg => coarsetime_reg,
280
281 fine_time => fine_time_49,
282 fine_time_new => fine_time_new_49,
283 coarse_time => coarse_time_49,
284 coarse_time_new => coarse_time_new_49);
285
208 286 END Behavioral;
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@@ -21,247 +21,83 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY lpp;
24 USE lpp.general_purpose.Clk_divider;
24 USE lpp.lpp_lfr_time_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
28 masterclk : INTEGER := 25000000; -- master clock in Hz
29 timeclk : INTEGER := 49152000; -- 2nd clock in Hz
30 finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter
31 nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state
28 nb_time_code_missing_limit : INTEGER := 60
32 29 );
33 30 PORT (
34 master_clock : IN STD_LOGIC; --! Clock -- 25MHz
35 time_clock : IN STD_LOGIC; --! 2nd Clock -- 49MHz
36 resetn : IN STD_LOGIC; --! Reset
37 grspw_tick : IN STD_LOGIC;
38 soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value -- 25MHz
39 coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
41 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
42 next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
43 -- reset_next_commutation : OUT STD_LOGIC;
44 irq1 : OUT STD_LOGIC; -- 25MHz
45 irq2 : OUT STD_LOGIC -- 25MHz
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33
34 new_timecode : IN STD_LOGIC; -- transition signal information
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
36 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
39 fine_time_new : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 coarse_time_new : OUT STD_LOGIC
46 42 );
47 43 END lfr_time_management;
48 44
49 45 ARCHITECTURE Behavioral OF lfr_time_management IS
50 46
51 SIGNAL resetn_clk_div : STD_LOGIC;
52 SIGNAL clk_div : STD_LOGIC;
53 --
54 SIGNAL flag : STD_LOGIC;
55 SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL cpt : INTEGER RANGE 0 TO 100000;
58 SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000;
59 --
60 SIGNAL sirq1 : STD_LOGIC;
61 SIGNAL sirq2 : STD_LOGIC;
62 SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000;
63 SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 SIGNAL p_clk_div : STD_LOGIC;
66 --
67 TYPE state_type IS (auto, slave);
68 SIGNAL state : state_type;
69 TYPE timer_type IS (idle, engaged);
70 SIGNAL commutation_timer : timer_type;
47 SIGNAL counter_clear : STD_LOGIC;
48 SIGNAL counter_full : STD_LOGIC;
49
50 SIGNAL nb_time_code_missing : INTEGER;
51 SIGNAL coarse_time_s : INTEGER;
71 52
72 53 BEGIN
73 54
74 --*******************************************
75 -- COMMUTATION TIMER AND INTERRUPT GENERATION
76 PROCESS(master_clock, resetn)
77 BEGIN
78
79 IF resetn = '0' THEN
80 commutation_timer <= idle;
81 cpt_next_commutation <= 0;
82 sirq1 <= '0';
83 sirq2 <= '0';
84 latched_next_commutation <= x"ffffffff";
85 p_next_commutation <= (others => '0');
86 p_clk_div <= '0';
87 ELSIF master_clock'EVENT AND master_clock = '1' THEN
88
89 CASE commutation_timer IS
55 lpp_counter_1 : lpp_counter
56 GENERIC MAP (
57 nb_wait_period => 750,
58 nb_bit_of_data => 16)
59 PORT MAP (
60 clk => clk,
61 rstn => rstn,
62 clear => counter_clear,
63 full => counter_full,
64 data => fine_time,
65 new_data => fine_time_new);
90 66
91 WHEN idle =>
92 sirq1 <= '0';
93 sirq2 <= '0';
94 IF s_coarse_time = latched_next_commutation THEN
95 commutation_timer <= engaged; -- transition to state "engaged"
96 sirq1 <= '1'; -- start the pulse on sirq1
97 latched_next_commutation <= x"ffffffff";
98 ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed
99 latched_next_commutation <= next_commutation; -- latch the value
67 PROCESS (clk, rstn)
68 BEGIN -- PROCESS
69 IF rstn = '0' THEN -- asynchronous reset (active low)
70 nb_time_code_missing <= 0;
71 counter_clear <= '0';
72 coarse_time_s <= 0;
73 coarse_time_new <= '0';
74 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
75 IF new_timecode = '1' THEN
76 coarse_time_new <= '1';
77 IF new_coarsetime = '1' THEN
78 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
100 79 ELSE
101 commutation_timer <= idle;
80 coarse_time_s <= coarse_time_s + 1;
102 81 END IF;
103
104 WHEN engaged =>
105 sirq1 <= '0'; -- stop the pulse on sirq1
106 IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge
107 IF cpt_next_commutation = 65536 THEN
108 cpt_next_commutation <= 0;
109 commutation_timer <= idle;
110 sirq2 <= '1'; -- start the pulse on sirq2
82 nb_time_code_missing <= 0;
83 counter_clear <= '1';
111 84 ELSE
112 cpt_next_commutation <= cpt_next_commutation + 1;
85 coarse_time_new <= '0';
86 counter_clear <= '0';
87 IF counter_full = '1' THEN
88 coarse_time_new <= '1';
89 coarse_time_s <= coarse_time_s + 1;
90 IF nb_time_code_missing = nb_time_code_missing_limit THEN
91 nb_time_code_missing <= nb_time_code_missing_limit;
92 ELSE
93 nb_time_code_missing <= nb_time_code_missing + 1;
113 94 END IF;
114 95 END IF;
115
116 WHEN OTHERS =>
117 commutation_timer <= idle;
118
119 END CASE;
120
121 p_next_commutation <= next_commutation;
122 p_clk_div <= clk_div;
123
124 96 END IF;
125
97 END IF;
126 98 END PROCESS;
127 99
128 irq1 <= sirq1;
129 irq2 <= sirq2;
130 -- reset_next_commutation <= '0';
131
132 --
133 --*******************************************
134
135 --**********************
136 -- synchronization stage
137 PROCESS(master_clock, resetn) -- resynchronisation with clk
138 BEGIN
139
140 IF resetn = '0' THEN
141 coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
142
143 ELSIF master_clock'EVENT AND master_clock = '1' THEN
144 coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk
145 END IF;
146
147 END PROCESS;
148 --
149 --**********************
150
151
152 -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC
153 PROCESS(clk_div, resetn) -- JC
154 BEGIN
155
156 IF resetn = '0' THEN
157 flag <= '0';
158 cpt <= 0;
159 secondary_cpt <= 0;
160 s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
161 previous_coarse_time_load <= x"80000000";
162 state <= auto;
163
164 --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN
165 -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
166 -- -- s_coarse_time <= coarse_time_load;
167 -- -- flag <= '0';
168 -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously
169 -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
170 -- --END IF;
171
172 -- cpt <= 0;
173 -- secondary_cpt <= 0;
174 -- state <= slave;
175
176 ELSIF clk_div'EVENT AND clk_div = '1' THEN
177
178 CASE state IS
179
180 WHEN auto =>
181 IF grspw_tick = '1' OR soft_tick = '1' THEN
182 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
183 s_coarse_time <= coarse_time_load;
184 ELSE -- if coarse_time_load has not changed, increment the value autonomously
185 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
186 END IF;
187 flag <= '0';
188 cpt <= 0;
189 secondary_cpt <= 0;
190 state <= slave;
191 ELSE
192 IF cpt = 65535 THEN
193 IF flag = '1' THEN
194 s_coarse_time <= coarse_time_load;
195 flag <= '0';
196 ELSE
197 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
198 END IF;
199 cpt <= 0;
200 secondary_cpt <= secondary_cpt + 1;
201 ELSE
202 cpt <= cpt + 1;
203 END IF;
204 END IF;
205
206 WHEN slave =>
207 IF grspw_tick = '1' OR soft_tick = '1' THEN
208 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
209 s_coarse_time <= coarse_time_load;
210 ELSE -- if coarse_time_load has not changed, increment the value autonomously
211 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
212 END IF;
213 flag <= '0';
214 cpt <= 0;
215 secondary_cpt <= 0;
216 state <= slave;
217 ELSE
218 IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us
219 state <= auto; -- commutation to AUTO state
220 IF flag = '1' THEN
221 s_coarse_time <= coarse_time_load;
222 flag <= '0';
223 ELSE
224 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
225 END IF;
226 cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
227 secondary_cpt <= secondary_cpt + 1;
228 ELSE
229 cpt <= cpt + 1;
230 END IF;
231 END IF;
232
233 WHEN OTHERS =>
234 state <= auto;
235
236 END CASE;
237
238 IF secondary_cpt > 60 THEN
239 s_coarse_time(31) <= '1';
240 END IF;
241
242 IF NOT(previous_coarse_time_load = coarse_time_load) THEN
243 flag <= '1';
244 END IF;
245
246 previous_coarse_time_load <= coarse_time_load;
247
248 END IF;
249
250 END PROCESS;
251
252 fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32));
253
254 -- resetn grspw_tick soft_tick resetn_clk_div
255 -- 0 0 0 0
256 -- 0 0 1 0
257 -- 0 1 0 0
258 -- 0 1 1 0
259 -- 1 0 0 1
260 -- 1 0 1 0
261 -- 1 1 0 0
262 -- 1 1 1 0
263 resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0';
264 Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
265 GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div);
100 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
101 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
266 102
267 103 END Behavioral;
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@@ -17,67 +17,68
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.all;
22 library grlib;
23 use grlib.amba.all;
24 use grlib.stdlib.all;
25 use grlib.devices.all;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
26 26
27 package lpp_lfr_time_management is
27 PACKAGE lpp_lfr_time_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_TIME_MANAGEMENT
31 31
32 component apb_lfr_time_management is
32 COMPONENT apb_lfr_time_management IS
33 33
34 generic(
35 pindex : integer := 0; --! APB slave index
36 paddr : integer := 0; --! ADDR field of the APB BAR
37 pmask : integer := 16#fff#; --! MASK field of the APB BAR
38 pirq : integer := 0; --! 2 consecutive IRQ lines are used
39 masterclk : integer := 25000000; --! master clock in Hz
40 timeclk : integer := 49152000; --! other clock in Hz
41 finetimeclk : integer := 65536 --! divided clock used for the fine time counter
34 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : INTEGER := 0
42 39 );
43 40
44 Port (
45 clk25MHz : in STD_LOGIC; --! Clock
46 clk49_152MHz : in STD_LOGIC; --! secondary clock
47 resetn : in STD_LOGIC; --! Reset
48 grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbi : in apb_slv_in_type; --! APB slave input signals
50 apbo : out apb_slv_out_type; --! APB slave output signals
51 coarse_time : out std_logic_vector(31 downto 0); --! coarse time
52 fine_time : out std_logic_vector(31 downto 0) --! fine time
41 PORT (
42 clk25MHz : IN STD_LOGIC; --! Clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
44 resetn : IN STD_LOGIC; --! Reset
45 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
46 apbi : IN apb_slv_in_type; --! APB slave input signals
47 apbo : OUT apb_slv_out_type; --! APB slave output signals
48 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
49 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 50 );
54 51
55 end component;
56
57 component lfr_time_management is
52 END COMPONENT;
58 53
59 generic (
60 masterclk : integer := 25000000; -- master clock in Hz
61 timeclk : integer := 49152000; -- 2nd clock in Hz
62 finetimeclk : integer := 65536; -- divided clock used for the fine time counter
63 nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state
54 COMPONENT lfr_time_management
55 GENERIC (
56 nb_time_code_missing_limit : INTEGER);
57 PORT (
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 new_timecode : IN STD_LOGIC;
61 new_coarsetime : IN STD_LOGIC;
62 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
64 fine_time_new : OUT STD_LOGIC;
65 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_new : OUT STD_LOGIC
64 67 );
65 Port (
66 master_clock : in std_logic; --! Clock
67 time_clock : in std_logic; --! 2nd Clock
68 resetn : in std_logic; --! Reset
69 grspw_tick : in std_logic;
70 soft_tick : in std_logic; --! soft tick, load the coarse_time value
71 coarse_time_load : in std_logic_vector(31 downto 0);
72 coarse_time : out std_logic_vector(31 downto 0);
73 fine_time : out std_logic_vector(31 downto 0);
74 next_commutation : in std_logic_vector(31 downto 0);
75 -- reset_next_commutation: out std_logic;
76 irq1 : out std_logic;
77 irq2 : out std_logic
78 );
68 END COMPONENT;
79 69
80 end component;
70 COMPONENT lpp_counter
71 GENERIC (
72 nb_wait_period : INTEGER;
73 nb_bit_of_data : INTEGER);
74 PORT (
75 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
77 clear : IN STD_LOGIC;
78 full : OUT STD_LOGIC;
79 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
80 new_data : OUT STD_LOGIC );
81 END COMPONENT;
81 82
82 end lpp_lfr_time_management;
83 END lpp_lfr_time_management;
83 84
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@@ -1,3 +1,4
1 1 lpp_lfr_time_management.vhd
2 lpp_counter.vhd
2 3 lfr_time_management.vhd
3 4 apb_lfr_time_management.vhd
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@@ -110,17 +110,17 ARCHITECTURE Behavioral OF lpp_dma_ip IS
110 110 WAIT_DATA_ACK,
111 111 CHECK_LENGTH
112 112 );
113 SIGNAL state : state_DMAWriteBurst := IDLE;
113 SIGNAL state : state_DMAWriteBurst;-- := IDLE;
114 114
115 SIGNAL nbSend : INTEGER;
115 -- SIGNAL nbSend : INTEGER;
116 116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 119 SIGNAL header_check_ok : STD_LOGIC;
120 120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL send_matrix : STD_LOGIC;
122 SIGNAL request : STD_LOGIC;
123 SIGNAL remaining_data_request : INTEGER;
122 -- SIGNAL request : STD_LOGIC;
123 -- SIGNAL remaining_data_request : INTEGER;
124 124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 125 -----------------------------------------------------------------------------
126 126 -----------------------------------------------------------------------------
@@ -362,4 +362,4 BEGIN
362 362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
363 363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
364 364
365 END Behavioral;
365 END Behavioral; No newline at end of file
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@@ -184,4 +184,4 BEGIN
184 184 ZZ_pad : outpad GENERIC MAP (tech => tech)
185 185 PORT MAP (ZZ, '0');
186 186
187 END ARCHITECTURE;
187 END ARCHITECTURE; No newline at end of file
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@@ -139,10 +139,10 ARCHITECTURE beh OF lpp_lfr IS
139 139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141 141
142 SIGNAL val_f0_wfp : STD_LOGIC;
143 SIGNAL val_f1_wfp : STD_LOGIC;
144 SIGNAL val_f2_wfp : STD_LOGIC;
145 SIGNAL val_f3_wfp : STD_LOGIC;
142 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 -- SIGNAL val_f2_wfp : STD_LOGIC;
145 -- SIGNAL val_f3_wfp : STD_LOGIC;
146 146 BEGIN
147 147
148 148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -287,6 +287,8 BEGIN
287 287 data_f2_in_valid => sample_f2_val,
288 288 data_f3_in_valid => sample_f3_val);
289 289
290 time_info <= (others => '0');
291
290 292 data_f0_wfp <= sample_f0_data & time_info;
291 293 data_f1_wfp <= sample_f1_data & time_info;
292 294 data_f2_wfp <= sample_f2_data & time_info;
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@@ -73,10 +73,10 ARCHITECTURE tb OF lpp_lfr_filter IS
73 73 CONSTANT CoefPerCel : INTEGER := 5;
74 74 CONSTANT Cels_count : INTEGER := 5;
75 75
76 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
77 77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
78 78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 80 --
81 81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
82 82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -107,10 +107,10 ARCHITECTURE tb OF lpp_lfr_filter IS
107 107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
108 108
109 109 -----------------------------------------------------------------------------
110 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
110 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 114 -----------------------------------------------------------------------------
115 115
116 116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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@@ -4,9 +4,9 USE ieee.std_logic_1164.ALL;
4 4 LIBRARY lpp;
5 5 USE lpp.lpp_amba.ALL;
6 6 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 8 USE lpp.lpp_matrix.ALL;
9 USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 10 USE lpp.lpp_fft.ALL;
11 11 USE lpp.fft_components.ALL;
12 12 USE lpp.lpp_ad_conv.ALL;
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@@ -165,4 +165,32 PACKAGE lpp_lfr_pkg IS
165 165 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
166 166 END COMPONENT;
167 167
168 COMPONENT lpp_top_ms
169 GENERIC (
170 Mem_use : INTEGER;
171 nb_burst_available_size : INTEGER;
172 nb_snapshot_param_size : INTEGER;
173 delta_snapshot_size : INTEGER;
174 delta_f2_f0_size : INTEGER;
175 delta_f2_f1_size : INTEGER;
176 pindex : INTEGER;
177 paddr : INTEGER;
178 pmask : INTEGER;
179 pirq_ms : INTEGER;
180 pirq_wfp : INTEGER;
181 hindex_wfp : INTEGER;
182 hindex_ms : INTEGER);
183 PORT (
184 clk : IN STD_LOGIC;
185 rstn : IN STD_LOGIC;
186 sample_B : IN Samples14v(2 DOWNTO 0);
187 sample_E : IN Samples14v(4 DOWNTO 0);
188 sample_val : IN STD_LOGIC;
189 apbi : IN apb_slv_in_type;
190 apbo : OUT apb_slv_out_type;
191 ahbi_ms : IN AHB_Mst_In_Type;
192 ahbo_ms : OUT AHB_Mst_Out_Type;
193 data_shaping_BW : OUT STD_LOGIC);
194 END COMPONENT;
195
168 196 END lpp_lfr_pkg;
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@@ -10,4 +10,5 lpp_lfr_apbreg.vhd
10 10 top_wf_picker.vhd
11 11 lpp_lfr_filter.vhd
12 12 lpp_lfr_ms.vhd
13 lpp_top_ms.vhd
13 14 lpp_lfr.vhd
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@@ -94,7 +94,8 ARCHITECTURE beh OF lpp_waveform IS
94 94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 99 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 100 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 101 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -103,6 +104,7 ARCHITECTURE beh OF lpp_waveform IS
103 104 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 105 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 106 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
106 108
107 109 BEGIN -- beh
108 110
@@ -222,14 +224,15 BEGIN -- beh
222 224 data_wen => data_wen,
223 225 data => wdata);
224 226
225 ready_arb <= NOT ready;
227 ready_arb <= NOT data_ready;
226 228
227 229 lpp_waveform_fifo_1: lpp_waveform_fifo
228 230 GENERIC MAP (tech => tech)
229 231 PORT MAP (
230 232 clk => clk,
231 233 rstn => rstn,
232 ready => ready,
234 time_ready => time_ready,
235 data_ready => data_ready,
233 236 time_ren => time_ren, -- todo
234 237 data_ren => data_ren, -- todo
235 238 rdata => rdata, -- todo
@@ -238,6 +241,8 BEGIN -- beh
238 241 data_wen => data_wen,
239 242 wdata => wdata);
240 243
244 enable <= enable_f3 & enable_f2 & enable_f1 & enable_f0;
245
241 246 pp_waveform_dma_1: lpp_waveform_dma
242 247 GENERIC MAP (
243 248 data_size => data_size,
@@ -249,7 +254,9 BEGIN -- beh
249 254 HRESETn => rstn,
250 255 AHB_Master_In => AHB_Master_In,
251 256 AHB_Master_Out => AHB_Master_Out,
252 data_ready => ready,
257 enable => enable, -- todo
258 time_ready => time_ready, -- todo
259 data_ready => data_ready,
253 260 data => rdata,
254 261 data_data_ren => data_ren,
255 262 data_time_ren => time_ren,
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@@ -57,10 +57,12 ENTITY lpp_waveform_dma IS
57 57 AHB_Master_In : IN AHB_Mst_In_Type;
58 58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 59 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
60 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
63 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
65 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
64 66 -- Reg
65 67 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 68 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -79,7 +81,7 ARCHITECTURE Behavioral OF lpp_waveform_
79 81 SIGNAL DMAIn : DMA_In_Type;
80 82 SIGNAL DMAOut : DMA_OUt_Type;
81 83 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
84 TYPE state_DMAWriteBurst IS (IDLE,TRASH_FIFO_TIME,TRASH_FIFO_DATA,
83 85 SEND_TIME_0, WAIT_TIME_0,
84 86 SEND_TIME_1, WAIT_TIME_1,
85 87 SEND_5_TIME,
@@ -88,9 +90,12 ARCHITECTURE Behavioral OF lpp_waveform_
88 90 -----------------------------------------------------------------------------
89 91 -- CONTROL
90 92 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL sel_data_ss : STD_LOGIC;
94 SIGNAL sel_time_s : STD_LOGIC;
91 95 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 96 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 97 SIGNAL time_select : STD_LOGIC;
98 SIGNAL enable_sel : STD_LOGIC;
94 99 SIGNAL time_write : STD_LOGIC;
95 100 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 101 SIGNAL time_already_send_s : STD_LOGIC;
@@ -109,6 +114,7 ARCHITECTURE Behavioral OF lpp_waveform_
109 114 SIGNAL data_send_ok : STD_LOGIC;
110 115 SIGNAL data_send_ko : STD_LOGIC;
111 116 SIGNAL data_fifo_ren : STD_LOGIC;
117 SIGNAL trash_fifo_ren : STD_LOGIC;
112 118 SIGNAL data_ren : STD_LOGIC;
113 119 -----------------------------------------------------------------------------
114 120 -- SELECT ADDRESS
@@ -171,6 +177,21 BEGIN
171 177 "10" WHEN data_ready(2) = '1' ELSE
172 178 "11";
173 179
180 sel_data_ss <= data_ready(0) WHEN sel_data = "00" ELSE
181 data_ready(1) WHEN sel_data = "01" ELSE
182 data_ready(2) WHEN sel_data = "10" ELSE
183 data_ready(3);
184
185 sel_time_s <= time_ready(0) WHEN sel_data = "00" ELSE
186 time_ready(1) WHEN sel_data = "01" ELSE
187 time_ready(2) WHEN sel_data = "10" ELSE
188 time_ready(3);
189
190 enable_sel <= enable(0) WHEN sel_data = "00" ELSE
191 enable(1) WHEN sel_data = "01" ELSE
192 enable(2) WHEN sel_data = "10" ELSE
193 enable(3);
194
174 195 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
175 196 time_already_send(1) WHEN data_ready(1) = '1' ELSE
176 197 time_already_send(2) WHEN data_ready(2) = '1' ELSE
@@ -186,6 +207,7 BEGIN
186 207 update <= "00";
187 208 time_select <= '0';
188 209 time_fifo_ren <= '1';
210 trash_fifo_ren <= '1';
189 211 data_send <= '0';
190 212 time_send <= '0';
191 213 time_write <= '0';
@@ -203,14 +225,37 BEGIN
203 225 data_send <= '0';
204 226 time_send <= '0';
205 227 time_write <= '0';
206
228 trash_fifo_ren <= '1';
207 229 IF data_ready = "0000" THEN
208 230 state <= IDLE;
209 231 ELSE
210 232 sel_data <= sel_data_s;
233 IF enable_sel = '1' THEN
211 234 state <= SEND_5_TIME;
235 ELSE
236 state <= TRASH_FIFO_TIME;
212 237 END IF;
213 238
239 END IF;
240
241 WHEN TRASH_FIFO_TIME =>
242 time_select <= '1';
243 time_fifo_ren <= '0';
244 IF sel_time_s = '1' THEN
245 time_fifo_ren <= '1';
246 state <= TRASH_FIFO_DATA;
247 END IF;
248
249
250 WHEN TRASH_FIFO_DATA =>
251 time_select <= '1';
252 trash_fifo_ren <= '0';
253 IF sel_data_ss = '1' THEN
254 trash_fifo_ren <= '1';
255 state <= IDLE;
256 END IF;
257
258
214 259 WHEN SEND_5_TIME =>
215 260 update <= "00";
216 261 time_select <= '1';
@@ -284,7 +329,7 BEGIN
284 329 send_ko => data_send_ko);
285 330
286 331 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
287 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
332 data_ren <= trash_fifo_ren WHEN time_select = '1' ELSE data_fifo_ren;
288 333 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
289 334
290 335 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
@@ -306,6 +351,7 BEGIN
306 351 PORT MAP (
307 352 HCLK => HCLK,
308 353 HRESETn => HRESETn,
354 enable => enable(I),
309 355 update => update_and_sel((2*I)+1 DOWNTO 2*I),
310 356 nb_burst_available => nb_burst_available,
311 357 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
@@ -323,4 +369,4 BEGIN
323 369 -----------------------------------------------------------------------------
324 370
325 371
326 END Behavioral;
372 END Behavioral; No newline at end of file
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@@ -37,6 +37,7 ENTITY lpp_waveform_dma_selectaddress IS
37 37 HCLK : IN STD_ULOGIC;
38 38 HRESETn : IN STD_ULOGIC;
39 39
40 enable : IN STD_LOGIC;
40 41 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41 42
42 43 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
@@ -80,7 +81,9 BEGIN
80 81 update_r <= update;
81 82 CASE state IS
82 83 WHEN IDLE =>
83 IF update_s = '1' THEN
84 IF enable = '0' THEN
85 state <= UPDATED;
86 elsIF update_s = '1' THEN
84 87 state <= ADD;
85 88 END IF;
86 89
@@ -121,8 +124,10 BEGIN
121 124
122 125 WHEN UPDATED =>
123 126 status_full_err <= '0';
127 address <= addr_data_reg;
128 IF enable = '1' THEN
124 129 state <= IDLE;
125 address <= addr_data_reg;
130 END IF;
126 131
127 132 WHEN OTHERS => NULL;
128 133 END CASE;
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@@ -39,7 +39,8 ENTITY lpp_waveform_fifo IS
39 39 rstn : IN STD_LOGIC;
40 40
41 41 ---------------------------------------------------------------------------
42 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
42 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
43 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
43 44
44 45 ---------------------------------------------------------------------------
45 46 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -115,7 +116,7 BEGIN
115 116 GENERIC MAP (
116 117 offset => 32*I + 20,
117 118 length => 10,
118 enable_ready => '0')
119 enable_ready => '1')
119 120 PORT MAP (
120 121 clk => clk,
121 122 rstn => rstn,
@@ -125,7 +126,7 BEGIN
125 126 mem_we => time_mem_wen(I),
126 127 mem_addr_ren => time_mem_addr_r(I),
127 128 mem_addr_wen => time_mem_addr_w(I),
128 ready => OPEN);
129 ready => time_ready(I));
129 130 END GENERATE gen_fifo_ctrl_time;
130 131
131 132 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
@@ -143,7 +144,7 BEGIN
143 144 mem_we => data_mem_wen(I),
144 145 mem_addr_ren => data_mem_addr_r(I),
145 146 mem_addr_wen => data_mem_addr_w(I),
146 ready => ready(I));
147 ready => data_ready(I));
147 148 END GENERATE gen_fifo_ctrl_data;
148 149
149 150
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@@ -132,6 +132,7 PACKAGE lpp_waveform_pkg IS
132 132 PORT (
133 133 HCLK : IN STD_ULOGIC;
134 134 HRESETn : IN STD_ULOGIC;
135 enable : IN STD_LOGIC;
135 136 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
136 137 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
137 138 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -162,6 +163,8 PACKAGE lpp_waveform_pkg IS
162 163 HRESETn : IN STD_ULOGIC;
163 164 AHB_Master_In : IN AHB_Mst_In_Type;
164 165 AHB_Master_Out : OUT AHB_Mst_Out_Type;
166 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
167 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
165 168 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
166 169 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
167 170 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -229,7 +232,8 PACKAGE lpp_waveform_pkg IS
229 232 PORT (
230 233 clk : IN STD_LOGIC;
231 234 rstn : IN STD_LOGIC;
232 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
235 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
236 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 237 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 238 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
235 239 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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