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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 LIBRARY lpp;
27 USE lpp.general_purpose.ALL;
28
29 ENTITY SYNC_VALID_BIT IS
30 GENERIC (
31 NB_FF_OF_SYNC : INTEGER := 2);
32 PORT (
33 clk_in : IN STD_LOGIC;
34 clk_out : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 sin : IN STD_LOGIC;
37 sout : OUT STD_LOGIC);
38 END SYNC_VALID_BIT;
39
40 ARCHITECTURE beh OF SYNC_VALID_BIT IS
41 SIGNAL s_1 : STD_LOGIC;
42 SIGNAL s_2 : STD_LOGIC;
43 BEGIN -- beh
44
45 lpp_front_to_level_1: lpp_front_to_level
46 PORT MAP (
47 clk => clk_in,
48 rstn => rstn,
49 sin => sin,
50 sout => s_1);
51
52 SYNC_FF_1: SYNC_FF
53 GENERIC MAP (
54 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
55 PORT MAP (
56 clk => clk_out,
57 rstn => rstn,
58 A => s_1,
59 A_sync => s_2);
60
61 lpp_front_detection_1: lpp_front_detection
62 PORT MAP (
63 clk => clk_out,
64 rstn => rstn,
65 sin => s_2,
66 sout => sout);
67
68 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_detection IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_detection;
34
35 ARCHITECTURE beh OF lpp_front_detection IS
36
37 SIGNAL reg : STD_LOGIC;
38 SIGNAL sout_reg : STD_LOGIC;
39
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = NOT reg THEN
50 sout_reg <= '1';
51 ELSE
52 sout_reg <= '0';
53 END IF;
54 END IF;
55 END PROCESS;
56
57 sout <= sout_reg;
58
59 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_to_level IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_to_level;
34
35 ARCHITECTURE beh OF lpp_front_to_level IS
36
37 SIGNAL reg : STD_LOGIC;
38
39 SIGNAL sout_reg : STD_LOGIC;
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = '1' AND reg = '0' THEN
50 sout_reg <= NOT sout_reg;
51 END IF;
52 END IF;
53 END PROCESS;
54
55 sout <= sout_reg;
56
57 END beh;
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY lpp_counter IS
6
7 GENERIC (
8 nb_wait_period : INTEGER := 750;
9 nb_bit_of_data : INTEGER := 16
10 );
11 PORT (
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 clear : IN STD_LOGIC;
15 full : OUT STD_LOGIC;
16 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
17 new_data : OUT STD_LOGIC
18 );
19
20 END lpp_counter;
21
22 ARCHITECTURE beh OF lpp_counter IS
23
24 SIGNAL counter_wait : INTEGER;
25 SIGNAL counter_data : INTEGER;
26
27 SIGNAL new_data_s : STD_LOGIC;
28 BEGIN -- beh
29
30 PROCESS (clk, rstn)
31 BEGIN -- PROCESS
32 IF rstn = '0' THEN -- asynchronous reset (active low)
33 counter_wait <= 0;
34 counter_data <= 0;
35 full <= '0';
36 new_data_s <= '0';
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
38 IF clear = '1' THEN
39 counter_wait <= 0;
40 counter_data <= 0;
41 full <= '0';
42 new_data_s <= NOT new_data_s;
43 ELSE
44 IF counter_wait = nb_wait_period-1 THEN
45 counter_wait <= 0;
46 new_data_s <= NOT new_data_s;
47 IF counter_data = (2**nb_bit_of_data)-1 THEN
48 full <= '1';
49 counter_data <= 0;
50 ELSE
51 full <= '0';
52 counter_data <= counter_data +1;
53 END IF;
54 ELSE
55 full <= '0';
56 counter_wait <= counter_wait +1;
57 END IF;
58 END IF;
59 END IF;
60 END PROCESS;
61
62 data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data));
63 new_data <= new_data_s;
64
65 END beh;
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@@ -2,6 +2,7 iir_filter.vhd
2 FILTERcfg.vhd
2 FILTERcfg.vhd
3 RAM.vhd
3 RAM.vhd
4 RAM_CEL.vhd
4 RAM_CEL.vhd
5 RAM_CEL_N.vhd
5 RAM_CTRLR_v2.vhd
6 RAM_CTRLR_v2.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
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@@ -269,4 +269,31 Constant ctrl_CLRMAC : std_logic_vector(
269 A_sync : OUT STD_LOGIC);
269 A_sync : OUT STD_LOGIC);
270 END COMPONENT;
270 END COMPONENT;
271
271
272 COMPONENT lpp_front_to_level
273 PORT (
274 clk : IN STD_LOGIC;
275 rstn : IN STD_LOGIC;
276 sin : IN STD_LOGIC;
277 sout : OUT STD_LOGIC);
278 END COMPONENT;
279
280 COMPONENT lpp_front_detection
281 PORT (
282 clk : IN STD_LOGIC;
283 rstn : IN STD_LOGIC;
284 sin : IN STD_LOGIC;
285 sout : OUT STD_LOGIC);
286 END COMPONENT;
287
288 COMPONENT SYNC_VALID_BIT
289 GENERIC (
290 NB_FF_OF_SYNC : INTEGER);
291 PORT (
292 clk_in : IN STD_LOGIC;
293 clk_out : IN STD_LOGIC;
294 rstn : IN STD_LOGIC;
295 sin : IN STD_LOGIC;
296 sout : OUT STD_LOGIC);
297 END COMPONENT;
298
272 END;
299 END;
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@@ -16,3 +16,7 REG.vhd
16 SYNC_FF.vhd
16 SYNC_FF.vhd
17 Shifter.vhd
17 Shifter.vhd
18 TwoComplementer.vhd
18 TwoComplementer.vhd
19 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
21 SYNC_VALID_BIT.vhd
22
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@@ -26,29 +26,28 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30
31
31 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
32
33
33 GENERIC(
34 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used
38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
41 );
39 );
42
40
43 PORT (
41 PORT (
44 clk25MHz : IN STD_LOGIC; --! Clock
42 clk25MHz : IN STD_LOGIC; --! Clock
45 clk49_152MHz : IN STD_LOGIC; --! secondary clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
46 resetn : IN STD_LOGIC; --! Reset
44 resetn : IN STD_LOGIC; --! Reset
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45
48 apbi : IN apb_slv_in_type; --! APB slave input signals
46 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
47 apbi : IN apb_slv_in_type; --! APB slave input signals
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
48 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52 );
51 );
53
52
54 END apb_lfr_time_management;
53 END apb_lfr_time_management;
@@ -56,91 +55,83 END apb_lfr_time_management;
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
55 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57
56
58 CONSTANT REVISION : INTEGER := 1;
57 CONSTANT REVISION : INTEGER := 1;
59
60 --! the following types are defined in the grlib amba package
61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 CONSTANT pconfig : apb_config_type := (
58 CONSTANT pconfig : apb_config_type := (
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
59 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
66 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask)
61 );
67
62
68 TYPE apb_lfr_time_management_Reg IS RECORD
63 TYPE apb_lfr_time_management_Reg IS RECORD
69 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 END RECORD;
68 END RECORD;
75
69
76 SIGNAL r : apb_lfr_time_management_Reg;
70 SIGNAL r : apb_lfr_time_management_Reg;
77 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL force_tick : STD_LOGIC;
72 SIGNAL force_tick : STD_LOGIC;
79 SIGNAL previous_force_tick : STD_LOGIC;
73 SIGNAL previous_force_tick : STD_LOGIC;
80 SIGNAL soft_tick : STD_LOGIC;
74 SIGNAL soft_tick : STD_LOGIC;
81 -- SIGNAL reset_next_commutation : STD_LOGIC;
75
82
83 SIGNAL irq1 : STD_LOGIC;
76 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
77 SIGNAL irq2 : STD_LOGIC;
85
78
86 BEGIN
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
81
88 lfrtimemanagement0 : lfr_time_management
82 SIGNAL coarse_time_new : STD_LOGIC;
89 GENERIC MAP(
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
90 masterclk => masterclk,
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
91 timeclk => timeclk,
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
92 finetimeclk => finetimeclk,
86
93 nb_clk_div_ticks => 1)
87 SIGNAL fine_time_new : STD_LOGIC;
94 PORT MAP(
88 SIGNAL fine_time_new_temp : STD_LOGIC;
95 master_clock => clk25MHz,
89 SIGNAL fine_time_new_49 : STD_LOGIC;
96 time_clock => clk49_152MHz,
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
97 resetn => resetn,
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 grspw_tick => grspw_tick,
92 SIGNAL tick : STD_LOGIC;
99 soft_tick => soft_tick,
93 SIGNAL new_timecode : STD_LOGIC;
100 coarse_time_load => r.coarse_time_load,
94 SIGNAL new_coarsetime : STD_LOGIC;
101 coarse_time => r.coarse_time,
95
102 fine_time => r.fine_time,
96 BEGIN
103 next_commutation => r.next_commutation,
97 -----------------------------------------------------------------------------
104 -- reset_next_commutation => reset_next_commutation,
98 -- TODO
105 irq1 => irq1,--apbo.pirq(pirq),
99 -- IRQ 1 & 2
106 irq2 => irq2);--apbo.pirq(pirq+1));
100 -----------------------------------------------------------------------------
101 irq2 <= '0';
102 irq1 <= '0';
107
103
108 --apbo.pirq <= (OTHERS => '0');
104
105 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
106 --irq1_gen : IF I = pirq GENERATE
107 apbo.pirq(pirq) <= irq1;
108 --END GENERATE irq1_gen;
109 --irq2_gen : IF I = pirq+1 GENERATE
110 apbo.pirq(pirq+1) <= irq2;
111 -- END GENERATE irq2_gen;
112 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
113 -- apbo.pirq(I) <= '0';
114 -- END GENERATE others_irq;
115 --END GENERATE all_irq_gen;
109
116
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
117 PROCESS(resetn, clk25MHz)
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
124
125 PROCESS(resetn, clk25MHz)--, reset_next_commutation)
126 BEGIN
118 BEGIN
127
119
128 IF resetn = '0' THEN
120 IF resetn = '0' THEN
129 Rdata <= (OTHERS => '0');
121 Rdata <= (OTHERS => '0');
130 r.coarse_time_load <= x"80000000";
122 r.coarse_time_load <= x"80000000";
131 r.ctrl <= x"00000000";
123 r.ctrl <= x"00000000";
132 r.next_commutation <= x"ffffffff";
133 force_tick <= '0';
124 force_tick <= '0';
134 previous_force_tick <= '0';
125 previous_force_tick <= '0';
135 soft_tick <= '0';
126 soft_tick <= '0';
136
127
137 --ELSIF reset_next_commutation = '1' THEN
128 coarsetime_reg_updated <= '0';
138 -- r.next_commutation <= x"ffffffff";
139
129
140 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
130 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
131 coarsetime_reg_updated <= '0';
141
132
133 force_tick <= r.ctrl(0);
142 previous_force_tick <= force_tick;
134 previous_force_tick <= force_tick;
143 force_tick <= r.ctrl(0);
144 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
135 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
145 soft_tick <= '1';
136 soft_tick <= '1';
146 ELSE
137 ELSE
@@ -154,10 +145,8 BEGIN
154 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
145 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
155 WHEN "000001" =>
146 WHEN "000001" =>
156 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
147 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
157 WHEN "000100" =>
148 coarsetime_reg_updated <= '1';
158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
159 WHEN OTHERS =>
149 WHEN OTHERS =>
160 r.coarse_time_load <= x"00000000";
161 END CASE;
150 END CASE;
162 ELSIF r.ctrl(0) = '1' THEN
151 ELSIF r.ctrl(0) = '1' THEN
163 r.ctrl(0) <= '0';
152 r.ctrl(0) <= '0';
@@ -167,30 +156,14 BEGIN
167 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
156 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
168 CASE apbi.paddr(7 DOWNTO 2) IS
157 CASE apbi.paddr(7 DOWNTO 2) IS
169 WHEN "000000" =>
158 WHEN "000000" =>
170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
159 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
174 WHEN "000001" =>
160 WHEN "000001" =>
175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
161 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
179 WHEN "000010" =>
162 WHEN "000010" =>
180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
163 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
184 WHEN "000011" =>
164 WHEN "000011" =>
185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
165 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
166 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
189 WHEN "000100" =>
190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
194 WHEN OTHERS =>
167 WHEN OTHERS =>
195 Rdata(31 DOWNTO 0) <= x"00000000";
168 Rdata(31 DOWNTO 0) <= x"00000000";
196 END CASE;
169 END CASE;
@@ -199,10 +172,115 BEGIN
199 END IF;
172 END IF;
200 END PROCESS;
173 END PROCESS;
201
174
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
175 apbo.prdata <= Rdata;
176 apbo.pconfig <= pconfig;
177 apbo.pindex <= pindex;
178
203 coarse_time <= r.coarse_time;
179 coarse_time <= r.coarse_time;
204 fine_time <= r.fine_time;
180 fine_time <= r.fine_time;
205 apbo.pconfig <= pconfig;
181 -----------------------------------------------------------------------------
206 apbo.pindex <= pindex;
182
183 coarsetime_reg <= r.coarse_time_load;
184 r.coarse_time <= coarse_time_s;
185 r.fine_time <= fine_time_s;
186 -----------------------------------------------------------------------------
187 -- IN coarsetime_reg_updated
188 -- IN coarsetime_reg
189
190 -- OUT coarse_time_s -- ok
191 -- OUT fine_time_s -- ok
192 -----------------------------------------------------------------------------
193
194 tick <= grspw_tick OR soft_tick;
195
196 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
197 GENERIC MAP (
198 NB_FF_OF_SYNC => 2)
199 PORT MAP (
200 clk_in => clk25MHz,
201 clk_out => clk49_152MHz,
202 rstn => resetn,
203 sin => tick,
204 sout => new_timecode);
205
206 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
207 GENERIC MAP (
208 NB_FF_OF_SYNC => 2)
209 PORT MAP (
210 clk_in => clk25MHz,
211 clk_out => clk49_152MHz,
212 rstn => resetn,
213 sin => coarsetime_reg_updated,
214 sout => new_coarsetime);
215
216 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
217 -- GENERIC MAP (
218 -- NB_FF_OF_SYNC => 2)
219 -- PORT MAP (
220 -- clk_in => clk49_152MHz,
221 -- clk_out => clk25MHz,
222 -- rstn => resetn,
223 -- sin => 9,
224 -- sout => );
225
226 SYNC_FF_1: SYNC_FF
227 GENERIC MAP (
228 NB_FF_OF_SYNC => 2)
229 PORT MAP (
230 clk => clk25MHz,
231 rstn => resetn,
232 A => fine_time_new_49,
233 A_sync => fine_time_new_temp);
234
235 lpp_front_detection_1: lpp_front_detection
236 PORT MAP (
237 clk => clk25MHz,
238 rstn => resetn,
239 sin => fine_time_new_temp,
240 sout => fine_time_new);
241
242 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
243 GENERIC MAP (
244 NB_FF_OF_SYNC => 2)
245 PORT MAP (
246 clk_in => clk49_152MHz,
247 clk_out => clk25MHz,
248 rstn => resetn,
249 sin => coarse_time_new_49,
250 sout => coarse_time_new);
251
252 PROCESS (clk25MHz, resetn)
253 BEGIN -- PROCESS
254 IF resetn = '0' THEN -- asynchronous reset (active low)
255 fine_time_s <= (OTHERS => '0');
256 coarse_time_s <= (OTHERS => '0');
257 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
258 IF fine_time_new = '1' THEN
259 fine_time_s <= fine_time_49;
260 END IF;
261 IF coarse_time_new = '1' THEN
262 coarse_time_s <= coarse_time_49;
263 END IF;
264 END IF;
265 END PROCESS;
266
267 -----------------------------------------------------------------------------
268 -- LFR_TIME_MANAGMENT
269 -----------------------------------------------------------------------------
270 lfr_time_management_1 : lfr_time_management
271 GENERIC MAP (
272 nb_time_code_missing_limit => 60)
273 PORT MAP (
274 clk => clk49_152MHz,
275 rstn => resetn,
276
277 new_timecode => new_timecode,
278 new_coarsetime => new_coarsetime,
279 coarsetime_reg => coarsetime_reg,
280
281 fine_time => fine_time_49,
282 fine_time_new => fine_time_new_49,
283 coarse_time => coarse_time_49,
284 coarse_time_new => coarse_time_new_49);
207
285
208 END Behavioral;
286 END Behavioral;
Show file before | Show file after | Hide comments
@@ -21,247 +21,83 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.general_purpose.Clk_divider;
24 USE lpp.lpp_lfr_time_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 masterclk : INTEGER := 25000000; -- master clock in Hz
28 nb_time_code_missing_limit : INTEGER := 60
29 timeclk : INTEGER := 49152000; -- 2nd clock in Hz
30 finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter
31 nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state
32 );
29 );
33 PORT (
30 PORT (
34 master_clock : IN STD_LOGIC; --! Clock -- 25MHz
31 clk : IN STD_LOGIC;
35 time_clock : IN STD_LOGIC; --! 2nd Clock -- 49MHz
32 rstn : IN STD_LOGIC;
36 resetn : IN STD_LOGIC; --! Reset
33
37 grspw_tick : IN STD_LOGIC;
34 new_timecode : IN STD_LOGIC; -- transition signal information
38 soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value -- 25MHz
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
39 coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
36 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
37
41 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
42 next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
39 fine_time_new : OUT STD_LOGIC;
43 -- reset_next_commutation : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 irq1 : OUT STD_LOGIC; -- 25MHz
41 coarse_time_new : OUT STD_LOGIC
45 irq2 : OUT STD_LOGIC -- 25MHz
46 );
42 );
47 END lfr_time_management;
43 END lfr_time_management;
48
44
49 ARCHITECTURE Behavioral OF lfr_time_management IS
45 ARCHITECTURE Behavioral OF lfr_time_management IS
50
46
51 SIGNAL resetn_clk_div : STD_LOGIC;
47 SIGNAL counter_clear : STD_LOGIC;
52 SIGNAL clk_div : STD_LOGIC;
48 SIGNAL counter_full : STD_LOGIC;
53 --
54 SIGNAL flag : STD_LOGIC;
55 SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL cpt : INTEGER RANGE 0 TO 100000;
58 SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000;
59 --
60 SIGNAL sirq1 : STD_LOGIC;
61 SIGNAL sirq2 : STD_LOGIC;
62 SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000;
63 SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 SIGNAL p_clk_div : STD_LOGIC;
66 --
67 TYPE state_type IS (auto, slave);
68 SIGNAL state : state_type;
69 TYPE timer_type IS (idle, engaged);
70 SIGNAL commutation_timer : timer_type;
71
49
50 SIGNAL nb_time_code_missing : INTEGER;
51 SIGNAL coarse_time_s : INTEGER;
52
72 BEGIN
53 BEGIN
73
54
74 --*******************************************
55 lpp_counter_1 : lpp_counter
75 -- COMMUTATION TIMER AND INTERRUPT GENERATION
56 GENERIC MAP (
76 PROCESS(master_clock, resetn)
57 nb_wait_period => 750,
77 BEGIN
58 nb_bit_of_data => 16)
59 PORT MAP (
60 clk => clk,
61 rstn => rstn,
62 clear => counter_clear,
63 full => counter_full,
64 data => fine_time,
65 new_data => fine_time_new);
78
66
79 IF resetn = '0' THEN
67 PROCESS (clk, rstn)
80 commutation_timer <= idle;
68 BEGIN -- PROCESS
81 cpt_next_commutation <= 0;
69 IF rstn = '0' THEN -- asynchronous reset (active low)
82 sirq1 <= '0';
70 nb_time_code_missing <= 0;
83 sirq2 <= '0';
71 counter_clear <= '0';
84 latched_next_commutation <= x"ffffffff";
72 coarse_time_s <= 0;
85 p_next_commutation <= (others => '0');
73 coarse_time_new <= '0';
86 p_clk_div <= '0';
74 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
87 ELSIF master_clock'EVENT AND master_clock = '1' THEN
75 IF new_timecode = '1' THEN
88
76 coarse_time_new <= '1';
89 CASE commutation_timer IS
77 IF new_coarsetime = '1' THEN
90
78 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
91 WHEN idle =>
79 ELSE
92 sirq1 <= '0';
80 coarse_time_s <= coarse_time_s + 1;
93 sirq2 <= '0';
81 END IF;
94 IF s_coarse_time = latched_next_commutation THEN
82 nb_time_code_missing <= 0;
95 commutation_timer <= engaged; -- transition to state "engaged"
83 counter_clear <= '1';
96 sirq1 <= '1'; -- start the pulse on sirq1
84 ELSE
97 latched_next_commutation <= x"ffffffff";
85 coarse_time_new <= '0';
98 ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed
86 counter_clear <= '0';
99 latched_next_commutation <= next_commutation; -- latch the value
87 IF counter_full = '1' THEN
88 coarse_time_new <= '1';
89 coarse_time_s <= coarse_time_s + 1;
90 IF nb_time_code_missing = nb_time_code_missing_limit THEN
91 nb_time_code_missing <= nb_time_code_missing_limit;
100 ELSE
92 ELSE
101 commutation_timer <= idle;
93 nb_time_code_missing <= nb_time_code_missing + 1;
102 END IF;
94 END IF;
103
95 END IF;
104 WHEN engaged =>
96 END IF;
105 sirq1 <= '0'; -- stop the pulse on sirq1
106 IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge
107 IF cpt_next_commutation = 65536 THEN
108 cpt_next_commutation <= 0;
109 commutation_timer <= idle;
110 sirq2 <= '1'; -- start the pulse on sirq2
111 ELSE
112 cpt_next_commutation <= cpt_next_commutation + 1;
113 END IF;
114 END IF;
115
116 WHEN OTHERS =>
117 commutation_timer <= idle;
118
119 END CASE;
120
121 p_next_commutation <= next_commutation;
122 p_clk_div <= clk_div;
123
124 END IF;
97 END IF;
125
126 END PROCESS;
98 END PROCESS;
127
99
128 irq1 <= sirq1;
100 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
129 irq2 <= sirq2;
101 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
130 -- reset_next_commutation <= '0';
102
131
132 --
133 --*******************************************
134
135 --**********************
136 -- synchronization stage
137 PROCESS(master_clock, resetn) -- resynchronisation with clk
138 BEGIN
139
140 IF resetn = '0' THEN
141 coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
142
143 ELSIF master_clock'EVENT AND master_clock = '1' THEN
144 coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk
145 END IF;
146
147 END PROCESS;
148 --
149 --**********************
150
151
152 -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC
153 PROCESS(clk_div, resetn) -- JC
154 BEGIN
155
156 IF resetn = '0' THEN
157 flag <= '0';
158 cpt <= 0;
159 secondary_cpt <= 0;
160 s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
161 previous_coarse_time_load <= x"80000000";
162 state <= auto;
163
164 --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN
165 -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
166 -- -- s_coarse_time <= coarse_time_load;
167 -- -- flag <= '0';
168 -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously
169 -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
170 -- --END IF;
171
172 -- cpt <= 0;
173 -- secondary_cpt <= 0;
174 -- state <= slave;
175
176 ELSIF clk_div'EVENT AND clk_div = '1' THEN
177
178 CASE state IS
179
180 WHEN auto =>
181 IF grspw_tick = '1' OR soft_tick = '1' THEN
182 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
183 s_coarse_time <= coarse_time_load;
184 ELSE -- if coarse_time_load has not changed, increment the value autonomously
185 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
186 END IF;
187 flag <= '0';
188 cpt <= 0;
189 secondary_cpt <= 0;
190 state <= slave;
191 ELSE
192 IF cpt = 65535 THEN
193 IF flag = '1' THEN
194 s_coarse_time <= coarse_time_load;
195 flag <= '0';
196 ELSE
197 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
198 END IF;
199 cpt <= 0;
200 secondary_cpt <= secondary_cpt + 1;
201 ELSE
202 cpt <= cpt + 1;
203 END IF;
204 END IF;
205
206 WHEN slave =>
207 IF grspw_tick = '1' OR soft_tick = '1' THEN
208 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
209 s_coarse_time <= coarse_time_load;
210 ELSE -- if coarse_time_load has not changed, increment the value autonomously
211 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
212 END IF;
213 flag <= '0';
214 cpt <= 0;
215 secondary_cpt <= 0;
216 state <= slave;
217 ELSE
218 IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us
219 state <= auto; -- commutation to AUTO state
220 IF flag = '1' THEN
221 s_coarse_time <= coarse_time_load;
222 flag <= '0';
223 ELSE
224 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
225 END IF;
226 cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
227 secondary_cpt <= secondary_cpt + 1;
228 ELSE
229 cpt <= cpt + 1;
230 END IF;
231 END IF;
232
233 WHEN OTHERS =>
234 state <= auto;
235
236 END CASE;
237
238 IF secondary_cpt > 60 THEN
239 s_coarse_time(31) <= '1';
240 END IF;
241
242 IF NOT(previous_coarse_time_load = coarse_time_load) THEN
243 flag <= '1';
244 END IF;
245
246 previous_coarse_time_load <= coarse_time_load;
247
248 END IF;
249
250 END PROCESS;
251
252 fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32));
253
254 -- resetn grspw_tick soft_tick resetn_clk_div
255 -- 0 0 0 0
256 -- 0 0 1 0
257 -- 0 1 0 0
258 -- 0 1 1 0
259 -- 1 0 0 1
260 -- 1 0 1 0
261 -- 1 1 0 0
262 -- 1 1 1 0
263 resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0';
264 Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
265 GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div);
266
267 END Behavioral;
103 END Behavioral;
Show file before | Show file after | Hide comments
@@ -17,67 +17,68
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 library IEEE;
20 LIBRARY IEEE;
21 use IEEE.STD_LOGIC_1164.all;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 library grlib;
22 LIBRARY grlib;
23 use grlib.amba.all;
23 USE grlib.amba.ALL;
24 use grlib.stdlib.all;
24 USE grlib.stdlib.ALL;
25 use grlib.devices.all;
25 USE grlib.devices.ALL;
26
26
27 package lpp_lfr_time_management is
27 PACKAGE lpp_lfr_time_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_TIME_MANAGEMENT
31
31
32 component apb_lfr_time_management is
32 COMPONENT apb_lfr_time_management IS
33
33
34 generic(
34 GENERIC(
35 pindex : integer := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : integer := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : integer := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : integer := 0; --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0
39 masterclk : integer := 25000000; --! master clock in Hz
39 );
40 timeclk : integer := 49152000; --! other clock in Hz
41 finetimeclk : integer := 65536 --! divided clock used for the fine time counter
42 );
43
40
44 Port (
41 PORT (
45 clk25MHz : in STD_LOGIC; --! Clock
42 clk25MHz : IN STD_LOGIC; --! Clock
46 clk49_152MHz : in STD_LOGIC; --! secondary clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
47 resetn : in STD_LOGIC; --! Reset
44 resetn : IN STD_LOGIC; --! Reset
48 grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbi : in apb_slv_in_type; --! APB slave input signals
46 apbi : IN apb_slv_in_type; --! APB slave input signals
50 apbo : out apb_slv_out_type; --! APB slave output signals
47 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 coarse_time : out std_logic_vector(31 downto 0); --! coarse time
48 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
52 fine_time : out std_logic_vector(31 downto 0) --! fine time
49 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 );
50 );
54
51
55 end component;
52 END COMPONENT;
56
53
57 component lfr_time_management is
54 COMPONENT lfr_time_management
55 GENERIC (
56 nb_time_code_missing_limit : INTEGER);
57 PORT (
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 new_timecode : IN STD_LOGIC;
61 new_coarsetime : IN STD_LOGIC;
62 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
64 fine_time_new : OUT STD_LOGIC;
65 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_new : OUT STD_LOGIC
67 );
68 END COMPONENT;
58
69
59 generic (
70 COMPONENT lpp_counter
60 masterclk : integer := 25000000; -- master clock in Hz
71 GENERIC (
61 timeclk : integer := 49152000; -- 2nd clock in Hz
72 nb_wait_period : INTEGER;
62 finetimeclk : integer := 65536; -- divided clock used for the fine time counter
73 nb_bit_of_data : INTEGER);
63 nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state
74 PORT (
64 );
75 clk : IN STD_LOGIC;
65 Port (
76 rstn : IN STD_LOGIC;
66 master_clock : in std_logic; --! Clock
77 clear : IN STD_LOGIC;
67 time_clock : in std_logic; --! 2nd Clock
78 full : OUT STD_LOGIC;
68 resetn : in std_logic; --! Reset
79 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
69 grspw_tick : in std_logic;
80 new_data : OUT STD_LOGIC );
70 soft_tick : in std_logic; --! soft tick, load the coarse_time value
81 END COMPONENT;
71 coarse_time_load : in std_logic_vector(31 downto 0);
72 coarse_time : out std_logic_vector(31 downto 0);
73 fine_time : out std_logic_vector(31 downto 0);
74 next_commutation : in std_logic_vector(31 downto 0);
75 -- reset_next_commutation: out std_logic;
76 irq1 : out std_logic;
77 irq2 : out std_logic
78 );
79
80 end component;
81
82
82 end lpp_lfr_time_management;
83 END lpp_lfr_time_management;
83
84
Show file before | Show file after | Hide comments
@@ -1,3 +1,4
1 lpp_lfr_time_management.vhd
1 lpp_lfr_time_management.vhd
2 lpp_counter.vhd
2 lfr_time_management.vhd
3 lfr_time_management.vhd
3 apb_lfr_time_management.vhd
4 apb_lfr_time_management.vhd
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@@ -110,17 +110,17 ARCHITECTURE Behavioral OF lpp_dma_ip IS
110 WAIT_DATA_ACK,
110 WAIT_DATA_ACK,
111 CHECK_LENGTH
111 CHECK_LENGTH
112 );
112 );
113 SIGNAL state : state_DMAWriteBurst := IDLE;
113 SIGNAL state : state_DMAWriteBurst;-- := IDLE;
114
114
115 SIGNAL nbSend : INTEGER;
115 -- SIGNAL nbSend : INTEGER;
116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL header_check_ok : STD_LOGIC;
119 SIGNAL header_check_ok : STD_LOGIC;
120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL send_matrix : STD_LOGIC;
121 SIGNAL send_matrix : STD_LOGIC;
122 SIGNAL request : STD_LOGIC;
122 -- SIGNAL request : STD_LOGIC;
123 SIGNAL remaining_data_request : INTEGER;
123 -- SIGNAL remaining_data_request : INTEGER;
124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
@@ -362,4 +362,4 BEGIN
362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
364
364
365 END Behavioral;
365 END Behavioral; No newline at end of file
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@@ -104,7 +104,7 BEGIN
104 END IF;
104 END IF;
105 END PROCESS;
105 END PROCESS;
106
106
107 --nclk <= NOT clk;
107 --nclk <= NOT clk;
108 ssram_clk_pad : outpad GENERIC MAP (tech => tech)
108 ssram_clk_pad : outpad GENERIC MAP (tech => tech)
109 PORT MAP (SSRAM_CLK, NOT clk);
109 PORT MAP (SSRAM_CLK, NOT clk);
110
110
@@ -184,4 +184,4 BEGIN
184 ZZ_pad : outpad GENERIC MAP (tech => tech)
184 ZZ_pad : outpad GENERIC MAP (tech => tech)
185 PORT MAP (ZZ, '0');
185 PORT MAP (ZZ, '0');
186
186
187 END ARCHITECTURE;
187 END ARCHITECTURE; No newline at end of file
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@@ -139,10 +139,10 ARCHITECTURE beh OF lpp_lfr IS
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
141
141
142 SIGNAL val_f0_wfp : STD_LOGIC;
142 -- SIGNAL val_f0_wfp : STD_LOGIC;
143 SIGNAL val_f1_wfp : STD_LOGIC;
143 -- SIGNAL val_f1_wfp : STD_LOGIC;
144 SIGNAL val_f2_wfp : STD_LOGIC;
144 -- SIGNAL val_f2_wfp : STD_LOGIC;
145 SIGNAL val_f3_wfp : STD_LOGIC;
145 -- SIGNAL val_f3_wfp : STD_LOGIC;
146 BEGIN
146 BEGIN
147
147
148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -287,6 +287,8 BEGIN
287 data_f2_in_valid => sample_f2_val,
287 data_f2_in_valid => sample_f2_val,
288 data_f3_in_valid => sample_f3_val);
288 data_f3_in_valid => sample_f3_val);
289
289
290 time_info <= (others => '0');
291
290 data_f0_wfp <= sample_f0_data & time_info;
292 data_f0_wfp <= sample_f0_data & time_info;
291 data_f1_wfp <= sample_f1_data & time_info;
293 data_f1_wfp <= sample_f1_data & time_info;
292 data_f2_wfp <= sample_f2_data & time_info;
294 data_f2_wfp <= sample_f2_data & time_info;
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@@ -73,10 +73,10 ARCHITECTURE tb OF lpp_lfr_filter IS
73 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT CoefPerCel : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
75
75
76 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 --
80 --
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -107,10 +107,10 ARCHITECTURE tb OF lpp_lfr_filter IS
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
110 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115
115
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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This diff has been collapsed as it changes many lines, (690 lines changed) Show them Hide them
@@ -1,346 +1,346
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20
20
21 LIBRARY grlib;
21 LIBRARY grlib;
22 USE grlib.amba.ALL;
22 USE grlib.amba.ALL;
23 USE grlib.stdlib.ALL;
23 USE grlib.stdlib.ALL;
24 USE grlib.devices.ALL;
24 USE grlib.devices.ALL;
25 USE GRLIB.DMA2AHB_Package.ALL;
25 USE GRLIB.DMA2AHB_Package.ALL;
26
26
27
27
28 ENTITY lpp_lfr_ms IS
28 ENTITY lpp_lfr_ms IS
29 GENERIC (
29 GENERIC (
30 hindex : INTEGER := 2
30 hindex : INTEGER := 2
31 );
31 );
32 PORT (
32 PORT (
33 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35
35
36 ---------------------------------------------------------------------------
36 ---------------------------------------------------------------------------
37 -- DATA INPUT
37 -- DATA INPUT
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 --
39 --
40 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
41 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 --
42 --
43 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 --
45 --
46 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
47 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48
48
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 -- DMA
50 -- DMA
51 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
52
52
53 -- AMBA AHB Master Interface
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
56
57 -- Reg out
57 -- Reg out
58 ready_matrix_f0_0 : OUT STD_LOGIC;
58 ready_matrix_f0_0 : OUT STD_LOGIC;
59 ready_matrix_f0_1 : OUT STD_LOGIC;
59 ready_matrix_f0_1 : OUT STD_LOGIC;
60 ready_matrix_f1 : OUT STD_LOGIC;
60 ready_matrix_f1 : OUT STD_LOGIC;
61 ready_matrix_f2 : OUT STD_LOGIC;
61 ready_matrix_f2 : OUT STD_LOGIC;
62 error_anticipating_empty_fifo : OUT STD_LOGIC;
62 error_anticipating_empty_fifo : OUT STD_LOGIC;
63 error_bad_component_error : OUT STD_LOGIC;
63 error_bad_component_error : OUT STD_LOGIC;
64 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65
65
66 -- Reg In
66 -- Reg In
67 status_ready_matrix_f0_0 :IN STD_LOGIC;
67 status_ready_matrix_f0_0 :IN STD_LOGIC;
68 status_ready_matrix_f0_1 :IN STD_LOGIC;
68 status_ready_matrix_f0_1 :IN STD_LOGIC;
69 status_ready_matrix_f1 :IN STD_LOGIC;
69 status_ready_matrix_f1 :IN STD_LOGIC;
70 status_ready_matrix_f2 :IN STD_LOGIC;
70 status_ready_matrix_f2 :IN STD_LOGIC;
71 status_error_anticipating_empty_fifo :IN STD_LOGIC;
71 status_error_anticipating_empty_fifo :IN STD_LOGIC;
72 status_error_bad_component_error :IN STD_LOGIC;
72 status_error_bad_component_error :IN STD_LOGIC;
73
73
74 config_active_interruption_onNewMatrix : IN STD_LOGIC;
74 config_active_interruption_onNewMatrix : IN STD_LOGIC;
75 config_active_interruption_onError : IN STD_LOGIC;
75 config_active_interruption_onError : IN STD_LOGIC;
76 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
79 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
80 );
80 );
81 END;
81 END;
82
82
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
84 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
85 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
88 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
89 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
89 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
90 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
90 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
91
91
92 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
93 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
93 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
94 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
95 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
96 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
96 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
97
97
98 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
99 SIGNAL FFT_Load : STD_LOGIC;
99 SIGNAL FFT_Load : STD_LOGIC;
100 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
103 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
104
104
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL SM_FlagError : STD_LOGIC;
110 SIGNAL SM_FlagError : STD_LOGIC;
111 SIGNAL SM_Pong : STD_LOGIC;
111 SIGNAL SM_Pong : STD_LOGIC;
112 SIGNAL SM_Wen : STD_LOGIC;
112 SIGNAL SM_Wen : STD_LOGIC;
113 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
117 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
122 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
123
123
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL Head_Empty : STD_LOGIC;
127 SIGNAL Head_Empty : STD_LOGIC;
128 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL Head_Valid : STD_LOGIC;
129 SIGNAL Head_Valid : STD_LOGIC;
130 SIGNAL Head_Val : STD_LOGIC;
130 SIGNAL Head_Val : STD_LOGIC;
131
131
132 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
133 SIGNAL DMA_Read : STD_LOGIC;
133 SIGNAL DMA_Read : STD_LOGIC;
134 SIGNAL DMA_ack : STD_LOGIC;
134 SIGNAL DMA_ack : STD_LOGIC;
135
135
136 BEGIN
136 BEGIN
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 Memf0: lppFIFOxN
139 Memf0: lppFIFOxN
140 GENERIC MAP (
140 GENERIC MAP (
141 tech => 0, Mem_use => use_RAM, Data_sz => 16,
141 tech => 0, Mem_use => use_RAM, Data_sz => 16,
142 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
142 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
143 PORT MAP (
143 PORT MAP (
144 rst => rstn, wclk => clk, rclk => clk,
144 rst => rstn, wclk => clk, rclk => clk,
145 ReUse => (OTHERS => '0'),
145 ReUse => (OTHERS => '0'),
146 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
146 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
147 wdata => sample_f0_wdata, rdata => FifoF0_Data,
147 wdata => sample_f0_wdata, rdata => FifoF0_Data,
148 full => OPEN, empty => FifoF0_Empty);
148 full => OPEN, empty => FifoF0_Empty);
149
149
150 Memf1: lppFIFOxN
150 Memf1: lppFIFOxN
151 GENERIC MAP (
151 GENERIC MAP (
152 tech => 0, Mem_use => use_RAM, Data_sz => 16,
152 tech => 0, Mem_use => use_RAM, Data_sz => 16,
153 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
153 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
154 PORT MAP (
154 PORT MAP (
155 rst => rstn, wclk => clk, rclk => clk,
155 rst => rstn, wclk => clk, rclk => clk,
156 ReUse => (OTHERS => '0'),
156 ReUse => (OTHERS => '0'),
157 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
157 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
158 wdata => sample_f1_wdata, rdata => FifoF1_Data,
158 wdata => sample_f1_wdata, rdata => FifoF1_Data,
159 full => OPEN, empty => FifoF1_Empty);
159 full => OPEN, empty => FifoF1_Empty);
160
160
161
161
162 Memf2: lppFIFOxN
162 Memf2: lppFIFOxN
163 GENERIC MAP (
163 GENERIC MAP (
164 tech => 0, Mem_use => use_RAM, Data_sz => 16,
164 tech => 0, Mem_use => use_RAM, Data_sz => 16,
165 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
165 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
166 PORT MAP (
166 PORT MAP (
167 rst => rstn, wclk => clk, rclk => clk,
167 rst => rstn, wclk => clk, rclk => clk,
168 ReUse => (OTHERS => '0'),
168 ReUse => (OTHERS => '0'),
169 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
169 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
170 wdata => sample_f3_wdata, rdata => FifoF3_Data,
170 wdata => sample_f3_wdata, rdata => FifoF3_Data,
171 full => OPEN, empty => FifoF3_Empty);
171 full => OPEN, empty => FifoF3_Empty);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173
173
174
174
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176 DMUX0 : DEMUX
176 DMUX0 : DEMUX
177 GENERIC MAP (
177 GENERIC MAP (
178 Data_sz => 16)
178 Data_sz => 16)
179 PORT MAP (
179 PORT MAP (
180 clk => clk,
180 clk => clk,
181 rstn => rstn,
181 rstn => rstn,
182 Read => FFT_Read,
182 Read => FFT_Read,
183 Load => FFT_Load,
183 Load => FFT_Load,
184 EmptyF0 => FifoF0_Empty,
184 EmptyF0 => FifoF0_Empty,
185 EmptyF1 => FifoF1_Empty,
185 EmptyF1 => FifoF1_Empty,
186 EmptyF2 => FifoF3_Empty,
186 EmptyF2 => FifoF3_Empty,
187 DataF0 => FifoF0_Data,
187 DataF0 => FifoF0_Data,
188 DataF1 => FifoF1_Data,
188 DataF1 => FifoF1_Data,
189 DataF2 => FifoF3_Data,
189 DataF2 => FifoF3_Data,
190 WorkFreq => DMUX_WorkFreq,
190 WorkFreq => DMUX_WorkFreq,
191 Read_DEMUX => DMUX_Read,
191 Read_DEMUX => DMUX_Read,
192 Empty => DMUX_Empty,
192 Empty => DMUX_Empty,
193 Data => DMUX_Data);
193 Data => DMUX_Data);
194 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
195
195
196
196
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198 FFT0: FFT
198 FFT0: FFT
199 GENERIC MAP (
199 GENERIC MAP (
200 Data_sz => 16,
200 Data_sz => 16,
201 NbData => 256)
201 NbData => 256)
202 PORT MAP (
202 PORT MAP (
203 clkm => clk,
203 clkm => clk,
204 rstn => rstn,
204 rstn => rstn,
205 FifoIN_Empty => DMUX_Empty,
205 FifoIN_Empty => DMUX_Empty,
206 FifoIN_Data => DMUX_Data,
206 FifoIN_Data => DMUX_Data,
207 FifoOUT_Full => FifoINT_Full,
207 FifoOUT_Full => FifoINT_Full,
208 Load => FFT_Load,
208 Load => FFT_Load,
209 Read => FFT_Read,
209 Read => FFT_Read,
210 Write => FFT_Write,
210 Write => FFT_Write,
211 ReUse => FFT_ReUse,
211 ReUse => FFT_ReUse,
212 Data => FFT_Data);
212 Data => FFT_Data);
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214
214
215
215
216 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
217 MemInt : lppFIFOxN
217 MemInt : lppFIFOxN
218 GENERIC MAP (
218 GENERIC MAP (
219 tech => 0,
219 tech => 0,
220 Mem_use => use_RAM,
220 Mem_use => use_RAM,
221 Data_sz => 16,
221 Data_sz => 16,
222 Addr_sz => 8,
222 Addr_sz => 8,
223 FifoCnt => 5,
223 FifoCnt => 5,
224 Enable_ReUse => '1')
224 Enable_ReUse => '1')
225 PORT MAP (
225 PORT MAP (
226 rst => rstn,
226 rst => rstn,
227 wclk => clk,
227 wclk => clk,
228 rclk => clk,
228 rclk => clk,
229 ReUse => SM_ReUse,
229 ReUse => SM_ReUse,
230 wen => FFT_Write,
230 wen => FFT_Write,
231 ren => SM_Read,
231 ren => SM_Read,
232 wdata => FFT_Data,
232 wdata => FFT_Data,
233 rdata => FifoINT_Data,
233 rdata => FifoINT_Data,
234 full => FifoINT_Full,
234 full => FifoINT_Full,
235 empty => OPEN);
235 empty => OPEN);
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237
237
238 -----------------------------------------------------------------------------
238 -----------------------------------------------------------------------------
239 SM0 : MatriceSpectrale
239 SM0 : MatriceSpectrale
240 GENERIC MAP (
240 GENERIC MAP (
241 Input_SZ => 16,
241 Input_SZ => 16,
242 Result_SZ => 32)
242 Result_SZ => 32)
243 PORT MAP (
243 PORT MAP (
244 clkm => clk,
244 clkm => clk,
245 rstn => rstn,
245 rstn => rstn,
246 FifoIN_Full => FifoINT_Full,
246 FifoIN_Full => FifoINT_Full,
247 SetReUse => FFT_ReUse,
247 SetReUse => FFT_ReUse,
248 Valid => Head_Valid,
248 Valid => Head_Valid,
249 Data_IN => FifoINT_Data,
249 Data_IN => FifoINT_Data,
250 ACQ => DMA_ack,
250 ACQ => DMA_ack,
251 SM_Write => SM_Wen,
251 SM_Write => SM_Wen,
252 FlagError => SM_FlagError,
252 FlagError => SM_FlagError,
253 Pong => SM_Pong,
253 Pong => SM_Pong,
254 Statu => SM_Param,
254 Statu => SM_Param,
255 Write => SM_Write,
255 Write => SM_Write,
256 Read => SM_Read,
256 Read => SM_Read,
257 ReUse => SM_ReUse,
257 ReUse => SM_ReUse,
258 Data_OUT => SM_Data);
258 Data_OUT => SM_Data);
259 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
260
260
261 -----------------------------------------------------------------------------
261 -----------------------------------------------------------------------------
262 MemOut : lppFIFOxN
262 MemOut : lppFIFOxN
263 GENERIC MAP (
263 GENERIC MAP (
264 tech => 0,
264 tech => 0,
265 Mem_use => use_RAM,
265 Mem_use => use_RAM,
266 Data_sz => 32,
266 Data_sz => 32,
267 Addr_sz => 8,
267 Addr_sz => 8,
268 FifoCnt => 2,
268 FifoCnt => 2,
269 Enable_ReUse => '0')
269 Enable_ReUse => '0')
270 PORT MAP (
270 PORT MAP (
271 rst => rstn,
271 rst => rstn,
272 wclk => clk,
272 wclk => clk,
273 rclk => clk,
273 rclk => clk,
274 ReUse => (OTHERS => '0'),
274 ReUse => (OTHERS => '0'),
275 wen => SM_Write,
275 wen => SM_Write,
276 ren => Head_Read,
276 ren => Head_Read,
277 wdata => SM_Data,
277 wdata => SM_Data,
278 rdata => FifoOUT_Data,
278 rdata => FifoOUT_Data,
279 full => FifoOUT_Full,
279 full => FifoOUT_Full,
280 empty => FifoOUT_Empty);
280 empty => FifoOUT_Empty);
281 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
282
282
283 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
284 Head0 : HeaderBuilder
284 Head0 : HeaderBuilder
285 GENERIC MAP (
285 GENERIC MAP (
286 Data_sz => 32)
286 Data_sz => 32)
287 PORT MAP (
287 PORT MAP (
288 clkm => clk,
288 clkm => clk,
289 rstn => rstn,
289 rstn => rstn,
290 pong => SM_Pong,
290 pong => SM_Pong,
291 Statu => SM_Param,
291 Statu => SM_Param,
292 Matrix_Type => DMUX_WorkFreq,
292 Matrix_Type => DMUX_WorkFreq,
293 Matrix_Write => SM_Wen,
293 Matrix_Write => SM_Wen,
294 Valid => Head_Valid,
294 Valid => Head_Valid,
295 dataIN => FifoOUT_Data,
295 dataIN => FifoOUT_Data,
296 emptyIN => FifoOUT_Empty,
296 emptyIN => FifoOUT_Empty,
297 RenOUT => Head_Read,
297 RenOUT => Head_Read,
298 dataOUT => Head_Data,
298 dataOUT => Head_Data,
299 emptyOUT => Head_Empty,
299 emptyOUT => Head_Empty,
300 RenIN => DMA_Read,
300 RenIN => DMA_Read,
301 header => Head_Header,
301 header => Head_Header,
302 header_val => Head_Val,
302 header_val => Head_Val,
303 header_ack => DMA_ack );
303 header_ack => DMA_ack );
304 -----------------------------------------------------------------------------
304 -----------------------------------------------------------------------------
305
305
306 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
307 lpp_dma_ip_1: lpp_dma_ip
307 lpp_dma_ip_1: lpp_dma_ip
308 GENERIC MAP (
308 GENERIC MAP (
309 tech => 0,
309 tech => 0,
310 hindex => hindex)
310 hindex => hindex)
311 PORT MAP (
311 PORT MAP (
312 HCLK => clk,
312 HCLK => clk,
313 HRESETn => rstn,
313 HRESETn => rstn,
314 AHB_Master_In => AHB_Master_In,
314 AHB_Master_In => AHB_Master_In,
315 AHB_Master_Out => AHB_Master_Out,
315 AHB_Master_Out => AHB_Master_Out,
316
316
317 fifo_data => Head_Data,
317 fifo_data => Head_Data,
318 fifo_empty => Head_Empty,
318 fifo_empty => Head_Empty,
319 fifo_ren => DMA_Read,
319 fifo_ren => DMA_Read,
320
320
321 header => Head_Header,
321 header => Head_Header,
322 header_val => Head_Val,
322 header_val => Head_Val,
323 header_ack => DMA_ack,
323 header_ack => DMA_ack,
324
324
325 ready_matrix_f0_0 => ready_matrix_f0_0,
325 ready_matrix_f0_0 => ready_matrix_f0_0,
326 ready_matrix_f0_1 => ready_matrix_f0_1,
326 ready_matrix_f0_1 => ready_matrix_f0_1,
327 ready_matrix_f1 => ready_matrix_f1,
327 ready_matrix_f1 => ready_matrix_f1,
328 ready_matrix_f2 => ready_matrix_f2,
328 ready_matrix_f2 => ready_matrix_f2,
329 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
329 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
330 error_bad_component_error => error_bad_component_error,
330 error_bad_component_error => error_bad_component_error,
331 debug_reg => debug_reg,
331 debug_reg => debug_reg,
332 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
332 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
333 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
333 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
334 status_ready_matrix_f1 => status_ready_matrix_f1,
334 status_ready_matrix_f1 => status_ready_matrix_f1,
335 status_ready_matrix_f2 => status_ready_matrix_f2,
335 status_ready_matrix_f2 => status_ready_matrix_f2,
336 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
336 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
337 status_error_bad_component_error => status_error_bad_component_error,
337 status_error_bad_component_error => status_error_bad_component_error,
338 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
338 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
339 config_active_interruption_onError => config_active_interruption_onError,
339 config_active_interruption_onError => config_active_interruption_onError,
340 addr_matrix_f0_0 => addr_matrix_f0_0,
340 addr_matrix_f0_0 => addr_matrix_f0_0,
341 addr_matrix_f0_1 => addr_matrix_f0_1,
341 addr_matrix_f0_1 => addr_matrix_f0_1,
342 addr_matrix_f1 => addr_matrix_f1,
342 addr_matrix_f1 => addr_matrix_f1,
343 addr_matrix_f2 => addr_matrix_f2);
343 addr_matrix_f2 => addr_matrix_f2);
344 -----------------------------------------------------------------------------
344 -----------------------------------------------------------------------------
345
345
346 END Behavioral; No newline at end of file
346 END Behavioral;
Show file before | Show file after | Hide comments
@@ -164,5 +164,33 PACKAGE lpp_lfr_pkg IS
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
165 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
166 END COMPONENT;
166 END COMPONENT;
167
168 COMPONENT lpp_top_ms
169 GENERIC (
170 Mem_use : INTEGER;
171 nb_burst_available_size : INTEGER;
172 nb_snapshot_param_size : INTEGER;
173 delta_snapshot_size : INTEGER;
174 delta_f2_f0_size : INTEGER;
175 delta_f2_f1_size : INTEGER;
176 pindex : INTEGER;
177 paddr : INTEGER;
178 pmask : INTEGER;
179 pirq_ms : INTEGER;
180 pirq_wfp : INTEGER;
181 hindex_wfp : INTEGER;
182 hindex_ms : INTEGER);
183 PORT (
184 clk : IN STD_LOGIC;
185 rstn : IN STD_LOGIC;
186 sample_B : IN Samples14v(2 DOWNTO 0);
187 sample_E : IN Samples14v(4 DOWNTO 0);
188 sample_val : IN STD_LOGIC;
189 apbi : IN apb_slv_in_type;
190 apbo : OUT apb_slv_out_type;
191 ahbi_ms : IN AHB_Mst_In_Type;
192 ahbo_ms : OUT AHB_Mst_Out_Type;
193 data_shaping_BW : OUT STD_LOGIC);
194 END COMPONENT;
167
195
168 END lpp_lfr_pkg;
196 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -10,4 +10,5 lpp_lfr_apbreg.vhd
10 top_wf_picker.vhd
10 top_wf_picker.vhd
11 lpp_lfr_filter.vhd
11 lpp_lfr_filter.vhd
12 lpp_lfr_ms.vhd
12 lpp_lfr_ms.vhd
13 lpp_top_ms.vhd
13 lpp_lfr.vhd
14 lpp_lfr.vhd
Show file before | Show file after | Hide comments
@@ -94,7 +94,8 ARCHITECTURE beh OF lpp_waveform IS
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -103,6 +104,7 ARCHITECTURE beh OF lpp_waveform IS
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
106
108
107 BEGIN -- beh
109 BEGIN -- beh
108
110
@@ -222,14 +224,15 BEGIN -- beh
222 data_wen => data_wen,
224 data_wen => data_wen,
223 data => wdata);
225 data => wdata);
224
226
225 ready_arb <= NOT ready;
227 ready_arb <= NOT data_ready;
226
228
227 lpp_waveform_fifo_1: lpp_waveform_fifo
229 lpp_waveform_fifo_1: lpp_waveform_fifo
228 GENERIC MAP (tech => tech)
230 GENERIC MAP (tech => tech)
229 PORT MAP (
231 PORT MAP (
230 clk => clk,
232 clk => clk,
231 rstn => rstn,
233 rstn => rstn,
232 ready => ready,
234 time_ready => time_ready,
235 data_ready => data_ready,
233 time_ren => time_ren, -- todo
236 time_ren => time_ren, -- todo
234 data_ren => data_ren, -- todo
237 data_ren => data_ren, -- todo
235 rdata => rdata, -- todo
238 rdata => rdata, -- todo
@@ -237,7 +240,9 BEGIN -- beh
237 time_wen => time_wen,
240 time_wen => time_wen,
238 data_wen => data_wen,
241 data_wen => data_wen,
239 wdata => wdata);
242 wdata => wdata);
240
243
244 enable <= enable_f3 & enable_f2 & enable_f1 & enable_f0;
245
241 pp_waveform_dma_1: lpp_waveform_dma
246 pp_waveform_dma_1: lpp_waveform_dma
242 GENERIC MAP (
247 GENERIC MAP (
243 data_size => data_size,
248 data_size => data_size,
@@ -249,7 +254,9 BEGIN -- beh
249 HRESETn => rstn,
254 HRESETn => rstn,
250 AHB_Master_In => AHB_Master_In,
255 AHB_Master_In => AHB_Master_In,
251 AHB_Master_Out => AHB_Master_Out,
256 AHB_Master_Out => AHB_Master_Out,
252 data_ready => ready,
257 enable => enable, -- todo
258 time_ready => time_ready, -- todo
259 data_ready => data_ready,
253 data => rdata,
260 data => rdata,
254 data_data_ren => data_ren,
261 data_data_ren => data_ren,
255 data_time_ren => time_ren,
262 data_time_ren => time_ren,
Show file before | Show file after | Hide comments
@@ -57,10 +57,12 ENTITY lpp_waveform_dma IS
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
60 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
65 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
64 -- Reg
66 -- Reg
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
67 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -79,7 +81,7 ARCHITECTURE Behavioral OF lpp_waveform_
79 SIGNAL DMAIn : DMA_In_Type;
81 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
82 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
84 TYPE state_DMAWriteBurst IS (IDLE,TRASH_FIFO_TIME,TRASH_FIFO_DATA,
83 SEND_TIME_0, WAIT_TIME_0,
85 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
86 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
87 SEND_5_TIME,
@@ -88,9 +90,12 ARCHITECTURE Behavioral OF lpp_waveform_
88 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
89 -- CONTROL
91 -- CONTROL
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL sel_data_ss : STD_LOGIC;
94 SIGNAL sel_time_s : STD_LOGIC;
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
95 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
96 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
97 SIGNAL time_select : STD_LOGIC;
98 SIGNAL enable_sel : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
99 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
101 SIGNAL time_already_send_s : STD_LOGIC;
@@ -109,6 +114,7 ARCHITECTURE Behavioral OF lpp_waveform_
109 SIGNAL data_send_ok : STD_LOGIC;
114 SIGNAL data_send_ok : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
115 SIGNAL data_send_ko : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
116 SIGNAL data_fifo_ren : STD_LOGIC;
117 SIGNAL trash_fifo_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
118 SIGNAL data_ren : STD_LOGIC;
113 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
114 -- SELECT ADDRESS
120 -- SELECT ADDRESS
@@ -170,6 +176,21 BEGIN
170 "01" WHEN data_ready(1) = '1' ELSE
176 "01" WHEN data_ready(1) = '1' ELSE
171 "10" WHEN data_ready(2) = '1' ELSE
177 "10" WHEN data_ready(2) = '1' ELSE
172 "11";
178 "11";
179
180 sel_data_ss <= data_ready(0) WHEN sel_data = "00" ELSE
181 data_ready(1) WHEN sel_data = "01" ELSE
182 data_ready(2) WHEN sel_data = "10" ELSE
183 data_ready(3);
184
185 sel_time_s <= time_ready(0) WHEN sel_data = "00" ELSE
186 time_ready(1) WHEN sel_data = "01" ELSE
187 time_ready(2) WHEN sel_data = "10" ELSE
188 time_ready(3);
189
190 enable_sel <= enable(0) WHEN sel_data = "00" ELSE
191 enable(1) WHEN sel_data = "01" ELSE
192 enable(2) WHEN sel_data = "10" ELSE
193 enable(3);
173
194
174 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
195 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
175 time_already_send(1) WHEN data_ready(1) = '1' ELSE
196 time_already_send(1) WHEN data_ready(1) = '1' ELSE
@@ -186,6 +207,7 BEGIN
186 update <= "00";
207 update <= "00";
187 time_select <= '0';
208 time_select <= '0';
188 time_fifo_ren <= '1';
209 time_fifo_ren <= '1';
210 trash_fifo_ren <= '1';
189 data_send <= '0';
211 data_send <= '0';
190 time_send <= '0';
212 time_send <= '0';
191 time_write <= '0';
213 time_write <= '0';
@@ -203,14 +225,37 BEGIN
203 data_send <= '0';
225 data_send <= '0';
204 time_send <= '0';
226 time_send <= '0';
205 time_write <= '0';
227 time_write <= '0';
206
228 trash_fifo_ren <= '1';
207 IF data_ready = "0000" THEN
229 IF data_ready = "0000" THEN
208 state <= IDLE;
230 state <= IDLE;
209 ELSE
231 ELSE
210 sel_data <= sel_data_s;
232 sel_data <= sel_data_s;
211 state <= SEND_5_TIME;
233 IF enable_sel = '1' THEN
234 state <= SEND_5_TIME;
235 ELSE
236 state <= TRASH_FIFO_TIME;
237 END IF;
238
212 END IF;
239 END IF;
213
240
241 WHEN TRASH_FIFO_TIME =>
242 time_select <= '1';
243 time_fifo_ren <= '0';
244 IF sel_time_s = '1' THEN
245 time_fifo_ren <= '1';
246 state <= TRASH_FIFO_DATA;
247 END IF;
248
249
250 WHEN TRASH_FIFO_DATA =>
251 time_select <= '1';
252 trash_fifo_ren <= '0';
253 IF sel_data_ss = '1' THEN
254 trash_fifo_ren <= '1';
255 state <= IDLE;
256 END IF;
257
258
214 WHEN SEND_5_TIME =>
259 WHEN SEND_5_TIME =>
215 update <= "00";
260 update <= "00";
216 time_select <= '1';
261 time_select <= '1';
@@ -283,9 +328,9 BEGIN
283 send_ok => data_send_ok,
328 send_ok => data_send_ok,
284 send_ko => data_send_ko);
329 send_ko => data_send_ko);
285
330
286 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
331 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
287 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
332 data_ren <= trash_fifo_ren WHEN time_select = '1' ELSE data_fifo_ren;
288 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
333 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
289
334
290 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
335 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
291 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
336 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
@@ -306,6 +351,7 BEGIN
306 PORT MAP (
351 PORT MAP (
307 HCLK => HCLK,
352 HCLK => HCLK,
308 HRESETn => HRESETn,
353 HRESETn => HRESETn,
354 enable => enable(I),
309 update => update_and_sel((2*I)+1 DOWNTO 2*I),
355 update => update_and_sel((2*I)+1 DOWNTO 2*I),
310 nb_burst_available => nb_burst_available,
356 nb_burst_available => nb_burst_available,
311 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
357 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
@@ -323,4 +369,4 BEGIN
323 -----------------------------------------------------------------------------
369 -----------------------------------------------------------------------------
324
370
325
371
326 END Behavioral;
372 END Behavioral; No newline at end of file
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@@ -37,6 +37,7 ENTITY lpp_waveform_dma_selectaddress IS
37 HCLK : IN STD_ULOGIC;
37 HCLK : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
39
39
40 enable : IN STD_LOGIC;
40 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41
42
42 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
43 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
@@ -80,10 +81,12 BEGIN
80 update_r <= update;
81 update_r <= update;
81 CASE state IS
82 CASE state IS
82 WHEN IDLE =>
83 WHEN IDLE =>
83 IF update_s = '1' THEN
84 IF enable = '0' THEN
85 state <= UPDATED;
86 elsIF update_s = '1' THEN
84 state <= ADD;
87 state <= ADD;
85 END IF;
88 END IF;
86
89
87 WHEN ADD =>
90 WHEN ADD =>
88 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
91 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
89 state <= IDLE;
92 state <= IDLE;
@@ -121,8 +124,10 BEGIN
121
124
122 WHEN UPDATED =>
125 WHEN UPDATED =>
123 status_full_err <= '0';
126 status_full_err <= '0';
124 state <= IDLE;
125 address <= addr_data_reg;
127 address <= addr_data_reg;
128 IF enable = '1' THEN
129 state <= IDLE;
130 END IF;
126
131
127 WHEN OTHERS => NULL;
132 WHEN OTHERS => NULL;
128 END CASE;
133 END CASE;
Show file before | Show file after | Hide comments
@@ -39,7 +39,8 ENTITY lpp_waveform_fifo IS
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
42 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
43 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
43
44
44 ---------------------------------------------------------------------------
45 ---------------------------------------------------------------------------
45 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -115,7 +116,7 BEGIN
115 GENERIC MAP (
116 GENERIC MAP (
116 offset => 32*I + 20,
117 offset => 32*I + 20,
117 length => 10,
118 length => 10,
118 enable_ready => '0')
119 enable_ready => '1')
119 PORT MAP (
120 PORT MAP (
120 clk => clk,
121 clk => clk,
121 rstn => rstn,
122 rstn => rstn,
@@ -125,7 +126,7 BEGIN
125 mem_we => time_mem_wen(I),
126 mem_we => time_mem_wen(I),
126 mem_addr_ren => time_mem_addr_r(I),
127 mem_addr_ren => time_mem_addr_r(I),
127 mem_addr_wen => time_mem_addr_w(I),
128 mem_addr_wen => time_mem_addr_w(I),
128 ready => OPEN);
129 ready => time_ready(I));
129 END GENERATE gen_fifo_ctrl_time;
130 END GENERATE gen_fifo_ctrl_time;
130
131
131 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
132 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
@@ -143,7 +144,7 BEGIN
143 mem_we => data_mem_wen(I),
144 mem_we => data_mem_wen(I),
144 mem_addr_ren => data_mem_addr_r(I),
145 mem_addr_ren => data_mem_addr_r(I),
145 mem_addr_wen => data_mem_addr_w(I),
146 mem_addr_wen => data_mem_addr_w(I),
146 ready => ready(I));
147 ready => data_ready(I));
147 END GENERATE gen_fifo_ctrl_data;
148 END GENERATE gen_fifo_ctrl_data;
148
149
149
150
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@@ -133,7 +133,7 BEGIN
133 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
133 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
134
134
135 ready_gen: IF enable_ready = '1' GENERATE
135 ready_gen: IF enable_ready = '1' GENERATE
136 ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
136 ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
137 '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
137 '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
138 '0';
138 '0';
139 END GENERATE ready_gen;
139 END GENERATE ready_gen;
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@@ -132,6 +132,7 PACKAGE lpp_waveform_pkg IS
132 PORT (
132 PORT (
133 HCLK : IN STD_ULOGIC;
133 HCLK : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
135 enable : IN STD_LOGIC;
135 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
136 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
136 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
137 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
137 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -162,6 +163,8 PACKAGE lpp_waveform_pkg IS
162 HRESETn : IN STD_ULOGIC;
163 HRESETn : IN STD_ULOGIC;
163 AHB_Master_In : IN AHB_Mst_In_Type;
164 AHB_Master_In : IN AHB_Mst_In_Type;
164 AHB_Master_Out : OUT AHB_Mst_Out_Type;
165 AHB_Master_Out : OUT AHB_Mst_Out_Type;
166 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
167 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
165 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
168 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
166 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
170 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -229,7 +232,8 PACKAGE lpp_waveform_pkg IS
229 PORT (
232 PORT (
230 clk : IN STD_LOGIC;
233 clk : IN STD_LOGIC;
231 rstn : IN STD_LOGIC;
234 rstn : IN STD_LOGIC;
232 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
235 time_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
236 data_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
237 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
238 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
235 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
239 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
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