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save x.1.85
pellion -
r619:b515d4c55e1d simu_with_Leon3
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@@ -265,7 +265,9 BEGIN -- beh
265 265 ADDRESS_SIZE => 19,
266 266 USES_IAP_MEMCTRLR => 1,
267 267 BYPASS_EDAC_MEMCTRLR => '0',
268 SRBANKSZ => 8)
268 SRBANKSZ => 8,
269 SLOW_TIMING_EMULATION => 0
270 )
269 271 PORT MAP (
270 272 clk => clk_25,
271 273 reset => rstn_25,
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@@ -225,7 +225,7 BEGIN -- beh
225 225 ENABLE_FPU => 1,
226 226 FPU_NETLIST => 0,
227 227 ENABLE_DSU => 1,
228 ENABLE_AHB_UART => 1,
228 ENABLE_AHB_UART => 0,
229 229 ENABLE_APB_UART => 1,
230 230 ENABLE_IRQMP => 1,
231 231 ENABLE_GPT => 1,
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@@ -38,7 +38,8 DIRSKIP = b1553 pcif leon2 leon2ft crypt
38 38 ./lpp_sim \
39 39 ./lpp_lfr_pkg \
40 40 ./lpp_debug_lfr_pkg \
41 ./lpp_top_lfr
41 ./lpp_top_lfr \
42 ./lfr_management
42 43
43 44 FILESKIP =lpp_lfr_ms.vhd \
44 45 i2cmst.vhd \
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@@ -110,14 +110,42 ARCHITECTURE beh OF UT8ER1M32_test_board
110 110 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
111 111 --SRAM-----------------------------------------------------------------------
112 112 SIGNAL SRAM_CE : STD_LOGIC_VECTOR(1 downto 0);
113
114
115 SIGNAL rstn_25 : STD_LOGIC;
116 SIGNAL rstn_50 : STD_LOGIC;
117 SIGNAL rstn_49 : STD_LOGIC;
118
119 SIGNAL clk_lock : STD_LOGIC;
120 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
121 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
113 122
114 123 BEGIN -- beh
115 124
125 rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN);
126
127 PROCESS (clk_50, rstn_50)
128 BEGIN -- PROCESS
129 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
130 clk_lock <= '0';
131 clk_busy_counter <= (OTHERS => '0');
132 nSRAM_BUSY_reg <= '0';
133 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
134 nSRAM_BUSY_reg <= SRAM_nBUSY;
135 IF nSRAM_BUSY_reg = '1' AND SRAM_nBUSY = '0' THEN
136 IF clk_busy_counter = "1111" THEN
137 clk_lock <= '1';
138 ELSE
139 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
140 END IF;
141 END IF;
142 END IF;
143 END PROCESS;
144
145 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
116 146 -----------------------------------------------------------------------------
117 147 -- CLK
118 148 -----------------------------------------------------------------------------
119
120
121 149 PROCESS(clk_50)
122 150 BEGIN
123 151 IF clk_50'EVENT AND clk_50 = '1' THEN
@@ -126,15 +154,13 BEGIN -- beh
126 154 END PROCESS;
127 155
128 156 -----------------------------------------------------------------------------
129
130
131 PROCESS (clk_49, reset)
157 PROCESS (clk_49, rstn_49)
132 158 BEGIN -- PROCESS
133 IF reset = '0' THEN -- asynchronous reset (active low)
159 IF rstn_49 = '0' THEN -- asynchronous reset (active low)
134 160 I00_s <= '0';
135 161 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
136 I00_s <= NOT I00_s;
137 END IF;
162 I00_s <= NOT I00_s;
163 END IF;
138 164 END PROCESS;
139 165
140 166 nCTS1 <= '1';
@@ -143,7 +169,6 BEGIN -- beh
143 169 SRAM_nCE2 <= SRAM_CE(1);
144 170
145 171
146
147 172 leon3_soc_1 : leon3_soc
148 173 GENERIC MAP (
149 174 fabtech => apa3e,
@@ -166,15 +191,20 BEGIN -- beh
166 191 NB_AHB_SLAVE => NB_AHB_SLAVE,
167 192 NB_APB_SLAVE => NB_APB_SLAVE,
168 193 ADDRESS_SIZE => 19,
169 USES_IAP_MEMCTRLR => 1)
194 USES_IAP_MEMCTRLR => 1,
195 BYPASS_EDAC_MEMCTRLR => '0',
196 SRBANKSZ => 8,
197 SLOW_TIMING_EMULATION => 1
198 )
170 199 PORT MAP (
171 200 clk => clk_25,
172 reset => reset,
201 reset => rstn_25,
173 202 errorn => errorn,
174 203 ahbrxd => TXD1,
175 204 ahbtxd => RXD1,
176 205 urxd1 => TXD2,
177 206 utxd1 => RXD2,
207
178 208 address => SRAM_A,
179 209 data => SRAM_DQ,
180 210 nSRAM_BE0 => LED0,
@@ -193,7 +223,9 BEGIN -- beh
193 223 ahbo_s_ext => ahbo_s_ext,
194 224 ahbi_m_ext => ahbi_m_ext,
195 225 ahbo_m_ext => ahbo_m_ext);
226
227
196 228
197 229
198
199 END beh; No newline at end of file
230 END beh;
231
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@@ -74,7 +74,8 ENTITY leon3_soc IS
74 74 ADDRESS_SIZE : INTEGER := 19;
75 75 USES_IAP_MEMCTRLR : INTEGER := 1;
76 76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
77 SRBANKSZ : INTEGER := 8;
78 SLOW_TIMING_EMULATION : integer := 0
78 79
79 80 );
80 81 PORT (
@@ -250,7 +251,8 ARCHITECTURE Behavioral OF leon3_soc IS
250 251 SIGNAL dsui : dsu_in_type;
251 252 SIGNAL dsuo : dsu_out_type;
252 253 -----------------------------------------------------------------------------
253
254 SIGNAL memo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 SIGNAL memi_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 256
255 257 BEGIN
256 258
@@ -461,16 +463,37 BEGIN
461 463 memi.writen <= '1';
462 464 memi.wrn <= "1111";
463 465 memi.bwidth <= "10";
464
466
467 -----------------------------------------------------------------------------
468 -- SLOW TIMING EMULATION
469 -----------------------------------------------------------------------------
470 SLOW_TIMING_EMULATION_ON: IF SLOW_TIMING_EMULATION = 1 GENERATE
471 PROCESS (clkm, rstn)
472 BEGIN -- PROCESS
473 IF rstn = '0' THEN -- asynchronous reset (active low)
474 memi.data <= (OTHERS => '0');
475 memo_data <= (OTHERS => '0');
476 ELSIF clkm'event AND clkm = '1' THEN -- rising clock edge
477 memi.data <= memi_data;
478 memo_data <= memo.data;
479 END IF;
480 END PROCESS;
481 END GENERATE SLOW_TIMING_EMULATION_ON;
482 SLOW_TIMING_EMULATION_OFF: IF SLOW_TIMING_EMULATION = 0 GENERATE
483 memi.data <= memi_data;
484 memo_data <= memo.data;
485 END GENERATE SLOW_TIMING_EMULATION_OFF;
486
465 487 bdr : FOR i IN 0 TO 3 GENERATE
466 488 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
467 489 PORT MAP (
468 490 data(31-i*8 DOWNTO 24-i*8),
469 memo.data(31-i*8 DOWNTO 24-i*8),
491 memo_data(31-i*8 DOWNTO 24-i*8),
470 492 memo.bdrive(i),
471 memi.data(31-i*8 DOWNTO 24-i*8));
493 memi_data(31-i*8 DOWNTO 24-i*8));
472 494 END GENERATE;
473
495 -----------------------------------------------------------------------------
496
474 497 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
475 498 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
476 499 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
@@ -481,8 +504,6 BEGIN
481 504 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
482 505 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
483 506
484
485
486 507 ----------------------------------------------------------------------
487 508 --- AHB CONTROLLER -------------------------------------------------
488 509 ----------------------------------------------------------------------
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@@ -56,7 +56,8 PACKAGE lpp_leon3_soc_pkg IS
56 56 ADDRESS_SIZE : INTEGER;
57 57 USES_IAP_MEMCTRLR : INTEGER;
58 58 BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
59 SRBANKSZ : INTEGER := 8
59 SRBANKSZ : INTEGER := 8;
60 SLOW_TIMING_EMULATION : integer := 0
60 61 );
61 62 PORT (
62 63 clk : IN STD_ULOGIC;
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@@ -41,8 +41,9 ENTITY lpp_lfr IS
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
43 43
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
45 RTL_DESIGN_LIGHT : INTEGER := 0;
46 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
46 47 );
47 48 PORT (
48 49 clk : IN STD_LOGIC;
@@ -189,7 +190,8 BEGIN
189 190 -----------------------------------------------------------------------------
190 191 lpp_lfr_filter_1 : lpp_lfr_filter
191 192 GENERIC MAP (
192 Mem_use => Mem_use)
193 Mem_use => Mem_use,
194 RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
193 195 PORT MAP (
194 196 sample => sample_s,
195 197 sample_val => sample_val,
@@ -386,7 +388,8 BEGIN
386 388 -----------------------------------------------------------------------------
387 389 lpp_lfr_ms_1 : lpp_lfr_ms
388 390 GENERIC MAP (
389 Mem_use => Mem_use)
391 Mem_use => Mem_use,
392 WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
390 393 PORT MAP (
391 394 clk => clk,
392 395 rstn => rstn,
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@@ -45,7 +45,8 USE GRLIB.DMA2AHB_Package.ALL;
45 45
46 46 ENTITY lpp_lfr_filter IS
47 47 GENERIC(
48 Mem_use : INTEGER := use_RAM
48 Mem_use : INTEGER := use_RAM;
49 RTL_DESIGN_LIGHT : INTEGER := 0
49 50 );
50 51 PORT (
51 52 sample : IN Samples(7 DOWNTO 0);
@@ -549,34 +550,41 BEGIN
549 550 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
550 551 END GENERATE all_channel_sample_f_cic;
551 552
552
553 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
554 GENERIC MAP (
555 tech => 0,
556 Mem_use => Mem_use,
557 Sample_SZ => 18,
558 Coef_SZ => f2_f3_COEFFICIENT_SIZE,
559 Coef_Nb => f2_f3_CEL_NUMBER*5,
560 Coef_sel_SZ => 5,
561 Cels_count => f2_f3_CEL_NUMBER,
562 ChanelsCount => 6)
563 PORT MAP (
564 rstn => rstn,
565 clk => clk,
566 virg_pos => f2_f3_POINT_POSITION,
567 coefs => coefs_iir_cel_f2_f3,
553 NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE
554 sample_f2_filter_val <= sample_f2_cic_val;
555 sample_f2_filter <= sample_f2_cic_filter;
556 sample_f3_filter_val <= sample_f3_cic_val;
557 sample_f3_filter <= sample_f3_cic_filter;
558 END GENERATE NO_IIR_FILTER_f2_f3;
568 559
569 sample_in1_val => sample_f2_cic_val,
570 sample_in1 => sample_f2_cic_filter,
571
572 sample_in2_val => sample_f3_cic_val,
573 sample_in2 => sample_f3_cic_filter,
574
575 sample_out1_val => sample_f2_filter_val,
576 sample_out1 => sample_f2_filter,
577 sample_out2_val => sample_f3_filter_val,
578 sample_out2 => sample_f3_filter);
579
560 YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
561 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
562 GENERIC MAP (
563 tech => 0,
564 Mem_use => Mem_use,
565 Sample_SZ => 18,
566 Coef_SZ => f2_f3_COEFFICIENT_SIZE,
567 Coef_Nb => f2_f3_CEL_NUMBER*5,
568 Coef_sel_SZ => 5,
569 Cels_count => f2_f3_CEL_NUMBER,
570 ChanelsCount => 6)
571 PORT MAP (
572 rstn => rstn,
573 clk => clk,
574 virg_pos => f2_f3_POINT_POSITION,
575 coefs => coefs_iir_cel_f2_f3,
576
577 sample_in1_val => sample_f2_cic_val,
578 sample_in1 => sample_f2_cic_filter,
579
580 sample_in2_val => sample_f3_cic_val,
581 sample_in2 => sample_f3_cic_filter,
582
583 sample_out1_val => sample_f2_filter_val,
584 sample_out1 => sample_f2_filter,
585 sample_out2_val => sample_f3_filter_val,
586 sample_out2 => sample_f3_filter);
587 END GENERATE YES_IIR_FILTER_f2_f3;
580 588
581 589 all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
582 590 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
@@ -584,7 +592,6 BEGIN
584 592 sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
585 593 END GENERATE all_bit_sample_f_filter;
586 594 END GENERATE all_channel_sample_f_filter;
587
588 595
589 596 -----------------------------------------------------------------------------
590 597
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@@ -17,7 +17,8 USE lpp.fft_components.ALL;
17 17
18 18 ENTITY lpp_lfr_ms IS
19 19 GENERIC (
20 Mem_use : INTEGER := use_RAM
20 Mem_use : INTEGER := use_RAM;
21 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
21 22 );
22 23 PORT (
23 24 clk : IN STD_LOGIC;
@@ -710,6 +711,8 BEGIN
710 711 -- FFT
711 712 -----------------------------------------------------------------------------
712 713 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
714 GENERIC MAP (
715 WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
713 716 PORT MAP (
714 717 clk => clk,
715 718 rstn => rstn,
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@@ -16,6 +16,10 USE lpp.fft_components.ALL;
16 16 USE lpp.window_function_pkg.ALL;
17 17
18 18 ENTITY lpp_lfr_ms_FFT IS
19 GENERIC (
20 WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
21 );
22
19 23 PORT (
20 24 clk : IN STD_LOGIC;
21 25 rstn : IN STD_LOGIC;
@@ -40,20 +44,34 ARCHITECTURE Behavioral OF lpp_lfr_ms_FF
40 44 SIGNAL data_win : STD_LOGIC_VECTOR(15 DOWNTO 0);
41 45 SIGNAL data_win_valid : STD_LOGIC;
42 46
47 SIGNAL data_in_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
48 SIGNAL data_in_reg_valid : STD_LOGIC;
49
43 50 BEGIN
44 51
52 PROCESS (clk, rstn)
53 BEGIN -- PROCESS
54 IF rstn = '0' THEN -- asynchronous reset (active low)
55 data_in_reg <= (OTHERS => '0');
56 data_in_reg_valid <= '0';
57 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
58 data_in_reg <= sample_data;
59 data_in_reg_valid <= sample_valid;
60 END IF;
61 END PROCESS;
62
45 63 window_hanning: window_function
46 64 GENERIC MAP (
47 65 SIZE_DATA => 16,
48 SIZE_PARAM => 15,
66 SIZE_PARAM => WINDOWS_HAANNING_PARAM_SIZE,
49 67 NB_POINT_BY_WINDOW => 256)
50 68 PORT MAP (
51 69 clk => clk,
52 70 rstn => rstn,
53 71
54 72 restart_window => '0',
55 data_in => sample_data,
56 data_in_valid => sample_valid,
73 data_in => data_in_reg,
74 data_in_valid => data_in_reg_valid,
57 75
58 76 data_out => data_win,
59 77 data_out_valid => data_win_valid);
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@@ -69,7 +69,8 PACKAGE lpp_lfr_pkg IS
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 Mem_use : INTEGER);
72 Mem_use : INTEGER;
73 WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
73 74 PORT (
74 75 clk : IN STD_LOGIC;
75 76 rstn : IN STD_LOGIC;
@@ -151,6 +152,8 PACKAGE lpp_lfr_pkg IS
151 152 END COMPONENT;
152 153
153 154 COMPONENT lpp_lfr_ms_FFT
155 GENERIC (
156 WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
154 157 PORT (
155 158 clk : IN STD_LOGIC;
156 159 rstn : IN STD_LOGIC;
@@ -167,7 +170,9 PACKAGE lpp_lfr_pkg IS
167 170
168 171 COMPONENT lpp_lfr_filter
169 172 GENERIC (
170 Mem_use : INTEGER);
173 Mem_use : INTEGER;
174 RTL_DESIGN_LIGHT : INTEGER
175 );
171 176 PORT (
172 177 sample : IN Samples(7 DOWNTO 0);
173 178 sample_val : IN STD_LOGIC;
@@ -210,7 +215,9 PACKAGE lpp_lfr_pkg IS
210 215 pirq_wfp : INTEGER;
211 216 hindex : INTEGER;
212 217 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0);
213 DEBUG_FORCE_DATA_DMA : INTEGER
218 DEBUG_FORCE_DATA_DMA : INTEGER;
219 RTL_DESIGN_LIGHT : INTEGER;
220 WINDOWS_HAANNING_PARAM_SIZE : INTEGER
214 221 );
215 222 PORT (
216 223 clk : IN STD_LOGIC;
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