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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Fixed bug, now minor and major frame pulses have the good width....
Alexis Jeandet -
r222:b37e19fe4c0b alexis
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@@ -243,8 +243,8 rstn <= reset and RaZ;
243 SCLK <= Sclkint;
243 SCLK <= Sclkint;
244
244
245 Major_Frame <= MajF;
245 Major_Frame <= MajF;
246 --Minor_Frame <= MinF;
246 Minor_Frame <= MinF;
247 Minor_Frame <= MinFclk;
247 --Minor_Frame <= MinFclk;
248 gateint <= GateDC or GateLF or GateHF;
248 gateint <= GateDC or GateLF or GateHF;
249 Gate <= gateint;
249 Gate <= gateint;
250
250
@@ -259,8 +259,11 end process;
259
259
260 BUS0 <= WordClk;
260 BUS0 <= WordClk;
261 BUS12 <= MinFVector(0);
261 BUS12 <= MinFVector(0);
262 BUS13 <= MinFclk;
262 --BUS13 <= MinFclk;
263 BUS14 <= '1' when WordCount = 0 else '0';
263 --BUS14 <= '1' when WordCount = 0 else '0';
264 BUS13 <= MinF;
265 BUS14 <= MajF;
266
264
267
265 MinFVector <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
268 MinFVector <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
266
269
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@@ -23,6 +23,7 end entity;
23
23
24
24
25 architecture arMajF_Gen of MajF_Gen is
25 architecture arMajF_Gen of MajF_Gen is
26 signal monostable : std_logic := '0';
26
27
27 begin
28 begin
28
29
@@ -30,12 +31,18 process(clk)
30 begin
31 begin
31 if reset = '0' then
32 if reset = '0' then
32 MajF_Clk <= '0';
33 MajF_Clk <= '0';
34 monostable <= '1';
33 elsif clk'event and clk = '0' then
35 elsif clk'event and clk = '0' then
34 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' then
36 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
35 MajF_Clk <= '1';
37 MajF_Clk <= '1';
36 else
38 else
37 MajF_Clk <= '0';
39 MajF_Clk <= '0';
38 end if;
40 end if;
41 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
42 monostable <= '0';
43 elsif WordCnt_in /= 0 and monostable = '0' then
44 monostable <= '1';
45 end if;
39 end if;
46 end if;
40 end process;
47 end process;
41
48
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@@ -22,19 +22,25 end entity;
22
22
23
23
24 architecture arMinF_Gen of MinF_Gen is
24 architecture arMinF_Gen of MinF_Gen is
25
25 signal monostable : std_logic := '0';
26 begin
26 begin
27
27
28 process(clk)
28 process(clk)
29 begin
29 begin
30 if reset = '0' then
30 if reset = '0' then
31 MinF_Clk <= '0';
31 MinF_Clk <= '0';
32 monostable <= '1';
32 elsif clk'event and clk = '0' then
33 elsif clk'event and clk = '0' then
33 if WordCnt_in = 0 and WordClk = '1' then
34 if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
34 MinF_Clk <= '1';
35 MinF_Clk <= '1';
35 else
36 else
36 MinF_Clk <= '0';
37 MinF_Clk <= '0';
37 end if;
38 end if;
39 if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
40 monostable <= '0';
41 elsif WordCnt_in /= 0 and monostable = '0' then
42 monostable <= '1';
43 end if;
38 end if;
44 end if;
39 end process;
45 end process;
40
46
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