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Simu MINI-LFR_WFP_MS ...
pellion -
r458:a83061e50dc2 JC
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@@ -139,11 +139,11 ARCHITECTURE beh OF MINI_LFR_top IS
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -282,7 +282,8 BEGIN -- beh
282 ENABLE_GPT => 1,
282 ENABLE_GPT => 1,
283 NB_AHB_MASTER => NB_AHB_MASTER,
283 NB_AHB_MASTER => NB_AHB_MASTER,
284 NB_AHB_SLAVE => NB_AHB_SLAVE,
284 NB_AHB_SLAVE => NB_AHB_SLAVE,
285 NB_APB_SLAVE => NB_APB_SLAVE)
285 NB_APB_SLAVE => NB_APB_SLAVE,
286 ADDRESS_SIZE => 20)
286 PORT MAP (
287 PORT MAP (
287 clk => clk_25,
288 clk => clk_25,
288 reset => reset,
289 reset => reset,
@@ -436,7 +437,7 BEGIN -- beh
436 pirq_ms => 6,
437 pirq_ms => 6,
437 pirq_wfp => 14,
438 pirq_wfp => 14,
438 hindex => 2,
439 hindex => 2,
439 top_lfr_version => X"000120") -- aa.bb.cc version
440 top_lfr_version => X"000121") -- aa.bb.cc version
440 PORT MAP (
441 PORT MAP (
441 clk => clk_25,
442 clk => clk_25,
442 rstn => LFR_rstn,
443 rstn => LFR_rstn,
@@ -605,5 +606,24 BEGIN -- beh
605
606
606 END IF;
607 END IF;
607 END PROCESS;
608 END PROCESS;
609 -----------------------------------------------------------------------------
610 --
611 -----------------------------------------------------------------------------
612 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
613 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
614 apbo_ext(I) <= apb_none;
615 END GENERATE apbo_ext_not_used;
616 END GENERATE all_apbo_ext;
617
618
619 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
620 ahbo_s_ext(I) <= ahbs_none;
621 END GENERATE all_ahbo_ext;
622
623 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
624 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
625 ahbo_m_ext(I) <= ahbm_none;
626 END GENERATE ahbo_m_ext_not_used;
627 END GENERATE all_ahbo_m_ext;
608
628
609 END beh;
629 END beh;
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@@ -10,8 +10,9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
@@ -41,7 +42,8 FILESKIP =i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
42 APB_SIMPLE_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45 APB_FFT.vhd \
46 CoreFFT_simu.vhd
45
47
46 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
49 include $(GRLIB)/software/leon3/Makefile
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@@ -5,8 +5,8
5 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
6 ./lpp_amba
7 ./dsp/chirp
7 ./dsp/chirp
8 ./dsp/iir_filter
8 ./dsp/cic
9 ./dsp/cic
9 ./dsp/iir_filter
10 ./dsp/lpp_downsampling
10 ./dsp/lpp_downsampling
11 ./dsp/lpp_fft_rtax
11 ./dsp/lpp_fft_rtax
12 ./lpp_memory
12 ./lpp_memory
@@ -21,10 +21,11
21 ./lpp_matrix
21 ./lpp_matrix
22 ./lpp_uart
22 ./lpp_uart
23 ./lpp_usb
23 ./lpp_usb
24 ./lpp_dma
24 ./lpp_waveform
25 ./lpp_waveform
25 ./lpp_dma
26 ./lpp_top_lfr
26 ./lpp_top_lfr
27 ./lpp_Header
27 ./lpp_Header
28 ./lpp_leon3_soc
28 ./lpp_leon3_soc
29 ./lpp_debug_lfr
29 ./lpp_debug_lfr
30 ./lpp_sim/CY7C1061DV33
30 ./lpp_sim/CY7C1061DV33
31 ./lpp_sim
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@@ -28,6 +28,8 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
31 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
32
31
33
32 ENTITY apb_lfr_time_management IS
34 ENTITY apb_lfr_time_management IS
33
35
@@ -151,11 +153,11 BEGIN
151 --APB Write OP
153 --APB Write OP
152 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
154 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
153 CASE apbi.paddr(7 DOWNTO 2) IS
155 CASE apbi.paddr(7 DOWNTO 2) IS
154 WHEN "000000" =>
156 WHEN ADDR_LFR_TM_CONTROL =>
155 r.ctrl <= apbi.pwdata(0);
157 r.ctrl <= apbi.pwdata(0);
156 r.soft_reset <= apbi.pwdata(1);
158 r.soft_reset <= apbi.pwdata(1);
157 r.LFR_soft_reset <= apbi.pwdata(2);
159 r.LFR_soft_reset <= apbi.pwdata(2);
158 WHEN "000001" =>
160 WHEN ADDR_LFR_TM_TIME_LOAD =>
159 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
161 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
160 coarsetime_reg_updated <= '1';
162 coarsetime_reg_updated <= '1';
161 WHEN OTHERS =>
163 WHEN OTHERS =>
@@ -173,16 +175,16 BEGIN
173 --APB READ OP
175 --APB READ OP
174 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
176 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
175 CASE apbi.paddr(7 DOWNTO 2) IS
177 CASE apbi.paddr(7 DOWNTO 2) IS
176 WHEN "000000" =>
178 WHEN ADDR_LFR_TM_CONTROL =>
177 Rdata(0) <= r.ctrl;
179 Rdata(0) <= r.ctrl;
178 Rdata(1) <= r.soft_reset;
180 Rdata(1) <= r.soft_reset;
179 Rdata(2) <= r.LFR_soft_reset;
181 Rdata(2) <= r.LFR_soft_reset;
180 Rdata(31 DOWNTO 3) <= (others => '0');
182 Rdata(31 DOWNTO 3) <= (others => '0');
181 WHEN "000001" =>
183 WHEN ADDR_LFR_TM_TIME_LOAD =>
182 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
184 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
183 WHEN "000010" =>
185 WHEN ADDR_LFR_TM_TIME_COARSE =>
184 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
186 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
185 WHEN "000011" =>
187 WHEN ADDR_LFR_TM_TIME_FINE =>
186 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
188 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
187 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
189 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
188 WHEN OTHERS =>
190 WHEN OTHERS =>
@@ -193,6 +195,7 BEGIN
193 END IF;
195 END IF;
194 END PROCESS;
196 END PROCESS;
195
197
198 apbo.pirq <= (OTHERS => '0');
196 apbo.prdata <= Rdata;
199 apbo.prdata <= Rdata;
197 apbo.pconfig <= pconfig;
200 apbo.pconfig <= pconfig;
198 apbo.pindex <= pindex;
201 apbo.pindex <= pindex;
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@@ -1,4 +1,5
1 lpp_lfr_time_management.vhd
1 lpp_lfr_time_management.vhd
2 lpp_lfr_time_management_apbreg_pkg.vhd
2 apb_lfr_time_management.vhd
3 apb_lfr_time_management.vhd
3 lfr_time_management.vhd
4 lfr_time_management.vhd
4 fine_time_counter.vhd
5 fine_time_counter.vhd
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@@ -418,7 +418,7 BEGIN
418 -- AHB_Master -------------------------------------------------------------
418 -- AHB_Master -------------------------------------------------------------
419 ahbi_m_ext <= ahbmi;
419 ahbi_m_ext <= ahbmi;
420 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
420 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
421 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
421 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
422 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
422 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
423 END GENERATE max_16_ahbm;
423 END GENERATE max_16_ahbm;
424 END GENERATE all_ahbm;
424 END GENERATE all_ahbm;
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@@ -19,26 +19,28
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26 LIBRARY grlib;
27 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31
30 LIBRARY lpp;
32 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
33 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37
35 LIBRARY techmap;
38 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
37
40
38 ENTITY lpp_lfr_apbreg IS
41 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
42 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
43 nb_data_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
45 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
46 delta_vector_size_f0_2 : INTEGER := 3;
@@ -146,9 +148,13 ARCHITECTURE beh OF lpp_lfr_apbreg IS
146 CONSTANT REVISION : INTEGER := 1;
148 CONSTANT REVISION : INTEGER := 1;
147
149
148 CONSTANT pconfig : apb_config_type := (
150 CONSTANT pconfig : apb_config_type := (
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
151 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
150 1 => apb_iobar(paddr, pmask));
152 1 => apb_iobar(paddr, pmask));
151
153
154 --CONSTANT pconfig : apb_config_type := (
155 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
156 -- 1 => apb_iobar(paddr, pmask));
157
152 TYPE lpp_SpectralMatrix_regs IS RECORD
158 TYPE lpp_SpectralMatrix_regs IS RECORD
153 config_active_interruption_onNewMatrix : STD_LOGIC;
159 config_active_interruption_onNewMatrix : STD_LOGIC;
154 config_active_interruption_onError : STD_LOGIC;
160 config_active_interruption_onError : STD_LOGIC;
@@ -258,6 +264,8 ARCHITECTURE beh OF lpp_lfr_apbreg IS
258 SIGNAL apbo_irq_wfp : STD_LOGIC;
264 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 -----------------------------------------------------------------------------
265 -----------------------------------------------------------------------------
260 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
266 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
267
268 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
269
262 BEGIN -- beh
270 BEGIN -- beh
263
271
@@ -385,6 +393,11 BEGIN -- beh
385
393
386 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
394 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
387 reg_wp.length_buffer <= (OTHERS => '0');
395 reg_wp.length_buffer <= (OTHERS => '0');
396
397 pirq_temp <= (OTHERS => '0');
398
399 reg_wp.addr_buffer_f <= (OTHERS => '0');
400
388 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
401 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
389
402
390 -- status_full_ack <= (OTHERS => '0');
403 -- status_full_ack <= (OTHERS => '0');
@@ -420,135 +433,107 BEGIN -- beh
420 IF apbi.psel(pindex) = '1' THEN
433 IF apbi.psel(pindex) = '1' THEN
421 -- APB DMA READ --
434 -- APB DMA READ --
422 CASE paddr(7 DOWNTO 2) IS
435 CASE paddr(7 DOWNTO 2) IS
423 --0
436
424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
437 WHEN ADDR_LFR_SM_CONFIG =>
425 prdata(1) <= reg_sp.config_active_interruption_onError;
438 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
426 prdata(2) <= reg_sp.config_ms_run;
439 prdata(1) <= reg_sp.config_active_interruption_onError;
427 --1
440 prdata(2) <= reg_sp.config_ms_run;
428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
441
429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
442 WHEN ADDR_LFR_SM_STATUS =>
430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
443 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
444 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
445 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
446 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
447 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
435 prdata(7) <= reg_sp.status_error_buffer_full;
448 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
449 -- prdata(6) <= reg_sp.status_error_bad_component_error;
437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
450 prdata(7) <= reg_sp.status_error_buffer_full;
438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
451 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
439 --2
452 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
453 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
441 --3
454
442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
455 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
443 --4
456 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
457 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
445 --5
458 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
459 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
447 --6
460 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
461 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
449 --7
462 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
463 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
451 --8
464 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
465 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
453 --9
466 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
467 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
455 --10
468 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
469 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
457 --11
470 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
471 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
459 --12
472 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
473 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
461 --13
474 ---------------------------------------------------------------------
462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
475 WHEN ADDR_LFR_WP_DATASHAPING =>
463 --14
476 prdata(0) <= reg_wp.data_shaping_BW;
464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
477 prdata(1) <= reg_wp.data_shaping_SP0;
465 --15
478 prdata(2) <= reg_wp.data_shaping_SP1;
466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
479 prdata(3) <= reg_wp.data_shaping_R0;
467 --16
480 prdata(4) <= reg_wp.data_shaping_R1;
468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
481 prdata(5) <= reg_wp.data_shaping_R2;
469 --17
482 WHEN ADDR_LFR_WP_CONTROL =>
470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
483 prdata(0) <= reg_wp.enable_f0;
471 --18
484 prdata(1) <= reg_wp.enable_f1;
472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
485 prdata(2) <= reg_wp.enable_f2;
473 --19
486 prdata(3) <= reg_wp.enable_f3;
474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
487 prdata(4) <= reg_wp.burst_f0;
475 --20
488 prdata(5) <= reg_wp.burst_f1;
476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
489 prdata(6) <= reg_wp.burst_f2;
477 ---------------------------------------------------------------------
490 prdata(7) <= reg_wp.run;
478 --20
491 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
492 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
480 prdata(1) <= reg_wp.data_shaping_SP0;
493 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
481 prdata(2) <= reg_wp.data_shaping_SP1;
494 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
482 prdata(3) <= reg_wp.data_shaping_R0;
495 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
483 prdata(4) <= reg_wp.data_shaping_R1;
496 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
484 prdata(5) <= reg_wp.data_shaping_R2;
497 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
485 --21
498 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
499
487 prdata(1) <= reg_wp.enable_f1;
500 WHEN ADDR_LFR_WP_STATUS =>
488 prdata(2) <= reg_wp.enable_f2;
501 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
489 prdata(3) <= reg_wp.enable_f3;
502 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
490 prdata(4) <= reg_wp.burst_f0;
503 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
491 prdata(5) <= reg_wp.burst_f1;
504
492 prdata(6) <= reg_wp.burst_f2;
505 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
493 prdata(7) <= reg_wp.run;
506 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
494 --22
507 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
495 --ON GOING \/
508 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
509 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
510 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
511 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
512 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
513
501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
514 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
515 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
516 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
504 --ON GOING /\
517 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
510 --27
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
512 --28
513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
514 --29
515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
516 --30
517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
518 --31
519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
520 --32
521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
522 --33
523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
524 --34
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
526 --35
527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
531
518
532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
519 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
520 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
521 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
522 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
536
537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
541
523
542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
524 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
525 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
526 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
527 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
528
529 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
530 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
531 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
532 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
546
533
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
534 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
548
535 ---------------------------------------------------------------------
549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
536 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
550 ----------------------------------------------------
551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
552 WHEN OTHERS => NULL;
537 WHEN OTHERS => NULL;
553
538
554 END CASE;
539 END CASE;
@@ -556,11 +541,12 BEGIN -- beh
556 -- APB DMA WRITE --
541 -- APB DMA WRITE --
557 CASE paddr(7 DOWNTO 2) IS
542 CASE paddr(7 DOWNTO 2) IS
558 --
543 --
559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
544 WHEN ADDR_LFR_SM_CONFIG =>
560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
545 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
561 reg_sp.config_ms_run <= apbi.pwdata(2);
546 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
547 reg_sp.config_ms_run <= apbi.pwdata(2);
562
548
563 WHEN "000001" =>
549 WHEN ADDR_LFR_SM_STATUS =>
564 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
550 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
565 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
551 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
566 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
552 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
@@ -571,42 +557,40 BEGIN -- beh
571 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
557 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
572 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
558 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
573 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
559 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
574 --2
560 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
561 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
562 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
563 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
564 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
565 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
566
581 --8 to 19
567 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
582 --20
568 ---------------------------------------------------------------------
583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
569 WHEN ADDR_LFR_WP_DATASHAPING =>
584 --20
570 reg_wp.data_shaping_BW <= apbi.pwdata(0);
585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
571 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
572 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
573 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
574 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
575 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
576 WHEN ADDR_LFR_WP_CONTROL =>
591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
577 reg_wp.enable_f0 <= apbi.pwdata(0);
592 reg_wp.enable_f1 <= apbi.pwdata(1);
578 reg_wp.enable_f1 <= apbi.pwdata(1);
593 reg_wp.enable_f2 <= apbi.pwdata(2);
579 reg_wp.enable_f2 <= apbi.pwdata(2);
594 reg_wp.enable_f3 <= apbi.pwdata(3);
580 reg_wp.enable_f3 <= apbi.pwdata(3);
595 reg_wp.burst_f0 <= apbi.pwdata(4);
581 reg_wp.burst_f0 <= apbi.pwdata(4);
596 reg_wp.burst_f1 <= apbi.pwdata(5);
582 reg_wp.burst_f1 <= apbi.pwdata(5);
597 reg_wp.burst_f2 <= apbi.pwdata(6);
583 reg_wp.burst_f2 <= apbi.pwdata(6);
598 reg_wp.run <= apbi.pwdata(7);
584 reg_wp.run <= apbi.pwdata(7);
599 --22
585 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
586 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
587 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
588 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
589 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
590 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
591 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
592 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
593 WHEN ADDR_LFR_WP_STATUS =>
608 --26
609 WHEN "011111" =>
610 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
594 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
611 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
595 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
612 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
596 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
@@ -614,28 +598,24 BEGIN -- beh
614 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
598 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
615 END LOOP all_reg_wp_status_bit;
599 END LOOP all_reg_wp_status_bit;
616
600
617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
601 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
602 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
603 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
604 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
605 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
606 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
607 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
608 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
625
609
626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
610 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
627
628
629
611
630
631
632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
633 --
634 WHEN OTHERS => NULL;
612 WHEN OTHERS => NULL;
635 END CASE;
613 END CASE;
636 END IF;
614 END IF;
637 END IF;
615 END IF;
638 --apbo.pirq(pirq_ms) <=
616 --apbo.pirq(pirq_ms) <=
617 pirq_temp( pirq_ms) <= apbo_irq_ms;
618 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
639 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
619 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
640 ready_matrix_f1 OR
620 ready_matrix_f1 OR
641 ready_matrix_f2)
621 ready_matrix_f2)
@@ -653,9 +633,24 BEGIN -- beh
653
633
654 END IF;
634 END IF;
655 END PROCESS lpp_lfr_apbreg;
635 END PROCESS lpp_lfr_apbreg;
636
637 apbo.pirq <= pirq_temp;
638
656
639
657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
640 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
641 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
642 -- apbo.pirq(I) <= apbo_irq_ms;
643 -- END GENERATE IRQ_is_PIRQ_MS;
644 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
645 -- apbo.pirq(I) <= apbo_irq_wfp;
646 -- END GENERATE IRQ_is_PIRQ_WFP;
647 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
648 -- apbo.pirq(I) <= '0';
649 -- END GENERATE IRQ_OTHERS;
650
651 --END GENERATE all_irq;
652
653
659
654
660 apbo.pindex <= pindex;
655 apbo.pindex <= pindex;
661 apbo.pconfig <= pconfig;
656 apbo.pconfig <= pconfig;
@@ -782,3 +777,5 BEGIN -- beh
782 -----------------------------------------------------------------------------
777 -----------------------------------------------------------------------------
783
778
784 END beh;
779 END beh;
780
781 -------------------------------------------------------------------------------
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@@ -1,5 +1,6
1 lpp_top_lfr_pkg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
3 lpp_lfr_apbreg_pkg.vhd
3 lpp_lfr_filter.vhd
4 lpp_lfr_filter.vhd
4 lpp_lfr_apbreg.vhd
5 lpp_lfr_apbreg.vhd
5 lpp_lfr_apbreg_ms_pointer.vhd
6 lpp_lfr_apbreg_ms_pointer.vhd
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