@@ -13,7 +13,7 XSTOPT= | |||||
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
15 | VHDLSYNFILES=config.vhd leon3mp.vhd |
|
15 | VHDLSYNFILES=config.vhd leon3mp.vhd | |
16 | VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd |
|
16 | VHDLSIMFILES=testbench_package.vhd tb_waveform.vhd ../../lib/lpp/dsp/lpp_fft/actram.vhd | |
17 | SIMTOP=testbench |
|
17 | SIMTOP=testbench | |
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc |
|
18 | #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc | |
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc |
|
19 | #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc |
@@ -6,6 +6,11 vcom -quiet -93 -work lpp ../../../grl | |||||
6 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
|
6 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |
7 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
|
7 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd | |
8 |
|
8 | |||
|
9 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
|
10 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_test.vhd | |||
|
11 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_test.vhd | |||
|
12 | vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |||
|
13 | ||||
9 | vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd |
|
14 | vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd | |
10 |
|
15 | |||
11 | vcom -quiet -93 -work lpp testbench_package.vhd |
|
16 | vcom -quiet -93 -work lpp testbench_package.vhd | |
@@ -16,6 +21,6 vsim work.testbench | |||||
16 |
|
21 | |||
17 | log -r * |
|
22 | log -r * | |
18 |
|
23 | |||
19 |
do |
|
24 | do wave_ms.do | |
20 |
|
25 | |||
21 | run -all |
|
26 | run -all |
@@ -48,9 +48,17 ENTITY testbenc h IS | |||||
48 | END; |
|
48 | END; | |
49 |
|
49 | |||
50 | ARCHITECTURE behav OF testbench IS |
|
50 | ARCHITECTURE behav OF testbench IS | |
51 | -- REG ADDRESS |
|
51 | CONSTANT INDEX_LFR : INTEGER := 15; | |
52 |
CONSTANT |
|
52 | CONSTANT ADDR_LFR : INTEGER := 15; | |
53 | CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15; |
|
53 | -- REG MS | |
|
54 | CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; | |||
|
55 | CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; | |||
|
56 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; | |||
|
57 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; | |||
|
58 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; | |||
|
59 | CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; | |||
|
60 | CONSTANT ADDR_SPECTRAL_MATRIX_DEBUG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; | |||
|
61 | -- REG WAVEFORM | |||
54 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; |
|
62 | CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; | |
55 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; |
|
63 | CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; | |
56 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; |
|
64 | CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; | |
@@ -168,7 +176,7 ARCHITECTURE behav OF testbench IS | |||||
168 | SIGNAL wpo : wprot_out_type; |
|
176 | SIGNAL wpo : wprot_out_type; | |
169 | SIGNAL sdo : sdram_out_type; |
|
177 | SIGNAL sdo : sdram_out_type; | |
170 |
|
178 | |||
171 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
179 | SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; | |
172 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
180 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
173 | SIGNAL nSRAM_BE0 : STD_LOGIC; |
|
181 | SIGNAL nSRAM_BE0 : STD_LOGIC; | |
174 | SIGNAL nSRAM_BE1 : STD_LOGIC; |
|
182 | SIGNAL nSRAM_BE1 : STD_LOGIC; | |
@@ -231,13 +239,13 BEGIN | |||||
231 | nb_snapshot_param_size => 32, |
|
239 | nb_snapshot_param_size => 32, | |
232 | delta_vector_size => 32, |
|
240 | delta_vector_size => 32, | |
233 | delta_vector_size_f0_2 => 32, |
|
241 | delta_vector_size_f0_2 => 32, | |
234 |
pindex => INDEX_ |
|
242 | pindex => INDEX_LFR, | |
235 |
paddr => ADDR_ |
|
243 | paddr => ADDR_LFR, | |
236 | pmask => 16#fff#, |
|
244 | pmask => 16#fff#, | |
237 | pirq_ms => 6, |
|
245 | pirq_ms => 6, | |
238 | pirq_wfp => 14, |
|
246 | pirq_wfp => 14, | |
239 | hindex => 0, |
|
247 | hindex => 0, | |
240 |
top_lfr_version => X"00000 |
|
248 | top_lfr_version => X"000001") | |
241 | PORT MAP ( |
|
249 | PORT MAP ( | |
242 | clk => clk25MHz, |
|
250 | clk => clk25MHz, | |
243 | rstn => rstn, |
|
251 | rstn => rstn, | |
@@ -260,6 +268,8 BEGIN | |||||
260 | ioen => 0, nahbm => 1, nahbs => 1) |
|
268 | ioen => 0, nahbm => 1, nahbs => 1) | |
261 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); |
|
269 | PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); | |
262 |
|
270 | |||
|
271 | ||||
|
272 | ||||
263 |
|
|
273 | --- AHB RAM ---------------------------------------------------------- | |
264 | --ahbram0 : ahbram |
|
274 | --ahbram0 : ahbram | |
265 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) |
|
275 | -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) | |
@@ -278,75 +288,75 BEGIN | |||||
278 | ---------------------------------------------------------------------- |
|
288 | ---------------------------------------------------------------------- | |
279 | --- Memory controllers --------------------------------------------- |
|
289 | --- Memory controllers --------------------------------------------- | |
280 | ---------------------------------------------------------------------- |
|
290 | ---------------------------------------------------------------------- | |
281 | memctrlr : mctrl GENERIC MAP ( |
|
291 | --memctrlr : mctrl GENERIC MAP ( | |
282 |
|
|
292 | -- hindex => 0, | |
283 |
|
|
293 | -- pindex => 0, | |
284 | paddr => 0, |
|
294 | -- paddr => 0, | |
285 | srbanks => 1 |
|
295 | -- srbanks => 1 | |
286 | ) |
|
296 | -- ) | |
287 | PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
297 | -- PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
288 |
|
298 | |||
289 | memi.brdyn <= '1'; |
|
299 | --memi.brdyn <= '1'; | |
290 | memi.bexcn <= '1'; |
|
300 | --memi.bexcn <= '1'; | |
291 | memi.writen <= '1'; |
|
301 | --memi.writen <= '1'; | |
292 | memi.wrn <= "1111"; |
|
302 | --memi.wrn <= "1111"; | |
293 | memi.bwidth <= "10"; |
|
303 | --memi.bwidth <= "10"; | |
294 |
|
304 | |||
295 | bdr : FOR i IN 0 TO 3 GENERATE |
|
305 | --bdr : FOR i IN 0 TO 3 GENERATE | |
296 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
306 | -- data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
297 | PORT MAP ( |
|
307 | -- PORT MAP ( | |
298 | data(31-i*8 DOWNTO 24-i*8), |
|
308 | -- data(31-i*8 DOWNTO 24-i*8), | |
299 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
309 | -- memo.data(31-i*8 DOWNTO 24-i*8), | |
300 | memo.bdrive(i), |
|
310 | -- memo.bdrive(i), | |
301 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
311 | -- memi.data(31-i*8 DOWNTO 24-i*8)); | |
302 | END GENERATE; |
|
312 | --END GENERATE; | |
303 |
|
313 | |||
304 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
314 | --addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
305 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
315 | -- PORT MAP (address, memo.address(21 DOWNTO 2)); | |
306 |
|
316 | |||
307 | not_ramsn_0 <= NOT(memo.ramsn(0)); |
|
317 | --not_ramsn_0 <= NOT(memo.ramsn(0)); | |
308 |
|
318 | |||
309 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); |
|
319 | --rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); | |
310 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
320 | --oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
311 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
321 | --nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
312 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
322 | --nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
313 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
323 | --nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
314 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
324 | --nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
315 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
325 | --nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
316 |
|
326 | |||
317 | async_1Mx16_0: CY7C1061DV33 |
|
327 | --async_1Mx16_0: CY7C1061DV33 | |
318 | GENERIC MAP ( |
|
328 | -- GENERIC MAP ( | |
319 | ADDR_BITS => 20, |
|
329 | -- ADDR_BITS => 20, | |
320 | DATA_BITS => 16, |
|
330 | -- DATA_BITS => 16, | |
321 | depth => 1048576, |
|
331 | -- depth => 1048576, | |
322 | TimingInfo => TRUE, |
|
332 | -- TimingInfo => TRUE, | |
323 | TimingChecks => '1') |
|
333 | -- TimingChecks => '1') | |
324 | PORT MAP ( |
|
334 | -- PORT MAP ( | |
325 | CE1_b => '0', |
|
335 | -- CE1_b => '0', | |
326 | CE2 => nSRAM_CE, |
|
336 | -- CE2 => nSRAM_CE, | |
327 |
|
|
337 | -- WE_b => nSRAM_WE, | |
328 |
|
|
338 | -- OE_b => nSRAM_OE, | |
329 | BHE_b => nSRAM_BE1, |
|
339 | -- BHE_b => nSRAM_BE1, | |
330 | BLE_b => nSRAM_BE0, |
|
340 | -- BLE_b => nSRAM_BE0, | |
331 | A => address, |
|
341 | -- A => address, | |
332 | DQ => data(15 DOWNTO 0)); |
|
342 | -- DQ => data(15 DOWNTO 0)); | |
333 |
|
343 | |||
334 | async_1Mx16_1: CY7C1061DV33 |
|
344 | --async_1Mx16_1: CY7C1061DV33 | |
335 | GENERIC MAP ( |
|
345 | -- GENERIC MAP ( | |
336 | ADDR_BITS => 20, |
|
346 | -- ADDR_BITS => 20, | |
337 | DATA_BITS => 16, |
|
347 | -- DATA_BITS => 16, | |
338 | depth => 1048576, |
|
348 | -- depth => 1048576, | |
339 | TimingInfo => TRUE, |
|
349 | -- TimingInfo => TRUE, | |
340 | TimingChecks => '1') |
|
350 | -- TimingChecks => '1') | |
341 | PORT MAP ( |
|
351 | -- PORT MAP ( | |
342 | CE1_b => '0', |
|
352 | -- CE1_b => '0', | |
343 | CE2 => nSRAM_CE, |
|
353 | -- CE2 => nSRAM_CE, | |
344 |
|
|
354 | -- WE_b => nSRAM_WE, | |
345 |
|
|
355 | -- OE_b => nSRAM_OE, | |
346 | BHE_b => nSRAM_BE3, |
|
356 | -- BHE_b => nSRAM_BE3, | |
347 | BLE_b => nSRAM_BE2, |
|
357 | -- BLE_b => nSRAM_BE2, | |
348 | A => address, |
|
358 | -- A => address, | |
349 | DQ => data(31 DOWNTO 16)); |
|
359 | -- DQ => data(31 DOWNTO 16)); | |
350 |
|
360 | |||
351 |
|
361 | |||
352 | ----------------------------------------------------------------------------- |
|
362 | ----------------------------------------------------------------------------- | |
@@ -373,30 +383,40 BEGIN | |||||
373 | WAIT UNTIL clk25MHz = '1'; |
|
383 | WAIT UNTIL clk25MHz = '1'; | |
374 | rstn <= '1'; |
|
384 | rstn <= '1'; | |
375 | WAIT UNTIL clk25MHz = '1'; |
|
385 | WAIT UNTIL clk25MHz = '1'; | |
|
386 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"10000000"); | |||
|
387 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"20020000"); | |||
|
388 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1 , X"30040000"); | |||
|
389 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2 , X"40060000"); | |||
|
390 | ||||
|
391 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000000"); | |||
|
392 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); | |||
|
393 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); | |||
376 | WAIT UNTIL clk25MHz = '1'; |
|
394 | WAIT UNTIL clk25MHz = '1'; | |
377 | --------------------------------------------------------------------------- |
|
395 | --------------------------------------------------------------------------- | |
378 | -- CONFIGURATION STEP |
|
396 | -- CONFIGURATION STEP | |
379 |
APB_WRITE(clk25MHz, INDEX_ |
|
397 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); | |
380 |
APB_WRITE(clk25MHz, INDEX_ |
|
398 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); | |
381 |
APB_WRITE(clk25MHz, INDEX_ |
|
399 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); | |
382 |
APB_WRITE(clk25MHz, INDEX_ |
|
400 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); | |
383 |
|
401 | |||
384 |
APB_WRITE(clk25MHz, INDEX_ |
|
402 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020");--"00000020" | |
385 |
APB_WRITE(clk25MHz, INDEX_ |
|
403 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019");--"00000019" | |
386 |
APB_WRITE(clk25MHz, INDEX_ |
|
404 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" | |
387 |
APB_WRITE(clk25MHz, INDEX_ |
|
405 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019");--"00000019" | |
388 |
APB_WRITE(clk25MHz, INDEX_ |
|
406 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" | |
389 |
|
407 | |||
390 |
APB_WRITE(clk25MHz, INDEX_ |
|
408 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" | |
391 | -- |
|
409 | -- | |
392 |
APB_WRITE(clk25MHz, INDEX_ |
|
410 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); | |
393 |
APB_WRITE(clk25MHz, INDEX_ |
|
411 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); | |
394 |
APB_WRITE(clk25MHz, INDEX_ |
|
412 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); | |
395 |
|
413 | |||
396 |
|
414 | |||
397 | WAIT UNTIL clk25MHz = '1'; |
|
415 | WAIT UNTIL clk25MHz = '1'; | |
398 | WAIT UNTIL clk25MHz = '1'; |
|
416 | WAIT UNTIL clk25MHz = '1'; | |
399 | APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); |
|
417 | ||
|
418 | ||||
|
419 | --APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087"); | |||
400 | WAIT UNTIL clk25MHz = '1'; |
|
420 | WAIT UNTIL clk25MHz = '1'; | |
401 | WAIT UNTIL clk25MHz = '1'; |
|
421 | WAIT UNTIL clk25MHz = '1'; | |
402 | WAIT UNTIL clk25MHz = '1'; |
|
422 | WAIT UNTIL clk25MHz = '1'; | |
@@ -408,18 +428,18 BEGIN | |||||
408 | --------------------------------------------------------------------------- |
|
428 | --------------------------------------------------------------------------- | |
409 | -- RUN STEP |
|
429 | -- RUN STEP | |
410 | WAIT FOR 200 ms; |
|
430 | WAIT FOR 200 ms; | |
411 |
APB_WRITE(clk25MHz, INDEX_ |
|
431 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
412 |
APB_WRITE(clk25MHz, INDEX_ |
|
432 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); | |
413 | WAIT FOR 10 us; |
|
433 | WAIT FOR 10 us; | |
414 | WAIT UNTIL clk25MHz = '1'; |
|
434 | WAIT UNTIL clk25MHz = '1'; | |
415 | WAIT UNTIL clk25MHz = '1'; |
|
435 | WAIT UNTIL clk25MHz = '1'; | |
416 |
APB_WRITE(clk25MHz, INDEX_ |
|
436 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); | |
417 | WAIT UNTIL clk25MHz = '1'; |
|
437 | WAIT UNTIL clk25MHz = '1'; | |
418 | coarse_time <= X"00000010"; |
|
438 | coarse_time <= X"00000010"; | |
419 | WAIT FOR 100 ms; |
|
439 | WAIT FOR 100 ms; | |
420 |
APB_WRITE(clk25MHz, INDEX_ |
|
440 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); | |
421 | WAIT FOR 10 us; |
|
441 | WAIT FOR 10 us; | |
422 |
APB_WRITE(clk25MHz, INDEX_ |
|
442 | APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); | |
423 | WAIT FOR 200 ms; |
|
443 | WAIT FOR 200 ms; | |
424 | REPORT "*** END simulation ***" SEVERITY failure; |
|
444 | REPORT "*** END simulation ***" SEVERITY failure; | |
425 |
|
445 |
@@ -40,6 +40,6 PACKAGE apb_devices_list IS | |||||
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; |
|
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; | |
41 |
|
41 | |||
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; |
|
42 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; | |
43 | CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; |
|
43 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A1#; | |
44 |
|
44 | |||
45 | END; |
|
45 | END; |
@@ -235,6 +235,8 ARCHITECTURE Behavioral OF leon3_soc IS | |||||
235 | SIGNAL dsui : dsu_in_type; |
|
235 | SIGNAL dsui : dsu_in_type; | |
236 | SIGNAL dsuo : dsu_out_type; |
|
236 | SIGNAL dsuo : dsu_out_type; | |
237 | ----------------------------------------------------------------------------- |
|
237 | ----------------------------------------------------------------------------- | |
|
238 | ||||
|
239 | SIGNAL nSRAM_CE_s : STD_LOGIC; | |||
238 | BEGIN |
|
240 | BEGIN | |
239 |
|
241 | |||
240 |
|
242 | |||
@@ -326,8 +328,8 BEGIN | |||||
326 |
|
328 | |||
327 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
329 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
328 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
330 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
329 |
|
331 | nSRAM_CE_s <= NOT(memo.ramsn(0)); | ||
330 |
rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, |
|
332 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
331 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
333 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
332 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
334 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
333 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
335 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
@@ -59,47 +59,47 ENTITY lpp_lfr IS | |||||
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
61 | -- |
|
61 | -- | |
62 | data_shaping_BW : OUT STD_LOGIC; |
|
62 | data_shaping_BW : OUT STD_LOGIC--; | |
63 |
|
63 | |||
64 | --debug |
|
64 | --debug | |
65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
65 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
66 | debug_f0_data_valid : OUT STD_LOGIC; |
|
66 | --debug_f0_data_valid : OUT STD_LOGIC; | |
67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
67 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
68 | debug_f1_data_valid : OUT STD_LOGIC; |
|
68 | --debug_f1_data_valid : OUT STD_LOGIC; | |
69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
69 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
70 | debug_f2_data_valid : OUT STD_LOGIC; |
|
70 | --debug_f2_data_valid : OUT STD_LOGIC; | |
71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
|
71 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); | |
72 | debug_f3_data_valid : OUT STD_LOGIC; |
|
72 | --debug_f3_data_valid : OUT STD_LOGIC; | |
73 |
|
73 | |||
74 | -- debug FIFO_IN |
|
74 | ---- debug FIFO_IN | |
75 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
|
76 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; | |
77 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
77 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
78 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
|
78 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; | |
79 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
|
80 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; | |
81 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
81 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
|
82 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; | |
83 |
|
83 | |||
84 | --debug FIFO OUT |
|
84 | ----debug FIFO OUT | |
85 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
|
86 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; | |
87 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
88 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
|
88 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; | |
89 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
89 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
90 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
|
90 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; | |
91 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
|
92 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; | |
93 |
|
93 | |||
94 | --debug DMA IN |
|
94 | ----debug DMA IN | |
95 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
95 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
96 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
|
96 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; | |
97 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
98 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
|
98 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; | |
99 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
99 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
100 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
|
100 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; | |
101 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
101 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
102 | debug_f3_data_dma_in_valid : OUT STD_LOGIC |
|
102 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC | |
103 | ); |
|
103 | ); | |
104 | END lpp_lfr; |
|
104 | END lpp_lfr; | |
105 |
|
105 | |||
@@ -227,9 +227,13 ARCHITECTURE beh OF lpp_lfr IS | |||||
227 | -- DMA RR |
|
227 | -- DMA RR | |
228 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
229 | SIGNAL dma_sel_valid : STD_LOGIC; |
|
229 | SIGNAL dma_sel_valid : STD_LOGIC; | |
230 | SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
|||
231 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
230 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
232 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
231 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
232 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
233 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
|
234 | ||||
|
235 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
|
236 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); | |||
233 |
|
237 | |||
234 | ----------------------------------------------------------------------------- |
|
238 | ----------------------------------------------------------------------------- | |
235 | -- DMA_REG |
|
239 | -- DMA_REG | |
@@ -271,6 +275,17 ARCHITECTURE beh OF lpp_lfr IS | |||||
271 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
272 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
276 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
273 |
|
277 | |||
|
278 | ----------------------------------------------------------------------------- | |||
|
279 | -- MS | |||
|
280 | ----------------------------------------------------------------------------- | |||
|
281 | ||||
|
282 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
283 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
284 | SIGNAL data_ms_valid : STD_LOGIC; | |||
|
285 | SIGNAL data_ms_valid_burst : STD_LOGIC; | |||
|
286 | SIGNAL data_ms_ren : STD_LOGIC; | |||
|
287 | SIGNAL data_ms_done : STD_LOGIC; | |||
|
288 | ||||
274 | BEGIN |
|
289 | BEGIN | |
275 |
|
290 | |||
276 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
|
291 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
@@ -472,41 +487,41 BEGIN | |||||
472 | data_f3_data_out => data_f3_data_out, |
|
487 | data_f3_data_out => data_f3_data_out, | |
473 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
488 | data_f3_data_out_valid => data_f3_data_out_valid_s, | |
474 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
489 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, | |
475 | data_f3_data_out_ren => data_f3_data_out_ren, |
|
490 | data_f3_data_out_ren => data_f3_data_out_ren --, | |
476 |
|
491 | |||
477 | -- debug SNAPSHOT_OUT |
|
492 | ---- debug SNAPSHOT_OUT | |
478 | debug_f0_data => debug_f0_data, |
|
493 | --debug_f0_data => debug_f0_data, | |
479 | debug_f0_data_valid => debug_f0_data_valid , |
|
494 | --debug_f0_data_valid => debug_f0_data_valid , | |
480 | debug_f1_data => debug_f1_data , |
|
495 | --debug_f1_data => debug_f1_data , | |
481 | debug_f1_data_valid => debug_f1_data_valid, |
|
496 | --debug_f1_data_valid => debug_f1_data_valid, | |
482 | debug_f2_data => debug_f2_data , |
|
497 | --debug_f2_data => debug_f2_data , | |
483 | debug_f2_data_valid => debug_f2_data_valid , |
|
498 | --debug_f2_data_valid => debug_f2_data_valid , | |
484 | debug_f3_data => debug_f3_data , |
|
499 | --debug_f3_data => debug_f3_data , | |
485 | debug_f3_data_valid => debug_f3_data_valid, |
|
500 | --debug_f3_data_valid => debug_f3_data_valid, | |
486 |
|
501 | |||
487 | -- debug FIFO_IN |
|
502 | ---- debug FIFO_IN | |
488 | debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
|
503 | --debug_f0_data_fifo_in => debug_f0_data_fifo_in , | |
489 | debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
|
504 | --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, | |
490 | debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
|
505 | --debug_f1_data_fifo_in => debug_f1_data_fifo_in , | |
491 | debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
|
506 | --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, | |
492 | debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
|
507 | --debug_f2_data_fifo_in => debug_f2_data_fifo_in , | |
493 | debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
|
508 | --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, | |
494 | debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
|
509 | --debug_f3_data_fifo_in => debug_f3_data_fifo_in , | |
495 | debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
|
510 | --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid | |
496 |
|
511 | |||
497 | ); |
|
512 | ); | |
498 |
|
513 | |||
499 |
|
514 | |||
500 | ----------------------------------------------------------------------------- |
|
515 | ----------------------------------------------------------------------------- | |
501 | -- DEBUG -- WFP OUT |
|
516 | -- DEBUG -- WFP OUT | |
502 | debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
|
517 | --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; | |
503 | debug_f0_data_fifo_out <= data_f0_data_out; |
|
518 | --debug_f0_data_fifo_out <= data_f0_data_out; | |
504 | debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
|
519 | --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; | |
505 | debug_f1_data_fifo_out <= data_f1_data_out; |
|
520 | --debug_f1_data_fifo_out <= data_f1_data_out; | |
506 | debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
|
521 | --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; | |
507 | debug_f2_data_fifo_out <= data_f2_data_out; |
|
522 | --debug_f2_data_fifo_out <= data_f2_data_out; | |
508 | debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
|
523 | --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; | |
509 | debug_f3_data_fifo_out <= data_f3_data_out; |
|
524 | --debug_f3_data_fifo_out <= data_f3_data_out; | |
510 | ----------------------------------------------------------------------------- |
|
525 | ----------------------------------------------------------------------------- | |
511 |
|
526 | |||
512 |
|
527 | |||
@@ -556,7 +571,21 BEGIN | |||||
556 | clk => clk, |
|
571 | clk => clk, | |
557 | rstn => rstn, |
|
572 | rstn => rstn, | |
558 | in_valid => dma_rr_valid, |
|
573 | in_valid => dma_rr_valid, | |
559 | out_grant => dma_rr_grant); |
|
574 | out_grant => dma_rr_grant_s); | |
|
575 | ||||
|
576 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; | |||
|
577 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; | |||
|
578 | dma_rr_valid_ms(2) <= '0'; | |||
|
579 | dma_rr_valid_ms(3) <= '0'; | |||
|
580 | ||||
|
581 | RR_Arbiter_4_2 : RR_Arbiter_4 | |||
|
582 | PORT MAP ( | |||
|
583 | clk => clk, | |||
|
584 | rstn => rstn, | |||
|
585 | in_valid => dma_rr_valid_ms, | |||
|
586 | out_grant => dma_rr_grant_ms); | |||
|
587 | ||||
|
588 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; | |||
560 |
|
589 | |||
561 |
|
|
590 | ||
562 |
|
|
591 | ----------------------------------------------------------------------------- | |
@@ -574,8 +603,7 BEGIN | |||||
574 | dma_valid_burst <= '0'; |
|
603 | dma_valid_burst <= '0'; | |
575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
604 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
576 | IF run = '1' THEN |
|
605 | IF run = '1' THEN | |
577 |
|
|
606 | IF dma_sel = "00000" OR dma_done = '1' THEN | |
578 | IF dma_sel = "0000" OR dma_done = '1' THEN |
|
|||
579 | dma_sel <= dma_rr_grant; |
|
607 | dma_sel <= dma_rr_grant; | |
580 | IF dma_rr_grant(0) = '1' THEN |
|
608 | IF dma_rr_grant(0) = '1' THEN | |
581 | dma_send <= '1'; |
|
609 | dma_send <= '1'; | |
@@ -593,6 +621,14 BEGIN | |||||
593 | dma_send <= '1'; |
|
621 | dma_send <= '1'; | |
594 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
622 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
595 | dma_sel_valid <= data_f3_data_out_valid; |
|
623 | dma_sel_valid <= data_f3_data_out_valid; | |
|
624 | ELSIF dma_rr_grant(4) = '1' THEN | |||
|
625 | dma_send <= '1'; | |||
|
626 | dma_valid_burst <= data_ms_valid_burst; | |||
|
627 | dma_sel_valid <= data_ms_valid; | |||
|
628 | END IF; | |||
|
629 | ||||
|
630 | IF dma_sel(4) = '1' THEN | |||
|
631 | data_ms_done <= '1'; | |||
596 | END IF; |
|
632 | END IF; | |
597 | ELSE |
|
633 | ELSE | |
598 | dma_sel <= dma_sel; |
|
634 | dma_sel <= dma_sel; | |
@@ -610,17 +646,20 BEGIN | |||||
610 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
646 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE | |
611 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
647 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE | |
612 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
648 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE | |
613 |
data_f3_addr_out |
|
649 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE | |
|
650 | data_ms_addr; | |||
614 |
|
651 | |||
615 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
652 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE | |
616 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
653 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE | |
617 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
654 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE | |
618 |
data_f3_data_out |
|
655 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE | |
|
656 | data_ms_data; | |||
619 |
|
657 | |||
620 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
658 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; | |
621 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
659 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; | |
622 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
660 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; | |
623 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
661 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; | |
|
662 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; | |||
624 |
|
663 | |||
625 | dma_data_2 <= dma_data; |
|
664 | dma_data_2 <= dma_data; | |
626 |
|
665 | |||
@@ -630,14 +669,14 BEGIN | |||||
630 |
|
669 | |||
631 | ----------------------------------------------------------------------------- |
|
670 | ----------------------------------------------------------------------------- | |
632 | -- DEBUG -- DMA IN |
|
671 | -- DEBUG -- DMA IN | |
633 | debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
672 | --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; | |
634 | debug_f0_data_dma_in <= dma_data; |
|
673 | --debug_f0_data_dma_in <= dma_data; | |
635 | debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
674 | --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; | |
636 | debug_f1_data_dma_in <= dma_data; |
|
675 | --debug_f1_data_dma_in <= dma_data; | |
637 | debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
676 | --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; | |
638 | debug_f2_data_dma_in <= dma_data; |
|
677 | --debug_f2_data_dma_in <= dma_data; | |
639 | debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
678 | --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; | |
640 | debug_f3_data_dma_in <= dma_data; |
|
679 | --debug_f3_data_dma_in <= dma_data; | |
641 | ----------------------------------------------------------------------------- |
|
680 | ----------------------------------------------------------------------------- | |
642 |
|
681 | |||
643 | ----------------------------------------------------------------------------- |
|
682 | ----------------------------------------------------------------------------- | |
@@ -662,53 +701,58 BEGIN | |||||
662 | data => dma_data_2); |
|
701 | data => dma_data_2); | |
663 |
|
702 | |||
664 | ----------------------------------------------------------------------------- |
|
703 | ----------------------------------------------------------------------------- | |
665 |
-- Matrix Spectral |
|
704 | -- Matrix Spectral | |
666 | ----------------------------------------------------------------------------- |
|
|||
667 | ----------------------------------------------------------------------------- |
|
705 | ----------------------------------------------------------------------------- | |
668 |
|
|
706 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & | |
669 |
|
|
707 | NOT(sample_f0_val) & NOT(sample_f0_val) ; | |
670 |
|
|
708 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
671 |
|
|
709 | NOT(sample_f1_val) & NOT(sample_f1_val) ; | |
672 |
|
|
710 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & | |
673 |
|
|
711 | NOT(sample_f3_val) & NOT(sample_f3_val) ; | |
674 |
|
712 | |||
675 |
|
|
713 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
676 |
|
|
714 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
677 |
|
|
715 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); | |
678 | ------------------------------------------------------------------------------- |
|
716 | ------------------------------------------------------------------------------- | |
679 |
|
|
717 | lpp_lfr_ms_1: lpp_lfr_ms | |
680 |
|
|
718 | GENERIC MAP ( | |
681 | -- hindex => hindex_ms) |
|
719 | Mem_use => Mem_use ) | |
682 |
|
|
720 | PORT MAP ( | |
683 |
|
|
721 | clk => clk, | |
684 |
|
|
722 | rstn => rstn, | |
685 | -- sample_f0_wen => sample_f0_wen, |
|
723 | ||
686 |
|
|
724 | sample_f0_wen => sample_f0_wen, | |
687 |
|
|
725 | sample_f0_wdata => sample_f0_wdata, | |
688 |
|
|
726 | sample_f1_wen => sample_f1_wen, | |
689 |
|
|
727 | sample_f1_wdata => sample_f1_wdata, | |
690 |
|
|
728 | sample_f3_wen => sample_f3_wen, | |
691 | -- AHB_Master_In => ahbi_ms, |
|
729 | sample_f3_wdata => sample_f3_wdata, | |
692 | -- AHB_Master_Out => ahbo_ms, |
|
|||
693 |
|
730 | |||
694 | -- ready_matrix_f0_0 => ready_matrix_f0_0, |
|
731 | dma_addr => data_ms_addr, -- | |
695 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
732 | dma_data => data_ms_data, -- | |
696 | -- ready_matrix_f1 => ready_matrix_f1, |
|
733 | dma_valid => data_ms_valid, -- | |
697 | -- ready_matrix_f2 => ready_matrix_f2, |
|
734 | dma_valid_burst => data_ms_valid_burst, -- | |
698 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
735 | dma_ren => data_ms_ren, -- | |
699 | -- error_bad_component_error => error_bad_component_error, |
|
736 | dma_done => data_ms_done, -- | |
700 | -- debug_reg => debug_reg, |
|
737 | ||
701 |
|
|
738 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
702 |
|
|
739 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
703 |
|
|
740 | ready_matrix_f1 => ready_matrix_f1, | |
704 |
|
|
741 | ready_matrix_f2 => ready_matrix_f2, | |
705 |
|
|
742 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |
706 |
|
|
743 | error_bad_component_error => error_bad_component_error, | |
707 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
744 | debug_reg => debug_reg, | |
708 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
745 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |
709 |
|
|
746 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |
710 |
|
|
747 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
711 |
|
|
748 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
712 | -- addr_matrix_f2 => addr_matrix_f2); |
|
749 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |
|
750 | status_error_bad_component_error => status_error_bad_component_error, | |||
|
751 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
|
752 | config_active_interruption_onError => config_active_interruption_onError, | |||
|
753 | addr_matrix_f0_0 => addr_matrix_f0_0, | |||
|
754 | addr_matrix_f0_1 => addr_matrix_f0_1, | |||
|
755 | addr_matrix_f1 => addr_matrix_f1, | |||
|
756 | addr_matrix_f2 => addr_matrix_f2); | |||
713 |
|
757 | |||
714 | END beh; |
|
758 | END beh; |
@@ -17,6 +17,7 USE lpp.lpp_demux.ALL; | |||||
17 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
17 | USE lpp.lpp_top_lfr_pkg.ALL; | |
18 | USE lpp.lpp_dma_pkg.ALL; |
|
18 | USE lpp.lpp_dma_pkg.ALL; | |
19 | USE lpp.lpp_Header.ALL; |
|
19 | USE lpp.lpp_Header.ALL; | |
|
20 | USE lpp.lpp_lfr_pkg.ALL; | |||
20 |
|
21 | |||
21 | LIBRARY grlib; |
|
22 | LIBRARY grlib; | |
22 | USE grlib.amba.ALL; |
|
23 | USE grlib.amba.ALL; | |
@@ -27,7 +28,7 USE GRLIB.DMA2AHB_Package.ALL; | |||||
27 |
|
28 | |||
28 | ENTITY lpp_lfr_ms IS |
|
29 | ENTITY lpp_lfr_ms IS | |
29 | GENERIC ( |
|
30 | GENERIC ( | |
30 |
|
|
31 | Mem_use : INTEGER | |
31 | ); |
|
32 | ); | |
32 | PORT ( |
|
33 | PORT ( | |
33 | clk : IN STD_LOGIC; |
|
34 | clk : IN STD_LOGIC; | |
@@ -49,10 +50,12 ENTITY lpp_lfr_ms IS | |||||
49 | --------------------------------------------------------------------------- |
|
50 | --------------------------------------------------------------------------- | |
50 | -- DMA |
|
51 | -- DMA | |
51 | --------------------------------------------------------------------------- |
|
52 | --------------------------------------------------------------------------- | |
52 |
|
53 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | ||
53 | -- AMBA AHB Master Interface |
|
54 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
55 | dma_valid : OUT STD_LOGIC; | |
55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
56 | dma_valid_burst : OUT STD_LOGIC; | |
|
57 | dma_ren : IN STD_LOGIC; | |||
|
58 | dma_done : IN STD_LOGIC; | |||
56 |
|
59 | |||
57 | -- Reg out |
|
60 | -- Reg out | |
58 | ready_matrix_f0_0 : OUT STD_LOGIC; |
|
61 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
@@ -108,7 +111,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |||||
108 |
|
111 | |||
109 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
110 | SIGNAL SM_FlagError : STD_LOGIC; |
|
113 | SIGNAL SM_FlagError : STD_LOGIC; | |
111 | SIGNAL SM_Pong : STD_LOGIC; |
|
114 | -- SIGNAL SM_Pong : STD_LOGIC; | |
112 | SIGNAL SM_Wen : STD_LOGIC; |
|
115 | SIGNAL SM_Wen : STD_LOGIC; | |
113 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
116 | SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
114 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
117 | SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
@@ -138,10 +141,10 BEGIN | |||||
138 | ----------------------------------------------------------------------------- |
|
141 | ----------------------------------------------------------------------------- | |
139 | Memf0: lppFIFOxN |
|
142 | Memf0: lppFIFOxN | |
140 | GENERIC MAP ( |
|
143 | GENERIC MAP ( | |
141 |
tech => 0, Mem_use => use |
|
144 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
142 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') |
|
145 | Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0') | |
143 | PORT MAP ( |
|
146 | PORT MAP ( | |
144 | rst => rstn, wclk => clk, rclk => clk, |
|
147 | rstn => rstn, wclk => clk, rclk => clk, | |
145 | ReUse => (OTHERS => '0'), |
|
148 | ReUse => (OTHERS => '0'), | |
146 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), |
|
149 | wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0), | |
147 | wdata => sample_f0_wdata, rdata => FifoF0_Data, |
|
150 | wdata => sample_f0_wdata, rdata => FifoF0_Data, | |
@@ -149,10 +152,10 BEGIN | |||||
149 |
|
152 | |||
150 | Memf1: lppFIFOxN |
|
153 | Memf1: lppFIFOxN | |
151 | GENERIC MAP ( |
|
154 | GENERIC MAP ( | |
152 |
tech => 0, Mem_use => use |
|
155 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
153 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
156 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
154 | PORT MAP ( |
|
157 | PORT MAP ( | |
155 | rst => rstn, wclk => clk, rclk => clk, |
|
158 | rstn => rstn, wclk => clk, rclk => clk, | |
156 | ReUse => (OTHERS => '0'), |
|
159 | ReUse => (OTHERS => '0'), | |
157 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), |
|
160 | wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5), | |
158 | wdata => sample_f1_wdata, rdata => FifoF1_Data, |
|
161 | wdata => sample_f1_wdata, rdata => FifoF1_Data, | |
@@ -161,10 +164,10 BEGIN | |||||
161 |
|
164 | |||
162 | Memf2: lppFIFOxN |
|
165 | Memf2: lppFIFOxN | |
163 | GENERIC MAP ( |
|
166 | GENERIC MAP ( | |
164 |
tech => 0, Mem_use => use |
|
167 | tech => 0, Mem_use => Mem_use, Data_sz => 16, | |
165 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') |
|
168 | Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0') | |
166 | PORT MAP ( |
|
169 | PORT MAP ( | |
167 | rst => rstn, wclk => clk, rclk => clk, |
|
170 | rstn => rstn, wclk => clk, rclk => clk, | |
168 | ReUse => (OTHERS => '0'), |
|
171 | ReUse => (OTHERS => '0'), | |
169 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), |
|
172 | wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10), | |
170 | wdata => sample_f3_wdata, rdata => FifoF3_Data, |
|
173 | wdata => sample_f3_wdata, rdata => FifoF3_Data, | |
@@ -217,13 +220,13 BEGIN | |||||
217 | MemInt : lppFIFOxN |
|
220 | MemInt : lppFIFOxN | |
218 | GENERIC MAP ( |
|
221 | GENERIC MAP ( | |
219 | tech => 0, |
|
222 | tech => 0, | |
220 |
Mem_use => use |
|
223 | Mem_use => Mem_use, | |
221 | Data_sz => 16, |
|
224 | Data_sz => 16, | |
222 | Addr_sz => 8, |
|
225 | Addr_sz => 8, | |
223 | FifoCnt => 5, |
|
226 | FifoCnt => 5, | |
224 | Enable_ReUse => '1') |
|
227 | Enable_ReUse => '1') | |
225 | PORT MAP ( |
|
228 | PORT MAP ( | |
226 | rst => rstn, |
|
229 | rstn => rstn, | |
227 | wclk => clk, |
|
230 | wclk => clk, | |
228 | rclk => clk, |
|
231 | rclk => clk, | |
229 | ReUse => SM_ReUse, |
|
232 | ReUse => SM_ReUse, | |
@@ -247,10 +250,10 BEGIN | |||||
247 | SetReUse => FFT_ReUse, |
|
250 | SetReUse => FFT_ReUse, | |
248 | Valid => Head_Valid, |
|
251 | Valid => Head_Valid, | |
249 | Data_IN => FifoINT_Data, |
|
252 | Data_IN => FifoINT_Data, | |
250 |
AC |
|
253 | ACK => DMA_ack, | |
251 | SM_Write => SM_Wen, |
|
254 | SM_Write => SM_Wen, | |
252 | FlagError => SM_FlagError, |
|
255 | FlagError => SM_FlagError, | |
253 | Pong => SM_Pong, |
|
256 | -- Pong => SM_Pong, | |
254 | Statu => SM_Param, |
|
257 | Statu => SM_Param, | |
255 | Write => SM_Write, |
|
258 | Write => SM_Write, | |
256 | Read => SM_Read, |
|
259 | Read => SM_Read, | |
@@ -262,13 +265,13 BEGIN | |||||
262 | MemOut : lppFIFOxN |
|
265 | MemOut : lppFIFOxN | |
263 | GENERIC MAP ( |
|
266 | GENERIC MAP ( | |
264 | tech => 0, |
|
267 | tech => 0, | |
265 |
Mem_use => use |
|
268 | Mem_use => Mem_use, | |
266 | Data_sz => 32, |
|
269 | Data_sz => 32, | |
267 | Addr_sz => 8, |
|
270 | Addr_sz => 8, | |
268 | FifoCnt => 2, |
|
271 | FifoCnt => 2, | |
269 | Enable_ReUse => '0') |
|
272 | Enable_ReUse => '0') | |
270 | PORT MAP ( |
|
273 | PORT MAP ( | |
271 | rst => rstn, |
|
274 | rstn => rstn, | |
272 | wclk => clk, |
|
275 | wclk => clk, | |
273 | rclk => clk, |
|
276 | rclk => clk, | |
274 | ReUse => (OTHERS => '0'), |
|
277 | ReUse => (OTHERS => '0'), | |
@@ -287,7 +290,7 BEGIN | |||||
287 | PORT MAP ( |
|
290 | PORT MAP ( | |
288 | clkm => clk, |
|
291 | clkm => clk, | |
289 | rstn => rstn, |
|
292 | rstn => rstn, | |
290 | pong => SM_Pong, |
|
293 | -- pong => SM_Pong, | |
291 | Statu => SM_Param, |
|
294 | Statu => SM_Param, | |
292 | Matrix_Type => DMUX_WorkFreq, |
|
295 | Matrix_Type => DMUX_WorkFreq, | |
293 | Matrix_Write => SM_Wen, |
|
296 | Matrix_Write => SM_Wen, | |
@@ -303,16 +306,11 BEGIN | |||||
303 | header_ack => DMA_ack ); |
|
306 | header_ack => DMA_ack ); | |
304 | ----------------------------------------------------------------------------- |
|
307 | ----------------------------------------------------------------------------- | |
305 |
|
308 | |||
306 | ----------------------------------------------------------------------------- |
|
309 | ||
307 |
lpp_dma |
|
310 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
308 | GENERIC MAP ( |
|
|||
309 | tech => 0, |
|
|||
310 | hindex => hindex) |
|
|||
311 | PORT MAP ( |
|
311 | PORT MAP ( | |
312 | HCLK => clk, |
|
312 | HCLK => clk, | |
313 | HRESETn => rstn, |
|
313 | HRESETn => rstn, | |
314 | AHB_Master_In => AHB_Master_In, |
|
|||
315 | AHB_Master_Out => AHB_Master_Out, |
|
|||
316 |
|
314 | |||
317 | fifo_data => Head_Data, |
|
315 | fifo_data => Head_Data, | |
318 | fifo_empty => Head_Empty, |
|
316 | fifo_empty => Head_Empty, | |
@@ -322,6 +320,13 BEGIN | |||||
322 |
|
|
320 | header_val => Head_Val, | |
323 |
|
|
321 | header_ack => DMA_ack, | |
324 |
|
|
322 | ||
|
323 | dma_addr => dma_addr, | |||
|
324 | dma_data => dma_data, | |||
|
325 | dma_valid => dma_valid, | |||
|
326 | dma_valid_burst => dma_valid_burst, | |||
|
327 | dma_ren => dma_ren, | |||
|
328 | dma_done => dma_done, | |||
|
329 | ||||
325 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
330 | ready_matrix_f0_0 => ready_matrix_f0_0, | |
326 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
331 | ready_matrix_f0_1 => ready_matrix_f0_1, | |
327 | ready_matrix_f1 => ready_matrix_f1, |
|
332 | ready_matrix_f1 => ready_matrix_f1, | |
@@ -341,6 +346,48 BEGIN | |||||
341 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
346 | addr_matrix_f0_1 => addr_matrix_f0_1, | |
342 | addr_matrix_f1 => addr_matrix_f1, |
|
347 | addr_matrix_f1 => addr_matrix_f1, | |
343 | addr_matrix_f2 => addr_matrix_f2); |
|
348 | addr_matrix_f2 => addr_matrix_f2); | |
|
349 | ||||
|
350 | ||||
|
351 | ||||
|
352 | ||||
344 |
|
|
353 | ----------------------------------------------------------------------------- | |
|
354 | --lpp_dma_ip_1: lpp_dma_ip | |||
|
355 | -- GENERIC MAP ( | |||
|
356 | -- tech => 0, | |||
|
357 | -- hindex => hindex) | |||
|
358 | -- PORT MAP ( | |||
|
359 | -- HCLK => clk, | |||
|
360 | -- HRESETn => rstn, | |||
|
361 | -- AHB_Master_In => AHB_Master_In, | |||
|
362 | -- AHB_Master_Out => AHB_Master_Out, | |||
|
363 | ||||
|
364 | -- fifo_data => Head_Data, | |||
|
365 | -- fifo_empty => Head_Empty, | |||
|
366 | -- fifo_ren => DMA_Read, | |||
|
367 | ||||
|
368 | -- header => Head_Header, | |||
|
369 | -- header_val => Head_Val, | |||
|
370 | -- header_ack => DMA_ack, | |||
345 |
|
371 | |||
346 | END Behavioral; No newline at end of file |
|
372 | -- ready_matrix_f0_0 => ready_matrix_f0_0, | |
|
373 | -- ready_matrix_f0_1 => ready_matrix_f0_1, | |||
|
374 | -- ready_matrix_f1 => ready_matrix_f1, | |||
|
375 | -- ready_matrix_f2 => ready_matrix_f2, | |||
|
376 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, | |||
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377 | -- error_bad_component_error => error_bad_component_error, | |||
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378 | -- debug_reg => debug_reg, | |||
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379 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, | |||
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380 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, | |||
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381 | -- status_ready_matrix_f1 => status_ready_matrix_f1, | |||
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382 | -- status_ready_matrix_f2 => status_ready_matrix_f2, | |||
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383 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, | |||
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384 | -- status_error_bad_component_error => status_error_bad_component_error, | |||
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385 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |||
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386 | -- config_active_interruption_onError => config_active_interruption_onError, | |||
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387 | -- addr_matrix_f0_0 => addr_matrix_f0_0, | |||
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388 | -- addr_matrix_f0_1 => addr_matrix_f0_1, | |||
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389 | -- addr_matrix_f1 => addr_matrix_f1, | |||
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390 | -- addr_matrix_f2 => addr_matrix_f2); | |||
|
391 | ------------------------------------------------------------------------------- | |||
|
392 | ||||
|
393 | END Behavioral; |
@@ -16,7 +16,8 PACKAGE lpp_lfr_pkg IS | |||||
16 |
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16 | |||
17 | COMPONENT lpp_lfr_ms |
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17 | COMPONENT lpp_lfr_ms | |
18 | GENERIC ( |
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18 | GENERIC ( | |
19 |
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19 | Mem_use : INTEGER | |
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20 | ); | |||
20 | PORT ( |
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21 | PORT ( | |
21 | clk : IN STD_LOGIC; |
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22 | clk : IN STD_LOGIC; | |
22 | rstn : IN STD_LOGIC; |
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23 | rstn : IN STD_LOGIC; | |
@@ -26,8 +27,14 PACKAGE lpp_lfr_pkg IS | |||||
26 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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27 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
27 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
28 | sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
28 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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29 | sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
29 | AHB_Master_In : IN AHB_Mst_In_Type; |
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30 | ||
30 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
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31 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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32 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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33 | dma_valid : OUT STD_LOGIC; | |||
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34 | dma_valid_burst : OUT STD_LOGIC; | |||
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35 | dma_ren : IN STD_LOGIC; | |||
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36 | dma_done : IN STD_LOGIC; | |||
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37 | ||||
31 |
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38 | ready_matrix_f0_0 : OUT STD_LOGIC; | |
32 | ready_matrix_f0_1 : OUT STD_LOGIC; |
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39 | ready_matrix_f0_1 : OUT STD_LOGIC; | |
33 | ready_matrix_f1 : OUT STD_LOGIC; |
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40 | ready_matrix_f1 : OUT STD_LOGIC; | |
@@ -49,6 +56,44 PACKAGE lpp_lfr_pkg IS | |||||
49 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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56 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
50 | END COMPONENT; |
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57 | END COMPONENT; | |
51 |
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58 | |||
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59 | COMPONENT lpp_lfr_ms_fsmdma | |||
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60 | PORT ( | |||
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61 | HCLK : IN STD_ULOGIC; | |||
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62 | HRESETn : IN STD_ULOGIC; | |||
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63 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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64 | fifo_empty : IN STD_LOGIC; | |||
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65 | fifo_ren : OUT STD_LOGIC; | |||
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66 | header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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67 | header_val : IN STD_LOGIC; | |||
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68 | header_ack : OUT STD_LOGIC; | |||
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69 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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70 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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71 | dma_valid : OUT STD_LOGIC; | |||
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72 | dma_valid_burst : OUT STD_LOGIC; | |||
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73 | dma_ren : IN STD_LOGIC; | |||
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74 | dma_done : IN STD_LOGIC; | |||
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75 | ready_matrix_f0_0 : OUT STD_LOGIC; | |||
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76 | ready_matrix_f0_1 : OUT STD_LOGIC; | |||
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77 | ready_matrix_f1 : OUT STD_LOGIC; | |||
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78 | ready_matrix_f2 : OUT STD_LOGIC; | |||
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79 | error_anticipating_empty_fifo : OUT STD_LOGIC; | |||
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80 | error_bad_component_error : OUT STD_LOGIC; | |||
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81 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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82 | status_ready_matrix_f0_0 : IN STD_LOGIC; | |||
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83 | status_ready_matrix_f0_1 : IN STD_LOGIC; | |||
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84 | status_ready_matrix_f1 : IN STD_LOGIC; | |||
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85 | status_ready_matrix_f2 : IN STD_LOGIC; | |||
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86 | status_error_anticipating_empty_fifo : IN STD_LOGIC; | |||
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87 | status_error_bad_component_error : IN STD_LOGIC; | |||
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88 | config_active_interruption_onNewMatrix : IN STD_LOGIC; | |||
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89 | config_active_interruption_onError : IN STD_LOGIC; | |||
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90 | addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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91 | addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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92 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
93 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); | |||
|
94 | END COMPONENT; | |||
|
95 | ||||
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96 | ||||
52 |
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97 | COMPONENT lpp_lfr_filter | |
53 | GENERIC ( |
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98 | GENERIC ( | |
54 | Mem_use : INTEGER); |
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99 | Mem_use : INTEGER); | |
@@ -99,47 +144,7 PACKAGE lpp_lfr_pkg IS | |||||
99 | ahbo : OUT AHB_Mst_Out_Type; |
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144 | ahbo : OUT AHB_Mst_Out_Type; | |
100 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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145 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
101 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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146 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
102 |
data_shaping_BW : OUT STD_LOGIC |
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147 | data_shaping_BW : OUT STD_LOGIC | |
103 |
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||||
104 | --debug |
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105 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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106 | debug_f0_data_valid : OUT STD_LOGIC; |
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107 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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108 | debug_f1_data_valid : OUT STD_LOGIC; |
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109 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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110 | debug_f2_data_valid : OUT STD_LOGIC; |
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111 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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112 | debug_f3_data_valid : OUT STD_LOGIC; |
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113 |
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||||
114 | -- debug FIFO_IN |
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115 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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116 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
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117 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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118 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
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119 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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120 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
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121 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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122 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
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123 |
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||||
124 | --debug FIFO OUT |
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|||
125 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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126 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
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127 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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128 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
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129 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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130 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
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131 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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132 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
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133 |
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134 | --debug DMA IN |
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135 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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136 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
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137 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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138 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
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139 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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140 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
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141 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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142 | debug_f3_data_dma_in_valid : OUT STD_LOGIC |
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|||
143 | ); |
|
148 | ); | |
144 | END COMPONENT; |
|
149 | END COMPONENT; | |
145 |
|
150 |
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