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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31
32
33 entity FFTDriver is
34 generic (
35 pindex : integer := 0;
36 paddr : integer := 0;
37 pmask : integer := 16#fff#;
38 pirq : integer := 0;
39 abits : integer := 8;
40 LPP_DEVICE : integer;
41 Data_sz : integer := 16;
42 Addr_sz : integer := 8;
43 addr_max_int : integer := 256);
44 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 Rz : out std_logic;
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 );
59 end FFTDriver;
60
61 architecture ar_FFTDriver of FFTDriver is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 type DEVICE_ctrlr_Reg is record
70 DEVICE_Cfg : std_logic_vector(3 downto 0);
71 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
72 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
73 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
74 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
75 end record;
76
77 signal Rec : DEVICE_ctrlr_Reg;
78 signal Rdata : std_logic_vector(31 downto 0);
79
80 signal FlagWR : std_logic;
81 begin
82
83 Rz <= Rec.DEVICE_Cfg(0);
84 ReadEnable <= Rec.DEVICE_Cfg(1);
85 Rec.DEVICE_Cfg(2) <= FlagEmpty;
86 Rec.DEVICE_Cfg(3) <= FlagFull;
87
88 DataIn <= Rec.DEVICE_DataW;
89 Rec.DEVICE_DataR <= DataOut;
90 Rec.DEVICE_AddrW <= AddrIn;
91 Rec.DEVICE_AddrR <= AddrOut;
92
93
94
95 process(rst,clk)
96 begin
97 if(rst='0')then
98 Rec.DEVICE_DataW <= (others => '0');
99 Rec.DEVICE_Cfg(0) <= '0';
100 Rec.DEVICE_Cfg(1) <= '0';
101 FlagWR <= '0';
102
103 elsif(clk'event and clk='1')then
104
105 --APB Write OP
106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 FlagWR <= '1';
110 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
111 When "000010" =>
112 Rec.DEVICE_Cfg(0) <= apbi.pwdata(0);
113 Rec.DEVICE_Cfg(1) <= apbi.pwdata(4);
114 when others =>
115 null;
116 end case;
117 else
118 FlagWR <= '0';
119 end if;
120
121 --APB Read OP
122 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
123 case apbi.paddr(abits-1 downto 2) is
124 when "000000" =>
125 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
126 when "000001" =>
127 Rdata(31 downto 8) <= X"AAAAAA";
128 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
129 when "000101" =>
130 Rdata(31 downto 8) <= X"AAAAAA";
131 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
132 when "000010" =>
133 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
134 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
135 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
136 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
137 Rdata(31 downto 16) <= X"CCCC";
138 when others =>
139 Rdata <= (others => '0');
140 end case;
141 end if;
142
143 end if;
144 apbo.pconfig <= pconfig;
145 end process;
146
147 apbo.prdata <= Rdata when apbi.penable = '1';
148 WriteEnable <= FlagWR;
149
150 end ar_FFTDriver; No newline at end of file
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@@ -41,12 +41,16 entity APB_FFT is
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 43 abits : integer := 8;
44 Data_sz : integer := 16;
44 Data_sz : integer := 32;
45 45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 48 clk : in std_logic; --! Horloge du composant
49 49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
50 54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
51 55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 56 );
@@ -59,6 +63,10 signal ReadEnable : std_logic;
59 63 signal WriteEnable : std_logic;
60 64 signal FlagEmpty : std_logic;
61 65 signal FlagFull : std_logic;
66 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
67 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
68 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
69 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
62 70 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
63 71 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
64 72 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
@@ -67,18 +75,18 signal AddrOut : std_logic_vector(A
67 75 signal start : std_logic;
68 76 signal load : std_logic;
69 77 signal rdy : std_logic;
70 signal DummyIn : std_logic_vector(Data_sz-1 downto 0);
78 signal raz : std_logic;
71 79
72 80
73 81 begin
74 82
75 83 APB : ApbDriver
76 84 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
85 port map(clk,rst,raz,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
78 86
79 87
80 88 Extremum : Flag_Extremum
81 port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty);
89 port map(clk,raz,load,rdy,FlagFull,FlagEmpty);
82 90
83 91
84 92 DEVICE : CoreFFT
@@ -94,11 +102,22 begin
94 102 PTS => gPTS,
95 103 HALFPTS => gHALFPTS,
96 104 inBuf_RWDLY => gInBuf_RWDLY)
97 port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy);
105 port map(clk,start,raz,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
98 106
99 107 start <= not rst;
100 --FlagFull <= not load;
101 --FlagEmpty <= not rdy;
102 DummyIn <= (others => '0');
108
109 DataIn_re <= DataIn(31 downto 16);
110 DataIn_im <= DataIn(15 downto 0);
111 DataOut <= DataOut_re & DataOut_im;
112
113
114 full <= FlagFull;
115 empty <= FlagEmpty;
116 WR <= WriteEnable;
117 RE <= ReadEnable;
118 flg_load <= load;
119 flg_rdy <= rdy;
120 RZ <= raz;
121
103 122
104 123 end ar_APB_FFT; No newline at end of file
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@@ -29,8 +29,6 entity Flag_Extremum is
29 29 clk,raz : in std_logic;
30 30 load : in std_logic;
31 31 y_rdy : in std_logic;
32 d_valid_WR : in std_logic;
33 read_y_RE : in std_logic;
34 32 full : out std_logic;
35 33 empty : out std_logic
36 34 );
@@ -38,82 +36,80 end Flag_Extremum;
38 36
39 37 architecture ar_Flag_Extremum of Flag_Extremum is
40 38
41 type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3);
42 signal ect : etat;
39 --type etat is (eA,eB,eC,e0,e1,e2);
40 --signal ect : etat;
43 41
44 42 signal load_reg : std_logic;
45 43 signal y_rdy_reg : std_logic;
46 signal RE_reg : std_logic;
47 signal WR_reg : std_logic;
48 44
49 45 begin
50 46 process (clk,raz)
51 47 begin
52 48 if(raz='0')then
53 full <= '0';
49 full <= '1';
54 50 empty <= '1';
55 ect <= eA;
51 -- ect <= eA;
56 52
57 53 elsif(clk' event and clk='1')then
58 load_reg <= load;
59 y_rdy_reg <= y_rdy;
60 RE_reg <= read_y_RE;
61 WR_reg <= d_valid_WR;
54 -- load_reg <= load;
55 -- y_rdy_reg <= y_rdy;
62 56
63 case ect is
57 if(load='1' and y_rdy='0')then
58 full <= '0';
59 empty <= '1';
64 60
65 when eA =>
66 if(WR_reg='0' and d_valid_WR='1')then
61 elsif(y_rdy='1')then
62 full <= '1';
67 63 empty <= '0';
68 ect <= eB;
69 end if;
70 64
71 when eB =>
72 if(load_reg='1' and load='0')then
73 ect <= eC;
74 end if;
65 else
66 full <= '1';
67 empty <= '1';
75 68
76 when eC =>
77 if(load_reg='1' and load='0')then
78 full <= '1';
79 ect <= eD;
80 69 end if;
81 70
82 when eD =>
83 if(RE_reg='0' and read_y_RE='1')then
84 full <= '0';
85 ect <= eX;
86 end if;
71 -- case ect is
87 72
88 when eX =>
89 empty <= '1';
90 ect <= e0;
73 -- when eA =>
74 -- if(load_reg='0' and load='1')then
75 -- full <= '0';
76 -- ect <= eB;
77 -- end if;
78 --
79 -- when eB =>
80 -- if(load_reg='1' and load='0')then
81 -- ect <= eC;
82 -- end if;
83 --
84 -- when eC =>
85 -- if(load_reg='1' and load='0')then
86 -- full <= '1';
87 -- ect <= e0;
88 -- end if;
91 89
92 when e0 =>
93 if(WR_reg='0' and d_valid_WR='1')then
94 empty <= '0';
95 ect <= e1;
96 end if;
90 --===================================================================================
97 91
98 when e1 =>
99 if(load_reg='1' and load='0')then
100 full <= '1';
101 ect <= e2;
102 end if;
103
104 when e2 =>
105 if(RE_reg='0' and read_y_RE='1')then
106 full <= '0';
107 ect <= e3;
108 end if;
109
110 when e3 =>
111 if(y_rdy_reg='1' and y_rdy='0')then
112 empty <= '1';
113 ect <= e0;
114 end if;
115
116 end case;
92 -- when e0 =>
93 -- if(load_reg='0' and load='1')then
94 -- full <= '0';
95 -- ect <= e1;
96 -- end if;
97 --
98 -- when e1 =>
99 -- if(load_reg='1' and load='0')then
100 -- full <= '1';
101 -- empty <= '0';
102 -- ect <= e2;
103 -- end if;
104 --
105 -- when e2 =>
106 -- if(y_rdy_reg='1' and y_rdy='0')then
107 -- empty <= '1';
108 -- ect <= e0;
109 -- end if;
110 --
111 --
112 -- end case;
117 113 end if;
118 114 end process;
119 115
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@@ -41,14 +41,18 component APB_FFT is
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 43 abits : integer := 8;
44 Data_sz : integer := 16;
44 Data_sz : integer := 32;
45 45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 clk : in std_logic;
49 rst : in std_logic;
50 apbi : in apb_slv_in_type;
51 apbo : out apb_slv_out_type
48 clk : in std_logic; --! Horloge du composant
49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 56 );
53 57 end component;
54 58
@@ -58,8 +62,6 component Flag_Extremum is
58 62 clk,raz : in std_logic;
59 63 load : in std_logic;
60 64 y_rdy : in std_logic;
61 d_valid_WR : in std_logic;
62 read_y_RE : in std_logic;
63 65 full : out std_logic;
64 66 empty : out std_logic
65 67 );
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@@ -45,6 +45,7 entity ApbDriver is
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 RZ : out std_logic;
48 49 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
49 50 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 51 FlagEmpty : in std_logic; --! Flag, M�moire vide
@@ -69,7 +70,7 constant pconfig : apb_config_type := (
69 70 1 => apb_iobar(paddr, pmask));
70 71
71 72 type DEVICE_ctrlr_Reg is record
72 DEVICE_Cfg : std_logic_vector(3 downto 0);
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
73 74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
74 75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
75 76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
@@ -87,6 +88,7 Rec.DEVICE_Cfg(0) <= FlagRE;
87 88 Rec.DEVICE_Cfg(1) <= FlagWR;
88 89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
89 90 Rec.DEVICE_Cfg(3) <= FlagFull;
91 Rz <= Rec.DEVICE_Cfg(4);
90 92
91 93 DataIn <= Rec.DEVICE_DataW;
92 94 Rec.DEVICE_DataR <= DataOut;
@@ -99,6 +101,7 Rec.DEVICE_AddrR <= AddrOut;
99 101 begin
100 102 if(rst='0')then
101 103 Rec.DEVICE_DataW <= (others => '0');
104 Rec.DEVICE_Cfg(4) <= '0';
102 105 FlagWR <= '0';
103 106 FlagRE <= '0';
104 107
@@ -109,7 +112,9 Rec.DEVICE_AddrR <= AddrOut;
109 112 case apbi.paddr(abits-1 downto 2) is
110 113 when "000000" =>
111 114 FlagWR <= '1';
112 Rec.DEVICE_DataW <= apbi.pwdata(15 downto 0);
115 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
116 when "000010" =>
117 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
113 118 when others =>
114 119 null;
115 120 end case;
@@ -122,8 +127,7 Rec.DEVICE_AddrR <= AddrOut;
122 127 case apbi.paddr(abits-1 downto 2) is
123 128 when "000000" =>
124 129 FlagRE <= '1';
125 Rdata(31 downto 16) <= X"DDDD";
126 Rdata(15 downto 0) <= Rec.DEVICE_DataR;
130 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
127 131 when "000001" =>
128 132 Rdata(31 downto 8) <= X"AAAAAA";
129 133 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
@@ -135,7 +139,8 Rec.DEVICE_AddrR <= AddrOut;
135 139 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
136 140 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
137 141 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
138 Rdata(31 downto 16) <= X"CCCC";
142 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
143 Rdata(31 downto 20) <= X"CCC";
139 144 when others =>
140 145 Rdata <= (others => '0');
141 146 end case;
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@@ -69,6 +69,7 component ApbDriver is
69 69 port (
70 70 clk : in std_logic;
71 71 rst : in std_logic;
72 RZ : out std_logic;
72 73 ReadEnable : in std_logic;
73 74 WriteEnable : in std_logic;
74 75 FlagEmpty : in std_logic;
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