# HG changeset patch # User martin # Date 2011-04-06 08:04:29 # Node ID 9747167434f28a721afcaa4510a3cfe5dc4da124 # Parent 253be828d400bd2a78a1fcedcdee4a4efda79ff2 svg FFT okai diff --git a/lib/lpp/dsp/lpp_fft/APB_FFT.vhd b/lib/lpp/dsp/lpp_fft/APB_FFT.vhd --- a/lib/lpp/dsp/lpp_fft/APB_FFT.vhd +++ b/lib/lpp/dsp/lpp_fft/APB_FFT.vhd @@ -41,12 +41,16 @@ entity APB_FFT is pmask : integer := 16#fff#; pirq : integer := 0; abits : integer := 8; - Data_sz : integer := 16; + Data_sz : integer := 32; Addr_sz : integer := 8; addr_max_int : integer := 256); port ( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant + full,empty : out std_logic; + WR,RE : out std_logic; + flg_load,flg_rdy : out std_logic; + RZ : out std_logic; apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); @@ -55,31 +59,35 @@ end APB_FFT; architecture ar_APB_FFT of APB_FFT is -signal ReadEnable : std_logic; -signal WriteEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); +signal ReadEnable : std_logic; +signal WriteEnable : std_logic; +signal FlagEmpty : std_logic; +signal FlagFull : std_logic; +signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0); +signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0); +signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0); +signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0); +signal DataIn : std_logic_vector(Data_sz-1 downto 0); +signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); signal start : std_logic; signal load : std_logic; signal rdy : std_logic; -signal DummyIn : std_logic_vector(Data_sz-1 downto 0); +signal raz : std_logic; - + begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - + port map(clk,rst,raz,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + Extremum : Flag_Extremum - port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty); - + port map(clk,raz,load,rdy,FlagFull,FlagEmpty); + DEVICE : CoreFFT generic map( @@ -94,11 +102,22 @@ begin PTS => gPTS, HALFPTS => gHALFPTS, inBuf_RWDLY => gInBuf_RWDLY) - port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy); + port map(clk,start,raz,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy); + +start <= not rst; + +DataIn_re <= DataIn(31 downto 16); +DataIn_im <= DataIn(15 downto 0); +DataOut <= DataOut_re & DataOut_im; + -start <= not rst; ---FlagFull <= not load; ---FlagEmpty <= not rdy; -DummyIn <= (others => '0'); +full <= FlagFull; +empty <= FlagEmpty; +WR <= WriteEnable; +RE <= ReadEnable; +flg_load <= load; +flg_rdy <= rdy; +RZ <= raz; + end ar_APB_FFT; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/FFTDriver.vhd b/lib/lpp/dsp/lpp_fft/FFTDriver.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/lpp_fft/FFTDriver.vhd @@ -0,0 +1,150 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; + + +entity FFTDriver is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + LPP_DEVICE : integer; + Data_sz : integer := 16; + Addr_sz : integer := 8; + addr_max_int : integer := 256); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + Rz : out std_logic; + ReadEnable : out std_logic; --! Instruction de lecture en m�moire + WriteEnable : out std_logic; --! Instruction d'�criture en m�moire + FlagEmpty : in std_logic; --! Flag, M�moire vide + FlagFull : in std_logic; --! Flag, M�moire pleine + DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e + DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie + AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture) + AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end FFTDriver; + +architecture ar_FFTDriver of FFTDriver is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +type DEVICE_ctrlr_Reg is record + DEVICE_Cfg : std_logic_vector(3 downto 0); + DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); + DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); + DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); + DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); +end record; + +signal Rec : DEVICE_ctrlr_Reg; +signal Rdata : std_logic_vector(31 downto 0); + +signal FlagWR : std_logic; +begin + +Rz <= Rec.DEVICE_Cfg(0); +ReadEnable <= Rec.DEVICE_Cfg(1); +Rec.DEVICE_Cfg(2) <= FlagEmpty; +Rec.DEVICE_Cfg(3) <= FlagFull; + +DataIn <= Rec.DEVICE_DataW; +Rec.DEVICE_DataR <= DataOut; +Rec.DEVICE_AddrW <= AddrIn; +Rec.DEVICE_AddrR <= AddrOut; + + + + process(rst,clk) + begin + if(rst='0')then + Rec.DEVICE_DataW <= (others => '0'); + Rec.DEVICE_Cfg(0) <= '0'; + Rec.DEVICE_Cfg(1) <= '0'; + FlagWR <= '0'; + + elsif(clk'event and clk='1')then + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + FlagWR <= '1'; + Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); + When "000010" => + Rec.DEVICE_Cfg(0) <= apbi.pwdata(0); + Rec.DEVICE_Cfg(1) <= apbi.pwdata(4); + when others => + null; + end case; + else + FlagWR <= '0'; + end if; + + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; + when "000001" => + Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(7 downto 0) <= Rec.DEVICE_AddrR; + when "000101" => + Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(7 downto 0) <= Rec.DEVICE_AddrW; + when "000010" => + Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); + Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); + Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); + Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); + Rdata(31 downto 16) <= X"CCCC"; + when others => + Rdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +WriteEnable <= FlagWR; + +end ar_FFTDriver; \ No newline at end of file diff --git a/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd --- a/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd +++ b/lib/lpp/dsp/lpp_fft/Flag_Extremum.vhd @@ -29,8 +29,6 @@ entity Flag_Extremum is clk,raz : in std_logic; load : in std_logic; y_rdy : in std_logic; - d_valid_WR : in std_logic; - read_y_RE : in std_logic; full : out std_logic; empty : out std_logic ); @@ -38,82 +36,80 @@ end Flag_Extremum; architecture ar_Flag_Extremum of Flag_Extremum is -type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3); -signal ect : etat; +--type etat is (eA,eB,eC,e0,e1,e2); +--signal ect : etat; signal load_reg : std_logic; signal y_rdy_reg : std_logic; -signal RE_reg : std_logic; -signal WR_reg : std_logic; begin process (clk,raz) begin if(raz='0')then - full <= '0'; + full <= '1'; empty <= '1'; - ect <= eA; +-- ect <= eA; elsif(clk' event and clk='1')then - load_reg <= load; - y_rdy_reg <= y_rdy; - RE_reg <= read_y_RE; - WR_reg <= d_valid_WR; - - case ect is +-- load_reg <= load; +-- y_rdy_reg <= y_rdy; - when eA => - if(WR_reg='0' and d_valid_WR='1')then - empty <= '0'; - ect <= eB; - end if; - - when eB => - if(load_reg='1' and load='0')then - ect <= eC; - end if; - - when eC => - if(load_reg='1' and load='0')then - full <= '1'; - ect <= eD; - end if; + if(load='1' and y_rdy='0')then + full <= '0'; + empty <= '1'; + + elsif(y_rdy='1')then + full <= '1'; + empty <= '0'; + + else + full <= '1'; + empty <= '1'; + + end if; + +-- case ect is - when eD => - if(RE_reg='0' and read_y_RE='1')then - full <= '0'; - ect <= eX; - end if; - - when eX => - empty <= '1'; - ect <= e0; - - when e0 => - if(WR_reg='0' and d_valid_WR='1')then - empty <= '0'; - ect <= e1; - end if; - - when e1 => - if(load_reg='1' and load='0')then - full <= '1'; - ect <= e2; - end if; +-- when eA => +-- if(load_reg='0' and load='1')then +-- full <= '0'; +-- ect <= eB; +-- end if; +-- +-- when eB => +-- if(load_reg='1' and load='0')then +-- ect <= eC; +-- end if; +-- +-- when eC => +-- if(load_reg='1' and load='0')then +-- full <= '1'; +-- ect <= e0; +-- end if; + +--=================================================================================== - when e2 => - if(RE_reg='0' and read_y_RE='1')then - full <= '0'; - ect <= e3; - end if; - - when e3 => - if(y_rdy_reg='1' and y_rdy='0')then - empty <= '1'; - ect <= e0; - end if; - - end case; +-- when e0 => +-- if(load_reg='0' and load='1')then +-- full <= '0'; +-- ect <= e1; +-- end if; +-- +-- when e1 => +-- if(load_reg='1' and load='0')then +-- full <= '1'; +-- empty <= '0'; +-- ect <= e2; +-- end if; +-- +-- when e2 => +-- if(y_rdy_reg='1' and y_rdy='0')then +-- empty <= '1'; +-- ect <= e0; +-- end if; +-- +-- +-- end case; end if; end process; diff --git a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd --- a/lib/lpp/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/lpp/dsp/lpp_fft/lpp_fft.vhd @@ -40,15 +40,19 @@ component APB_FFT is paddr : integer := 0; pmask : integer := 16#fff#; pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; + abits : integer := 8; + Data_sz : integer := 32; + Addr_sz : integer := 8; addr_max_int : integer := 256); port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + full,empty : out std_logic; + WR,RE : out std_logic; + flg_load,flg_rdy : out std_logic; + RZ : out std_logic; + apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end component; @@ -58,8 +62,6 @@ component Flag_Extremum is clk,raz : in std_logic; load : in std_logic; y_rdy : in std_logic; - d_valid_WR : in std_logic; - read_y_RE : in std_logic; full : out std_logic; empty : out std_logic ); diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ b/lib/lpp/lpp_memory/ApbDriver.vhd @@ -45,6 +45,7 @@ entity ApbDriver is port ( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant + RZ : out std_logic; ReadEnable : out std_logic; --! Instruction de lecture en m�moire WriteEnable : out std_logic; --! Instruction d'�criture en m�moire FlagEmpty : in std_logic; --! Flag, M�moire vide @@ -69,7 +70,7 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(3 downto 0); + DEVICE_Cfg : std_logic_vector(4 downto 0); DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); @@ -87,6 +88,7 @@ Rec.DEVICE_Cfg(0) <= FlagRE; Rec.DEVICE_Cfg(1) <= FlagWR; Rec.DEVICE_Cfg(2) <= FlagEmpty; Rec.DEVICE_Cfg(3) <= FlagFull; +Rz <= Rec.DEVICE_Cfg(4); DataIn <= Rec.DEVICE_DataW; Rec.DEVICE_DataR <= DataOut; @@ -99,6 +101,7 @@ Rec.DEVICE_AddrR <= AddrOut; begin if(rst='0')then Rec.DEVICE_DataW <= (others => '0'); + Rec.DEVICE_Cfg(4) <= '0'; FlagWR <= '0'; FlagRE <= '0'; @@ -109,7 +112,9 @@ Rec.DEVICE_AddrR <= AddrOut; case apbi.paddr(abits-1 downto 2) is when "000000" => FlagWR <= '1'; - Rec.DEVICE_DataW <= apbi.pwdata(15 downto 0); + Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); + when "000010" => + Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); when others => null; end case; @@ -122,8 +127,7 @@ Rec.DEVICE_AddrR <= AddrOut; case apbi.paddr(abits-1 downto 2) is when "000000" => FlagRE <= '1'; - Rdata(31 downto 16) <= X"DDDD"; - Rdata(15 downto 0) <= Rec.DEVICE_DataR; + Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; when "000001" => Rdata(31 downto 8) <= X"AAAAAA"; Rdata(7 downto 0) <= Rec.DEVICE_AddrR; @@ -135,7 +139,8 @@ Rec.DEVICE_AddrR <= AddrOut; Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); - Rdata(31 downto 16) <= X"CCCC"; + Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); + Rdata(31 downto 20) <= X"CCC"; when others => Rdata <= (others => '0'); end case; diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -69,6 +69,7 @@ component ApbDriver is port ( clk : in std_logic; rst : in std_logic; + RZ : out std_logic; ReadEnable : in std_logic; WriteEnable : in std_logic; FlagEmpty : in std_logic;