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1
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
7
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 library grlib;
12 use grlib.amba.all;
13 use std.textio.all;
14
15
16 package apb_devices_list is
17
18
19 constant VENDOR_LPP : amba_vendor_type := 16#19#;
20
21 constant ROCKET_TM : amba_device_type := 16#1#;
22 constant otherCore : amba_device_type := 16#2#;
23 constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 constant LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 constant LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 constant LPP_UART : amba_device_type := 16#6#;
27 constant LPP_CNA : amba_device_type := 16#7#;
28 constant LPP_APB_ADC : amba_device_type := 16#8#;
29 constant LPP_CHENILLARD : amba_device_type := 16#9#;
30 constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 constant LPP_FIFO_PID : amba_device_type := 16#11#;
32 constant LPP_FFT : amba_device_type := 16#12#;
33 constant LPP_MATRIX : amba_device_type := 16#13#;
34 constant LPP_BALISE : amba_device_type := 16#14#;
35 constant LPP_USB : amba_device_type := 16#15#;
36 constant LPP_DELAY : amba_device_type := 16#16#;
37 constant LPP_DMA_TYPE : amba_device_type := 16#17#;
38 constant LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39
40
41 end;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5
6 LIBRARY lpp;
7 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.FILTERcfg.ALL;
10 USE lpp.lpp_memory.ALL;
11 LIBRARY techmap;
12 USE techmap.gencomp.ALL;
13
14 PACKAGE lpp_top_lfr_pkg IS
15
16 COMPONENT lpp_top_acq
17 GENERIC (
18 tech : integer);
19 PORT (
20 cnv_run : IN STD_LOGIC;
21 cnv : OUT STD_LOGIC;
22 sck : OUT STD_LOGIC;
23 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
24 cnv_clk : IN STD_LOGIC;
25 cnv_rstn : IN STD_LOGIC;
26 clk : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
37 END COMPONENT;
38
39 COMPONENT lpp_top_apbreg
40 GENERIC (
41 pindex : INTEGER;
42 paddr : INTEGER;
43 pmask : INTEGER;
44 pirq : INTEGER);
45 PORT (
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48 apbi : IN apb_slv_in_type;
49 apbo : OUT apb_slv_out_type;
50 ready_matrix_f0_0 : IN STD_LOGIC;
51 ready_matrix_f0_1 : IN STD_LOGIC;
52 ready_matrix_f1 : IN STD_LOGIC;
53 ready_matrix_f2 : IN STD_LOGIC;
54 error_anticipating_empty_fifo : IN STD_LOGIC;
55 error_bad_component_error : IN STD_LOGIC;
56 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 status_ready_matrix_f0_0 : OUT STD_LOGIC;
58 status_ready_matrix_f0_1 : OUT STD_LOGIC;
59 status_ready_matrix_f1 : OUT STD_LOGIC;
60 status_ready_matrix_f2 : OUT STD_LOGIC;
61 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
62 status_error_bad_component_error : OUT STD_LOGIC;
63 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
64 config_active_interruption_onError : OUT STD_LOGIC;
65 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
69 END COMPONENT;
70
71 END lpp_top_lfr_pkg; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 use ieee.numeric_std.all;
24 use ieee.numeric_std.all;
25 library grlib;
25 library grlib;
26 use grlib.amba.all;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
28 use grlib.devices.all;
29 library lpp;
29 library lpp;
30 use lpp.iir_filter.all;
30 use lpp.iir_filter.all;
31 use lpp.general_purpose.all;
31 use lpp.general_purpose.all;
32 use lpp.lpp_amba.all;
32 use lpp.lpp_amba.all;
33 use lpp.apb_devices_list.all;
33 use lpp.apb_devices_list.all;
34
34
35 entity APB_IIR_CEL is
35 entity APB_IIR_CEL is
36 generic (
36 generic (
37 tech : integer := 0;
37 tech : integer := 0;
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Sample_SZ : integer := 16;
43 Sample_SZ : integer := 16;
44 ChanelsCount : integer := 1;
44 ChanelsCount : integer := 1;
45 Coef_SZ : integer := 9;
45 Coef_SZ : integer := 9;
46 CoefCntPerCel: integer := 6;
46 CoefCntPerCel: integer := 6;
47 Cels_count : integer := 5;
47 Cels_count : integer := 5;
48 virgPos : integer := 3;
48 virgPos : integer := 3;
49 Mem_use : integer := use_RAM
49 Mem_use : integer := use_RAM
50 );
50 );
51 port (
51 port (
52 rst : in std_logic;
52 rst : in std_logic;
53 clk : in std_logic;
53 clk : in std_logic;
54 apbi : in apb_slv_in_type;
54 apbi : in apb_slv_in_type;
55 apbo : out apb_slv_out_type;
55 apbo : out apb_slv_out_type;
56 sample_clk : in std_logic;
56 sample_clk : in std_logic;
57 sample_clk_out : out std_logic;
57 sample_clk_out : out std_logic;
58 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
58 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
59 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
59 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
60 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
60 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
61 );
61 );
62 end;
62 end;
63
63
64
64
65 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
65 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
66
66
67 constant REVISION : integer := 1;
67 constant REVISION : integer := 1;
68
68
69 constant pconfig : apb_config_type := (
69 constant pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
70 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
71 1 => apb_iobar(paddr, pmask));
71 1 => apb_iobar(paddr, pmask));
72
72
73
73
74
74
75 type FILTERreg is record
75 type FILTERreg is record
76 regin : in_IIR_CEL_reg;
76 regin : in_IIR_CEL_reg;
77 regout : out_IIR_CEL_reg;
77 regout : out_IIR_CEL_reg;
78 end record;
78 end record;
79
79
80 signal Rdata : std_logic_vector(31 downto 0);
80 signal Rdata : std_logic_vector(31 downto 0);
81 signal r : FILTERreg;
81 signal r : FILTERreg;
82 signal filter_reset : std_logic:='0';
82 signal filter_reset : std_logic:='0';
83 signal smp_cnt : integer :=0;
83 signal smp_cnt : integer :=0;
84 signal sample_clk_out_R : std_logic;
84 signal sample_clk_out_R : std_logic;
85 signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
85 signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
86
86
87 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
87 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
88 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
88 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
89
89
90 type CoefsRegT is record
90 type CoefsRegT is record
91 numCoefs : CoefTblT;
91 numCoefs : CoefTblT;
92 denCoefs : CoefTblT;
92 denCoefs : CoefTblT;
93 end record;
93 end record;
94
94
95 signal CoefsReg : CoefsRegT;
95 signal CoefsReg : CoefsRegT;
96 signal CoefsReg_d : CoefsRegT;
96 signal CoefsReg_d : CoefsRegT;
97
97
98
98
99 begin
99 begin
100
100
101 filter_reset <= rst and r.regin.config(0);
101 filter_reset <= rst and r.regin.config(0);
102 sample_clk_out <= sample_clk_out_R;
102 sample_clk_out <= sample_clk_out_R;
103 --
103 --
104 filter : IIR_CEL_FILTER
104 filter : IIR_CEL_FILTER
105 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
105 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
106 port map(
106 port map(
107 reset => filter_reset,
107 reset => filter_reset,
108 clk => clk,
108 clk => clk,
109 sample_clk => sample_clk,
109 sample_clk => sample_clk,
110 regs_in => r.regin,
110 regs_in => r.regin,
111 regs_out => r.regout,
111 regs_out => r.regout,
112 sample_in => sample_in,
112 sample_in => sample_in,
113 sample_out => sample_out,
113 sample_out => sample_out,
114 coefs => RawCoefs
114 coefs => RawCoefs
115 );
115 );
116
116
117 process(rst,sample_clk)
117 process(rst,sample_clk)
118 begin
118 begin
119 if rst = '0' then
119 if rst = '0' then
120 smp_cnt <= 0;
120 smp_cnt <= 0;
121 sample_clk_out_R <= '0';
121 sample_clk_out_R <= '0';
122 elsif sample_clk'event and sample_clk = '1' then
122 elsif sample_clk'event and sample_clk = '1' then
123 if smp_cnt = 1 then
123 if smp_cnt = 1 then
124 smp_cnt <= 0;
124 smp_cnt <= 0;
125 sample_clk_out_R <= not sample_clk_out_R;
125 sample_clk_out_R <= not sample_clk_out_R;
126 else
126 else
127 smp_cnt <= smp_cnt +1;
127 smp_cnt <= smp_cnt +1;
128 end if;
128 end if;
129 end if;
129 end if;
130 end process;
130 end process;
131
131
132
132
133 coefsConnectL0: for z in 0 to Cels_count-1 generate
133 coefsConnectL0: for z in 0 to Cels_count-1 generate
134 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
134 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
135 RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
135 RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
136 RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
136 RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
137 end generate;
137 end generate;
138 end generate;
138 end generate;
139
139
140
140
141 process(rst,clk)
141 process(rst,clk)
142 begin
142 begin
143 if rst = '0' then
143 if rst = '0' then
144 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
144 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
145 coefsRstL0: for z in 0 to Cels_count-1 loop
145 coefsRstL0: for z in 0 to Cels_count-1 loop
146 coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
146 coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
147 CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
147 CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
148 CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
148 CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
149 end loop;
149 end loop;
150 end loop;
150 end loop;
151 elsif clk'event and clk = '1' then
151 elsif clk'event and clk = '1' then
152 CoefsReg_d <= CoefsReg;
152 CoefsReg_d <= CoefsReg;
153
153
154 --APB Write OP
154 --APB Write OP
155 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
155 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
156 if apbi.paddr(7 downto 2) = "000000" then
156 if apbi.paddr(7 downto 2) = "000000" then
157 r.regin.config(0) <= apbi.pwdata(0);
157 r.regin.config(0) <= apbi.pwdata(0);
158 elsif apbi.paddr(7 downto 2) = "000001" then
158 elsif apbi.paddr(7 downto 2) = "000001" then
159 r.regin.virgPos <= apbi.pwdata(4 downto 0);
159 r.regin.virgPos <= apbi.pwdata(4 downto 0);
160 else
160 else
161 for i in 0 to Cels_count-1 loop
161 for i in 0 to Cels_count-1 loop
162 for j in 0 to (CoefCntPerCel/2) - 1 loop
162 for j in 0 to (CoefCntPerCel/2) - 1 loop
163 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
163 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
164 CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0);
164 CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0);
165 CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16);
165 CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16);
166 end if;
166 end if;
167 end loop;
167 end loop;
168 end loop;
168 end loop;
169 end if;
169 end if;
170 end if;
170 end if;
171
171
172 --APB READ OP
172 --APB READ OP
173 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
173 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
174 if apbi.paddr(7 downto 2) = "000000" then
174 if apbi.paddr(7 downto 2) = "000000" then
175 Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
175 Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
176 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
176 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
177 Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
177 Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
178 Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8));
178 Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8));
179 elsif apbi.paddr(7 downto 2) = "000001" then
179 elsif apbi.paddr(7 downto 2) = "000001" then
180 Rdata(4 downto 0) <= r.regin.virgPos;
180 Rdata(4 downto 0) <= r.regin.virgPos;
181 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
181 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
182 Rdata(7 downto 5) <= (others => '0');
182 Rdata(7 downto 5) <= (others => '0');
183 Rdata(31 downto 16) <= (others => '0');
183 Rdata(31 downto 16) <= (others => '0');
184 else
184 else
185 for i in 0 to Cels_count-1 loop
185 for i in 0 to Cels_count-1 loop
186 for j in 0 to (CoefCntPerCel/2) - 1 loop
186 for j in 0 to (CoefCntPerCel/2) - 1 loop
187 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
187 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
188 Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j);
188 Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j);
189 Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j);
189 Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j);
190 end if;
190 end if;
191 end loop;
191 end loop;
192 end loop;
192 end loop;
193 end if;
193 end if;
194 end if;
194 end if;
195 end if;
195 end if;
196 apbo.pconfig <= pconfig;
196 apbo.pconfig <= pconfig;
197 end process;
197 end process;
198
198
199 apbo.prdata <= Rdata when apbi.penable = '1' ;
199 apbo.prdata <= Rdata when apbi.penable = '1' ;
200
200
201 -- pragma translate_off
201 -- pragma translate_off
202 bootmsg : report_version
202 bootmsg : report_version
203 generic map ("apb IIR filter" & tost(pindex) &
203 generic map ("apb IIR filter" & tost(pindex) &
204 ": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
204 ": IIR filter rev " & tost(REVISION)&
205 --", fifo " & tost(fifosize) &
205 ", irq " & tost(pirq));
206 ", irq " & tost(pirq));
206 -- pragma translate_on
207 -- pragma translate_on
207
208
208
209
209
210
210
211
211 end ar_APB_IIR_CEL;
212 end ar_APB_IIR_CEL;
212
213
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@@ -1,107 +1,107
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 library lpp;
26 use lpp.iir_filter.all;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
28 use lpp.general_purpose.all;
29 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
29 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs)
30 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
30 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s
31 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
31 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs
32
32
33 entity FILTER is
33 entity FILTER is
34 generic(Smpl_SZ : integer := 16;
34 generic(Smpl_SZ : integer := 16;
35 ChanelsCNT : integer := 3
35 ChanelsCNT : integer := 3
36 );
36 );
37 port(
37 port(
38
38
39 reset : in std_logic;
39 reset : in std_logic;
40 clk : in std_logic;
40 clk : in std_logic;
41 sample_clk : in std_logic;
41 sample_clk : in std_logic;
42 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
42 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
43 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
43 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
44 );
44 );
45 end entity;
45 end entity;
46
46
47
47
48
48
49
49
50
50
51 architecture ar_FILTER of FILTER is
51 architecture ar_FILTER of FILTER is
52
52
53
53
54
54
55
55
56 signal ALU_ctrl : std_logic_vector(3 downto 0);
56 signal ALU_ctrl : std_logic_vector(3 downto 0);
57 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
57 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0);
58 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
58 signal Coef : std_logic_vector(Coef_SZ-1 downto 0);
59 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
59 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0);
60
60
61 begin
61 begin
62
62
63 --==============================================================
63 --==============================================================
64 --=========================A L U================================
64 --=========================A L U================================
65 --==============================================================
65 --==============================================================
66 ALU1 : entity ALU
66 ALU1 : ALU
67 generic map(
67 generic map(
68 Arith_en => 1,
68 Arith_en => 1,
69 Logic_en => 0,
69 Logic_en => 0,
70 Input_SZ_1 => Smpl_SZ,
70 Input_SZ_1 => Smpl_SZ,
71 Input_SZ_2 => Coef_SZ
71 Input_SZ_2 => Coef_SZ
72
72
73 )
73 )
74 port map(
74 port map(
75 clk => clk,
75 clk => clk,
76 reset => reset,
76 reset => reset,
77 ctrl => ALU_ctrl,
77 ctrl => ALU_ctrl,
78 OP1 => Sample,
78 OP1 => Sample,
79 OP2 => Coef,
79 OP2 => Coef,
80 RES => ALU_OUT
80 RES => ALU_OUT
81 );
81 );
82 --==============================================================
82 --==============================================================
83
83
84 --==============================================================
84 --==============================================================
85 --===============F I L T E R C O N T R O L E R================
85 --===============F I L T E R C O N T R O L E R================
86 --==============================================================
86 --==============================================================
87 filterctrlr1 : FilterCTRLR
87 filterctrlr1 : FilterCTRLR
88 port map(
88 port map(
89 reset => reset,
89 reset => reset,
90 clk => clk,
90 clk => clk,
91 sample_clk => sample_clk,
91 sample_clk => sample_clk,
92 ALU_Ctrl => ALU_ctrl,
92 ALU_Ctrl => ALU_ctrl,
93 sample_in => sample_Tbl,
93 sample_in => sample_Tbl,
94 coef => Coef,
94 coef => Coef,
95 sample => Sample
95 sample => Sample
96 );
96 );
97 --==============================================================
97 --==============================================================
98
98
99 chanelCut : for i in 0 to ChanelsCNT-1 generate
99 chanelCut : for i in 0 to ChanelsCNT-1 generate
100 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
100 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ);
101 end generate;
101 end generate;
102
102
103
103
104
104
105
105
106 end ar_FILTER;
106 end ar_FILTER;
107
107
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@@ -1,114 +1,197
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 -- MODIFIED by Jean-christophe PELLION
23 use IEEE.STD_LOGIC_1164.ALL;
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 library lpp;
24 -------------------------------------------------------------------------------
25 use lpp.lpp_ad_conv.all;
25 LIBRARY IEEE;
26 use lpp.general_purpose.Clk_divider;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
27
30
28 --! \brief AD7688 driver, generates all needed signal to drive this ADC.
31 ENTITY AD7688_drvr IS
29 --!
32 GENERIC(
30 --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
36 PORT (
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
31
42
32 entity AD7688_drvr is
43 -- DATA --
33 generic(
44 clk : IN STD_LOGIC;
34 ChanelCount :integer; --! Number of ADC you whant to drive
45 rstn : IN STD_LOGIC;
35 clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width.
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
36 );
51 );
37 Port(
52 END AD7688_drvr;
38 clk : in STD_LOGIC; --! System clock
53
39 rstn : in STD_LOGIC; --! System reset
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
40 enable : in std_logic; --! Negative enable
41 smplClk : in STD_LOGIC; --! Sampling clock
42 DataReady : out std_logic; --! New sample available
43 smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples
44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
45 AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv
46 );
47 end AD7688_drvr;
48
55
49 architecture ar_AD7688_drvr of AD7688_drvr is
56 COMPONENT SYNC_FF
50
57 GENERIC (
51 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
52
65
53 signal i : integer range 0 to convTrigger :=0;
66
54 signal clk_int : std_logic;
67 SIGNAL cnv_cycle_counter : INTEGER;
55 signal clk_int_inv : std_logic;
68 SIGNAL cnv_s : STD_LOGIC;
56 signal smplClk_reg : std_logic;
69 SIGNAL cnv_sync : STD_LOGIC;
57 signal cnv_int : std_logic;
70 SIGNAL cnv_sync_r : STD_LOGIC;
58 signal reset : std_logic;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
74
75 SIGNAL cnv_run_sync : STD_LOGIC;
59
76
60 begin
77 BEGIN
61
78 -----------------------------------------------------------------------------
62 clkdiv: if clkkHz>=66000 generate
79 -- CONV
63 clkdivider: entity work.Clk_divider
80 -----------------------------------------------------------------------------
64 generic map(clkkHz*1000,60000000)
81 PROCESS (cnv_clk, cnv_rstn)
65 Port map( clk ,reset,clk_int);
82 BEGIN -- PROCESS
66 end generate;
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
92 ELSE
93 cnv_s <= '0';
94 END IF;
95 ELSE
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
98 END IF;
99 ELSE
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
102 END IF;
103 END IF;
104 END PROCESS;
67
105
68 clknodiv: if clkkHz<66000 generate
106 cnv <= cnv_s;
69 nodiv: clk_int <= clk;
70 end generate;
71
107
72 clk_int_inv <= not clk_int;
108 -----------------------------------------------------------------------------
73
109
74 AD_out.CNV <= cnv_int;
75 AD_out.SCK <= clk_int;
76 reset <= rstn and enable;
77
110
78 sckgen: process(clk,reset)
111 -----------------------------------------------------------------------------
79 begin
112 -- SYNC CNV
80 if reset = '0' then
113 -----------------------------------------------------------------------------
81 i <= 0;
114
82 cnv_int <= '0';
115 SYNC_FF_cnv : SYNC_FF
83 smplClk_reg <= '0';
116 GENERIC MAP (
84 elsif clk'event and clk = '1' then
117 NB_FF_OF_SYNC => 2)
85 if smplClk = '1' and smplClk_reg = '0' then
118 PORT MAP (
86 if i = convTrigger then
119 clk => clk,
87 smplClk_reg <= '1';
120 rstn => rstn,
88 i <= 0;
121 A => cnv_s,
89 cnv_int <= '0';
122 A_sync => cnv_sync);
90 else
123
91 i <= i+1;
124 PROCESS (clk, rstn)
92 cnv_int <= '1';
125 BEGIN
93 end if;
126 IF rstn = '0' THEN
94 elsif smplClk = '0' and smplClk_reg = '1' then
127 cnv_sync_r <= '0';
95 smplClk_reg <= '0';
128 cnv_done <= '0';
96 end if;
129 ELSIF clk'EVENT AND clk = '1' THEN
97 end if;
130 cnv_sync_r <= cnv_sync;
98 end process;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
133 END PROCESS;
134
135 -----------------------------------------------------------------------------
136
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
141 clk => clk,
142 rstn => rstn,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
99
145
100
146
101
147
102 spidrvr: entity work.AD7688_spi_if
148 -----------------------------------------------------------------------------
103 generic map(ChanelCount)
149 -- DATA
104 Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout);
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
105
161
106
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
107
169
108 end ar_AD7688_drvr;
170 IF (sample_bit_counter MOD 2) = 1 THEN
109
171 FOR l IN 0 TO ChanelCount-1 LOOP
110
172 --shift_reg(l)(15) <= sdo(l);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
176 END LOOP;
177 SCK <= '0';
178 ELSE
179 SCK <= '1';
180 END IF;
111
181
112
182 IF sample_bit_counter = 31 THEN
183 sample_val <= '1';
184 FOR l IN 0 TO ChanelCount-1 LOOP
185 --sample(l)(15) <= sdo(l);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
189 END LOOP;
190 ELSE
191 sample_val <= '0';
192 END IF;
193 END IF;
194 END PROCESS;
113
195
196 END ar_AD7688_drvr;
114
197
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@@ -1,191 +1,191
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29
29
30
30
31 PACKAGE lpp_ad_conv IS
31 PACKAGE lpp_ad_conv IS
32
32
33
33
34 --CONSTANT AD7688 : INTEGER := 0;
34 --CONSTANT AD7688 : INTEGER := 0;
35 --CONSTANT ADS7886 : INTEGER := 1;
35 --CONSTANT ADS7886 : INTEGER := 1;
36
36
37
37
38 --TYPE AD7688_out IS
38 --TYPE AD7688_out IS
39 --RECORD
39 --RECORD
40 -- CNV : STD_LOGIC;
40 -- CNV : STD_LOGIC;
41 -- SCK : STD_LOGIC;
41 -- SCK : STD_LOGIC;
42 --END RECORD;
42 --END RECORD;
43
43
44 --TYPE AD7688_in_element IS
44 --TYPE AD7688_in_element IS
45 --RECORD
45 --RECORD
46 -- SDI : STD_LOGIC;
46 -- SDI : STD_LOGIC;
47 --END RECORD;
47 --END RECORD;
48
48
49 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
49 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
50
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52
52
53 COMPONENT ADS7886_drvr
53 COMPONENT AD7688_drvr
54 GENERIC (
54 GENERIC (
55 ChanelCount : INTEGER;
55 ChanelCount : INTEGER;
56 ncycle_cnv_high : INTEGER := 79;
56 ncycle_cnv_high : INTEGER := 79;
57 ncycle_cnv : INTEGER := 500);
57 ncycle_cnv : INTEGER := 500);
58 PORT (
58 PORT (
59 cnv_clk : IN STD_LOGIC;
59 cnv_clk : IN STD_LOGIC;
60 cnv_rstn : IN STD_LOGIC;
60 cnv_rstn : IN STD_LOGIC;
61 cnv_run : IN STD_LOGIC;
61 cnv_run : IN STD_LOGIC;
62 cnv : OUT STD_LOGIC;
62 cnv : OUT STD_LOGIC;
63 clk : IN STD_LOGIC;
63 clk : IN STD_LOGIC;
64 rstn : IN STD_LOGIC;
64 rstn : IN STD_LOGIC;
65 sck : OUT STD_LOGIC;
65 sck : OUT STD_LOGIC;
66 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
66 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
67 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
67 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
68 sample_val : OUT STD_LOGIC);
68 sample_val : OUT STD_LOGIC);
69 END COMPONENT;
69 END COMPONENT;
70
70
71 --COMPONENT AD7688_drvr IS
71 --COMPONENT AD7688_drvr IS
72 -- GENERIC(ChanelCount : INTEGER;
72 -- GENERIC(ChanelCount : INTEGER;
73 -- clkkHz : INTEGER);
73 -- clkkHz : INTEGER);
74 -- PORT (clk : IN STD_LOGIC;
74 -- PORT (clk : IN STD_LOGIC;
75 -- rstn : IN STD_LOGIC;
75 -- rstn : IN STD_LOGIC;
76 -- enable : IN STD_LOGIC;
76 -- enable : IN STD_LOGIC;
77 -- smplClk : IN STD_LOGIC;
77 -- smplClk : IN STD_LOGIC;
78 -- DataReady : OUT STD_LOGIC;
78 -- DataReady : OUT STD_LOGIC;
79 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
79 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
80 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
80 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
81 -- AD_out : OUT AD7688_out);
81 -- AD_out : OUT AD7688_out);
82 --END COMPONENT;
82 --END COMPONENT;
83
83
84
84
85 --COMPONENT AD7688_spi_if IS
85 --COMPONENT AD7688_spi_if IS
86 -- GENERIC(ChanelCount : INTEGER);
86 -- GENERIC(ChanelCount : INTEGER);
87 -- PORT(clk : IN STD_LOGIC;
87 -- PORT(clk : IN STD_LOGIC;
88 -- reset : IN STD_LOGIC;
88 -- reset : IN STD_LOGIC;
89 -- cnv : IN STD_LOGIC;
89 -- cnv : IN STD_LOGIC;
90 -- DataReady : OUT STD_LOGIC;
90 -- DataReady : OUT STD_LOGIC;
91 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
91 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
92 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
92 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
93 -- );
93 -- );
94 --END COMPONENT;
94 --END COMPONENT;
95
95
96
96
97 --COMPONENT lpp_apb_ad_conv
97 --COMPONENT lpp_apb_ad_conv
98 -- GENERIC(
98 -- GENERIC(
99 -- pindex : INTEGER := 0;
99 -- pindex : INTEGER := 0;
100 -- paddr : INTEGER := 0;
100 -- paddr : INTEGER := 0;
101 -- pmask : INTEGER := 16#fff#;
101 -- pmask : INTEGER := 16#fff#;
102 -- pirq : INTEGER := 0;
102 -- pirq : INTEGER := 0;
103 -- abits : INTEGER := 8;
103 -- abits : INTEGER := 8;
104 -- ChanelCount : INTEGER := 1;
104 -- ChanelCount : INTEGER := 1;
105 -- clkkHz : INTEGER := 50000;
105 -- clkkHz : INTEGER := 50000;
106 -- smpClkHz : INTEGER := 100;
106 -- smpClkHz : INTEGER := 100;
107 -- ADCref : INTEGER := AD7688);
107 -- ADCref : INTEGER := AD7688);
108 -- PORT (
108 -- PORT (
109 -- clk : IN STD_LOGIC;
109 -- clk : IN STD_LOGIC;
110 -- reset : IN STD_LOGIC;
110 -- reset : IN STD_LOGIC;
111 -- apbi : IN apb_slv_in_type;
111 -- apbi : IN apb_slv_in_type;
112 -- apbo : OUT apb_slv_out_type;
112 -- apbo : OUT apb_slv_out_type;
113 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
113 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
114 -- AD_out : OUT AD7688_out);
114 -- AD_out : OUT AD7688_out);
115 --END COMPONENT;
115 --END COMPONENT;
116
116
117 --COMPONENT ADS7886_drvr IS
117 --COMPONENT ADS7886_drvr IS
118 -- GENERIC(ChanelCount : INTEGER;
118 -- GENERIC(ChanelCount : INTEGER;
119 -- clkkHz : INTEGER);
119 -- clkkHz : INTEGER);
120 -- PORT (
120 -- PORT (
121 -- clk : IN STD_LOGIC;
121 -- clk : IN STD_LOGIC;
122 -- reset : IN STD_LOGIC;
122 -- reset : IN STD_LOGIC;
123 -- smplClk : IN STD_LOGIC;
123 -- smplClk : IN STD_LOGIC;
124 -- DataReady : OUT STD_LOGIC;
124 -- DataReady : OUT STD_LOGIC;
125 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
125 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
126 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
126 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
127 -- AD_out : OUT AD7688_out
127 -- AD_out : OUT AD7688_out
128 -- );
128 -- );
129 --END COMPONENT;
129 --END COMPONENT;
130
130
131 --COMPONENT WriteGen_ADC IS
131 --COMPONENT WriteGen_ADC IS
132 -- PORT(
132 -- PORT(
133 -- clk : IN STD_LOGIC;
133 -- clk : IN STD_LOGIC;
134 -- rstn : IN STD_LOGIC;
134 -- rstn : IN STD_LOGIC;
135 -- SmplCLK : IN STD_LOGIC;
135 -- SmplCLK : IN STD_LOGIC;
136 -- DataReady : IN STD_LOGIC;
136 -- DataReady : IN STD_LOGIC;
137 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
137 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
138 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
138 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
139 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
139 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
140 -- );
140 -- );
141 --END COMPONENT;
141 --END COMPONENT;
142
142
143
143
144 --===========================================================|
144 --===========================================================|
145 --======================= ADS 127X =========================|
145 --======================= ADS 127X =========================|
146 --===========================================================|
146 --===========================================================|
147
147
148 Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic;
148 Type ADS127X_FORMAT_Type is array(2 downto 0) of std_logic;
149 constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
149 constant ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
150 constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
150 constant ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
151
151
152 Type ADS127X_MODE_Type is array(1 downto 0) of std_logic;
152 Type ADS127X_MODE_Type is array(1 downto 0) of std_logic;
153 constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
153 constant ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
154 constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
154 constant ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
155 constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
155 constant ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
156
156
157 Type ADS127X_config is
157 Type ADS127X_config is
158 record
158 record
159 SYNC : std_logic;
159 SYNC : std_logic;
160 CLKDIV : std_logic;
160 CLKDIV : std_logic;
161 FORMAT : ADS127X_FORMAT_Type;
161 FORMAT : ADS127X_FORMAT_Type;
162 MODE : ADS127X_MODE_Type;
162 MODE : ADS127X_MODE_Type;
163 end record;
163 end record;
164
164
165 COMPONENT ADS1274_DRIVER is
165 COMPONENT ADS1274_DRIVER is
166 generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
166 generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
167 port(
167 port(
168 Clk : in std_logic;
168 Clk : in std_logic;
169 reset : in std_logic;
169 reset : in std_logic;
170 SpiClk : out std_logic;
170 SpiClk : out std_logic;
171 DIN : in std_logic_vector(3 downto 0);
171 DIN : in std_logic_vector(3 downto 0);
172 Ready : in std_logic;
172 Ready : in std_logic;
173 Format : out std_logic_vector(2 downto 0);
173 Format : out std_logic_vector(2 downto 0);
174 Mode : out std_logic_vector(1 downto 0);
174 Mode : out std_logic_vector(1 downto 0);
175 ClkDiv : out std_logic;
175 ClkDiv : out std_logic;
176 PWDOWN : out std_logic_vector(3 downto 0);
176 PWDOWN : out std_logic_vector(3 downto 0);
177 SmplClk : in std_logic;
177 SmplClk : in std_logic;
178 OUT0 : out std_logic_vector(23 downto 0);
178 OUT0 : out std_logic_vector(23 downto 0);
179 OUT1 : out std_logic_vector(23 downto 0);
179 OUT1 : out std_logic_vector(23 downto 0);
180 OUT2 : out std_logic_vector(23 downto 0);
180 OUT2 : out std_logic_vector(23 downto 0);
181 OUT3 : out std_logic_vector(23 downto 0);
181 OUT3 : out std_logic_vector(23 downto 0);
182 FSynch : out std_logic;
182 FSynch : out std_logic;
183 test : out std_logic
183 test : out std_logic
184 );
184 );
185 end COMPONENT;
185 end COMPONENT;
186
186
187
187
188
188
189 END lpp_ad_conv;
189 END lpp_ad_conv;
190
190
191
191
Show file before | Show file after | Hide comments
@@ -1,8 +1,7
1 fifo_latency_correction.vhd
1 fifo_latency_correction.vhd
2 lpp_dma.vhd
2 lpp_dma.vhd
3 lpp_dma_apbreg.vhd
3 lpp_dma_apbreg.vhd
4 lpp_dma_fsm.vhd
5 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
6 lpp_dma_pkg.vhd
5 lpp_dma_pkg.vhd
7 lpp_dma_send_16word.vhd
6 lpp_dma_send_16word.vhd
8 lpp_dma_send_1word.vhd
7 lpp_dma_send_1word.vhd
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