# HG changeset patch
# User pellion
# Date 2013-04-23 10:52:54
# Node ID 941888d85bdafa54909c743af17ec227b85b692c
# Parent  6e4fef3f3bb079cee3912bcae48552b9780868da

temp

diff --git a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd
--- a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd
+++ b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd
@@ -1,212 +1,213 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
--------------------------------------------------------------------------------
---                    Author : Alexis Jeandet
---                     Mail : alexis.jeandet@lpp.polytechnique.fr
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library grlib;
-use grlib.amba.all;
-use grlib.stdlib.all;
-use grlib.devices.all;
-library lpp;
-use lpp.iir_filter.all;
-use lpp.general_purpose.all;
-use lpp.lpp_amba.all;
-use lpp.apb_devices_list.all;
-
-entity APB_IIR_CEL is
-  generic (
-    tech : integer := 0;
-    pindex   : integer  := 0;
-    paddr    : integer  := 0;
-    pmask    : integer  := 16#fff#;
-    pirq     : integer  := 0;
-    abits    : integer  := 8;
-    Sample_SZ : integer := 16;
-    ChanelsCount : integer := 1;
-    Coef_SZ      : integer := 9;
-    CoefCntPerCel: integer := 6;
-    Cels_count   : integer := 5;
-    virgPos      : integer := 3;
-    Mem_use      : integer := use_RAM
-    );
-  port (
-    rst             : in  std_logic;
-    clk             : in  std_logic;
-    apbi            : in  apb_slv_in_type;
-    apbo            : out apb_slv_out_type;
-    sample_clk      : in  std_logic;
-    sample_clk_out  : out std_logic;
-    sample_in   :   in  samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    sample_out  :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
-    CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
-    );
-end;
-
-
-architecture AR_APB_IIR_CEL of APB_IIR_CEL is 
-
-constant REVISION : integer := 1;
-
-constant pconfig : apb_config_type := (
-  0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
-  1 => apb_iobar(paddr, pmask));
-
-
-
-type FILTERreg is record
-  regin     :   in_IIR_CEL_reg;
-  regout    :   out_IIR_CEL_reg;
-end record;
-
-signal Rdata	  :  std_logic_vector(31 downto 0);
-signal  r : FILTERreg;
-signal  filter_reset    :   std_logic:='0';
-signal  smp_cnt : integer :=0;
-signal  sample_clk_out_R : std_logic;
-signal  RawCoefs       :     std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
-
-type    CoefCelT  is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
-type    CoefTblT  is array(0 to Cels_count-1) of CoefCelT;
-
-type    CoefsRegT is record
-        numCoefs    : CoefTblT;
-        denCoefs    : CoefTblT;
-end record;
-
-signal  CoefsReg   : CoefsRegT;
-signal  CoefsReg_d   : CoefsRegT;
-
-
-begin
-
-filter_reset    <=  rst and r.regin.config(0);
-sample_clk_out  <=  sample_clk_out_R;
---
-filter : IIR_CEL_FILTER
-generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
-port map(
-    reset       =>  filter_reset,
-    clk         =>  clk,
-    sample_clk  =>  sample_clk,
-    regs_in     =>  r.regin,
-    regs_out    =>  r.regout,
-    sample_in   =>  sample_in,
-    sample_out  =>  sample_out,
-    coefs       =>  RawCoefs
-    );
-
-process(rst,sample_clk)
-begin
-if rst = '0' then
-    smp_cnt <= 0;
-    sample_clk_out_R <= '0';
-elsif sample_clk'event and sample_clk = '1' then
-  if smp_cnt = 1 then
-    smp_cnt <= 0;
-    sample_clk_out_R <= not sample_clk_out_R;
-  else
-    smp_cnt <= smp_cnt +1;
-  end if;
-end if;
-end process;
-
-
-coefsConnectL0: for z in 0 to Cels_count-1 generate
-     coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
-		          RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) )     <=   CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
-		          RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ))   <=   CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
-     end generate;
-end generate;
-
-
-process(rst,clk)
-begin
-    if rst = '0' then
-        r.regin.virgPos          <= std_logic_vector(to_unsigned(virgPos,5));
-coefsRstL0: for z in 0 to Cels_count-1 loop
-     coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
-                     CoefsReg.numCoefs(z)(y)  <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
-                     CoefsReg.denCoefs(z)(y)  <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
-     end loop;
-end loop;
-    elsif clk'event and clk = '1' then
-    CoefsReg_d <=     CoefsReg;
-
---APB Write OP
-        if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
-           if apbi.paddr(7 downto 2) =  "000000" then
-              r.regin.config(0) <= apbi.pwdata(0);
-           elsif apbi.paddr(7 downto 2) =  "000001" then
-                 r.regin.virgPos <= apbi.pwdata(4 downto 0);
-           else
-               for i in 0 to Cels_count-1 loop
-                   for j in 0 to (CoefCntPerCel/2) - 1  loop
-                       if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
-                           CoefsReg.numCoefs(i)(j)        <=  apbi.pwdata(Coef_SZ-1 downto 0);
-                           CoefsReg.denCoefs(i)(j)        <=  apbi.pwdata((Coef_SZ+15) downto 16);
-                       end if;
-                   end loop;
-               end loop;
-           end if;
-        end if;
-
---APB READ OP
-        if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
-           if apbi.paddr(7 downto 2) =  "000000" then
-               Rdata(7 downto 0)   <=   std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
-               Rdata(15 downto 8)  <=   std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
-               Rdata(23 downto 16) <=   std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
-               Rdata(31 downto 24) <=   std_logic_vector(TO_UNSIGNED(Cels_count,8));
-           elsif apbi.paddr(7 downto 2) =  "000001" then
-               Rdata(4 downto 0)   <=   r.regin.virgPos;
-               Rdata(15 downto 8)  <=   std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
-               Rdata(7 downto 5)   <=   (others => '0');
-               Rdata(31 downto 16) <=   (others => '0');
-           else
-               for i in 0 to Cels_count-1 loop
-                    for j in 0 to (CoefCntPerCel/2) - 1  loop
-                        if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
-                           Rdata(Coef_SZ-1 downto 0)      <= CoefsReg_d.numCoefs(i)(j);
-                           Rdata((Coef_SZ+15) downto 16)  <= CoefsReg_d.denCoefs(i)(j);
-                        end if;
-                    end loop;
-                  end loop;
-           end if;
-        end if;
-    end if;
-    apbo.pconfig <= pconfig;
-end process;
-
-apbo.prdata <=	Rdata when apbi.penable = '1' ;
-
--- pragma translate_off
-    bootmsg : report_version
-    generic map ("apb IIR filter" & tost(pindex) &
-	": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
-	", irq " & tost(pirq));
--- pragma translate_on
-
-
-
-
-end ar_APB_IIR_CEL;
-
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Alexis Jeandet
+--                     Mail : alexis.jeandet@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library grlib;
+use grlib.amba.all;
+use grlib.stdlib.all;
+use grlib.devices.all;
+library lpp;
+use lpp.iir_filter.all;
+use lpp.general_purpose.all;
+use lpp.lpp_amba.all;
+use lpp.apb_devices_list.all;
+
+entity APB_IIR_CEL is
+  generic (
+    tech : integer := 0;
+    pindex   : integer  := 0;
+    paddr    : integer  := 0;
+    pmask    : integer  := 16#fff#;
+    pirq     : integer  := 0;
+    abits    : integer  := 8;
+    Sample_SZ : integer := 16;
+    ChanelsCount : integer := 1;
+    Coef_SZ      : integer := 9;
+    CoefCntPerCel: integer := 6;
+    Cels_count   : integer := 5;
+    virgPos      : integer := 3;
+    Mem_use      : integer := use_RAM
+    );
+  port (
+    rst             : in  std_logic;
+    clk             : in  std_logic;
+    apbi            : in  apb_slv_in_type;
+    apbo            : out apb_slv_out_type;
+    sample_clk      : in  std_logic;
+    sample_clk_out  : out std_logic;
+    sample_in   :   in  samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
+    sample_out  :   out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
+    CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
+    );
+end;
+
+
+architecture AR_APB_IIR_CEL of APB_IIR_CEL is 
+
+constant REVISION : integer := 1;
+
+constant pconfig : apb_config_type := (
+  0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
+  1 => apb_iobar(paddr, pmask));
+
+
+
+type FILTERreg is record
+  regin     :   in_IIR_CEL_reg;
+  regout    :   out_IIR_CEL_reg;
+end record;
+
+signal Rdata	  :  std_logic_vector(31 downto 0);
+signal  r : FILTERreg;
+signal  filter_reset    :   std_logic:='0';
+signal  smp_cnt : integer :=0;
+signal  sample_clk_out_R : std_logic;
+signal  RawCoefs       :     std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
+
+type    CoefCelT  is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
+type    CoefTblT  is array(0 to Cels_count-1) of CoefCelT;
+
+type    CoefsRegT is record
+        numCoefs    : CoefTblT;
+        denCoefs    : CoefTblT;
+end record;
+
+signal  CoefsReg   : CoefsRegT;
+signal  CoefsReg_d   : CoefsRegT;
+
+
+begin
+
+filter_reset    <=  rst and r.regin.config(0);
+sample_clk_out  <=  sample_clk_out_R;
+--
+filter : IIR_CEL_FILTER
+generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
+port map(
+    reset       =>  filter_reset,
+    clk         =>  clk,
+    sample_clk  =>  sample_clk,
+    regs_in     =>  r.regin,
+    regs_out    =>  r.regout,
+    sample_in   =>  sample_in,
+    sample_out  =>  sample_out,
+    coefs       =>  RawCoefs
+    );
+
+process(rst,sample_clk)
+begin
+if rst = '0' then
+    smp_cnt <= 0;
+    sample_clk_out_R <= '0';
+elsif sample_clk'event and sample_clk = '1' then
+  if smp_cnt = 1 then
+    smp_cnt <= 0;
+    sample_clk_out_R <= not sample_clk_out_R;
+  else
+    smp_cnt <= smp_cnt +1;
+  end if;
+end if;
+end process;
+
+
+coefsConnectL0: for z in 0 to Cels_count-1 generate
+     coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
+		          RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) )     <=   CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
+		          RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ))   <=   CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
+     end generate;
+end generate;
+
+
+process(rst,clk)
+begin
+    if rst = '0' then
+        r.regin.virgPos          <= std_logic_vector(to_unsigned(virgPos,5));
+coefsRstL0: for z in 0 to Cels_count-1 loop
+     coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
+                     CoefsReg.numCoefs(z)(y)  <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
+                     CoefsReg.denCoefs(z)(y)  <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
+     end loop;
+end loop;
+    elsif clk'event and clk = '1' then
+    CoefsReg_d <=     CoefsReg;
+
+--APB Write OP
+        if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
+           if apbi.paddr(7 downto 2) =  "000000" then
+              r.regin.config(0) <= apbi.pwdata(0);
+           elsif apbi.paddr(7 downto 2) =  "000001" then
+                 r.regin.virgPos <= apbi.pwdata(4 downto 0);
+           else
+               for i in 0 to Cels_count-1 loop
+                   for j in 0 to (CoefCntPerCel/2) - 1  loop
+                       if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
+                           CoefsReg.numCoefs(i)(j)        <=  apbi.pwdata(Coef_SZ-1 downto 0);
+                           CoefsReg.denCoefs(i)(j)        <=  apbi.pwdata((Coef_SZ+15) downto 16);
+                       end if;
+                   end loop;
+               end loop;
+           end if;
+        end if;
+
+--APB READ OP
+        if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
+           if apbi.paddr(7 downto 2) =  "000000" then
+               Rdata(7 downto 0)   <=   std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
+               Rdata(15 downto 8)  <=   std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
+               Rdata(23 downto 16) <=   std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
+               Rdata(31 downto 24) <=   std_logic_vector(TO_UNSIGNED(Cels_count,8));
+           elsif apbi.paddr(7 downto 2) =  "000001" then
+               Rdata(4 downto 0)   <=   r.regin.virgPos;
+               Rdata(15 downto 8)  <=   std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
+               Rdata(7 downto 5)   <=   (others => '0');
+               Rdata(31 downto 16) <=   (others => '0');
+           else
+               for i in 0 to Cels_count-1 loop
+                    for j in 0 to (CoefCntPerCel/2) - 1  loop
+                        if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
+                           Rdata(Coef_SZ-1 downto 0)      <= CoefsReg_d.numCoefs(i)(j);
+                           Rdata((Coef_SZ+15) downto 16)  <= CoefsReg_d.denCoefs(i)(j);
+                        end if;
+                    end loop;
+                  end loop;
+           end if;
+        end if;
+    end if;
+    apbo.pconfig <= pconfig;
+end process;
+
+apbo.prdata <=	Rdata when apbi.penable = '1' ;
+
+-- pragma translate_off
+    bootmsg : report_version
+    generic map ("apb IIR filter" & tost(pindex) &
+	": IIR filter rev " & tost(REVISION)& 
+	--", fifo " & tost(fifosize) &
+	", irq " & tost(pirq));
+-- pragma translate_on
+
+
+
+
+end ar_APB_IIR_CEL;
+
diff --git a/lib/lpp/dsp/iir_filter/FILTER.vhd b/lib/lpp/dsp/iir_filter/FILTER.vhd
--- a/lib/lpp/dsp/iir_filter/FILTER.vhd
+++ b/lib/lpp/dsp/iir_filter/FILTER.vhd
@@ -63,7 +63,7 @@ begin
 --==============================================================
 --=========================A L U================================
 --==============================================================
-ALU1 : entity ALU 
+ALU1 : ALU 
 generic map(
     Arith_en        =>  1,
     Logic_en        =>  0,
diff --git a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd
--- a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd
+++ b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd
@@ -18,97 +18,180 @@
 -------------------------------------------------------------------------------
 --                    Author : Alexis Jeandet
 --                     Mail : alexis.jeandet@lpp.polytechnique.fr
-----------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-library lpp;
-use lpp.lpp_ad_conv.all;
-use lpp.general_purpose.Clk_divider;
-
---! \brief AD7688 driver, generates all needed signal to drive this ADC.
---!
---! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+-- MODIFIED by  Jean-christophe PELLION
+--              jean-christophe.pellion@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+LIBRARY lpp;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.general_purpose.SYNC_FF;
 
-entity AD7688_drvr is
-generic(
-        ChanelCount     :integer; --! Number of ADC you whant to drive
-        clkkHz          :integer  --! System clock frequency in kHz usefull to generate some pulses with good width.
-        );
-Port(
-        clk       : in  STD_LOGIC; --! System clock
-        rstn      : in  STD_LOGIC; --! System reset
-        enable    : in std_logic;  --! Negative enable
-        smplClk   : in  STD_LOGIC; --! Sampling clock
-        DataReady : out std_logic; --! New sample available
-        smpout    : out Samples_out(ChanelCount-1 downto 0); --! Samples 	
-        AD_in     : in  AD7688_in(ChanelCount-1 downto 0);   --! Input signals for ADC see lpp.lpp_ad_conv
-        AD_out    : out AD7688_out                           --! Output signals for ADC see lpp.lpp_ad_conv
-);
-end AD7688_drvr;
-
-architecture ar_AD7688_drvr of AD7688_drvr is
-
-constant        convTrigger     :       integer:=  clkkHz*16/10000;  --tconv = 1.6µs
-
-signal i                : integer range 0 to convTrigger :=0;
-signal clk_int          : std_logic;
-signal clk_int_inv      : std_logic;
-signal smplClk_reg      : std_logic;
-signal cnv_int          : std_logic;
-signal reset            : std_logic;
+ENTITY AD7688_drvr IS
+  GENERIC(
+    ChanelCount     : INTEGER;
+    ncycle_cnv_high : INTEGER := 79;
+    ncycle_cnv      : INTEGER := 500);
+  PORT (
+    -- CONV --
+    cnv_clk   : IN  STD_LOGIC;
+    cnv_rstn  : IN  STD_LOGIC;
+    cnv_run : IN  STD_LOGIC;
+    cnv       : OUT STD_LOGIC;
 
-begin
-
-clkdiv: if clkkHz>=66000 generate 
-        clkdivider: entity work.Clk_divider
-                generic map(clkkHz*1000,60000000)
-                Port map( clk ,reset,clk_int);
-end generate;
+    -- DATA --
+    clk  : IN  STD_LOGIC;
+    rstn : IN  STD_LOGIC;
+    sck  : OUT STD_LOGIC;
+    sdo  : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
 
-clknodiv: if clkkHz<66000 generate 
-nodiv:  clk_int <=      clk;
-end generate;
-
-clk_int_inv     <=      not clk_int;
-
-AD_out.CNV      <=      cnv_int;	
-AD_out.SCK      <=      clk_int;
-reset           <=      rstn and enable;
+    sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
+    sample_val : OUT STD_LOGIC
+    );    
+END AD7688_drvr;
 
-sckgen: process(clk,reset)
-begin
-        if reset = '0' then
-                i <= 0;
-                cnv_int         <=      '0';
-                smplClk_reg     <=      '0';
-        elsif clk'event and clk = '1' then
-                if smplClk = '1' and smplClk_reg = '0' then
-                        if i = convTrigger then
-                                smplClk_reg     <=      '1';
-                                i       <=      0;
-                                cnv_int	<=      '0';
-                        else
-                                i       <=      i+1;
-                                cnv_int <=      '1';
-                        end if;
-                elsif smplClk = '0' and smplClk_reg = '1' then
-                        smplClk_reg     <=      '0';
-                end if;
-        end if;
-end process;
+ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
+
+  COMPONENT SYNC_FF
+    GENERIC (
+      NB_FF_OF_SYNC : INTEGER);
+    PORT (
+      clk    : IN  STD_LOGIC;
+      rstn   : IN  STD_LOGIC;
+      A      : IN  STD_LOGIC;
+      A_sync : OUT STD_LOGIC);
+  END COMPONENT;
 
 
+  SIGNAL cnv_cycle_counter  : INTEGER;
+  SIGNAL cnv_s              : STD_LOGIC;
+  SIGNAL cnv_sync           : STD_LOGIC;
+  SIGNAL cnv_sync_r         : STD_LOGIC;
+  SIGNAL cnv_done           : STD_LOGIC;
+  SIGNAL sample_bit_counter : INTEGER;
+  SIGNAL shift_reg          : Samples(ChanelCount-1 DOWNTO 0);
 
-spidrvr: entity work.AD7688_spi_if 
-        generic map(ChanelCount)
-        Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout);
+  SIGNAL cnv_run_sync : STD_LOGIC;
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- CONV
+  -----------------------------------------------------------------------------
+  PROCESS (cnv_clk, cnv_rstn)
+  BEGIN  -- PROCESS
+    IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+      cnv_cycle_counter <= 0;
+      cnv_s             <= '0';
+    ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+      IF cnv_run = '1' THEN
+        IF cnv_cycle_counter < ncycle_cnv THEN
+          cnv_cycle_counter <= cnv_cycle_counter +1;
+          IF cnv_cycle_counter < ncycle_cnv_high THEN
+            cnv_s <= '1';
+          ELSE
+            cnv_s <= '0';
+          END IF;
+        ELSE
+          cnv_s             <= '1';
+          cnv_cycle_counter <= 0;
+        END IF;
+      ELSE
+        cnv_s             <= '0';
+        cnv_cycle_counter <= 0;
+      END IF;
+    END IF;
+  END PROCESS;
 
+  cnv <= cnv_s;
+
+  -----------------------------------------------------------------------------
 
 
-end ar_AD7688_drvr;
+  -----------------------------------------------------------------------------
+  -- SYNC CNV
+  -----------------------------------------------------------------------------
+  
+  SYNC_FF_cnv : SYNC_FF
+    GENERIC MAP (
+      NB_FF_OF_SYNC => 2)
+    PORT MAP (
+      clk    => clk,
+      rstn   => rstn,
+      A      => cnv_s,
+      A_sync => cnv_sync);
 
+  PROCESS (clk, rstn)
+  BEGIN
+    IF rstn = '0' THEN
+      cnv_sync_r <= '0';
+      cnv_done   <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN
+      cnv_sync_r <= cnv_sync;
+      cnv_done   <= (NOT cnv_sync) AND cnv_sync_r;
+    END IF;
+  END PROCESS;
+
+  -----------------------------------------------------------------------------
+  
+  SYNC_FF_run : SYNC_FF
+    GENERIC MAP (
+      NB_FF_OF_SYNC => 2)
+    PORT MAP (
+      clk    => clk,
+      rstn   => rstn,
+      A      => cnv_run,
+      A_sync => cnv_run_sync);
 
 
-
+  
+  -----------------------------------------------------------------------------
+  -- DATA
+  -----------------------------------------------------------------------------
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN
+      FOR l IN 0 TO ChanelCount-1 LOOP
+        shift_reg(l) <= (OTHERS => '0');
+      END LOOP;
+      sample_bit_counter <= 0;
+      sample_val         <= '0';
+      SCK                <= '1';
+    ELSIF clk'EVENT AND clk = '1' THEN
+      
+      IF cnv_run_sync = '0' THEN
+        sample_bit_counter <= 0;
+      ELSIF cnv_done = '1' THEN
+        sample_bit_counter <= 1;
+      ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
+        sample_bit_counter <= sample_bit_counter + 1;
+      END IF;
 
+      IF (sample_bit_counter MOD 2) = 1 THEN
+        FOR l IN 0 TO ChanelCount-1 LOOP
+          --shift_reg(l)(15)          <= sdo(l);
+          --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+          shift_reg(l)(0)           <= sdo(l);
+          shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
+        END LOOP;
+        SCK <= '0';
+      ELSE
+        SCK <= '1';
+      END IF;
 
+      IF sample_bit_counter = 31 THEN
+        sample_val <= '1';
+        FOR l IN 0 TO ChanelCount-1 LOOP
+          --sample(l)(15)          <= sdo(l);
+          --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
+          sample(l)(0)           <= sdo(l);
+          sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
+        END LOOP;
+      ELSE
+        sample_val <= '0';
+      END IF;
+    END IF;
+  END PROCESS;
+  
+END ar_AD7688_drvr;
+
diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
--- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
+++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
@@ -50,7 +50,7 @@ PACKAGE lpp_ad_conv IS
 
   TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
 
-  COMPONENT ADS7886_drvr
+  COMPONENT AD7688_drvr
     GENERIC (
       ChanelCount     : INTEGER;
       ncycle_cnv_high : INTEGER := 79;
@@ -162,26 +162,26 @@ Type ADS127X_config is
         MODE    : ADS127X_MODE_Type;
 end record;
 
-COMPONENT ADS1274_DRIVER is 
-generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
-port(
-    Clk     :   in  std_logic;
-    reset   :   in  std_logic;
-    SpiClk  :   out std_logic;
-    DIN     :   in  std_logic_vector(3 downto 0);
-    Ready   :   in  std_logic;
-    Format  :   out std_logic_vector(2 downto 0);
-    Mode    :   out std_logic_vector(1 downto 0);
-    ClkDiv  :   out std_logic;
-    PWDOWN  :   out std_logic_vector(3 downto 0);
-    SmplClk :   in  std_logic;
-    OUT0    :   out std_logic_vector(23 downto 0);
-    OUT1    :   out std_logic_vector(23 downto 0);
-    OUT2    :   out std_logic_vector(23 downto 0);
-    OUT3    :   out std_logic_vector(23 downto 0);
-    FSynch  :   out std_logic;
-    test    :   out std_logic
-);
+COMPONENT ADS1274_DRIVER is 
+generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
+port(
+    Clk     :   in  std_logic;
+    reset   :   in  std_logic;
+    SpiClk  :   out std_logic;
+    DIN     :   in  std_logic_vector(3 downto 0);
+    Ready   :   in  std_logic;
+    Format  :   out std_logic_vector(2 downto 0);
+    Mode    :   out std_logic_vector(1 downto 0);
+    ClkDiv  :   out std_logic;
+    PWDOWN  :   out std_logic_vector(3 downto 0);
+    SmplClk :   in  std_logic;
+    OUT0    :   out std_logic_vector(23 downto 0);
+    OUT1    :   out std_logic_vector(23 downto 0);
+    OUT2    :   out std_logic_vector(23 downto 0);
+    OUT3    :   out std_logic_vector(23 downto 0);
+    FSynch  :   out std_logic;
+    test    :   out std_logic
+);
 end COMPONENT;
 
 
diff --git a/lib/lpp/lpp_amba/apb_devices_list.vhd b/lib/lpp/lpp_amba/apb_devices_list.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_amba/apb_devices_list.vhd
@@ -0,0 +1,41 @@
+
+--=================================================================================
+--THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
+--
+--TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
+--=================================================================================
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use std.textio.all;
+
+
+package apb_devices_list is
+
+
+constant VENDOR_LPP   : amba_vendor_type := 16#19#;
+ 
+constant ROCKET_TM   : amba_device_type := 16#1#;
+constant otherCore   : amba_device_type := 16#2#;
+constant LPP_SIMPLE_DIODE   : amba_device_type := 16#3#;
+constant LPP_MULTI_DIODE   : amba_device_type := 16#4#;
+constant LPP_LCD_CTRLR   : amba_device_type := 16#5#;
+constant LPP_UART   : amba_device_type := 16#6#;
+constant LPP_CNA   : amba_device_type := 16#7#;
+constant LPP_APB_ADC   : amba_device_type := 16#8#;
+constant LPP_CHENILLARD   : amba_device_type := 16#9#;
+constant LPP_IIR_CEL_FILTER   : amba_device_type := 16#10#;
+constant LPP_FIFO_PID   : amba_device_type := 16#11#;
+constant LPP_FFT   : amba_device_type := 16#12#;
+constant LPP_MATRIX   : amba_device_type := 16#13#;
+constant LPP_BALISE   : amba_device_type := 16#14#;
+constant LPP_USB   : amba_device_type := 16#15#;
+constant LPP_DELAY   : amba_device_type := 16#16#;
+constant LPP_DMA_TYPE   : amba_device_type := 16#17#;
+constant LPP_BOOTLOADER_TYPE   : amba_device_type := 16#18#;
+
+
+end;
diff --git a/lib/lpp/lpp_dma/vhdlsyn.txt b/lib/lpp/lpp_dma/vhdlsyn.txt
--- a/lib/lpp/lpp_dma/vhdlsyn.txt
+++ b/lib/lpp/lpp_dma/vhdlsyn.txt
@@ -1,7 +1,6 @@
 fifo_latency_correction.vhd
 lpp_dma.vhd
 lpp_dma_apbreg.vhd
-lpp_dma_fsm.vhd
 lpp_dma_ip.vhd
 lpp_dma_pkg.vhd
 lpp_dma_send_16word.vhd
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd.bak
@@ -0,0 +1,71 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+LIBRARY grlib;
+
+LIBRARY lpp;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.iir_filter.ALL;
+USE lpp.FILTERcfg.ALL;
+USE lpp.lpp_memory.ALL;
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
+
+PACKAGE lpp_top_lfr_pkg IS
+
+  COMPONENT lpp_top_acq
+    GENERIC (
+      tech : integer);
+    PORT (
+      cnv_run         : IN  STD_LOGIC;
+      cnv             : OUT STD_LOGIC;
+      sck             : OUT STD_LOGIC;
+      sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+      cnv_clk         : IN  STD_LOGIC;
+      cnv_rstn        : IN  STD_LOGIC;
+      clk             : IN  STD_LOGIC;
+      rstn            : IN  STD_LOGIC;
+      sample_f0_0_wen : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
+      sample_f0_1_wen : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
+      sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+      sample_f1_wen   : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
+      sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+      sample_f2_wen   : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
+      sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+      sample_f3_wen   : OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);
+      sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
+  END COMPONENT;
+
+  COMPONENT lpp_top_apbreg
+    GENERIC (
+      pindex : INTEGER;
+      paddr  : INTEGER;
+      pmask  : INTEGER;
+      pirq   : INTEGER);
+    PORT (
+      HCLK                                   : IN  STD_ULOGIC;
+      HRESETn                                : IN  STD_ULOGIC;
+      apbi                                   : IN  apb_slv_in_type;
+      apbo                                   : OUT apb_slv_out_type;
+      ready_matrix_f0_0                      : IN  STD_LOGIC;
+      ready_matrix_f0_1                      : IN  STD_LOGIC;
+      ready_matrix_f1                        : IN  STD_LOGIC;
+      ready_matrix_f2                        : IN  STD_LOGIC;
+      error_anticipating_empty_fifo          : IN  STD_LOGIC;
+      error_bad_component_error              : IN  STD_LOGIC;
+      debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+      status_ready_matrix_f0_0               : OUT STD_LOGIC;
+      status_ready_matrix_f0_1               : OUT STD_LOGIC;
+      status_ready_matrix_f1                 : OUT STD_LOGIC;
+      status_ready_matrix_f2                 : OUT STD_LOGIC;
+      status_error_anticipating_empty_fifo   : OUT STD_LOGIC;
+      status_error_bad_component_error       : OUT STD_LOGIC;
+      config_active_interruption_onNewMatrix : OUT STD_LOGIC;
+      config_active_interruption_onError     : OUT STD_LOGIC;
+      addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
+  END COMPONENT;
+
+END lpp_top_lfr_pkg;
\ No newline at end of file