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1
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
7
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 library grlib;
12 use grlib.amba.all;
13 use std.textio.all;
14
15
16 package apb_devices_list is
17
18
19 constant VENDOR_LPP : amba_vendor_type := 16#19#;
20
21 constant ROCKET_TM : amba_device_type := 16#1#;
22 constant otherCore : amba_device_type := 16#2#;
23 constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 constant LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 constant LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 constant LPP_UART : amba_device_type := 16#6#;
27 constant LPP_CNA : amba_device_type := 16#7#;
28 constant LPP_APB_ADC : amba_device_type := 16#8#;
29 constant LPP_CHENILLARD : amba_device_type := 16#9#;
30 constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 constant LPP_FIFO_PID : amba_device_type := 16#11#;
32 constant LPP_FFT : amba_device_type := 16#12#;
33 constant LPP_MATRIX : amba_device_type := 16#13#;
34 constant LPP_BALISE : amba_device_type := 16#14#;
35 constant LPP_USB : amba_device_type := 16#15#;
36 constant LPP_DELAY : amba_device_type := 16#16#;
37 constant LPP_DMA_TYPE : amba_device_type := 16#17#;
38 constant LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39
40
41 end;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5
6 LIBRARY lpp;
7 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.FILTERcfg.ALL;
10 USE lpp.lpp_memory.ALL;
11 LIBRARY techmap;
12 USE techmap.gencomp.ALL;
13
14 PACKAGE lpp_top_lfr_pkg IS
15
16 COMPONENT lpp_top_acq
17 GENERIC (
18 tech : integer);
19 PORT (
20 cnv_run : IN STD_LOGIC;
21 cnv : OUT STD_LOGIC;
22 sck : OUT STD_LOGIC;
23 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
24 cnv_clk : IN STD_LOGIC;
25 cnv_rstn : IN STD_LOGIC;
26 clk : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
37 END COMPONENT;
38
39 COMPONENT lpp_top_apbreg
40 GENERIC (
41 pindex : INTEGER;
42 paddr : INTEGER;
43 pmask : INTEGER;
44 pirq : INTEGER);
45 PORT (
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48 apbi : IN apb_slv_in_type;
49 apbo : OUT apb_slv_out_type;
50 ready_matrix_f0_0 : IN STD_LOGIC;
51 ready_matrix_f0_1 : IN STD_LOGIC;
52 ready_matrix_f1 : IN STD_LOGIC;
53 ready_matrix_f2 : IN STD_LOGIC;
54 error_anticipating_empty_fifo : IN STD_LOGIC;
55 error_bad_component_error : IN STD_LOGIC;
56 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 status_ready_matrix_f0_0 : OUT STD_LOGIC;
58 status_ready_matrix_f0_1 : OUT STD_LOGIC;
59 status_ready_matrix_f1 : OUT STD_LOGIC;
60 status_ready_matrix_f2 : OUT STD_LOGIC;
61 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
62 status_error_bad_component_error : OUT STD_LOGIC;
63 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
64 config_active_interruption_onError : OUT STD_LOGIC;
65 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
69 END COMPONENT;
70
71 END lpp_top_lfr_pkg; No newline at end of file
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@@ -201,7 +201,8 apbo.prdata <= Rdata when apbi.penable =
201 201 -- pragma translate_off
202 202 bootmsg : report_version
203 203 generic map ("apb IIR filter" & tost(pindex) &
204 ": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
204 ": IIR filter rev " & tost(REVISION)&
205 --", fifo " & tost(fifosize) &
205 206 ", irq " & tost(pirq));
206 207 -- pragma translate_on
207 208
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@@ -63,7 +63,7 begin
63 63 --==============================================================
64 64 --=========================A L U================================
65 65 --==============================================================
66 ALU1 : entity ALU
66 ALU1 : ALU
67 67 generic map(
68 68 Arith_en => 1,
69 69 Logic_en => 0,
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@@ -18,97 +18,180
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 library lpp;
25 use lpp.lpp_ad_conv.all;
26 use lpp.general_purpose.Clk_divider;
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
25 LIBRARY IEEE;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
27 30
28 --! \brief AD7688 driver, generates all needed signal to drive this ADC.
29 --!
30 --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
31 ENTITY AD7688_drvr IS
32 GENERIC(
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
36 PORT (
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
31 42
32 entity AD7688_drvr is
33 generic(
34 ChanelCount :integer; --! Number of ADC you whant to drive
35 clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width.
43 -- DATA --
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
36 51 );
37 Port(
38 clk : in STD_LOGIC; --! System clock
39 rstn : in STD_LOGIC; --! System reset
40 enable : in std_logic; --! Negative enable
41 smplClk : in STD_LOGIC; --! Sampling clock
42 DataReady : out std_logic; --! New sample available
43 smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples
44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
45 AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv
46 );
47 end AD7688_drvr;
52 END AD7688_drvr;
53
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
48 55
49 architecture ar_AD7688_drvr of AD7688_drvr is
50
51 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
56 COMPONENT SYNC_FF
57 GENERIC (
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
52 65
53 signal i : integer range 0 to convTrigger :=0;
54 signal clk_int : std_logic;
55 signal clk_int_inv : std_logic;
56 signal smplClk_reg : std_logic;
57 signal cnv_int : std_logic;
58 signal reset : std_logic;
66
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
74
75 SIGNAL cnv_run_sync : STD_LOGIC;
59 76
60 begin
61
62 clkdiv: if clkkHz>=66000 generate
63 clkdivider: entity work.Clk_divider
64 generic map(clkkHz*1000,60000000)
65 Port map( clk ,reset,clk_int);
66 end generate;
77 BEGIN
78 -----------------------------------------------------------------------------
79 -- CONV
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
92 ELSE
93 cnv_s <= '0';
94 END IF;
95 ELSE
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
98 END IF;
99 ELSE
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
102 END IF;
103 END IF;
104 END PROCESS;
67 105
68 clknodiv: if clkkHz<66000 generate
69 nodiv: clk_int <= clk;
70 end generate;
106 cnv <= cnv_s;
71 107
72 clk_int_inv <= not clk_int;
108 -----------------------------------------------------------------------------
73 109
74 AD_out.CNV <= cnv_int;
75 AD_out.SCK <= clk_int;
76 reset <= rstn and enable;
77 110
78 sckgen: process(clk,reset)
79 begin
80 if reset = '0' then
81 i <= 0;
82 cnv_int <= '0';
83 smplClk_reg <= '0';
84 elsif clk'event and clk = '1' then
85 if smplClk = '1' and smplClk_reg = '0' then
86 if i = convTrigger then
87 smplClk_reg <= '1';
88 i <= 0;
89 cnv_int <= '0';
90 else
91 i <= i+1;
92 cnv_int <= '1';
93 end if;
94 elsif smplClk = '0' and smplClk_reg = '1' then
95 smplClk_reg <= '0';
96 end if;
97 end if;
98 end process;
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
114
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
119 clk => clk,
120 rstn => rstn,
121 A => cnv_s,
122 A_sync => cnv_sync);
123
124 PROCESS (clk, rstn)
125 BEGIN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
133 END PROCESS;
134
135 -----------------------------------------------------------------------------
136
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
141 clk => clk,
142 rstn => rstn,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
99 145
100 146
101 147
102 spidrvr: entity work.AD7688_spi_if
103 generic map(ChanelCount)
104 Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout);
148 -----------------------------------------------------------------------------
149 -- DATA
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
105 161
106
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
107 169
108 end ar_AD7688_drvr;
109
110
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 --shift_reg(l)(15) <= sdo(l);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
176 END LOOP;
177 SCK <= '0';
178 ELSE
179 SCK <= '1';
180 END IF;
111 181
112
182 IF sample_bit_counter = 31 THEN
183 sample_val <= '1';
184 FOR l IN 0 TO ChanelCount-1 LOOP
185 --sample(l)(15) <= sdo(l);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
189 END LOOP;
190 ELSE
191 sample_val <= '0';
192 END IF;
193 END IF;
194 END PROCESS;
113 195
196 END ar_AD7688_drvr;
114 197
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@@ -50,7 +50,7 PACKAGE lpp_ad_conv IS
50 50
51 51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52 52
53 COMPONENT ADS7886_drvr
53 COMPONENT AD7688_drvr
54 54 GENERIC (
55 55 ChanelCount : INTEGER;
56 56 ncycle_cnv_high : INTEGER := 79;
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@@ -1,7 +1,6
1 1 fifo_latency_correction.vhd
2 2 lpp_dma.vhd
3 3 lpp_dma_apbreg.vhd
4 lpp_dma_fsm.vhd
5 4 lpp_dma_ip.vhd
6 5 lpp_dma_pkg.vhd
7 6 lpp_dma_send_16word.vhd
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