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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY lpp;
27 USE lpp.lpp_memory.ALL;
28 USE lpp.iir_filter.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_fifo_4_shared IS
34 GENERIC(
35 tech : INTEGER := 0;
36 Mem_use : INTEGER := use_RAM;
37 EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
38 FULL_THRESHOLD_LIMIT : INTEGER := 5;
39 DataSz : INTEGER RANGE 1 TO 32 := 8;
40 AddrSz : INTEGER RANGE 3 TO 12 := 8
41 );
42 PORT(
43 clk : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
45 ---------------------------------------------------------------------------
46 run : IN STD_LOGIC;
47
48 ---------------------------------------------------------------------------
49 empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
50 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
51 r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53
54 ---------------------------------------------------------------------------
55 full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
56 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
57 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
59 w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
60 );
61 END ENTITY;
62
63
64 ARCHITECTURE beh OF lpp_fifo_4_shared IS
65
66 SIGNAL full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
67
68 TYPE LPP_TYPE_ADDR_FIFO_SHARED IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(AddrSz-3 DOWNTO 0);
69 SIGNAL mem_r_addr_v : LPP_TYPE_ADDR_FIFO_SHARED;
70 SIGNAL mem_w_addr_v : LPP_TYPE_ADDR_FIFO_SHARED;
71 SIGNAL mem_r_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
72 SIGNAL mem_w_addr : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
73
74 SIGNAL fifo_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SIGNAL fifo_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SIGNAL mem_r_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SIGNAL mem_w_en_v : STD_LOGIC_VECTOR(3 DOWNTO 0);
78 SIGNAL mem_r_e : STD_LOGIC;
79 SIGNAL mem_w_e : STD_LOGIC;
80
81 SIGNAL NB_DATA_IN_FIFO : INTEGER;
82
83
84 CONSTANT length : INTEGER := 2**(AddrSz-2);
85 TYPE INTEGER_ARRAY_4 IS ARRAY (3 DOWNTO 0) OF INTEGER;
86 SIGNAL mem_r_addr_v_int : INTEGER_ARRAY_4;
87 SIGNAL mem_w_addr_v_int : INTEGER_ARRAY_4;
88 SIGNAL space_busy : INTEGER_ARRAY_4;
89 SIGNAL space_free : INTEGER_ARRAY_4;
90
91 BEGIN
92
93 -----------------------------------------------------------------------------
94 SRAM : syncram_2p
95 GENERIC MAP(tech, AddrSz, DataSz)
96 PORT MAP(clk, mem_r_e, mem_r_addr, r_data,
97 clk, mem_w_e, mem_w_addr, w_data);
98 -----------------------------------------------------------------------------
99
100 mem_r_addr <= "00" & mem_r_addr_v(0) WHEN fifo_r_en_v(0) = '0' ELSE
101 "01" & mem_r_addr_v(1) WHEN fifo_r_en_v(1) = '0' ELSE
102 "10" & mem_r_addr_v(2) WHEN fifo_r_en_v(2) = '0' ELSE
103 "11" & mem_r_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE
104
105 mem_w_addr <= "00" & mem_w_addr_v(0) WHEN fifo_w_en_v(0) = '0' ELSE
106 "01" & mem_w_addr_v(1) WHEN fifo_w_en_v(1) = '0' ELSE
107 "10" & mem_w_addr_v(2) WHEN fifo_w_en_v(2) = '0' ELSE
108 "11" & mem_w_addr_v(3); -- WHEN fifo_r_en(2) = '0' ELSE
109
110 mem_r_e <= '0' WHEN mem_r_en_v = "1111" ELSE '1';
111 mem_w_e <= '0' WHEN mem_w_en_v = "1111" ELSE '1';
112
113 ----------------------------------------------------------------------------
114 all_fifo : FOR I IN 3 DOWNTO 0 GENERATE
115 fifo_r_en_v(I) <= r_en(I);
116 fifo_w_en_v(I) <= w_en(I);
117
118 lpp_fifo_control_1 : lpp_fifo_control
119 GENERIC MAP (
120 AddrSz => AddrSz-2,
121 EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT,
122 FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT)
123 PORT MAP (
124 clk => clk,
125 rstn => rstn,
126 reUse => '0',
127 run => run,
128 fifo_r_en => fifo_r_en_v(I),
129 fifo_w_en => fifo_w_en_v(I),
130 mem_r_en => mem_r_en_v(I),
131 mem_w_en => mem_w_en_v(I),
132 mem_r_addr => mem_r_addr_v(I),
133 mem_w_addr => mem_w_addr_v(I),
134 empty => empty(I),
135 full => full_s(I),
136 full_almost => full_almost(I),
137 empty_threshold => empty_threshold(I),
138 full_threshold => full_threshold(I)
139 );
140
141 --full(I) <= full_s(I);
142
143 --mem_w_addr_v_int(I) <= to_integer(UNSIGNED(mem_w_addr_v(I)));
144 --mem_r_addr_v_int(I) <= to_integer(UNSIGNED(mem_r_addr_v(I)));
145
146 --space_busy(I) <= length WHEN full_s(I) = '1' ELSE
147 -- length + mem_w_addr_v_int(I) - mem_r_addr_v_int(I) WHEN mem_w_addr_v_int(I) < mem_r_addr_v_int(I) ELSE
148 -- mem_w_addr_v_int(I) - mem_r_addr_v_int(I);
149
150 --space_free(I) <= length - space_busy(I);
151
152 --empty_threshold(I) <= '0' WHEN space_busy(I) > EMPTY_THRESHOLD_LIMIT ELSE '1';
153 --full_threshold(I) <= '0' WHEN space_free(I) > FULL_THRESHOLD_LIMIT ELSE '1';
154
155 END GENERATE all_fifo;
156
157
158
159 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28
29 ENTITY lpp_fifo_4_shared_headreg_latency_0 IS
30 PORT(
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 ---------------------------------------------------------------------------
34 run : IN STD_LOGIC;
35 ---------------------------------------------------------------------------
36 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
37 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
38
39 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
40 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
43 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
44 ---------------------------------------------------------------------------
45 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
47 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
48 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
49 );
50 END ENTITY;
51
52
53 ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_0 IS
54
55 TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL reg_head_data : REG_HEAD_TYPE;
57
58
59 SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
60 SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
65
66
67 BEGIN
68 --i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
69 i_data_ren <= i_data_ren_s;
70 o_empty_almost <= i_empty_almost; --TODO
71
72 o_rdata_0 <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ;
73 o_rdata_1 <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ;
74 o_rdata_2 <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ;
75 o_rdata_3 <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ;
76
77 i_data_ren_s(0) <= i_data_ren_s_temp(0);
78 i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1';
79 i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1';
80 i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1';
81
82 each_fifo: FOR I IN 3 DOWNTO 0 GENERATE
83 o_empty(I) <= NOT reg_head_full(I);
84
85 -- i_data_ren_pre(I) <= i_data_ren_s(I);
86
87 PROCESS (clk, rstn)
88 BEGIN
89 IF rstn = '0' THEN
90 reg_head_data(I) <= (OTHERS => '0');
91 i_data_ren_pre(I) <= '1';
92 reg_head_full(I) <= '0';
93 o_data_ren_pre(I) <= '1';
94 ELSIF clk'event AND clk = '1' THEN
95 o_data_ren_pre(I) <= o_data_ren(I) ;
96 IF i_data_ren_pre(I) = '0' THEN
97 reg_head_data(I) <= i_rdata;
98 END IF;
99 i_data_ren_pre(I) <= i_data_ren_s(I);
100
101 -- IF i_data_ren_pre(I) = '0' THEN
102 IF i_data_ren_s(I) = '0' THEN
103 reg_head_full(I) <= '1';
104 -- ELSIF o_data_ren_pre(I) = '0' THEN
105 ELSIF o_data_ren(I) = '0' THEN
106 reg_head_full(I) <= '0';
107 END IF;
108
109 END IF;
110 END PROCESS;
111
112 i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE
113 '0' WHEN o_data_ren(I) = '0' ELSE
114 '0' WHEN reg_head_full(I) = '0' ELSE
115 '1';
116
117
118 PROCESS (clk, rstn)
119 BEGIN
120 IF rstn = '0' THEN
121 i_empty_reg(I) <= '1';
122 ELSIF clk'event AND clk = '1' THEN
123 i_empty_reg(I) <= i_empty(I);
124 END IF;
125 END PROCESS;
126
127
128
129 END GENERATE each_fifo;
130
131
132 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28
29 ENTITY lpp_fifo_4_shared_headreg_latency_1 IS
30 PORT(
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 ---------------------------------------------------------------------------
34 run : IN STD_LOGIC;
35 ---------------------------------------------------------------------------
36 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
37 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
38
39 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
40 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
43 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
44 ---------------------------------------------------------------------------
45 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
47 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
48 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
49 );
50 END ENTITY;
51
52
53 ARCHITECTURE beh OF lpp_fifo_4_shared_headreg_latency_1 IS
54
55 TYPE REG_HEAD_TYPE IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL reg_head_data : REG_HEAD_TYPE;
57
58
59 SIGNAL reg_head_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
60 SIGNAL i_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 SIGNAL o_data_ren_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL i_data_ren_s_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL i_data_ren_s : STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 SIGNAL i_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 SIGNAL o_rdata_0_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
66 SIGNAL o_rdata_1_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
67 SIGNAL o_rdata_2_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
68 SIGNAL o_rdata_3_s : STD_LOGIC_VECTOR(31 DOWNTO 0); --
69
70
71 BEGIN
72 --i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
73 i_data_ren <= i_data_ren_s;
74
75 o_rdata_0_s <= i_rdata WHEN o_data_ren_pre(0) = '0' AND o_data_ren(0) = '0' ELSE reg_head_data(0) ;
76 o_rdata_1_s <= i_rdata WHEN o_data_ren_pre(1) = '0' AND o_data_ren(1) = '0' ELSE reg_head_data(1) ;
77 o_rdata_2_s <= i_rdata WHEN o_data_ren_pre(2) = '0' AND o_data_ren(2) = '0' ELSE reg_head_data(2) ;
78 o_rdata_3_s <= i_rdata WHEN o_data_ren_pre(3) = '0' AND o_data_ren(3) = '0' ELSE reg_head_data(3) ;
79
80
81 PROCESS (clk, rstn)
82 BEGIN -- PROCESS
83 IF rstn = '0' THEN -- asynchronous reset (active low)
84 o_rdata_0 <= (OTHERS => '0');
85 o_rdata_1 <= (OTHERS => '0');
86 o_rdata_2 <= (OTHERS => '0');
87 o_rdata_3 <= (OTHERS => '0');
88 --o_empty_almost <= (OTHERS => '0');
89 --o_empty <= (OTHERS => '0');
90 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
91 o_rdata_0 <= o_rdata_0_s;
92 o_rdata_1 <= o_rdata_1_s;
93 o_rdata_2 <= o_rdata_2_s;
94 o_rdata_3 <= o_rdata_3_s;
95
96 --o_empty_almost <= i_empty_almost; --TODO
97 --o_empty <= NOT reg_head_full;
98 END IF;
99 END PROCESS;
100
101
102 o_empty_almost <= i_empty_almost; --TODO
103 o_empty <= NOT reg_head_full OR (i_empty AND o_data_ren);
104
105
106
107 i_data_ren_s(0) <= i_data_ren_s_temp(0);
108 i_data_ren_s(1) <= i_data_ren_s_temp(1) WHEN i_data_ren_s_temp(0) = '1' ELSE '1';
109 i_data_ren_s(2) <= i_data_ren_s_temp(2) WHEN i_data_ren_s_temp(1 DOWNTO 0) = "11" ELSE '1';
110 i_data_ren_s(3) <= i_data_ren_s_temp(3) WHEN i_data_ren_s_temp(2 DOWNTO 0) = "111" ELSE '1';
111
112 each_fifo: FOR I IN 3 DOWNTO 0 GENERATE
113
114 -- i_data_ren_pre(I) <= i_data_ren_s(I);
115
116 PROCESS (clk, rstn)
117 BEGIN
118 IF rstn = '0' THEN
119 reg_head_data(I) <= (OTHERS => '0');
120 i_data_ren_pre(I) <= '1';
121 reg_head_full(I) <= '0';
122 o_data_ren_pre(I) <= '1';
123 ELSIF clk'event AND clk = '1' THEN
124 o_data_ren_pre(I) <= o_data_ren(I) ;
125 IF i_data_ren_pre(I) = '0' THEN
126 reg_head_data(I) <= i_rdata;
127 END IF;
128 i_data_ren_pre(I) <= i_data_ren_s(I);
129 IF i_data_ren_s(I) = '0' THEN
130 reg_head_full(I) <= '1';
131 ELSIF o_data_ren(I) = '0' THEN
132 reg_head_full(I) <= '0';
133 END IF;
134
135 END IF;
136 END PROCESS;
137
138 i_data_ren_s_temp(I) <= '1' WHEN i_empty_reg(I) = '1' ELSE
139 '0' WHEN o_data_ren(I) = '0' ELSE
140 '0' WHEN reg_head_full(I) = '0' ELSE
141 '1';
142
143
144 PROCESS (clk, rstn)
145 BEGIN
146 IF rstn = '0' THEN
147 i_empty_reg(I) <= '1';
148 ELSIF clk'event AND clk = '1' THEN
149 i_empty_reg(I) <= i_empty(I);
150 END IF;
151 END PROCESS;
152
153
154
155 END GENERATE each_fifo;
156
157
158 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY lpp_fifo_control IS
27 GENERIC(
28 AddrSz : INTEGER RANGE 2 TO 12 := 8;
29 EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
30 FULL_THRESHOLD_LIMIT : INTEGER := 5
31 );
32 PORT(
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 --
36 reUse : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38
39 --IN
40 fifo_r_en : IN STD_LOGIC;
41 fifo_w_en : IN STD_LOGIC;
42
43 mem_r_en : OUT STD_LOGIC;
44 mem_w_en : OUT STD_LOGIC;
45 mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
46 mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
47
48 empty : OUT STD_LOGIC;
49 full : OUT STD_LOGIC;
50 full_almost : OUT STD_LOGIC;
51 empty_threshold : OUT STD_LOGIC;
52 full_threshold : OUT STD_LOGIC
53
54 );
55 END ENTITY;
56
57
58 ARCHITECTURE beh OF lpp_fifo_control IS
59
60 SIGNAL sFull : STD_LOGIC;
61 SIGNAL sFull_s : STD_LOGIC;
62 SIGNAL sEmpty_s : STD_LOGIC;
63
64 SIGNAL sEmpty : STD_LOGIC;
65 SIGNAL sREN : STD_LOGIC;
66 SIGNAL sWEN : STD_LOGIC;
67
68 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
69 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
70 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
71 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72
73 SIGNAL almost_full_s : STD_LOGIC;
74 SIGNAL almost_full_r : STD_LOGIC;
75
76 SIGNAL mem_r_addr_int : INTEGER;
77 SIGNAL mem_w_addr_int : INTEGER;
78 SIGNAL space_busy : INTEGER;
79 SIGNAL space_free : INTEGER;
80
81 CONSTANT length : INTEGER := 2**(AddrSz);
82
83 BEGIN
84
85 mem_r_addr <= Raddr_vect;
86 mem_w_addr <= Waddr_vect;
87
88
89 mem_r_en <= sREN;
90 mem_w_en <= sWEN;
91 --=============================
92 -- Read section
93 --=============================
94 sREN <= FIFO_R_EN OR sEmpty;
95 --sRE <= NOT sREN;
96
97 sEmpty_s <= '0' WHEN ReUse = '1' ELSE
98 '1' WHEN sEmpty = '1' AND Fifo_W_En = '1' ELSE
99 '1' WHEN sEmpty = '0' AND (Fifo_W_En = '1' AND Fifo_R_en = '0' AND Raddr_vect_s = Waddr_vect) ELSE
100 '0';
101
102 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
103
104 PROCESS (clk, rstn)
105 BEGIN
106 IF(rstn = '0')THEN
107 Raddr_vect <= (OTHERS => '0');
108 sempty <= '1';
109 ELSIF(clk'EVENT AND clk = '1')THEN
110
111 IF run = '0' THEN
112 Raddr_vect <= (OTHERS => '0');
113 sempty <= '1';
114 ELSE
115 sEmpty <= sempty_s;
116
117 IF(sREN = '0' AND sempty = '0')THEN
118 Raddr_vect <= Raddr_vect_s;
119 END IF;
120 END IF;
121
122 END IF;
123 END PROCESS;
124
125 --=============================
126 -- Write section
127 --=============================
128 sWEN <= FIFO_W_EN OR sFull;
129 -- sWE <= NOT sWEN;
130
131 sFull_s <= '1' WHEN ReUse = '1' ELSE
132 '1' WHEN Waddr_vect_s = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE
133 '1' WHEN sFull = '1' AND FIFO_R_EN = '1' ELSE
134 '0';
135
136 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND FIFO_R_EN = '1' AND FIFO_W_EN = '0' ELSE
137 '1' WHEN almost_full_r = '1' AND FIFO_W_EN = FIFO_R_EN ELSE
138 '0';
139
140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
141
142 PROCESS (clk, rstn)
143 BEGIN
144 IF(rstn = '0')THEN
145 Waddr_vect <= (OTHERS => '0');
146 sfull <= '0';
147 almost_full_r <= '0';
148 ELSIF(clk'EVENT AND clk = '1')THEN
149 IF run = '0' THEN
150 Waddr_vect <= (OTHERS => '0');
151 sfull <= '0';
152 almost_full_r <= '0';
153 ELSE
154 sfull <= sfull_s;
155 almost_full_r <= almost_full_s;
156
157 IF(sWEN = '0' AND sfull = '0')THEN
158 Waddr_vect <= Waddr_vect_s;
159 END IF;
160 END IF;
161 END IF;
162 END PROCESS;
163
164 full_almost <= almost_full_s;
165 full <= sFull_s;
166 empty <= sEmpty_s;
167
168 -----------------------------------------------------------------------------
169 mem_w_addr_int <= to_integer(UNSIGNED(Waddr_vect));
170 mem_r_addr_int <= to_integer(UNSIGNED(Raddr_vect));
171
172 space_busy <= length WHEN sFull = '1' ELSE
173 length + mem_w_addr_int - mem_r_addr_int WHEN mem_w_addr_int < mem_r_addr_int ELSE
174 mem_w_addr_int - mem_r_addr_int;
175
176 space_free <= length - space_busy;
177
178 empty_threshold <= '0' WHEN space_busy > EMPTY_THRESHOLD_LIMIT ELSE '1';
179 full_threshold <= '0' WHEN space_free > FULL_THRESHOLD_LIMIT ELSE '1';
180 -----------------------------------------------------------------------------
181
182
183 END ARCHITECTURE;
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@@ -1,604 +1,604
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 nb_word_by_buffer_size => 30,
421 nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"000118") -- aa.bb.cc version
431 top_lfr_version => X"00011B") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig,
444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
446 observation_vector_1 => observation_vector_1,
447 observation_reg => observation_reg);
447 observation_reg => observation_reg);
448
448
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 END GENERATE all_sample;
451 END GENERATE all_sample;
452
452
453
453
454
454
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 GENERIC MAP(
456 GENERIC MAP(
457 ChannelCount => 8,
457 ChannelCount => 8,
458 SampleNbBits => 14,
458 SampleNbBits => 14,
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 PORT MAP (
461 PORT MAP (
462 -- CONV
462 -- CONV
463 cnv_clk => clk_24,
463 cnv_clk => clk_24,
464 cnv_rstn => reset,
464 cnv_rstn => reset,
465 cnv => ADC_nCS_sig,
465 cnv => ADC_nCS_sig,
466 -- DATA
466 -- DATA
467 clk => clk_25,
467 clk => clk_25,
468 rstn => reset,
468 rstn => reset,
469 sck => ADC_CLK_sig,
469 sck => ADC_CLK_sig,
470 sdo => ADC_SDO_sig,
470 sdo => ADC_SDO_sig,
471 -- SAMPLE
471 -- SAMPLE
472 sample => sample,
472 sample => sample,
473 sample_val => sample_val);
473 sample_val => sample_val);
474
474
475 --IO10 <= ADC_SDO_sig(5);
475 --IO10 <= ADC_SDO_sig(5);
476 --IO9 <= ADC_SDO_sig(4);
476 --IO9 <= ADC_SDO_sig(4);
477 --IO8 <= ADC_SDO_sig(3);
477 --IO8 <= ADC_SDO_sig(3);
478
478
479 ADC_nCS <= ADC_nCS_sig;
479 ADC_nCS <= ADC_nCS_sig;
480 ADC_CLK <= ADC_CLK_sig;
480 ADC_CLK <= ADC_CLK_sig;
481 ADC_SDO_sig <= ADC_SDO;
481 ADC_SDO_sig <= ADC_SDO;
482
482
483 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
485 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
486
486
487 grgpio0 : grgpio
487 grgpio0 : grgpio
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490
490
491 --pio_pad_0 : iopad
491 --pio_pad_0 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 --pio_pad_1 : iopad
494 --pio_pad_1 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 --pio_pad_2 : iopad
497 --pio_pad_2 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 --pio_pad_3 : iopad
500 --pio_pad_3 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 --pio_pad_4 : iopad
503 --pio_pad_4 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 --pio_pad_5 : iopad
506 --pio_pad_5 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 --pio_pad_6 : iopad
509 --pio_pad_6 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 --pio_pad_7 : iopad
512 --pio_pad_7 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
513 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515
515
516 PROCESS (clk_25, reset)
516 PROCESS (clk_25, reset)
517 BEGIN -- PROCESS
517 BEGIN -- PROCESS
518 IF reset = '0' THEN -- asynchronous reset (active low)
518 IF reset = '0' THEN -- asynchronous reset (active low)
519 IO0 <= '0';
519 IO0 <= '0';
520 IO1 <= '0';
520 IO1 <= '0';
521 IO2 <= '0';
521 IO2 <= '0';
522 IO3 <= '0';
522 IO3 <= '0';
523 IO4 <= '0';
523 IO4 <= '0';
524 IO5 <= '0';
524 IO5 <= '0';
525 IO6 <= '0';
525 IO6 <= '0';
526 IO7 <= '0';
526 IO7 <= '0';
527 IO8 <= '0';
527 IO8 <= '0';
528 IO9 <= '0';
528 IO9 <= '0';
529 IO10 <= '0';
529 IO10 <= '0';
530 IO11 <= '0';
530 IO11 <= '0';
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 CASE gpioo.dout(2 DOWNTO 0) IS
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "011" =>
533 WHEN "011" =>
534 IO0 <= observation_reg(0 );
534 IO0 <= observation_reg(0 );
535 IO1 <= observation_reg(1 );
535 IO1 <= observation_reg(1 );
536 IO2 <= observation_reg(2 );
536 IO2 <= observation_reg(2 );
537 IO3 <= observation_reg(3 );
537 IO3 <= observation_reg(3 );
538 IO4 <= observation_reg(4 );
538 IO4 <= observation_reg(4 );
539 IO5 <= observation_reg(5 );
539 IO5 <= observation_reg(5 );
540 IO6 <= observation_reg(6 );
540 IO6 <= observation_reg(6 );
541 IO7 <= observation_reg(7 );
541 IO7 <= observation_reg(7 );
542 IO8 <= observation_reg(8 );
542 IO8 <= observation_reg(8 );
543 IO9 <= observation_reg(9 );
543 IO9 <= observation_reg(9 );
544 IO10 <= observation_reg(10);
544 IO10 <= observation_reg(10);
545 IO11 <= observation_reg(11);
545 IO11 <= observation_reg(11);
546 WHEN "001" =>
546 WHEN "001" =>
547 IO0 <= observation_reg(0 + 12);
547 IO0 <= observation_reg(0 + 12);
548 IO1 <= observation_reg(1 + 12);
548 IO1 <= observation_reg(1 + 12);
549 IO2 <= observation_reg(2 + 12);
549 IO2 <= observation_reg(2 + 12);
550 IO3 <= observation_reg(3 + 12);
550 IO3 <= observation_reg(3 + 12);
551 IO4 <= observation_reg(4 + 12);
551 IO4 <= observation_reg(4 + 12);
552 IO5 <= observation_reg(5 + 12);
552 IO5 <= observation_reg(5 + 12);
553 IO6 <= observation_reg(6 + 12);
553 IO6 <= observation_reg(6 + 12);
554 IO7 <= observation_reg(7 + 12);
554 IO7 <= observation_reg(7 + 12);
555 IO8 <= observation_reg(8 + 12);
555 IO8 <= observation_reg(8 + 12);
556 IO9 <= observation_reg(9 + 12);
556 IO9 <= observation_reg(9 + 12);
557 IO10 <= observation_reg(10 + 12);
557 IO10 <= observation_reg(10 + 12);
558 IO11 <= observation_reg(11 + 12);
558 IO11 <= observation_reg(11 + 12);
559 WHEN "010" =>
559 WHEN "010" =>
560 IO0 <= observation_reg(0 + 12 + 12);
560 IO0 <= observation_reg(0 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
568 IO8 <= '0';
568 IO8 <= '0';
569 IO9 <= '0';
569 IO9 <= '0';
570 IO10 <= '0';
570 IO10 <= '0';
571 IO11 <= '0';
571 IO11 <= '0';
572 WHEN "000" =>
572 WHEN "000" =>
573 IO0 <= observation_vector_0(0 );
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
597 IO11 <= observation_vector_1(11);
598 WHEN OTHERS => NULL;
598 WHEN OTHERS => NULL;
599 END CASE;
599 END CASE;
600
600
601 END IF;
601 END IF;
602 END PROCESS;
602 END PROCESS;
603
603
604 END beh;
604 END beh;
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@@ -1,53 +1,53
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
15 VHDLSYNFILES=
16 VHDLSIMFILES= tb.vhd
16 VHDLSIMFILES= FIFO_Verif.vhd tb.vhd
17 SIMTOP=testbench
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
22 CLEAN=soft-clean
23
23
24 TECHLIBS = proasic3e
24 TECHLIBS = proasic3e
25
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
35 ./lpp_bootloader \
36 ./lpp_cna \
36 ./lpp_cna \
37 ./lpp_uart \
37 ./lpp_uart \
38 ./lpp_usb \
38 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
39 ./dsp/lpp_fft_rtax \
40
40
41 FILESKIP = i2cmst.vhd \
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
45 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
46 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
47 CoreFFT.vhd
48
48
49 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
50 include $(GRLIB)/software/leon3/Makefile
51
51
52 ################## project specific targets ##########################
52 ################## project specific targets ##########################
53
53
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@@ -1,9 +1,11
1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO_control.vhd
2 vcom -quiet -93 -work work FIFO_Verif.vhd
1 vcom -quiet -93 -work work tb.vhd
3 vcom -quiet -93 -work work tb.vhd
2
4
3 vsim work.testbench
5 vsim work.testbench
4
6
5 log -r *
7 log -r *
6
8
7 do wave.do
9 do wave.do
8
10
9 run -all
11 run -all
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@@ -1,248 +1,147
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
5 USE ieee.numeric_std.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_memory.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10
10
11
11
12 ENTITY testbench IS
12 ENTITY testbench IS
13 END;
13 END;
14
14
15 ARCHITECTURE behav OF testbench IS
15 ARCHITECTURE behav OF testbench IS
16
17 COMPONENT fifo_verif
18 PORT (
19 verif_clk : OUT STD_LOGIC;
20 verif_rstn : OUT STD_LOGIC;
21 verif_ren : OUT STD_LOGIC;
22 verif_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
23 verif_wen : OUT STD_LOGIC;
24 verif_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
25 verif_empty : IN STD_LOGIC;
26 verif_full : IN STD_LOGIC;
27 verif_almost_full : IN STD_LOGIC;
28 error_now : OUT STD_LOGIC;
29 error_new : OUT STD_LOGIC);
30 END COMPONENT;
16
31
17 -----------------------------------------------------------------------------
32 -----------------------------------------------------------------------------
18 -- Common signal
33 SIGNAL CEL_clk : STD_LOGIC := '0';
19 SIGNAL clk : STD_LOGIC := '0';
34 SIGNAL CEL_rstn : STD_LOGIC := '0';
20 SIGNAL rstn : STD_LOGIC := '0';
35 -----------------------------------------------------------------------------
21 SIGNAL run : STD_LOGIC := '0';
36 SIGNAL CEL_data_ren : STD_LOGIC;
22
37 SIGNAL CEL_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
38 SIGNAL CEL_data_wen : STD_LOGIC;
39 SIGNAL CEL_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL CEL_full_almost : STD_LOGIC;
41 SIGNAL CEL_full : STD_LOGIC;
42 SIGNAL CEL_empty : STD_LOGIC;
43 -----------------------------------------------------------------------------
44 SIGNAL CEL_error_now : STD_LOGIC;
45 SIGNAL CEL_error_new : STD_LOGIC;
23 -----------------------------------------------------------------------------
46 -----------------------------------------------------------------------------
24
47
25 SIGNAL full_almost : STD_LOGIC;
48 -----------------------------------------------------------------------------
26 SIGNAL full : STD_LOGIC;
49 SIGNAL RAM_clk : STD_LOGIC := '0';
27 SIGNAL data_wen : STD_LOGIC;
50 SIGNAL RAM_rstn : STD_LOGIC := '0';
28 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
29
30 SIGNAL empty : STD_LOGIC;
31 SIGNAL data_ren : STD_LOGIC;
32 SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
33 SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0);
34
35 SIGNAL empty_reg : STD_LOGIC;
36 SIGNAL full_reg : STD_LOGIC;
37
38 -----------------------------------------------------------------------------
51 -----------------------------------------------------------------------------
39 TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
52 SIGNAL RAM_data_ren : STD_LOGIC;
40 SIGNAL data_in : DATA_CHANNEL;
53 SIGNAL RAM_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
41
54 SIGNAL RAM_data_wen : STD_LOGIC;
55 SIGNAL RAM_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 SIGNAL RAM_full_almost : STD_LOGIC;
57 SIGNAL RAM_full : STD_LOGIC;
58 SIGNAL RAM_empty : STD_LOGIC;
42 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
43 CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE
60 SIGNAL RAM_error_now : STD_LOGIC;
44 CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0;
61 SIGNAL RAM_error_new : STD_LOGIC;
45 SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
62 -----------------------------------------------------------------------------
46 --
63
47 SIGNAL rand_ren : STD_LOGIC;
48 SIGNAL rand_wen : STD_LOGIC;
49
50 SIGNAL pointer_read : INTEGER;
51 SIGNAL pointer_write : INTEGER := 0;
52
53 SIGNAL error_now : STD_LOGIC;
54 SIGNAL error_new : STD_LOGIC;
55
56 SIGNAL read_stop : STD_LOGIC;
57 BEGIN
64 BEGIN
58
65
59
66
60 all_J : FOR J IN 0 TO 127 GENERATE
61 data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32));
62 END GENERATE all_J;
63
64
65 -----------------------------------------------------------------------------
67 -----------------------------------------------------------------------------
66 lpp_fifo_1 : lpp_fifo
68 lpp_fifo_CEL : lpp_fifo
67 GENERIC MAP (
69 GENERIC MAP (
68 tech => 0,
70 tech => 0,
69 Mem_use => use_CEL,
71 Mem_use => use_CEL,
72 EMPTY_THRESHOLD_LIMIT => 1,
73 FULL_THRESHOLD_LIMIT => 1,
70 DataSz => 32,
74 DataSz => 32,
71 AddrSz => 8)
75 AddrSz => 8)
72 PORT MAP (
76 PORT MAP (
73 clk => clk,
77 clk => CEL_clk,
74 rstn => rstn,
78 rstn => CEL_rstn,
75 reUse => '0',
79 reUse => '0',
76 ren => data_ren,
80 ren => CEL_data_ren,
77 rdata => data_out,
81 rdata => CEL_data_out,
78 wen => data_wen,
82 wen => CEL_data_wen,
79 wdata => wdata,
83 wdata => CEL_wdata,
80 empty => empty,
84 empty => CEL_empty,
81 full => full,
85 full => CEL_full,
82 almost_full => full_almost);
86 full_almost => CEL_full_almost,
83
87 empty_threshold => OPEN,
88 full_threshold => OPEN);
84 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
85
90 fifo_verif_CEL : fifo_verif
91 PORT MAP (
92 verif_clk => CEL_clk,
93 verif_rstn => CEL_rstn,
94 verif_ren => CEL_data_ren,
95 verif_rdata => CEL_data_out,
96 verif_wen => CEL_data_wen,
97 verif_wdata => CEL_wdata,
98 verif_empty => CEL_empty,
99 verif_full => CEL_full,
100 verif_almost_full => CEL_full_almost,
101 error_now => CEL_error_now,
102 error_new => CEL_error_new
103 );
104 -----------------------------------------------------------------------------
86
105
87
106
88 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
89 -- READ
108 lpp_fifo_RAM : lpp_fifo
109 GENERIC MAP (
110 tech => 0,
111 Mem_use => use_RAM,
112 EMPTY_THRESHOLD_LIMIT => 1,
113 FULL_THRESHOLD_LIMIT => 1,
114 DataSz => 32,
115 AddrSz => 8)
116 PORT MAP (
117 clk => RAM_clk,
118 rstn => RAM_rstn,
119 reUse => '0',
120 ren => RAM_data_ren,
121 rdata => RAM_data_out,
122 wen => RAM_data_wen,
123 wdata => RAM_wdata,
124 empty => RAM_empty,
125 full => RAM_full,
126 full_almost => RAM_full_almost,
127 empty_threshold => OPEN,
128 full_threshold => OPEN);
90 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
91 PROCESS (clk, rstn)
130 fifo_verif_RAM : fifo_verif
92 BEGIN -- PROCESS
131 PORT MAP (
93 IF rstn = '0' THEN -- asynchronous reset (active low)
132 verif_clk => RAM_clk,
94 empty_reg <= '1';
133 verif_rstn => RAM_rstn,
95 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
134 verif_ren => RAM_data_ren,
96 empty_reg <= empty;
135 verif_rdata => RAM_data_out,
97 END IF;
136 verif_wen => RAM_data_wen,
98 END PROCESS;
137 verif_wdata => RAM_wdata,
99
138 verif_empty => RAM_empty,
100 PROCESS (clk, rstn)
139 verif_full => RAM_full,
101 BEGIN -- PROCESS
140 verif_almost_full => RAM_full_almost,
102 IF rstn = '0' THEN -- asynchronous reset (active low)
141 error_now => RAM_error_now,
103 data_out_obs <= (OTHERS => '0');
142 error_new => RAM_error_new
104
143 );
105 pointer_read <= 0;
106 error_now <= '0';
107 error_new <= '0';
108
109 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
110 error_now <= '0';
111 IF empty_reg = '0' THEN
112 IF data_ren = '0' THEN
113 --IF data_ren_and_not_empty = '0' THEN
114 error_new <= '0';
115 data_out_obs <= data_out;
116
117 IF pointer_read < 127 THEN
118 pointer_read <= pointer_read + 1;
119 ELSE
120 pointer_read <= 0;
121 END IF;
122
123 IF data_out /= data_in(pointer_read) THEN
124 error_now <= '1';
125 error_new <= '1';
126 END IF;
127 END IF;
128
129 END IF;
130 END IF;
131 END PROCESS;
132 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
133
145
134
146
135
136
137 -----------------------------------------------------------------------------
138 -- WRITE
139 -----------------------------------------------------------------------------
140 PROCESS (clk, rstn)
141 BEGIN -- PROCESS
142 IF rstn = '0' THEN -- asynchronous reset (active low)
143 full_reg <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 full_reg <= full;
146 END IF;
147 END PROCESS;
148
149 proc_verif : PROCESS (clk, rstn)
150 BEGIN -- PROCESS proc_verif
151 IF rstn = '0' THEN -- asynchronous reset (active low)
152 pointer_write <= 0;
153 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
154 IF data_wen = '0' THEN
155 IF full_reg = '0' THEN
156 IF pointer_write < 127 THEN
157 pointer_write <= pointer_write+1;
158 ELSE
159 pointer_write <= 0;
160 END IF;
161 END IF;
162 END IF;
163 END IF;
164 END PROCESS proc_verif;
165
166 wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X');
167 -----------------------------------------------------------------------------
168
169
170
171 -----------------------------------------------------------------------------
172 clk <= NOT clk AFTER 5 ns; -- 100 MHz
173 -----------------------------------------------------------------------------
174 WaveGen_Proc : PROCESS
175 BEGIN
176 -- insert signal assignments here
177 WAIT UNTIL clk = '1';
178 read_stop <= '0';
179 rstn <= '0';
180 run <= '0';
181 WAIT UNTIL clk = '1';
182 WAIT UNTIL clk = '1';
183 WAIT UNTIL clk = '1';
184 rstn <= '1';
185 WAIT UNTIL clk = '1';
186 WAIT UNTIL clk = '1';
187 WAIT UNTIL clk = '1';
188 WAIT UNTIL clk = '1';
189 WAIT UNTIL clk = '1';
190 run <= '1';
191 WAIT UNTIL clk = '1';
192 WAIT UNTIL clk = '1';
193 WAIT UNTIL clk = '1';
194 WAIT UNTIL clk = '1';
195 WAIT FOR 10 us;
196 read_stop <= '1';
197 WAIT FOR 10 us;
198 read_stop <= '0';
199 WAIT FOR 80 us;
200 REPORT "*** END simulation ***" SEVERITY failure;
201 WAIT;
202 END PROCESS WaveGen_Proc;
203 -----------------------------------------------------------------------------
204
205
206
207 -----------------------------------------------------------------------------
208 -- RANDOM GENERATOR
209 -----------------------------------------------------------------------------
210 PROCESS (clk, rstn)
211 VARIABLE seed1, seed2 : POSITIVE;
212 VARIABLE rand1 : REAL;
213 VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
214 BEGIN -- PROCESS
215 IF rstn = '0' THEN -- asynchronous reset (active low)
216 random_vector <= (OTHERS => '0');
217 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
218 UNIFORM(seed1, seed2, rand1);
219 RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
220 to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
221 RANDOM_VECTOR_VAR'LENGTH)
222 );
223 random_vector <= RANDOM_VECTOR_VAR;
224 END IF;
225 END PROCESS;
226 -----------------------------------------------------------------------------
227 rand_wen <= random_vector(1);
228 rand_ren <= random_vector(0);
229 -----------------------------------------------------------------------------
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 data_wen <= '1';
234 data_ren <= '1';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 data_wen <= rand_wen;
237 IF read_stop = '0' THEN
238 data_ren <= rand_ren;
239 ELSE
240 data_ren <= '1';
241 END IF;
242 END IF;
243 END PROCESS;
244 -----------------------------------------------------------------------------
245
246
247
248 END;
147 END;
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@@ -1,35 +1,54
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group COMMON /testbench/clk
3 add wave -noupdate -expand -group FIFO_CEL -expand -group COMMON /testbench/cel_clk
4 add wave -noupdate -expand -group COMMON /testbench/rstn
4 add wave -noupdate -expand -group FIFO_CEL -expand -group COMMON /testbench/cel_rstn
5 add wave -noupdate -expand -group COMMON /testbench/run
5 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_data_out
6 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost
6 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_data_ren
7 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full
7 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_READ /testbench/cel_empty
8 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen
8 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_data_wen
9 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata
9 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_full
10 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty
10 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_full_almost
11 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren
11 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_WRITE /testbench/cel_wdata
12 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out
12 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_ERROR /testbench/cel_error_new
13 add wave -noupdate -radix hexadecimal /testbench/data_out_obs
13 add wave -noupdate -expand -group FIFO_CEL -expand -group FIFO_ERROR /testbench/cel_error_now
14 add wave -noupdate /testbench/pointer_read
14 add wave -noupdate -expand -group FIFO_RAM -group COMMON /testbench/ram_clk
15 add wave -noupdate /testbench/pointer_write
15 add wave -noupdate -expand -group FIFO_RAM -group COMMON /testbench/ram_rstn
16 add wave -noupdate /testbench/error_now
16 add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_data_out
17 add wave -noupdate /testbench/error_new
17 add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_data_ren
18 add wave -noupdate /testbench/read_stop
18 add wave -noupdate -expand -group FIFO_RAM -group FIFO_READ /testbench/ram_empty
19 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_data_wen
20 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_full
21 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_full_almost
22 add wave -noupdate -expand -group FIFO_RAM -group FIFO_WRITE /testbench/ram_wdata
23 add wave -noupdate -expand -group FIFO_RAM -expand -group FIFO_ERROR /testbench/ram_error_new
24 add wave -noupdate -expand -group FIFO_RAM -expand -group FIFO_ERROR /testbench/ram_error_now
25 add wave -noupdate -format Analog-Step -height 74 -max 256.0 /testbench/lpp_fifo_ram/lpp_fifo_control_1/space_busy
26 add wave -noupdate -format Analog-Step -height 74 -max 256.0 /testbench/lpp_fifo_ram/lpp_fifo_control_1/space_free
27 add wave -noupdate /testbench/fifo_verif_ram/read_stop
28 add wave -noupdate /testbench/fifo_verif_ram/write_stop
29 add wave -noupdate -expand -group EMPTY_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/empty
30 add wave -noupdate -expand -group EMPTY_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/empty_threshold
31 add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full
32 add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full_almost
33 add wave -noupdate -expand -group FULL_FIFO_RAM /testbench/lpp_fifo_ram/lpp_fifo_control_1/full_threshold
34 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/waddr_vect
35 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/raddr_vect
36 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/waddr_vect_s
37 add wave -noupdate -radix unsigned /testbench/lpp_fifo_ram/lpp_fifo_control_1/raddr_vect_s
19 TreeUpdate [SetDefaultTree]
38 TreeUpdate [SetDefaultTree]
20 WaveRestoreCursors {{Cursor 1} {56085000 ps} 0}
39 WaveRestoreCursors {{Cursor 1} {4865000 ps} 0}
21 configure wave -namecolwidth 510
40 configure wave -namecolwidth 510
22 configure wave -valuecolwidth 172
41 configure wave -valuecolwidth 172
23 configure wave -justifyvalue left
42 configure wave -justifyvalue left
24 configure wave -signalnamewidth 0
43 configure wave -signalnamewidth 0
25 configure wave -snapdistance 10
44 configure wave -snapdistance 10
26 configure wave -datasetprefix 0
45 configure wave -datasetprefix 0
27 configure wave -rowmargin 4
46 configure wave -rowmargin 4
28 configure wave -childrowmargin 2
47 configure wave -childrowmargin 2
29 configure wave -gridoffset 0
48 configure wave -gridoffset 0
30 configure wave -gridperiod 1
49 configure wave -gridperiod 1
31 configure wave -griddelta 40
50 configure wave -griddelta 40
32 configure wave -timeline 0
51 configure wave -timeline 0
33 configure wave -timelineunits ns
52 configure wave -timelineunits ns
34 update
53 update
35 WaveRestoreZoom {0 ps} {105131250 ps}
54 WaveRestoreZoom {0 ps} {127181250 ps}
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@@ -1,82 +1,90
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30
30
31 ENTITY lppFIFOxN IS
31 ENTITY lppFIFOxN IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 Data_sz : INTEGER RANGE 1 TO 32 := 8;
35 Data_sz : INTEGER RANGE 1 TO 32 := 8;
36 Addr_sz : INTEGER RANGE 2 TO 12 := 8;
36 Addr_sz : INTEGER RANGE 2 TO 12 := 8;
37 FifoCnt : INTEGER := 1
37 FifoCnt : INTEGER := 1
38 );
38 );
39 PORT(
39 PORT(
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42
42
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
43 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
44
44
45 run : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
46
45 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
47 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
46 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
48 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
47
49
48 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
50 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
51 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
50
52
51 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
53 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
52 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
54 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
53 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
55 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
54 );
56 );
55 END ENTITY;
57 END ENTITY;
56
58
57
59
58 ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
60 ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
59
61
60 BEGIN
62 BEGIN
61
63
62 fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
64 fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
63 lpp_fifo_1: lpp_fifo
65 lpp_fifo_1: lpp_fifo
64 GENERIC MAP (
66 GENERIC MAP (
65 tech => tech,
67 tech => tech,
66 Mem_use => Mem_use,
68 Mem_use => Mem_use,
69 EMPTY_THRESHOLD_LIMIT => 1,
70 FULL_THRESHOLD_LIMIT => 1,
67 DataSz => Data_sz,
71 DataSz => Data_sz,
68 AddrSz => Addr_sz)
72 AddrSz => Addr_sz)
69 PORT MAP (
73 PORT MAP (
70 clk => clk,
74 clk => clk,
71 rstn => rstn,
75 rstn => rstn,
72 reUse => reUse(I),
76 reUse => reUse(I),
77 run => run(I),
73 ren => ren(I),
78 ren => ren(I),
74 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
79 rdata => rdata( ((I+1)*Data_sz)-1 DOWNTO (I*Data_sz) ),
75 wen => wen(I),
80 wen => wen(I),
76 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
81 wdata => wdata(((I+1)*Data_sz)-1 DOWNTO (I*Data_sz)),
77 empty => empty(I),
82 empty => empty(I),
78 full => full(I),
83 full => full(I),
79 almost_full => almost_full(I));
84 full_almost => almost_full(I),
85 empty_threshold => OPEN,
86 full_threshold => OPEN
87 );
80 END GENERATE;
88 END GENERATE;
81
89
82 END ARCHITECTURE;
90 END ARCHITECTURE;
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@@ -1,190 +1,144
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
27 USE lpp.iir_filter.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30
30
31 ENTITY lpp_fifo IS
31 ENTITY lpp_fifo IS
32 GENERIC(
32 GENERIC(
33 tech : INTEGER := 0;
33 tech : INTEGER := 0;
34 Mem_use : INTEGER := use_RAM;
34 Mem_use : INTEGER := use_RAM;
35 DataSz : INTEGER RANGE 1 TO 32 := 8;
35 EMPTY_THRESHOLD_LIMIT : INTEGER := 16;
36 AddrSz : INTEGER RANGE 2 TO 12 := 8
36 FULL_THRESHOLD_LIMIT : INTEGER := 5;
37 DataSz : INTEGER RANGE 1 TO 32 := 8;
38 AddrSz : INTEGER RANGE 2 TO 12 := 8
37 );
39 );
38 PORT(
40 PORT(
39 clk : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
41 --
43 --
42 reUse : IN STD_LOGIC;
44 reUse : IN STD_LOGIC;
43
45 run : IN STD_LOGIC;
46
44 --IN
47 --IN
45 ren : IN STD_LOGIC;
48 ren : IN STD_LOGIC;
46 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
49 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
47
50
48 --OUT
51 --OUT
49 wen : IN STD_LOGIC;
52 wen : IN STD_LOGIC;
50 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
51
54
52 empty : OUT STD_LOGIC;
55 empty : OUT STD_LOGIC;
53 full : OUT STD_LOGIC;
56 full : OUT STD_LOGIC;
54 almost_full : OUT STD_LOGIC
57 full_almost : OUT STD_LOGIC;
58 empty_threshold : OUT STD_LOGIC;
59 full_threshold : OUT STD_LOGIC
55 );
60 );
56 END ENTITY;
61 END ENTITY;
57
62
58
63
59 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
64 ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
60
65
61 SIGNAL sFull : STD_LOGIC;
66 SIGNAL sREN : STD_LOGIC;
62 SIGNAL sFull_s : STD_LOGIC;
67 SIGNAL sWEN : STD_LOGIC;
63 SIGNAL sEmpty_s : STD_LOGIC;
68 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sWE : STD_LOGIC;
64
70
65 SIGNAL sEmpty : STD_LOGIC;
71 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
66 SIGNAL sREN : STD_LOGIC;
72 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
67 SIGNAL sWEN : STD_LOGIC;
68 SIGNAL sRE : STD_LOGIC;
69 SIGNAL sWE : STD_LOGIC;
70
73
71 SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72 SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
73 SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
74 SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
75
76 SIGNAL almost_full_s : STD_LOGIC;
77 SIGNAL almost_full_r : STD_LOGIC;
78 BEGIN
74 BEGIN
79
75
80 --==================================================================================
76 --==================================================================================
81 -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\
77 -- /!\ syncram_2p Write et Read actif a l'οΏ½tat haut /!\
82 -- A l'inverse de RAM_CEL !!!
78 -- A l'inverse de RAM_CEL !!!
83 --==================================================================================
79 --==================================================================================
84 memRAM : IF Mem_use = use_RAM GENERATE
80 memRAM : IF Mem_use = use_RAM GENERATE
85 SRAM : syncram_2p
81 SRAM : syncram_2p
86 GENERIC MAP(tech, AddrSz, DataSz)
82 GENERIC MAP(tech, AddrSz, DataSz)
87 PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
83 PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
88 END GENERATE;
84 END GENERATE;
89 --==================================================================================
85 --==================================================================================
90 memCEL : IF Mem_use = use_CEL GENERATE
86 memCEL : IF Mem_use = use_CEL GENERATE
91 CRAM : RAM_CEL
87 CRAM : RAM_CEL
92 GENERIC MAP(DataSz, AddrSz)
88 GENERIC MAP(DataSz, AddrSz)
93 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
89 PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
94 END GENERATE;
90 END GENERATE;
95 --==================================================================================
91 --==================================================================================
96
92 sRE <= NOT sREN;
97 --=============================
93 sWE <= NOT sWEN;
98 -- Read section
99 --=============================
100 sREN <= REN OR sEmpty;
101 sRE <= NOT sREN;
102
103 sEmpty_s <= '0' WHEN ReUse = '1' else
104 '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
105 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
106 '0';
107
108 Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
109
110 PROCESS (clk, rstn)
111 BEGIN
112 IF(rstn = '0')then
113 Raddr_vect <= (OTHERS => '0');
114 sempty <= '1';
115 ELSIF(clk'EVENT AND clk = '1')then
116 sEmpty <= sempty_s;
117
118 IF(sREN = '0' and sempty = '0')then
119 Raddr_vect <= Raddr_vect_s;
120 END IF;
121
122 END IF;
123 END PROCESS;
124
125 --=============================
126 -- Write section
127 --=============================
128 sWEN <= WEN OR sFull;
129 sWE <= NOT sWEN;
130
131 sFull_s <= '1' WHEN ReUse = '1' else
132 '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
133 '1' WHEN sFull = '1' AND REN = '1' ELSE
134 '0';
135
136 almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
137 '1' WHEN almost_full_r = '1' AND WEN = REN ELSE
138 '0';
139
140 Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
141
142 PROCESS (clk, rstn)
143 BEGIN
144 IF(rstn = '0')then
145 Waddr_vect <= (OTHERS => '0');
146 sfull <= '0';
147 almost_full_r <= '0';
148 ELSIF(clk'EVENT AND clk = '1')then
149 sfull <= sfull_s;
150 almost_full_r <= almost_full_s;
151
152 IF(sWEN = '0' and sfull = '0')THEN
153 Waddr_vect <= Waddr_vect_s;
154 END IF;
155
156 END IF;
157 END PROCESS;
158
159 almost_full <= almost_full_s;
160 full <= sFull_s;
161 empty <= sEmpty_s;
162
94
163
95
164
96 lpp_fifo_control_1 : lpp_fifo_control
97 GENERIC MAP (
98 AddrSz => AddrSz,
99 EMPTY_THRESHOLD_LIMIT => EMPTY_THRESHOLD_LIMIT,
100 FULL_THRESHOLD_LIMIT => FULL_THRESHOLD_LIMIT)
101 PORT MAP (
102 clk => clk,
103 rstn => rstn,
104 run => run,
105 reUse => reUse,
106 fifo_r_en => ren,
107 fifo_w_en => wen,
108 mem_r_en => sREN,
109 mem_w_en => SWEN,
110 mem_r_addr => Raddr_vect,
111 mem_w_addr => Waddr_vect,
112 empty => empty,
113 full => full,
114 full_almost => full_almost,
115 empty_threshold => empty_threshold,
116 full_threshold => full_threshold);
117
118
165 END ARCHITECTURE;
119 END ARCHITECTURE;
166
120
167
121
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127
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128
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@@ -1,241 +1,279
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY ieee;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
23 USE ieee.std_logic_1164.ALL;
24 LIBRARY grlib;
24 LIBRARY grlib;
25 USE grlib.amba.ALL;
25 USE grlib.amba.ALL;
26 USE std.textio.ALL;
26 USE std.textio.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_amba.ALL;
28 USE lpp.lpp_amba.ALL;
29 USE lpp.iir_filter.ALL;
29 USE lpp.iir_filter.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.misc.ALL;
31 USE gaisler.misc.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
37
37
38 PACKAGE lpp_memory IS
38 PACKAGE lpp_memory IS
39
39
40 COMPONENT lpp_fifo
40 COMPONENT lpp_fifo
41 GENERIC (
41 GENERIC (
42 tech : INTEGER;
42 tech : INTEGER;
43 Mem_use : INTEGER;
43 Mem_use : INTEGER;
44 DataSz : INTEGER RANGE 1 TO 32;
44 EMPTY_THRESHOLD_LIMIT : INTEGER;
45 AddrSz : INTEGER RANGE 2 TO 12);
45 FULL_THRESHOLD_LIMIT : INTEGER;
46 DataSz : INTEGER RANGE 1 TO 32;
47 AddrSz : INTEGER RANGE 2 TO 12);
48 PORT (
49 clk : IN STD_LOGIC;
50 rstn : IN STD_LOGIC;
51 reUse : IN STD_LOGIC;
52 run : IN STD_LOGIC;
53 ren : IN STD_LOGIC;
54 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
55 wen : IN STD_LOGIC;
56 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
57 empty : OUT STD_LOGIC;
58 full : OUT STD_LOGIC;
59 full_almost : OUT STD_LOGIC;
60 empty_threshold : OUT STD_LOGIC;
61 full_threshold : OUT STD_LOGIC);
62 END COMPONENT;
63
64 COMPONENT lpp_fifo_4_shared
65 GENERIC (
66 tech : INTEGER;
67 Mem_use : INTEGER;
68 EMPTY_THRESHOLD_LIMIT : INTEGER;
69 FULL_THRESHOLD_LIMIT : INTEGER;
70 DataSz : INTEGER RANGE 1 TO 32;
71 AddrSz : INTEGER RANGE 3 TO 12);
72 PORT (
73 clk : IN STD_LOGIC;
74 rstn : IN STD_LOGIC;
75 run : IN STD_LOGIC;
76 empty_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 r_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 r_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 full_threshold : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 w_en : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
84 w_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
85 END COMPONENT;
86
87 COMPONENT lpp_fifo_4_shared_headreg_latency_0
46 PORT (
88 PORT (
47 clk : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
48 rstn : IN STD_LOGIC;
90 rstn : IN STD_LOGIC;
49 reUse : IN STD_LOGIC;
91 run : IN STD_LOGIC;
50 ren : IN STD_LOGIC;
92 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
51 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
93 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
52 wen : IN STD_LOGIC;
94 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
95 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54 empty : OUT STD_LOGIC;
96 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 full : OUT STD_LOGIC;
97 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 almost_full : OUT STD_LOGIC);
98 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
103 END COMPONENT;
104
105 COMPONENT lpp_fifo_4_shared_headreg_latency_1
106 PORT (
107 clk : IN STD_LOGIC;
108 rstn : IN STD_LOGIC;
109 run : IN STD_LOGIC;
110 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
111 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
112 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
113 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
119 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
120 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
121 END COMPONENT;
122
123 COMPONENT lpp_fifo_control
124 GENERIC (
125 AddrSz : INTEGER RANGE 2 TO 12;
126 EMPTY_THRESHOLD_LIMIT : INTEGER;
127 FULL_THRESHOLD_LIMIT : INTEGER);
128 PORT (
129 clk : IN STD_LOGIC;
130 rstn : IN STD_LOGIC;
131 reUse : IN STD_LOGIC;
132 run : IN STD_LOGIC;
133 fifo_r_en : IN STD_LOGIC;
134 fifo_w_en : IN STD_LOGIC;
135 mem_r_en : OUT STD_LOGIC;
136 mem_w_en : OUT STD_LOGIC;
137 mem_r_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
138 mem_w_addr : OUT STD_LOGIC_VECTOR(AddrSz -1 DOWNTO 0);
139 empty : OUT STD_LOGIC;
140 full : OUT STD_LOGIC;
141 full_almost : OUT STD_LOGIC;
142 empty_threshold : OUT STD_LOGIC;
143 full_threshold : OUT STD_LOGIC);
57 END COMPONENT;
144 END COMPONENT;
58
145
59 COMPONENT lppFIFOxN
146 COMPONENT lppFIFOxN
60 GENERIC (
147 GENERIC (
61 tech : INTEGER;
148 tech : INTEGER;
62 Mem_use : INTEGER;
149 Mem_use : INTEGER;
63 Data_sz : INTEGER RANGE 1 TO 32;
150 Data_sz : INTEGER RANGE 1 TO 32;
64 Addr_sz : INTEGER RANGE 2 TO 12;
151 Addr_sz : INTEGER RANGE 2 TO 12;
65 FifoCnt : INTEGER);
152 FifoCnt : INTEGER);
66 PORT (
153 PORT (
67 clk : IN STD_LOGIC;
154 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
155 rstn : IN STD_LOGIC;
69 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
156 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
157 run : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
70 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
158 wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
71 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
159 wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
72 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
160 ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
73 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
161 rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
74 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
162 empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
75 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
163 full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
76 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
164 almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
77 END COMPONENT;
165 END COMPONENT;
78
166
79
167
80
168
81
169
82 COMPONENT APB_FIFO IS
170 COMPONENT APB_FIFO IS
83 GENERIC (
171 GENERIC (
84 tech : INTEGER := apa3;
172 tech : INTEGER := apa3;
85 pindex : INTEGER := 0;
173 pindex : INTEGER := 0;
86 paddr : INTEGER := 0;
174 paddr : INTEGER := 0;
87 pmask : INTEGER := 16#fff#;
175 pmask : INTEGER := 16#fff#;
88 pirq : INTEGER := 0;
176 pirq : INTEGER := 0;
89 abits : INTEGER := 8;
177 abits : INTEGER := 8;
90 FifoCnt : INTEGER := 2;
178 FifoCnt : INTEGER := 2;
91 Data_sz : INTEGER := 16;
179 Data_sz : INTEGER := 16;
92 Addr_sz : INTEGER := 9;
180 Addr_sz : INTEGER := 9;
93 Enable_ReUse : STD_LOGIC := '0';
181 Enable_ReUse : STD_LOGIC := '0';
94 Mem_use : INTEGER := use_RAM;
182 Mem_use : INTEGER := use_RAM;
95 R : INTEGER := 1;
183 R : INTEGER := 1;
96 W : INTEGER := 1
184 W : INTEGER := 1
97 );
185 );
98 PORT (
186 PORT (
99 clk : IN STD_LOGIC; --! Horloge du composant
187 clk : IN STD_LOGIC; --! Horloge du composant
100 rst : IN STD_LOGIC; --! Reset general du composant
188 rst : IN STD_LOGIC; --! Reset general du composant
101 rclk : IN STD_LOGIC;
189 rclk : IN STD_LOGIC;
102 wclk : IN STD_LOGIC;
190 wclk : IN STD_LOGIC;
103 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
191 ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
104 REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire
192 REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en mοΏ½moire
105 WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire
193 WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'οΏ½criture en mοΏ½moire
106 Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide
194 Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire vide
107 Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine
195 Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, MοΏ½moire pleine
108 RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e
196 RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en entrοΏ½e
109 WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie
197 WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donnοΏ½es en sortie
110 WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture)
198 WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (οΏ½criture)
111 RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
199 RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
112 apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
200 apbi : IN apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
113 apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
201 apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
114 );
202 );
115 END COMPONENT;
203 END COMPONENT;
116
204
117 COMPONENT FIFO_pipeline IS
205 COMPONENT FIFO_pipeline IS
118 GENERIC(
206 GENERIC(
119 tech : INTEGER := 0;
207 tech : INTEGER := 0;
120 Mem_use : INTEGER := use_RAM;
208 Mem_use : INTEGER := use_RAM;
121 fifoCount : INTEGER RANGE 2 TO 32 := 8;
209 fifoCount : INTEGER RANGE 2 TO 32 := 8;
122 DataSz : INTEGER RANGE 1 TO 32 := 8;
210 DataSz : INTEGER RANGE 1 TO 32 := 8;
123 abits : INTEGER RANGE 2 TO 12 := 8
211 abits : INTEGER RANGE 2 TO 12 := 8
124 );
212 );
125 PORT(
213 PORT(
126 rstn : IN STD_LOGIC;
214 rstn : IN STD_LOGIC;
127 ReUse : IN STD_LOGIC;
215 ReUse : IN STD_LOGIC;
128 rclk : IN STD_LOGIC;
216 rclk : IN STD_LOGIC;
129 ren : IN STD_LOGIC;
217 ren : IN STD_LOGIC;
130 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
218 rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
131 empty : OUT STD_LOGIC;
219 empty : OUT STD_LOGIC;
132 raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
220 raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
133 wclk : IN STD_LOGIC;
221 wclk : IN STD_LOGIC;
134 wen : IN STD_LOGIC;
222 wen : IN STD_LOGIC;
135 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
223 wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
136 full : OUT STD_LOGIC;
224 full : OUT STD_LOGIC;
137 waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
225 waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
138 );
226 );
139 END COMPONENT;
227 END COMPONENT;
140
228
141 --COMPONENT lpp_fifo IS
142 -- GENERIC(
143 -- tech : INTEGER := 0;
144 -- Mem_use : INTEGER := use_RAM;
145 -- Enable_ReUse : STD_LOGIC := '0';
146 -- DataSz : INTEGER RANGE 1 TO 32 := 8;
147 -- AddrSz : INTEGER RANGE 2 TO 12 := 8
148 -- );
149 -- PORT(
150 -- rstn : IN STD_LOGIC;
151 -- ReUse : IN STD_LOGIC; --27/01/12
152 -- rclk : IN STD_LOGIC;
153 -- ren : IN STD_LOGIC;
154 -- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
155 -- empty : OUT STD_LOGIC;
156 -- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
157 -- wclk : IN STD_LOGIC;
158 -- wen : IN STD_LOGIC;
159 -- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
160 -- full : OUT STD_LOGIC;
161 -- almost_full : OUT STD_LOGIC;
162 -- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
163 -- );
164 --END COMPONENT;
165
166
167 --COMPONENT lppFIFOxN IS
168 -- GENERIC(
169 -- tech : INTEGER := 0;
170 -- Mem_use : INTEGER := use_RAM;
171 -- Data_sz : INTEGER RANGE 1 TO 32 := 8;
172 -- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
173 -- FifoCnt : INTEGER := 1;
174 -- Enable_ReUse : STD_LOGIC := '0'
175 -- );
176 -- PORT(
177 -- rstn : IN STD_LOGIC;
178 -- wclk : IN STD_LOGIC;
179 -- rclk : IN STD_LOGIC;
180 -- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
181 -- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
182 -- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
183 -- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
184 -- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
185 -- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
186 -- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
187 -- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
188 -- );
189 --END COMPONENT;
190
191 COMPONENT FillFifo IS
229 COMPONENT FillFifo IS
192 GENERIC(
230 GENERIC(
193 Data_sz : INTEGER RANGE 1 TO 32 := 16;
231 Data_sz : INTEGER RANGE 1 TO 32 := 16;
194 Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
232 Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
195 );
233 );
196 PORT(
234 PORT(
197 clk : IN STD_LOGIC;
235 clk : IN STD_LOGIC;
198 raz : IN STD_LOGIC;
236 raz : IN STD_LOGIC;
199 write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
237 write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
200 reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
238 reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
201 data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
239 data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
202 );
240 );
203 END COMPONENT;
241 END COMPONENT;
204
242
205 COMPONENT Bridge IS
243 COMPONENT Bridge IS
206 PORT(
244 PORT(
207 clk : IN STD_LOGIC;
245 clk : IN STD_LOGIC;
208 raz : IN STD_LOGIC;
246 raz : IN STD_LOGIC;
209 EmptyUp : IN STD_LOGIC;
247 EmptyUp : IN STD_LOGIC;
210 FullDwn : IN STD_LOGIC;
248 FullDwn : IN STD_LOGIC;
211 WriteDwn : OUT STD_LOGIC;
249 WriteDwn : OUT STD_LOGIC;
212 ReadUp : OUT STD_LOGIC
250 ReadUp : OUT STD_LOGIC
213 );
251 );
214 END COMPONENT;
252 END COMPONENT;
215
253
216 COMPONENT ssram_plugin IS
254 COMPONENT ssram_plugin IS
217 GENERIC (tech : INTEGER := 0);
255 GENERIC (tech : INTEGER := 0);
218 PORT
256 PORT
219 (
257 (
220 clk : IN STD_LOGIC;
258 clk : IN STD_LOGIC;
221 mem_ctrlr_o : IN memory_out_type;
259 mem_ctrlr_o : IN memory_out_type;
222 SSRAM_CLK : OUT STD_LOGIC;
260 SSRAM_CLK : OUT STD_LOGIC;
223 nBWa : OUT STD_LOGIC;
261 nBWa : OUT STD_LOGIC;
224 nBWb : OUT STD_LOGIC;
262 nBWb : OUT STD_LOGIC;
225 nBWc : OUT STD_LOGIC;
263 nBWc : OUT STD_LOGIC;
226 nBWd : OUT STD_LOGIC;
264 nBWd : OUT STD_LOGIC;
227 nBWE : OUT STD_LOGIC;
265 nBWE : OUT STD_LOGIC;
228 nADSC : OUT STD_LOGIC;
266 nADSC : OUT STD_LOGIC;
229 nADSP : OUT STD_LOGIC;
267 nADSP : OUT STD_LOGIC;
230 nADV : OUT STD_LOGIC;
268 nADV : OUT STD_LOGIC;
231 nGW : OUT STD_LOGIC;
269 nGW : OUT STD_LOGIC;
232 nCE1 : OUT STD_LOGIC;
270 nCE1 : OUT STD_LOGIC;
233 CE2 : OUT STD_LOGIC;
271 CE2 : OUT STD_LOGIC;
234 nCE3 : OUT STD_LOGIC;
272 nCE3 : OUT STD_LOGIC;
235 nOE : OUT STD_LOGIC;
273 nOE : OUT STD_LOGIC;
236 MODE : OUT STD_LOGIC;
274 MODE : OUT STD_LOGIC;
237 ZZ : OUT STD_LOGIC
275 ZZ : OUT STD_LOGIC
238 );
276 );
239 END COMPONENT;
277 END COMPONENT;
240
278
241 END;
279 END;
Show file before | Show file after | Hide comments
@@ -1,4 +1,9
1 lpp_memory.vhd
1 lpp_memory.vhd
2 lpp_FIFO.vhd
2 lpp_FIFO.vhd
3 lpp_FIFO_4_Shared.vhd
4 lpp_FIFO_control.vhd
5 lpp_FIFO_4_Shared_headreg_latency_0.vhd
6 lpp_FIFO_4_Shared_headreg_latency_1.vhd
3 lppFIFOxN.vhd
7 lppFIFOxN.vhd
4
8
9
Show file before | Show file after | Hide comments
@@ -1,748 +1,751
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 --
64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
67
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
69
70 --debug
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
79
80 ---- debug FIFO_IN
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
89
90 ----debug FIFO OUT
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
99
100 ----debug DMA IN
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 );
109 );
110 END lpp_lfr;
110 END lpp_lfr;
111
111
112 ARCHITECTURE beh OF lpp_lfr IS
112 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 --
115 --
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
120 --
121 --
121 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 --
125 --
125 SIGNAL sample_f0_val : STD_LOGIC;
126 SIGNAL sample_f0_val : STD_LOGIC;
126 SIGNAL sample_f1_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
127 SIGNAL sample_f2_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
128 SIGNAL sample_f3_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
129 --
130 --
130 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 --
135 --
135 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138
139
139 -- SM
140 -- SM
140 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 SIGNAL error_bad_component_error : STD_LOGIC;
146 SIGNAL error_bad_component_error : STD_LOGIC;
146 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 SIGNAL config_active_interruption_onError : STD_LOGIC;
155 SIGNAL config_active_interruption_onError : STD_LOGIC;
155 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159
160
160 -- WFP
161 -- WFP
161 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
167 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
167 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
168 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
168 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170
171
171 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
172 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
172 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
173 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
173 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
174 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
174 SIGNAL enable_f0 : STD_LOGIC;
175 SIGNAL enable_f0 : STD_LOGIC;
175 SIGNAL enable_f1 : STD_LOGIC;
176 SIGNAL enable_f1 : STD_LOGIC;
176 SIGNAL enable_f2 : STD_LOGIC;
177 SIGNAL enable_f2 : STD_LOGIC;
177 SIGNAL enable_f3 : STD_LOGIC;
178 SIGNAL enable_f3 : STD_LOGIC;
178 SIGNAL burst_f0 : STD_LOGIC;
179 SIGNAL burst_f0 : STD_LOGIC;
179 SIGNAL burst_f1 : STD_LOGIC;
180 SIGNAL burst_f1 : STD_LOGIC;
180 SIGNAL burst_f2 : STD_LOGIC;
181 SIGNAL burst_f2 : STD_LOGIC;
181 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185
186
186 SIGNAL run : STD_LOGIC;
187 SIGNAL run : STD_LOGIC;
187 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
188 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
188
189
189 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f0_data_out_valid : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
193 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
193 SIGNAL data_f0_data_out_ren : STD_LOGIC;
194 SIGNAL data_f0_data_out_ren : STD_LOGIC;
194 --f1
195 --f1
195 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f1_data_out_valid : STD_LOGIC;
198 SIGNAL data_f1_data_out_valid : STD_LOGIC;
198 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
199 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
199 SIGNAL data_f1_data_out_ren : STD_LOGIC;
200 SIGNAL data_f1_data_out_ren : STD_LOGIC;
200 --f2
201 --f2
201 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f2_data_out_valid : STD_LOGIC;
204 SIGNAL data_f2_data_out_valid : STD_LOGIC;
204 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
205 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
205 SIGNAL data_f2_data_out_ren : STD_LOGIC;
206 SIGNAL data_f2_data_out_ren : STD_LOGIC;
206 --f3
207 --f3
207 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL data_f3_data_out_valid : STD_LOGIC;
210 SIGNAL data_f3_data_out_valid : STD_LOGIC;
210 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
211 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
211 SIGNAL data_f3_data_out_ren : STD_LOGIC;
212 SIGNAL data_f3_data_out_ren : STD_LOGIC;
212
213
213 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
214 --
215 --
215 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
216 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
219 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
219 --f1
220 --f1
220 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
223 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
223 --f2
224 --f2
224 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
227 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
227 --f3
228 --f3
228 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
230 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
230 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
231 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
231
232
232 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
233 -- DMA RR
234 -- DMA RR
234 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
235 SIGNAL dma_sel_valid : STD_LOGIC;
236 SIGNAL dma_sel_valid : STD_LOGIC;
236 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
237 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
237 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
240 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
240
241
241 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
242 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
242 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
243 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
243
244
244 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
245 -- DMA_REG
246 -- DMA_REG
246 -----------------------------------------------------------------------------
247 -----------------------------------------------------------------------------
247 SIGNAL ongoing_reg : STD_LOGIC;
248 SIGNAL ongoing_reg : STD_LOGIC;
248 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
249 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
249 SIGNAL dma_send_reg : STD_LOGIC;
250 SIGNAL dma_send_reg : STD_LOGIC;
250 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
251 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
251 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
253
254
254
255
255 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
256 -- DMA
257 -- DMA
257 -----------------------------------------------------------------------------
258 -----------------------------------------------------------------------------
258 SIGNAL dma_send : STD_LOGIC;
259 SIGNAL dma_send : STD_LOGIC;
259 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
260 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
260 SIGNAL dma_done : STD_LOGIC;
261 SIGNAL dma_done : STD_LOGIC;
261 SIGNAL dma_ren : STD_LOGIC;
262 SIGNAL dma_ren : STD_LOGIC;
262 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265
266
266 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
267 -- MS
268 -- MS
268 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
269
270
270 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL data_ms_valid : STD_LOGIC;
273 SIGNAL data_ms_valid : STD_LOGIC;
273 SIGNAL data_ms_valid_burst : STD_LOGIC;
274 SIGNAL data_ms_valid_burst : STD_LOGIC;
274 SIGNAL data_ms_ren : STD_LOGIC;
275 SIGNAL data_ms_ren : STD_LOGIC;
275 SIGNAL data_ms_done : STD_LOGIC;
276 SIGNAL data_ms_done : STD_LOGIC;
276 SIGNAL dma_ms_ongoing : STD_LOGIC;
277 SIGNAL dma_ms_ongoing : STD_LOGIC;
277
278
278 SIGNAL run_ms : STD_LOGIC;
279 SIGNAL run_ms : STD_LOGIC;
279 SIGNAL ms_softandhard_rstn : STD_LOGIC;
280 SIGNAL ms_softandhard_rstn : STD_LOGIC;
280
281
281 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
282 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
282 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285
286
286
287
287 SIGNAL error_buffer_full : STD_LOGIC;
288 SIGNAL error_buffer_full : STD_LOGIC;
288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
289 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
289
290
290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
292 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
292
293
293 BEGIN
294 BEGIN
294
295
295 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
296 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
296 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
297 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
297
298
298 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
299 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
299 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
300 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
300 --END GENERATE all_channel;
301 --END GENERATE all_channel;
301
302
302 -----------------------------------------------------------------------------
303 -----------------------------------------------------------------------------
303 lpp_lfr_filter_1 : lpp_lfr_filter
304 lpp_lfr_filter_1 : lpp_lfr_filter
304 GENERIC MAP (
305 GENERIC MAP (
305 Mem_use => Mem_use)
306 Mem_use => Mem_use)
306 PORT MAP (
307 PORT MAP (
307 sample => sample_s,
308 sample => sample_s,
308 sample_val => sample_val,
309 sample_val => sample_val,
309 clk => clk,
310 clk => clk,
310 rstn => rstn,
311 rstn => rstn,
311 data_shaping_SP0 => data_shaping_SP0,
312 data_shaping_SP0 => data_shaping_SP0,
312 data_shaping_SP1 => data_shaping_SP1,
313 data_shaping_SP1 => data_shaping_SP1,
313 data_shaping_R0 => data_shaping_R0,
314 data_shaping_R0 => data_shaping_R0,
314 data_shaping_R1 => data_shaping_R1,
315 data_shaping_R1 => data_shaping_R1,
316 data_shaping_R2 => data_shaping_R2,
315 sample_f0_val => sample_f0_val,
317 sample_f0_val => sample_f0_val,
316 sample_f1_val => sample_f1_val,
318 sample_f1_val => sample_f1_val,
317 sample_f2_val => sample_f2_val,
319 sample_f2_val => sample_f2_val,
318 sample_f3_val => sample_f3_val,
320 sample_f3_val => sample_f3_val,
319 sample_f0_wdata => sample_f0_data,
321 sample_f0_wdata => sample_f0_data,
320 sample_f1_wdata => sample_f1_data,
322 sample_f1_wdata => sample_f1_data,
321 sample_f2_wdata => sample_f2_data,
323 sample_f2_wdata => sample_f2_data,
322 sample_f3_wdata => sample_f3_data);
324 sample_f3_wdata => sample_f3_data);
323
325
324 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
325 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
327 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
326 GENERIC MAP (
328 GENERIC MAP (
327 nb_data_by_buffer_size => nb_data_by_buffer_size,
329 nb_data_by_buffer_size => nb_data_by_buffer_size,
328 nb_word_by_buffer_size => nb_word_by_buffer_size,
330 nb_word_by_buffer_size => nb_word_by_buffer_size,
329 nb_snapshot_param_size => nb_snapshot_param_size,
331 nb_snapshot_param_size => nb_snapshot_param_size,
330 delta_vector_size => delta_vector_size,
332 delta_vector_size => delta_vector_size,
331 delta_vector_size_f0_2 => delta_vector_size_f0_2,
333 delta_vector_size_f0_2 => delta_vector_size_f0_2,
332 pindex => pindex,
334 pindex => pindex,
333 paddr => paddr,
335 paddr => paddr,
334 pmask => pmask,
336 pmask => pmask,
335 pirq_ms => pirq_ms,
337 pirq_ms => pirq_ms,
336 pirq_wfp => pirq_wfp,
338 pirq_wfp => pirq_wfp,
337 top_lfr_version => top_lfr_version)
339 top_lfr_version => top_lfr_version)
338 PORT MAP (
340 PORT MAP (
339 HCLK => clk,
341 HCLK => clk,
340 HRESETn => rstn,
342 HRESETn => rstn,
341 apbi => apbi,
343 apbi => apbi,
342 apbo => apbo,
344 apbo => apbo,
343
345
344 run_ms => run_ms,
346 run_ms => run_ms,
345
347
346 ready_matrix_f0 => ready_matrix_f0,
348 ready_matrix_f0 => ready_matrix_f0,
347 -- ready_matrix_f0_1 => ready_matrix_f0_1,
349 -- ready_matrix_f0_1 => ready_matrix_f0_1,
348 ready_matrix_f1 => ready_matrix_f1,
350 ready_matrix_f1 => ready_matrix_f1,
349 ready_matrix_f2 => ready_matrix_f2,
351 ready_matrix_f2 => ready_matrix_f2,
350 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
352 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
351 error_bad_component_error => error_bad_component_error,
353 error_bad_component_error => error_bad_component_error,
352 error_buffer_full => error_buffer_full, -- TODO
354 error_buffer_full => error_buffer_full, -- TODO
353 error_input_fifo_write => error_input_fifo_write, -- TODO
355 error_input_fifo_write => error_input_fifo_write, -- TODO
354 -- debug_reg => debug_reg,
356 -- debug_reg => debug_reg,
355 status_ready_matrix_f0 => status_ready_matrix_f0,
357 status_ready_matrix_f0 => status_ready_matrix_f0,
356 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
358 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
357 status_ready_matrix_f1 => status_ready_matrix_f1,
359 status_ready_matrix_f1 => status_ready_matrix_f1,
358 status_ready_matrix_f2 => status_ready_matrix_f2,
360 status_ready_matrix_f2 => status_ready_matrix_f2,
359 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
361 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
360 -- status_error_bad_component_error => status_error_bad_component_error,
362 -- status_error_bad_component_error => status_error_bad_component_error,
361 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
363 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
362 config_active_interruption_onError => config_active_interruption_onError,
364 config_active_interruption_onError => config_active_interruption_onError,
363
365
364 matrix_time_f0 => matrix_time_f0,
366 matrix_time_f0 => matrix_time_f0,
365 -- matrix_time_f0_1 => matrix_time_f0_1,
367 -- matrix_time_f0_1 => matrix_time_f0_1,
366 matrix_time_f1 => matrix_time_f1,
368 matrix_time_f1 => matrix_time_f1,
367 matrix_time_f2 => matrix_time_f2,
369 matrix_time_f2 => matrix_time_f2,
368
370
369 addr_matrix_f0 => addr_matrix_f0,
371 addr_matrix_f0 => addr_matrix_f0,
370 -- addr_matrix_f0_1 => addr_matrix_f0_1,
372 -- addr_matrix_f0_1 => addr_matrix_f0_1,
371 addr_matrix_f1 => addr_matrix_f1,
373 addr_matrix_f1 => addr_matrix_f1,
372 addr_matrix_f2 => addr_matrix_f2,
374 addr_matrix_f2 => addr_matrix_f2,
373 -------------------------------------------------------------------------
375 -------------------------------------------------------------------------
374 status_full => status_full,
376 status_full => status_full,
375 status_full_ack => status_full_ack,
377 status_full_ack => status_full_ack,
376 status_full_err => status_full_err,
378 status_full_err => status_full_err,
377 status_new_err => status_new_err,
379 status_new_err => status_new_err,
378 data_shaping_BW => data_shaping_BW,
380 data_shaping_BW => data_shaping_BW,
379 data_shaping_SP0 => data_shaping_SP0,
381 data_shaping_SP0 => data_shaping_SP0,
380 data_shaping_SP1 => data_shaping_SP1,
382 data_shaping_SP1 => data_shaping_SP1,
381 data_shaping_R0 => data_shaping_R0,
383 data_shaping_R0 => data_shaping_R0,
382 data_shaping_R1 => data_shaping_R1,
384 data_shaping_R1 => data_shaping_R1,
385 data_shaping_R2 => data_shaping_R2,
383 delta_snapshot => delta_snapshot,
386 delta_snapshot => delta_snapshot,
384 delta_f0 => delta_f0,
387 delta_f0 => delta_f0,
385 delta_f0_2 => delta_f0_2,
388 delta_f0_2 => delta_f0_2,
386 delta_f1 => delta_f1,
389 delta_f1 => delta_f1,
387 delta_f2 => delta_f2,
390 delta_f2 => delta_f2,
388 nb_data_by_buffer => nb_data_by_buffer,
391 nb_data_by_buffer => nb_data_by_buffer,
389 nb_word_by_buffer => nb_word_by_buffer,
392 nb_word_by_buffer => nb_word_by_buffer,
390 nb_snapshot_param => nb_snapshot_param,
393 nb_snapshot_param => nb_snapshot_param,
391 enable_f0 => enable_f0,
394 enable_f0 => enable_f0,
392 enable_f1 => enable_f1,
395 enable_f1 => enable_f1,
393 enable_f2 => enable_f2,
396 enable_f2 => enable_f2,
394 enable_f3 => enable_f3,
397 enable_f3 => enable_f3,
395 burst_f0 => burst_f0,
398 burst_f0 => burst_f0,
396 burst_f1 => burst_f1,
399 burst_f1 => burst_f1,
397 burst_f2 => burst_f2,
400 burst_f2 => burst_f2,
398 run => run,
401 run => run,
399 addr_data_f0 => addr_data_f0,
402 addr_data_f0 => addr_data_f0,
400 addr_data_f1 => addr_data_f1,
403 addr_data_f1 => addr_data_f1,
401 addr_data_f2 => addr_data_f2,
404 addr_data_f2 => addr_data_f2,
402 addr_data_f3 => addr_data_f3,
405 addr_data_f3 => addr_data_f3,
403 start_date => start_date,
406 start_date => start_date,
404 debug_signal => debug_signal);
407 debug_signal => debug_signal);
405
408
406 -----------------------------------------------------------------------------
409 -----------------------------------------------------------------------------
407 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
408 lpp_waveform_1 : lpp_waveform
411 lpp_waveform_1 : lpp_waveform
409 GENERIC MAP (
412 GENERIC MAP (
410 tech => inferred,
413 tech => inferred,
411 data_size => 6*16,
414 data_size => 6*16,
412 nb_data_by_buffer_size => nb_data_by_buffer_size,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
413 nb_word_by_buffer_size => nb_word_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
414 nb_snapshot_param_size => nb_snapshot_param_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
415 delta_vector_size => delta_vector_size,
418 delta_vector_size => delta_vector_size,
416 delta_vector_size_f0_2 => delta_vector_size_f0_2
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
417 )
420 )
418 PORT MAP (
421 PORT MAP (
419 clk => clk,
422 clk => clk,
420 rstn => rstn,
423 rstn => rstn,
421
424
422 reg_run => run,
425 reg_run => run,
423 reg_start_date => start_date,
426 reg_start_date => start_date,
424 reg_delta_snapshot => delta_snapshot,
427 reg_delta_snapshot => delta_snapshot,
425 reg_delta_f0 => delta_f0,
428 reg_delta_f0 => delta_f0,
426 reg_delta_f0_2 => delta_f0_2,
429 reg_delta_f0_2 => delta_f0_2,
427 reg_delta_f1 => delta_f1,
430 reg_delta_f1 => delta_f1,
428 reg_delta_f2 => delta_f2,
431 reg_delta_f2 => delta_f2,
429
432
430 enable_f0 => enable_f0,
433 enable_f0 => enable_f0,
431 enable_f1 => enable_f1,
434 enable_f1 => enable_f1,
432 enable_f2 => enable_f2,
435 enable_f2 => enable_f2,
433 enable_f3 => enable_f3,
436 enable_f3 => enable_f3,
434 burst_f0 => burst_f0,
437 burst_f0 => burst_f0,
435 burst_f1 => burst_f1,
438 burst_f1 => burst_f1,
436 burst_f2 => burst_f2,
439 burst_f2 => burst_f2,
437
440
438 nb_data_by_buffer => nb_data_by_buffer,
441 nb_data_by_buffer => nb_data_by_buffer,
439 nb_word_by_buffer => nb_word_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
440 nb_snapshot_param => nb_snapshot_param,
443 nb_snapshot_param => nb_snapshot_param,
441 status_full => status_full,
444 status_full => status_full,
442 status_full_ack => status_full_ack,
445 status_full_ack => status_full_ack,
443 status_full_err => status_full_err,
446 status_full_err => status_full_err,
444 status_new_err => status_new_err,
447 status_new_err => status_new_err,
445
448
446 coarse_time => coarse_time,
449 coarse_time => coarse_time,
447 fine_time => fine_time,
450 fine_time => fine_time,
448
451
449 --f0
452 --f0
450 addr_data_f0 => addr_data_f0,
453 addr_data_f0 => addr_data_f0,
451 data_f0_in_valid => sample_f0_val,
454 data_f0_in_valid => sample_f0_val,
452 data_f0_in => sample_f0_data,
455 data_f0_in => sample_f0_data,
453 --f1
456 --f1
454 addr_data_f1 => addr_data_f1,
457 addr_data_f1 => addr_data_f1,
455 data_f1_in_valid => sample_f1_val,
458 data_f1_in_valid => sample_f1_val,
456 data_f1_in => sample_f1_data,
459 data_f1_in => sample_f1_data,
457 --f2
460 --f2
458 addr_data_f2 => addr_data_f2,
461 addr_data_f2 => addr_data_f2,
459 data_f2_in_valid => sample_f2_val,
462 data_f2_in_valid => sample_f2_val,
460 data_f2_in => sample_f2_data,
463 data_f2_in => sample_f2_data,
461 --f3
464 --f3
462 addr_data_f3 => addr_data_f3,
465 addr_data_f3 => addr_data_f3,
463 data_f3_in_valid => sample_f3_val,
466 data_f3_in_valid => sample_f3_val,
464 data_f3_in => sample_f3_data,
467 data_f3_in => sample_f3_data,
465 -- OUTPUT -- DMA interface
468 -- OUTPUT -- DMA interface
466 --f0
469 --f0
467 data_f0_addr_out => data_f0_addr_out_s,
470 data_f0_addr_out => data_f0_addr_out_s,
468 data_f0_data_out => data_f0_data_out,
471 data_f0_data_out => data_f0_data_out,
469 data_f0_data_out_valid => data_f0_data_out_valid_s,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
470 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
471 data_f0_data_out_ren => data_f0_data_out_ren,
474 data_f0_data_out_ren => data_f0_data_out_ren,
472 --f1
475 --f1
473 data_f1_addr_out => data_f1_addr_out_s,
476 data_f1_addr_out => data_f1_addr_out_s,
474 data_f1_data_out => data_f1_data_out,
477 data_f1_data_out => data_f1_data_out,
475 data_f1_data_out_valid => data_f1_data_out_valid_s,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
476 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
477 data_f1_data_out_ren => data_f1_data_out_ren,
480 data_f1_data_out_ren => data_f1_data_out_ren,
478 --f2
481 --f2
479 data_f2_addr_out => data_f2_addr_out_s,
482 data_f2_addr_out => data_f2_addr_out_s,
480 data_f2_data_out => data_f2_data_out,
483 data_f2_data_out => data_f2_data_out,
481 data_f2_data_out_valid => data_f2_data_out_valid_s,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
482 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
483 data_f2_data_out_ren => data_f2_data_out_ren,
486 data_f2_data_out_ren => data_f2_data_out_ren,
484 --f3
487 --f3
485 data_f3_addr_out => data_f3_addr_out_s,
488 data_f3_addr_out => data_f3_addr_out_s,
486 data_f3_data_out => data_f3_data_out,
489 data_f3_data_out => data_f3_data_out,
487 data_f3_data_out_valid => data_f3_data_out_valid_s,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
488 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
489 data_f3_data_out_ren => data_f3_data_out_ren ,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
490
493
491 -------------------------------------------------------------------------
494 -------------------------------------------------------------------------
492 observation_reg => OPEN
495 observation_reg => OPEN
493
496
494 );
497 );
495
498
496
499
497 -----------------------------------------------------------------------------
500 -----------------------------------------------------------------------------
498 -- TEMP
501 -- TEMP
499 -----------------------------------------------------------------------------
502 -----------------------------------------------------------------------------
500
503
501 PROCESS (clk, rstn)
504 PROCESS (clk, rstn)
502 BEGIN -- PROCESS
505 BEGIN -- PROCESS
503 IF rstn = '0' THEN -- asynchronous reset (active low)
506 IF rstn = '0' THEN -- asynchronous reset (active low)
504 data_f0_data_out_valid <= '0';
507 data_f0_data_out_valid <= '0';
505 data_f0_data_out_valid_burst <= '0';
508 data_f0_data_out_valid_burst <= '0';
506 data_f1_data_out_valid <= '0';
509 data_f1_data_out_valid <= '0';
507 data_f1_data_out_valid_burst <= '0';
510 data_f1_data_out_valid_burst <= '0';
508 data_f2_data_out_valid <= '0';
511 data_f2_data_out_valid <= '0';
509 data_f2_data_out_valid_burst <= '0';
512 data_f2_data_out_valid_burst <= '0';
510 data_f3_data_out_valid <= '0';
513 data_f3_data_out_valid <= '0';
511 data_f3_data_out_valid_burst <= '0';
514 data_f3_data_out_valid_burst <= '0';
512 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
515 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
513 data_f0_data_out_valid <= data_f0_data_out_valid_s;
516 data_f0_data_out_valid <= data_f0_data_out_valid_s;
514 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
517 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
515 data_f1_data_out_valid <= data_f1_data_out_valid_s;
518 data_f1_data_out_valid <= data_f1_data_out_valid_s;
516 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
519 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
517 data_f2_data_out_valid <= data_f2_data_out_valid_s;
520 data_f2_data_out_valid <= data_f2_data_out_valid_s;
518 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
521 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
519 data_f3_data_out_valid <= data_f3_data_out_valid_s;
522 data_f3_data_out_valid <= data_f3_data_out_valid_s;
520 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
523 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
521 END IF;
524 END IF;
522 END PROCESS;
525 END PROCESS;
523
526
524 data_f0_addr_out <= data_f0_addr_out_s;
527 data_f0_addr_out <= data_f0_addr_out_s;
525 data_f1_addr_out <= data_f1_addr_out_s;
528 data_f1_addr_out <= data_f1_addr_out_s;
526 data_f2_addr_out <= data_f2_addr_out_s;
529 data_f2_addr_out <= data_f2_addr_out_s;
527 data_f3_addr_out <= data_f3_addr_out_s;
530 data_f3_addr_out <= data_f3_addr_out_s;
528
531
529 -----------------------------------------------------------------------------
532 -----------------------------------------------------------------------------
530 -- RoundRobin Selection For DMA
533 -- RoundRobin Selection For DMA
531 -----------------------------------------------------------------------------
534 -----------------------------------------------------------------------------
532
535
533 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
536 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
534 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
537 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
535 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
538 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
536 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
539 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
537
540
538 RR_Arbiter_4_1 : RR_Arbiter_4
541 RR_Arbiter_4_1 : RR_Arbiter_4
539 PORT MAP (
542 PORT MAP (
540 clk => clk,
543 clk => clk,
541 rstn => rstn,
544 rstn => rstn,
542 in_valid => dma_rr_valid,
545 in_valid => dma_rr_valid,
543 out_grant => dma_rr_grant_s);
546 out_grant => dma_rr_grant_s);
544
547
545 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
548 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
546 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
549 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
547 dma_rr_valid_ms(2) <= '0';
550 dma_rr_valid_ms(2) <= '0';
548 dma_rr_valid_ms(3) <= '0';
551 dma_rr_valid_ms(3) <= '0';
549
552
550 RR_Arbiter_4_2 : RR_Arbiter_4
553 RR_Arbiter_4_2 : RR_Arbiter_4
551 PORT MAP (
554 PORT MAP (
552 clk => clk,
555 clk => clk,
553 rstn => rstn,
556 rstn => rstn,
554 in_valid => dma_rr_valid_ms,
557 in_valid => dma_rr_valid_ms,
555 out_grant => dma_rr_grant_ms);
558 out_grant => dma_rr_grant_ms);
556
559
557 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
560 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
558
561
559
562
560 -----------------------------------------------------------------------------
563 -----------------------------------------------------------------------------
561 -- in : dma_rr_grant
564 -- in : dma_rr_grant
562 -- send
565 -- send
563 -- out : dma_sel
566 -- out : dma_sel
564 -- dma_valid_burst
567 -- dma_valid_burst
565 -- dma_sel_valid
568 -- dma_sel_valid
566 -----------------------------------------------------------------------------
569 -----------------------------------------------------------------------------
567 PROCESS (clk, rstn)
570 PROCESS (clk, rstn)
568 BEGIN -- PROCESS
571 BEGIN -- PROCESS
569 IF rstn = '0' THEN -- asynchronous reset (active low)
572 IF rstn = '0' THEN -- asynchronous reset (active low)
570 dma_sel <= (OTHERS => '0');
573 dma_sel <= (OTHERS => '0');
571 dma_send <= '0';
574 dma_send <= '0';
572 dma_valid_burst <= '0';
575 dma_valid_burst <= '0';
573 data_ms_done <= '0';
576 data_ms_done <= '0';
574 dma_ms_ongoing <= '0';
577 dma_ms_ongoing <= '0';
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
578 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
576 IF run = '1' THEN
579 IF run = '1' THEN
577 data_ms_done <= '0';
580 data_ms_done <= '0';
578 IF dma_sel = "00000" OR dma_done = '1' THEN
581 IF dma_sel = "00000" OR dma_done = '1' THEN
579 dma_sel <= dma_rr_grant;
582 dma_sel <= dma_rr_grant;
580 IF dma_rr_grant(0) = '1' THEN
583 IF dma_rr_grant(0) = '1' THEN
581 dma_ms_ongoing <= '0';
584 dma_ms_ongoing <= '0';
582 dma_send <= '1';
585 dma_send <= '1';
583 dma_valid_burst <= data_f0_data_out_valid_burst;
586 dma_valid_burst <= data_f0_data_out_valid_burst;
584 dma_sel_valid <= data_f0_data_out_valid;
587 dma_sel_valid <= data_f0_data_out_valid;
585 ELSIF dma_rr_grant(1) = '1' THEN
588 ELSIF dma_rr_grant(1) = '1' THEN
586 dma_ms_ongoing <= '0';
589 dma_ms_ongoing <= '0';
587 dma_send <= '1';
590 dma_send <= '1';
588 dma_valid_burst <= data_f1_data_out_valid_burst;
591 dma_valid_burst <= data_f1_data_out_valid_burst;
589 dma_sel_valid <= data_f1_data_out_valid;
592 dma_sel_valid <= data_f1_data_out_valid;
590 ELSIF dma_rr_grant(2) = '1' THEN
593 ELSIF dma_rr_grant(2) = '1' THEN
591 dma_ms_ongoing <= '0';
594 dma_ms_ongoing <= '0';
592 dma_send <= '1';
595 dma_send <= '1';
593 dma_valid_burst <= data_f2_data_out_valid_burst;
596 dma_valid_burst <= data_f2_data_out_valid_burst;
594 dma_sel_valid <= data_f2_data_out_valid;
597 dma_sel_valid <= data_f2_data_out_valid;
595 ELSIF dma_rr_grant(3) = '1' THEN
598 ELSIF dma_rr_grant(3) = '1' THEN
596 dma_ms_ongoing <= '0';
599 dma_ms_ongoing <= '0';
597 dma_send <= '1';
600 dma_send <= '1';
598 dma_valid_burst <= data_f3_data_out_valid_burst;
601 dma_valid_burst <= data_f3_data_out_valid_burst;
599 dma_sel_valid <= data_f3_data_out_valid;
602 dma_sel_valid <= data_f3_data_out_valid;
600 ELSIF dma_rr_grant(4) = '1' THEN
603 ELSIF dma_rr_grant(4) = '1' THEN
601 dma_ms_ongoing <= '1';
604 dma_ms_ongoing <= '1';
602 dma_send <= '1';
605 dma_send <= '1';
603 dma_valid_burst <= data_ms_valid_burst;
606 dma_valid_burst <= data_ms_valid_burst;
604 dma_sel_valid <= data_ms_valid;
607 dma_sel_valid <= data_ms_valid;
605 --ELSE
608 --ELSE
606 --dma_ms_ongoing <= '0';
609 --dma_ms_ongoing <= '0';
607 END IF;
610 END IF;
608
611
609 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
612 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
610 data_ms_done <= '1';
613 data_ms_done <= '1';
611 END IF;
614 END IF;
612 ELSE
615 ELSE
613 dma_sel <= dma_sel;
616 dma_sel <= dma_sel;
614 dma_send <= '0';
617 dma_send <= '0';
615 END IF;
618 END IF;
616 ELSE
619 ELSE
617 data_ms_done <= '0';
620 data_ms_done <= '0';
618 dma_sel <= (OTHERS => '0');
621 dma_sel <= (OTHERS => '0');
619 dma_send <= '0';
622 dma_send <= '0';
620 dma_valid_burst <= '0';
623 dma_valid_burst <= '0';
621 END IF;
624 END IF;
622 END IF;
625 END IF;
623 END PROCESS;
626 END PROCESS;
624
627
625
628
626 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
629 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
627 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
630 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
628 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
631 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
629 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
632 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
630 data_ms_addr;
633 data_ms_addr;
631
634
632 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
635 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
633 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
636 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
634 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
637 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
635 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
638 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
636 data_ms_data;
639 data_ms_data;
637
640
638 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
641 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
639 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
642 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
640 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
643 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
641 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
644 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
642 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
645 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
643
646
644 dma_data_2 <= dma_data;
647 dma_data_2 <= dma_data;
645
648
646
649
647 -----------------------------------------------------------------------------
650 -----------------------------------------------------------------------------
648 -- DMA
651 -- DMA
649 -----------------------------------------------------------------------------
652 -----------------------------------------------------------------------------
650 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
653 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
651 GENERIC MAP (
654 GENERIC MAP (
652 tech => inferred,
655 tech => inferred,
653 hindex => hindex)
656 hindex => hindex)
654 PORT MAP (
657 PORT MAP (
655 HCLK => clk,
658 HCLK => clk,
656 HRESETn => rstn,
659 HRESETn => rstn,
657 run => run,
660 run => run,
658 AHB_Master_In => ahbi,
661 AHB_Master_In => ahbi,
659 AHB_Master_Out => ahbo,
662 AHB_Master_Out => ahbo,
660
663
661 send => dma_send,
664 send => dma_send,
662 valid_burst => dma_valid_burst,
665 valid_burst => dma_valid_burst,
663 done => dma_done,
666 done => dma_done,
664 ren => dma_ren,
667 ren => dma_ren,
665 address => dma_address,
668 address => dma_address,
666 data => dma_data_2);
669 data => dma_data_2);
667
670
668 -----------------------------------------------------------------------------
671 -----------------------------------------------------------------------------
669 -- Matrix Spectral
672 -- Matrix Spectral
670 -----------------------------------------------------------------------------
673 -----------------------------------------------------------------------------
671 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
674 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
672 NOT(sample_f0_val) & NOT(sample_f0_val);
675 NOT(sample_f0_val) & NOT(sample_f0_val);
673 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
676 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
674 NOT(sample_f1_val) & NOT(sample_f1_val);
677 NOT(sample_f1_val) & NOT(sample_f1_val);
675 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
678 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
676 NOT(sample_f2_val) & NOT(sample_f2_val);
679 NOT(sample_f2_val) & NOT(sample_f2_val);
677
680
678 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
681 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
679 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
682 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
680 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
683 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
681
684
682 -------------------------------------------------------------------------------
685 -------------------------------------------------------------------------------
683
686
684 ms_softandhard_rstn <= rstn AND run_ms AND run;
687 ms_softandhard_rstn <= rstn AND run_ms AND run;
685
688
686 -----------------------------------------------------------------------------
689 -----------------------------------------------------------------------------
687 lpp_lfr_ms_1 : lpp_lfr_ms
690 lpp_lfr_ms_1 : lpp_lfr_ms
688 GENERIC MAP (
691 GENERIC MAP (
689 Mem_use => Mem_use)
692 Mem_use => Mem_use)
690 PORT MAP (
693 PORT MAP (
691 clk => clk,
694 clk => clk,
692 rstn => ms_softandhard_rstn, --rstn,
695 rstn => ms_softandhard_rstn, --rstn,
693
696
694 coarse_time => coarse_time,
697 coarse_time => coarse_time,
695 fine_time => fine_time,
698 fine_time => fine_time,
696
699
697 sample_f0_wen => sample_f0_wen,
700 sample_f0_wen => sample_f0_wen,
698 sample_f0_wdata => sample_f0_wdata,
701 sample_f0_wdata => sample_f0_wdata,
699 sample_f1_wen => sample_f1_wen,
702 sample_f1_wen => sample_f1_wen,
700 sample_f1_wdata => sample_f1_wdata,
703 sample_f1_wdata => sample_f1_wdata,
701 sample_f2_wen => sample_f2_wen, -- TODO
704 sample_f2_wen => sample_f2_wen, -- TODO
702 sample_f2_wdata => sample_f2_wdata,-- TODO
705 sample_f2_wdata => sample_f2_wdata,-- TODO
703
706
704 dma_addr => data_ms_addr, --
707 dma_addr => data_ms_addr, --
705 dma_data => data_ms_data, --
708 dma_data => data_ms_data, --
706 dma_valid => data_ms_valid, --
709 dma_valid => data_ms_valid, --
707 dma_valid_burst => data_ms_valid_burst, --
710 dma_valid_burst => data_ms_valid_burst, --
708 dma_ren => data_ms_ren, --
711 dma_ren => data_ms_ren, --
709 dma_done => data_ms_done, --
712 dma_done => data_ms_done, --
710
713
711 ready_matrix_f0 => ready_matrix_f0,
714 ready_matrix_f0 => ready_matrix_f0,
712 ready_matrix_f1 => ready_matrix_f1,
715 ready_matrix_f1 => ready_matrix_f1,
713 ready_matrix_f2 => ready_matrix_f2,
716 ready_matrix_f2 => ready_matrix_f2,
714 error_bad_component_error => error_bad_component_error,
717 error_bad_component_error => error_bad_component_error,
715 error_buffer_full => error_buffer_full,
718 error_buffer_full => error_buffer_full,
716 error_input_fifo_write => error_input_fifo_write,
719 error_input_fifo_write => error_input_fifo_write,
717
720
718 debug_reg => debug_ms,--observation_reg,
721 debug_reg => debug_ms,--observation_reg,
719 observation_vector_0 => observation_vector_0,
722 observation_vector_0 => observation_vector_0,
720 observation_vector_1 => observation_vector_1,
723 observation_vector_1 => observation_vector_1,
721
724
722 status_ready_matrix_f0 => status_ready_matrix_f0,
725 status_ready_matrix_f0 => status_ready_matrix_f0,
723 status_ready_matrix_f1 => status_ready_matrix_f1,
726 status_ready_matrix_f1 => status_ready_matrix_f1,
724 status_ready_matrix_f2 => status_ready_matrix_f2,
727 status_ready_matrix_f2 => status_ready_matrix_f2,
725 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
728 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
726 config_active_interruption_onError => config_active_interruption_onError,
729 config_active_interruption_onError => config_active_interruption_onError,
727 addr_matrix_f0 => addr_matrix_f0,
730 addr_matrix_f0 => addr_matrix_f0,
728 addr_matrix_f1 => addr_matrix_f1,
731 addr_matrix_f1 => addr_matrix_f1,
729 addr_matrix_f2 => addr_matrix_f2,
732 addr_matrix_f2 => addr_matrix_f2,
730
733
731 matrix_time_f0 => matrix_time_f0,
734 matrix_time_f0 => matrix_time_f0,
732 matrix_time_f1 => matrix_time_f1,
735 matrix_time_f1 => matrix_time_f1,
733 matrix_time_f2 => matrix_time_f2);
736 matrix_time_f2 => matrix_time_f2);
734
737
735 -----------------------------------------------------------------------------
738 -----------------------------------------------------------------------------
736
739
737
740
738 observation_reg(31 DOWNTO 0) <=
741 observation_reg(31 DOWNTO 0) <=
739 dma_sel(4) & -- 31
742 dma_sel(4) & -- 31
740 dma_ms_ongoing & -- 30
743 dma_ms_ongoing & -- 30
741 data_ms_done & -- 29
744 data_ms_done & -- 29
742 dma_done & -- 28
745 dma_done & -- 28
743 ms_softandhard_rstn & --27
746 ms_softandhard_rstn & --27
744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
747 debug_ms(14 DOWNTO 12) & -- 26 .. 24
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
748 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
749 debug_signal(11 DOWNTO 0); -- 11 .. 0
747
750
748 END beh; No newline at end of file
751 END beh;
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@@ -1,697 +1,703
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
36 USE techmap.gencomp.ALL;
37
37
38 ENTITY lpp_lfr_apbreg IS
38 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
39 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
40 nb_data_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
43 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
44 delta_vector_size_f0_2 : INTEGER := 3;
45
45
46 pindex : INTEGER := 4;
46 pindex : INTEGER := 4;
47 paddr : INTEGER := 4;
47 paddr : INTEGER := 4;
48 pmask : INTEGER := 16#fff#;
48 pmask : INTEGER := 16#fff#;
49 pirq_ms : INTEGER := 0;
49 pirq_ms : INTEGER := 0;
50 pirq_wfp : INTEGER := 1;
50 pirq_wfp : INTEGER := 1;
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 -- Spectral Matrix Reg
62 -- Spectral Matrix Reg
63 run_ms : OUT STD_LOGIC;
63 run_ms : OUT STD_LOGIC;
64 -- IN
64 -- IN
65 ready_matrix_f0 : IN STD_LOGIC;
65 ready_matrix_f0 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68
68
69 error_bad_component_error : IN STD_LOGIC;
69 error_bad_component_error : IN STD_LOGIC;
70 error_buffer_full : IN STD_LOGIC; -- TODO
70 error_buffer_full : IN STD_LOGIC; -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72
72
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- OUT
75 -- OUT
76 status_ready_matrix_f0 : OUT STD_LOGIC;
76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90
90
91 ---------------------------------------------------------------------------
91 ---------------------------------------------------------------------------
92 ---------------------------------------------------------------------------
92 ---------------------------------------------------------------------------
93 -- WaveForm picker Reg
93 -- WaveForm picker Reg
94 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
94 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
95 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
95 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98
98
99 -- OUT
99 -- OUT
100 data_shaping_BW : OUT STD_LOGIC;
100 data_shaping_BW : OUT STD_LOGIC;
101 data_shaping_SP0 : OUT STD_LOGIC;
101 data_shaping_SP0 : OUT STD_LOGIC;
102 data_shaping_SP1 : OUT STD_LOGIC;
102 data_shaping_SP1 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
105 data_shaping_R2 : OUT STD_LOGIC;
105
106
106 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
109 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
109 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
112 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
112 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
113 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
113 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
114 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
114
115
115 enable_f0 : OUT STD_LOGIC;
116 enable_f0 : OUT STD_LOGIC;
116 enable_f1 : OUT STD_LOGIC;
117 enable_f1 : OUT STD_LOGIC;
117 enable_f2 : OUT STD_LOGIC;
118 enable_f2 : OUT STD_LOGIC;
118 enable_f3 : OUT STD_LOGIC;
119 enable_f3 : OUT STD_LOGIC;
119
120
120 burst_f0 : OUT STD_LOGIC;
121 burst_f0 : OUT STD_LOGIC;
121 burst_f1 : OUT STD_LOGIC;
122 burst_f1 : OUT STD_LOGIC;
122 burst_f2 : OUT STD_LOGIC;
123 burst_f2 : OUT STD_LOGIC;
123
124
124 run : OUT STD_LOGIC;
125 run : OUT STD_LOGIC;
125
126
126 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 ---------------------------------------------------------------------------
132 ---------------------------------------------------------------------------
132 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
133 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
133 ---------------------------------------------------------------------------
134 ---------------------------------------------------------------------------
134 );
135 );
135
136
136 END lpp_lfr_apbreg;
137 END lpp_lfr_apbreg;
137
138
138 ARCHITECTURE beh OF lpp_lfr_apbreg IS
139 ARCHITECTURE beh OF lpp_lfr_apbreg IS
139
140
140 CONSTANT REVISION : INTEGER := 1;
141 CONSTANT REVISION : INTEGER := 1;
141
142
142 CONSTANT pconfig : apb_config_type := (
143 CONSTANT pconfig : apb_config_type := (
143 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
144 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
144 1 => apb_iobar(paddr, pmask));
145 1 => apb_iobar(paddr, pmask));
145
146
146 TYPE lpp_SpectralMatrix_regs IS RECORD
147 TYPE lpp_SpectralMatrix_regs IS RECORD
147 config_active_interruption_onNewMatrix : STD_LOGIC;
148 config_active_interruption_onNewMatrix : STD_LOGIC;
148 config_active_interruption_onError : STD_LOGIC;
149 config_active_interruption_onError : STD_LOGIC;
149 config_ms_run : STD_LOGIC;
150 config_ms_run : STD_LOGIC;
150 status_ready_matrix_f0_0 : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
151 status_ready_matrix_f1_0 : STD_LOGIC;
152 status_ready_matrix_f1_0 : STD_LOGIC;
152 status_ready_matrix_f2_0 : STD_LOGIC;
153 status_ready_matrix_f2_0 : STD_LOGIC;
153 status_ready_matrix_f0_1 : STD_LOGIC;
154 status_ready_matrix_f0_1 : STD_LOGIC;
154 status_ready_matrix_f1_1 : STD_LOGIC;
155 status_ready_matrix_f1_1 : STD_LOGIC;
155 status_ready_matrix_f2_1 : STD_LOGIC;
156 status_ready_matrix_f2_1 : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
157 status_error_bad_component_error : STD_LOGIC;
157 status_error_buffer_full : STD_LOGIC;
158 status_error_buffer_full : STD_LOGIC;
158 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
159 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
159
160
160 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
166
167
167 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
173 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
173 END RECORD;
174 END RECORD;
174 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
175 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
175
176
176 TYPE lpp_WaveformPicker_regs IS RECORD
177 TYPE lpp_WaveformPicker_regs IS RECORD
177 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
180 data_shaping_BW : STD_LOGIC;
181 data_shaping_BW : STD_LOGIC;
181 data_shaping_SP0 : STD_LOGIC;
182 data_shaping_SP0 : STD_LOGIC;
182 data_shaping_SP1 : STD_LOGIC;
183 data_shaping_SP1 : STD_LOGIC;
183 data_shaping_R0 : STD_LOGIC;
184 data_shaping_R0 : STD_LOGIC;
184 data_shaping_R1 : STD_LOGIC;
185 data_shaping_R1 : STD_LOGIC;
186 data_shaping_R2 : STD_LOGIC;
185 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
187 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
186 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
188 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
187 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
189 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
188 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
190 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
189 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
191 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
190 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
192 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
191 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
193 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
192 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
194 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
193 enable_f0 : STD_LOGIC;
195 enable_f0 : STD_LOGIC;
194 enable_f1 : STD_LOGIC;
196 enable_f1 : STD_LOGIC;
195 enable_f2 : STD_LOGIC;
197 enable_f2 : STD_LOGIC;
196 enable_f3 : STD_LOGIC;
198 enable_f3 : STD_LOGIC;
197 burst_f0 : STD_LOGIC;
199 burst_f0 : STD_LOGIC;
198 burst_f1 : STD_LOGIC;
200 burst_f1 : STD_LOGIC;
199 burst_f2 : STD_LOGIC;
201 burst_f2 : STD_LOGIC;
200 run : STD_LOGIC;
202 run : STD_LOGIC;
201 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
207 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
206 END RECORD;
208 END RECORD;
207 SIGNAL reg_wp : lpp_WaveformPicker_regs;
209 SIGNAL reg_wp : lpp_WaveformPicker_regs;
208
210
209 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
210
212
211 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
212 -- IRQ
214 -- IRQ
213 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
214 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
216 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
215 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
217 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
216 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
218 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
217 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
219 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
218 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
220 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
219 SIGNAL ored_irq_wfp : STD_LOGIC;
221 SIGNAL ored_irq_wfp : STD_LOGIC;
220
222
221 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
222 --
224 --
223 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
224 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
226 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
225 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
227 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
226 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
227
229
228 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
230 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
229 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
231 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
230 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
231
233
232 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
234 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
233 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
235 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
234 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
235
237
236 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
238 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
237 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
240 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
239
241
240 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
242 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
241 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243
245
244 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
246 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
245 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
248 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 SIGNAL apbo_irq_ms : STD_LOGIC;
249 SIGNAL apbo_irq_ms : STD_LOGIC;
248 SIGNAL apbo_irq_wfp : STD_LOGIC;
250 SIGNAL apbo_irq_wfp : STD_LOGIC;
249
251
250 BEGIN -- beh
252 BEGIN -- beh
251
253
252 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
254 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
253 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
255 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
254 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
256 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
255
257
256 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
258 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
257 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
259 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
258
260
259
261
260 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
262 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
261 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
263 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
262 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
264 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
263
265
264
266
265 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
267 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
266 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
268 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
267 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
269 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
268 data_shaping_R0 <= reg_wp.data_shaping_R0;
270 data_shaping_R0 <= reg_wp.data_shaping_R0;
269 data_shaping_R1 <= reg_wp.data_shaping_R1;
271 data_shaping_R1 <= reg_wp.data_shaping_R1;
272 data_shaping_R2 <= reg_wp.data_shaping_R2;
270
273
271 delta_snapshot <= reg_wp.delta_snapshot;
274 delta_snapshot <= reg_wp.delta_snapshot;
272 delta_f0 <= reg_wp.delta_f0;
275 delta_f0 <= reg_wp.delta_f0;
273 delta_f0_2 <= reg_wp.delta_f0_2;
276 delta_f0_2 <= reg_wp.delta_f0_2;
274 delta_f1 <= reg_wp.delta_f1;
277 delta_f1 <= reg_wp.delta_f1;
275 delta_f2 <= reg_wp.delta_f2;
278 delta_f2 <= reg_wp.delta_f2;
276 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
279 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
277 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
280 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
278 nb_snapshot_param <= reg_wp.nb_snapshot_param;
281 nb_snapshot_param <= reg_wp.nb_snapshot_param;
279
282
280 enable_f0 <= reg_wp.enable_f0;
283 enable_f0 <= reg_wp.enable_f0;
281 enable_f1 <= reg_wp.enable_f1;
284 enable_f1 <= reg_wp.enable_f1;
282 enable_f2 <= reg_wp.enable_f2;
285 enable_f2 <= reg_wp.enable_f2;
283 enable_f3 <= reg_wp.enable_f3;
286 enable_f3 <= reg_wp.enable_f3;
284
287
285 burst_f0 <= reg_wp.burst_f0;
288 burst_f0 <= reg_wp.burst_f0;
286 burst_f1 <= reg_wp.burst_f1;
289 burst_f1 <= reg_wp.burst_f1;
287 burst_f2 <= reg_wp.burst_f2;
290 burst_f2 <= reg_wp.burst_f2;
288
291
289 run <= reg_wp.run;
292 run <= reg_wp.run;
290
293
291 addr_data_f0 <= reg_wp.addr_data_f0;
294 addr_data_f0 <= reg_wp.addr_data_f0;
292 addr_data_f1 <= reg_wp.addr_data_f1;
295 addr_data_f1 <= reg_wp.addr_data_f1;
293 addr_data_f2 <= reg_wp.addr_data_f2;
296 addr_data_f2 <= reg_wp.addr_data_f2;
294 addr_data_f3 <= reg_wp.addr_data_f3;
297 addr_data_f3 <= reg_wp.addr_data_f3;
295
298
296 start_date <= reg_wp.start_date;
299 start_date <= reg_wp.start_date;
297
300
298 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
301 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
299 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
302 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
300 BEGIN -- PROCESS lpp_dma_top
303 BEGIN -- PROCESS lpp_dma_top
301 IF HRESETn = '0' THEN -- asynchronous reset (active low)
304 IF HRESETn = '0' THEN -- asynchronous reset (active low)
302 reg_sp.config_active_interruption_onNewMatrix <= '0';
305 reg_sp.config_active_interruption_onNewMatrix <= '0';
303 reg_sp.config_active_interruption_onError <= '0';
306 reg_sp.config_active_interruption_onError <= '0';
304 reg_sp.config_ms_run <= '1';
307 reg_sp.config_ms_run <= '1';
305 reg_sp.status_ready_matrix_f0_0 <= '0';
308 reg_sp.status_ready_matrix_f0_0 <= '0';
306 reg_sp.status_ready_matrix_f1_0 <= '0';
309 reg_sp.status_ready_matrix_f1_0 <= '0';
307 reg_sp.status_ready_matrix_f2_0 <= '0';
310 reg_sp.status_ready_matrix_f2_0 <= '0';
308 reg_sp.status_ready_matrix_f0_1 <= '0';
311 reg_sp.status_ready_matrix_f0_1 <= '0';
309 reg_sp.status_ready_matrix_f1_1 <= '0';
312 reg_sp.status_ready_matrix_f1_1 <= '0';
310 reg_sp.status_ready_matrix_f2_1 <= '0';
313 reg_sp.status_ready_matrix_f2_1 <= '0';
311 reg_sp.status_error_bad_component_error <= '0';
314 reg_sp.status_error_bad_component_error <= '0';
312 reg_sp.status_error_buffer_full <= '0';
315 reg_sp.status_error_buffer_full <= '0';
313 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
316 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
314
317
315 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
318 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
316 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
319 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
317 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
320 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
318
321
319 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
322 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
320 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
323 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
321 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
324 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
322
325
323 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
326 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
324 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
327 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
328 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
326
329
327 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
330 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
328 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
331 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
329 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
332 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
330
333
331 prdata <= (OTHERS => '0');
334 prdata <= (OTHERS => '0');
332
335
333
336
334 apbo_irq_ms <= '0';
337 apbo_irq_ms <= '0';
335 apbo_irq_wfp <= '0';
338 apbo_irq_wfp <= '0';
336
339
337
340
338 status_full_ack <= (OTHERS => '0');
341 status_full_ack <= (OTHERS => '0');
339
342
340 reg_wp.data_shaping_BW <= '0';
343 reg_wp.data_shaping_BW <= '0';
341 reg_wp.data_shaping_SP0 <= '0';
344 reg_wp.data_shaping_SP0 <= '0';
342 reg_wp.data_shaping_SP1 <= '0';
345 reg_wp.data_shaping_SP1 <= '0';
343 reg_wp.data_shaping_R0 <= '0';
346 reg_wp.data_shaping_R0 <= '0';
344 reg_wp.data_shaping_R1 <= '0';
347 reg_wp.data_shaping_R1 <= '0';
348 reg_wp.data_shaping_R2 <= '0';
345 reg_wp.enable_f0 <= '0';
349 reg_wp.enable_f0 <= '0';
346 reg_wp.enable_f1 <= '0';
350 reg_wp.enable_f1 <= '0';
347 reg_wp.enable_f2 <= '0';
351 reg_wp.enable_f2 <= '0';
348 reg_wp.enable_f3 <= '0';
352 reg_wp.enable_f3 <= '0';
349 reg_wp.burst_f0 <= '0';
353 reg_wp.burst_f0 <= '0';
350 reg_wp.burst_f1 <= '0';
354 reg_wp.burst_f1 <= '0';
351 reg_wp.burst_f2 <= '0';
355 reg_wp.burst_f2 <= '0';
352 reg_wp.run <= '0';
356 reg_wp.run <= '0';
353 reg_wp.addr_data_f0 <= (OTHERS => '0');
357 reg_wp.addr_data_f0 <= (OTHERS => '0');
354 reg_wp.addr_data_f1 <= (OTHERS => '0');
358 reg_wp.addr_data_f1 <= (OTHERS => '0');
355 reg_wp.addr_data_f2 <= (OTHERS => '0');
359 reg_wp.addr_data_f2 <= (OTHERS => '0');
356 reg_wp.addr_data_f3 <= (OTHERS => '0');
360 reg_wp.addr_data_f3 <= (OTHERS => '0');
357 reg_wp.status_full <= (OTHERS => '0');
361 reg_wp.status_full <= (OTHERS => '0');
358 reg_wp.status_full_err <= (OTHERS => '0');
362 reg_wp.status_full_err <= (OTHERS => '0');
359 reg_wp.status_new_err <= (OTHERS => '0');
363 reg_wp.status_new_err <= (OTHERS => '0');
360 reg_wp.delta_snapshot <= (OTHERS => '0');
364 reg_wp.delta_snapshot <= (OTHERS => '0');
361 reg_wp.delta_f0 <= (OTHERS => '0');
365 reg_wp.delta_f0 <= (OTHERS => '0');
362 reg_wp.delta_f0_2 <= (OTHERS => '0');
366 reg_wp.delta_f0_2 <= (OTHERS => '0');
363 reg_wp.delta_f1 <= (OTHERS => '0');
367 reg_wp.delta_f1 <= (OTHERS => '0');
364 reg_wp.delta_f2 <= (OTHERS => '0');
368 reg_wp.delta_f2 <= (OTHERS => '0');
365 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
369 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
366 reg_wp.nb_snapshot_param <= (OTHERS => '0');
370 reg_wp.nb_snapshot_param <= (OTHERS => '0');
367 reg_wp.start_date <= (OTHERS => '0');
371 reg_wp.start_date <= (OTHERS => '0');
368
372
369 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
373 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
370
374
371 status_full_ack <= (OTHERS => '0');
375 status_full_ack <= (OTHERS => '0');
372
376
373 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
377 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
374 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
378 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
375 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
379 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
376
380
377 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
381 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
378 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
382 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
379 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
383 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
380
384
381 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
385 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
382
386
383 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
387 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
384 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
388 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
385 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
389 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
386 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
390 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
387
391
388
392
389
393
390 all_status : FOR I IN 3 DOWNTO 0 LOOP
394 all_status : FOR I IN 3 DOWNTO 0 LOOP
391 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
395 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
392 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
396 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
393 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
397 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
394 END LOOP all_status;
398 END LOOP all_status;
395
399
396 paddr := "000000";
400 paddr := "000000";
397 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
401 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
398 prdata <= (OTHERS => '0');
402 prdata <= (OTHERS => '0');
399 IF apbi.psel(pindex) = '1' THEN
403 IF apbi.psel(pindex) = '1' THEN
400 -- APB DMA READ --
404 -- APB DMA READ --
401 CASE paddr(7 DOWNTO 2) IS
405 CASE paddr(7 DOWNTO 2) IS
402 --0
406 --0
403 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
407 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
404 prdata(1) <= reg_sp.config_active_interruption_onError;
408 prdata(1) <= reg_sp.config_active_interruption_onError;
405 prdata(2) <= reg_sp.config_ms_run;
409 prdata(2) <= reg_sp.config_ms_run;
406 --1
410 --1
407 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
411 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
408 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
412 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
409 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
413 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
410 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
414 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
411 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
415 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
412 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
416 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
413 prdata(6) <= reg_sp.status_error_bad_component_error;
417 prdata(6) <= reg_sp.status_error_bad_component_error;
414 prdata(7) <= reg_sp.status_error_buffer_full;
418 prdata(7) <= reg_sp.status_error_buffer_full;
415 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
419 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
416 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
420 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
417 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
421 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
418 --2
422 --2
419 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
423 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
420 --3
424 --3
421 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
425 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
422 --4
426 --4
423 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
427 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
424 --5
428 --5
425 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
429 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
426 --6
430 --6
427 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
431 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
428 --7
432 --7
429 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
433 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
430 --8
434 --8
431 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
435 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
432 --9
436 --9
433 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
437 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
434 --10
438 --10
435 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
439 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
436 --11
440 --11
437 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
441 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
438 --12
442 --12
439 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
443 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
440 --13
444 --13
441 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
445 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
442 --14
446 --14
443 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
447 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
444 --15
448 --15
445 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
449 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
446 --16
450 --16
447 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
451 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
448 --17
452 --17
449 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
453 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
450 --18
454 --18
451 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
455 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
452 --19
456 --19
453 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
457 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
454 ---------------------------------------------------------------------
458 ---------------------------------------------------------------------
455 --20
459 --20
456 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
460 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
457 prdata(1) <= reg_wp.data_shaping_SP0;
461 prdata(1) <= reg_wp.data_shaping_SP0;
458 prdata(2) <= reg_wp.data_shaping_SP1;
462 prdata(2) <= reg_wp.data_shaping_SP1;
459 prdata(3) <= reg_wp.data_shaping_R0;
463 prdata(3) <= reg_wp.data_shaping_R0;
460 prdata(4) <= reg_wp.data_shaping_R1;
464 prdata(4) <= reg_wp.data_shaping_R1;
465 prdata(5) <= reg_wp.data_shaping_R2;
461 --21
466 --21
462 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
467 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
463 prdata(1) <= reg_wp.enable_f1;
468 prdata(1) <= reg_wp.enable_f1;
464 prdata(2) <= reg_wp.enable_f2;
469 prdata(2) <= reg_wp.enable_f2;
465 prdata(3) <= reg_wp.enable_f3;
470 prdata(3) <= reg_wp.enable_f3;
466 prdata(4) <= reg_wp.burst_f0;
471 prdata(4) <= reg_wp.burst_f0;
467 prdata(5) <= reg_wp.burst_f1;
472 prdata(5) <= reg_wp.burst_f1;
468 prdata(6) <= reg_wp.burst_f2;
473 prdata(6) <= reg_wp.burst_f2;
469 prdata(7) <= reg_wp.run;
474 prdata(7) <= reg_wp.run;
470 --22
475 --22
471 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
476 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
472 --23
477 --23
473 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
478 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
474 --24
479 --24
475 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
480 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
476 --25
481 --25
477 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
482 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
478 --26
483 --26
479 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
484 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
480 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
485 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
481 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
486 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
482 --27
487 --27
483 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
488 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
484 --28
489 --28
485 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
490 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
486 --29
491 --29
487 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
492 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
488 --30
493 --30
489 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
494 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
490 --31
495 --31
491 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
496 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
492 --32
497 --32
493 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
498 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
494 --33
499 --33
495 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
500 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
496 --34
501 --34
497 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
502 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
498 --35
503 --35
499 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
504 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
500 ----------------------------------------------------
505 ----------------------------------------------------
501 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
506 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
502 WHEN OTHERS => NULL;
507 WHEN OTHERS => NULL;
503
508
504 END CASE;
509 END CASE;
505 IF (apbi.pwrite AND apbi.penable) = '1' THEN
510 IF (apbi.pwrite AND apbi.penable) = '1' THEN
506 -- APB DMA WRITE --
511 -- APB DMA WRITE --
507 CASE paddr(7 DOWNTO 2) IS
512 CASE paddr(7 DOWNTO 2) IS
508 --
513 --
509 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
514 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
510 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
515 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
511 reg_sp.config_ms_run <= apbi.pwdata(2);
516 reg_sp.config_ms_run <= apbi.pwdata(2);
512
517
513 WHEN "000001" =>
518 WHEN "000001" =>
514 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
519 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
515 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
520 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
516 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
521 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
517 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
522 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
518 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
523 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
519 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
524 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
520 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
525 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
521 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
526 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
522 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
527 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
523 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
528 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
524 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
529 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
525 --2
530 --2
526 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
531 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
527 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
532 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
528 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
533 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
529 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
534 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
530 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
535 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
531 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
536 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
532 --8 to 19
537 --8 to 19
533 --20
538 --20
534 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
539 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
535 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
540 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
536 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
541 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
537 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
542 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
538 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
543 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
544 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
539 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
545 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
540 reg_wp.enable_f1 <= apbi.pwdata(1);
546 reg_wp.enable_f1 <= apbi.pwdata(1);
541 reg_wp.enable_f2 <= apbi.pwdata(2);
547 reg_wp.enable_f2 <= apbi.pwdata(2);
542 reg_wp.enable_f3 <= apbi.pwdata(3);
548 reg_wp.enable_f3 <= apbi.pwdata(3);
543 reg_wp.burst_f0 <= apbi.pwdata(4);
549 reg_wp.burst_f0 <= apbi.pwdata(4);
544 reg_wp.burst_f1 <= apbi.pwdata(5);
550 reg_wp.burst_f1 <= apbi.pwdata(5);
545 reg_wp.burst_f2 <= apbi.pwdata(6);
551 reg_wp.burst_f2 <= apbi.pwdata(6);
546 reg_wp.run <= apbi.pwdata(7);
552 reg_wp.run <= apbi.pwdata(7);
547 --22
553 --22
548 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
554 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
549 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
555 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
550 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
556 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
551 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
557 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
552 --26
558 --26
553 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
559 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
554 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
560 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
555 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
561 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
556 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
562 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
557 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
563 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
558 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
564 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
559 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
565 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
560 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
566 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
561 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
567 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
562 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
568 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
563 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
569 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
564 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
570 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
565 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
571 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
566 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
572 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
567 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
573 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
568 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
574 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
569 --
575 --
570 WHEN OTHERS => NULL;
576 WHEN OTHERS => NULL;
571 END CASE;
577 END CASE;
572 END IF;
578 END IF;
573 END IF;
579 END IF;
574 --apbo.pirq(pirq_ms) <=
580 --apbo.pirq(pirq_ms) <=
575 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
581 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
576 ready_matrix_f1 OR
582 ready_matrix_f1 OR
577 ready_matrix_f2)
583 ready_matrix_f2)
578 )
584 )
579 OR
585 OR
580 (reg_sp.config_active_interruption_onError AND (
586 (reg_sp.config_active_interruption_onError AND (
581 error_bad_component_error
587 error_bad_component_error
582 OR error_buffer_full
588 OR error_buffer_full
583 OR error_input_fifo_write(0)
589 OR error_input_fifo_write(0)
584 OR error_input_fifo_write(1)
590 OR error_input_fifo_write(1)
585 OR error_input_fifo_write(2))
591 OR error_input_fifo_write(2))
586 ));
592 ));
587 -- apbo.pirq(pirq_wfp)
593 -- apbo.pirq(pirq_wfp)
588 apbo_irq_wfp<= ored_irq_wfp;
594 apbo_irq_wfp<= ored_irq_wfp;
589
595
590 END IF;
596 END IF;
591 END PROCESS lpp_lfr_apbreg;
597 END PROCESS lpp_lfr_apbreg;
592
598
593 apbo.pirq(pirq_ms) <= apbo_irq_ms;
599 apbo.pirq(pirq_ms) <= apbo_irq_ms;
594 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
600 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
595
601
596 apbo.pindex <= pindex;
602 apbo.pindex <= pindex;
597 apbo.pconfig <= pconfig;
603 apbo.pconfig <= pconfig;
598 apbo.prdata <= prdata;
604 apbo.prdata <= prdata;
599
605
600 -----------------------------------------------------------------------------
606 -----------------------------------------------------------------------------
601 -- IRQ
607 -- IRQ
602 -----------------------------------------------------------------------------
608 -----------------------------------------------------------------------------
603 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
609 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
604
610
605 PROCESS (HCLK, HRESETn)
611 PROCESS (HCLK, HRESETn)
606 BEGIN -- PROCESS
612 BEGIN -- PROCESS
607 IF HRESETn = '0' THEN -- asynchronous reset (active low)
613 IF HRESETn = '0' THEN -- asynchronous reset (active low)
608 irq_wfp_reg <= (OTHERS => '0');
614 irq_wfp_reg <= (OTHERS => '0');
609 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
615 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
610 irq_wfp_reg <= irq_wfp_reg_s;
616 irq_wfp_reg <= irq_wfp_reg_s;
611 END IF;
617 END IF;
612 END PROCESS;
618 END PROCESS;
613
619
614 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
620 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
615 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
621 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
616 END GENERATE all_irq_wfp;
622 END GENERATE all_irq_wfp;
617
623
618 irq_wfp_ZERO <= (OTHERS => '0');
624 irq_wfp_ZERO <= (OTHERS => '0');
619 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
625 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
620
626
621 run_ms <= reg_sp.config_ms_run;
627 run_ms <= reg_sp.config_ms_run;
622
628
623 -----------------------------------------------------------------------------
629 -----------------------------------------------------------------------------
624 --
630 --
625 -----------------------------------------------------------------------------
631 -----------------------------------------------------------------------------
626 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
632 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
627 PORT MAP (
633 PORT MAP (
628 clk => HCLK,
634 clk => HCLK,
629 rstn => HRESETn,
635 rstn => HRESETn,
630
636
631 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
637 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
632 reg0_ready_matrix => reg0_ready_matrix_f0,
638 reg0_ready_matrix => reg0_ready_matrix_f0,
633 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
639 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
634 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
640 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
635
641
636 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
642 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
637 reg1_ready_matrix => reg1_ready_matrix_f0,
643 reg1_ready_matrix => reg1_ready_matrix_f0,
638 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
644 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
639 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
645 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
640
646
641 ready_matrix => ready_matrix_f0,
647 ready_matrix => ready_matrix_f0,
642 status_ready_matrix => status_ready_matrix_f0,
648 status_ready_matrix => status_ready_matrix_f0,
643 addr_matrix => addr_matrix_f0,
649 addr_matrix => addr_matrix_f0,
644 matrix_time => matrix_time_f0);
650 matrix_time => matrix_time_f0);
645
651
646 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
652 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
647 PORT MAP (
653 PORT MAP (
648 clk => HCLK,
654 clk => HCLK,
649 rstn => HRESETn,
655 rstn => HRESETn,
650
656
651 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
657 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
652 reg0_ready_matrix => reg0_ready_matrix_f1,
658 reg0_ready_matrix => reg0_ready_matrix_f1,
653 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
659 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
654 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
660 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
655
661
656 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
662 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
657 reg1_ready_matrix => reg1_ready_matrix_f1,
663 reg1_ready_matrix => reg1_ready_matrix_f1,
658 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
664 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
659 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
665 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
660
666
661 ready_matrix => ready_matrix_f1,
667 ready_matrix => ready_matrix_f1,
662 status_ready_matrix => status_ready_matrix_f1,
668 status_ready_matrix => status_ready_matrix_f1,
663 addr_matrix => addr_matrix_f1,
669 addr_matrix => addr_matrix_f1,
664 matrix_time => matrix_time_f1);
670 matrix_time => matrix_time_f1);
665
671
666 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
672 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
667 PORT MAP (
673 PORT MAP (
668 clk => HCLK,
674 clk => HCLK,
669 rstn => HRESETn,
675 rstn => HRESETn,
670
676
671 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
677 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
672 reg0_ready_matrix => reg0_ready_matrix_f2,
678 reg0_ready_matrix => reg0_ready_matrix_f2,
673 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
679 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
674 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
680 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
675
681
676 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
682 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
677 reg1_ready_matrix => reg1_ready_matrix_f2,
683 reg1_ready_matrix => reg1_ready_matrix_f2,
678 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
684 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
679 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
685 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
680
686
681 ready_matrix => ready_matrix_f2,
687 ready_matrix => ready_matrix_f2,
682 status_ready_matrix => status_ready_matrix_f2,
688 status_ready_matrix => status_ready_matrix_f2,
683 addr_matrix => addr_matrix_f2,
689 addr_matrix => addr_matrix_f2,
684 matrix_time => matrix_time_f2);
690 matrix_time => matrix_time_f2);
685
691
686 -----------------------------------------------------------------------------
692 -----------------------------------------------------------------------------
687 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
693 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
688 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
694 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
689 reg_sp.status_error_input_fifo_write(2) &--10
695 reg_sp.status_error_input_fifo_write(2) &--10
690 reg_sp.status_error_input_fifo_write(1) &--9
696 reg_sp.status_error_input_fifo_write(1) &--9
691 reg_sp.status_error_input_fifo_write(0) &--8
697 reg_sp.status_error_input_fifo_write(0) &--8
692 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
698 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
693 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
699 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
694 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
700 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
695 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
701 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
696
702
697 END beh;
703 END beh;
Show file before | Show file after | Hide comments
@@ -1,385 +1,386
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11
11
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 LIBRARY grlib;
15 LIBRARY grlib;
16 USE grlib.amba.ALL;
16 USE grlib.amba.ALL;
17 USE grlib.stdlib.ALL;
17 USE grlib.stdlib.ALL;
18 USE grlib.devices.ALL;
18 USE grlib.devices.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
20
20
21 ENTITY lpp_lfr_filter IS
21 ENTITY lpp_lfr_filter IS
22 GENERIC(
22 GENERIC(
23 Mem_use : INTEGER := use_RAM
23 Mem_use : INTEGER := use_RAM
24 );
24 );
25 PORT (
25 PORT (
26 sample : IN Samples(7 DOWNTO 0);
26 sample : IN Samples(7 DOWNTO 0);
27 sample_val : IN STD_LOGIC;
27 sample_val : IN STD_LOGIC;
28 --
28 --
29 clk : IN STD_LOGIC;
29 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
31 --
31 --
32 data_shaping_SP0 : IN STD_LOGIC;
32 data_shaping_SP0 : IN STD_LOGIC;
33 data_shaping_SP1 : IN STD_LOGIC;
33 data_shaping_SP1 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
34 data_shaping_R0 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
35 data_shaping_R1 : IN STD_LOGIC;
36 data_shaping_R2 : IN STD_LOGIC;
36 --
37 --
37 sample_f0_val : OUT STD_LOGIC;
38 sample_f0_val : OUT STD_LOGIC;
38 sample_f1_val : OUT STD_LOGIC;
39 sample_f1_val : OUT STD_LOGIC;
39 sample_f2_val : OUT STD_LOGIC;
40 sample_f2_val : OUT STD_LOGIC;
40 sample_f3_val : OUT STD_LOGIC;
41 sample_f3_val : OUT STD_LOGIC;
41 --
42 --
42 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
43 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
43 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
44 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
44 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
46 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
46 );
47 );
47 END lpp_lfr_filter;
48 END lpp_lfr_filter;
48
49
49 ARCHITECTURE tb OF lpp_lfr_filter IS
50 ARCHITECTURE tb OF lpp_lfr_filter IS
50
51
51 COMPONENT Downsampling
52 COMPONENT Downsampling
52 GENERIC (
53 GENERIC (
53 ChanelCount : INTEGER;
54 ChanelCount : INTEGER;
54 SampleSize : INTEGER;
55 SampleSize : INTEGER;
55 DivideParam : INTEGER);
56 DivideParam : INTEGER);
56 PORT (
57 PORT (
57 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 sample_in_val : IN STD_LOGIC;
60 sample_in_val : IN STD_LOGIC;
60 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
61 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
61 sample_out_val : OUT STD_LOGIC;
62 sample_out_val : OUT STD_LOGIC;
62 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
63 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
63 END COMPONENT;
64 END COMPONENT;
64
65
65 -----------------------------------------------------------------------------
66 -----------------------------------------------------------------------------
66 CONSTANT ChanelCount : INTEGER := 8;
67 CONSTANT ChanelCount : INTEGER := 8;
67
68
68 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
69 SIGNAL sample_val_delay : STD_LOGIC;
70 SIGNAL sample_val_delay : STD_LOGIC;
70 -----------------------------------------------------------------------------
71 -----------------------------------------------------------------------------
71 CONSTANT Coef_SZ : INTEGER := 9;
72 CONSTANT Coef_SZ : INTEGER := 9;
72 CONSTANT CoefCntPerCel : INTEGER := 6;
73 CONSTANT CoefCntPerCel : INTEGER := 6;
73 CONSTANT CoefPerCel : INTEGER := 5;
74 CONSTANT CoefPerCel : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
75 CONSTANT Cels_count : INTEGER := 5;
75
76
76 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
77 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
78 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 --
81 --
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
82 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
83 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
83 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
84 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
85 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
85 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
87 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
87 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
88 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
88 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
89 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
89 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
90 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
90 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
91 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
91 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
92 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
93 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
93 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
94 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
94 -----------------------------------------------------------------------------
95 -----------------------------------------------------------------------------
95 -- SIGNAL sample_f0_val : STD_LOGIC;
96 -- SIGNAL sample_f0_val : STD_LOGIC;
96 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
97 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
97 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
98 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
98 --
99 --
99 -- SIGNAL sample_f1_val : STD_LOGIC;
100 -- SIGNAL sample_f1_val : STD_LOGIC;
100 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
101 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
101 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
102 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
102 --
103 --
103 -- SIGNAL sample_f2_val : STD_LOGIC;
104 -- SIGNAL sample_f2_val : STD_LOGIC;
104 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
105 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
105 --
106 --
106 -- SIGNAL sample_f3_val : STD_LOGIC;
107 -- SIGNAL sample_f3_val : STD_LOGIC;
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
108 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
108
109
109 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
110 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 -----------------------------------------------------------------------------
115 -----------------------------------------------------------------------------
115
116
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
121
121 SIGNAL sample_f0_val_s : STD_LOGIC;
122 SIGNAL sample_f0_val_s : STD_LOGIC;
122 SIGNAL sample_f1_val_s : STD_LOGIC;
123 SIGNAL sample_f1_val_s : STD_LOGIC;
123 BEGIN
124 BEGIN
124
125
125 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
126 PROCESS (clk, rstn)
127 PROCESS (clk, rstn)
127 BEGIN -- PROCESS
128 BEGIN -- PROCESS
128 IF rstn = '0' THEN -- asynchronous reset (active low)
129 IF rstn = '0' THEN -- asynchronous reset (active low)
129 sample_val_delay <= '0';
130 sample_val_delay <= '0';
130 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
131 sample_val_delay <= sample_val;
132 sample_val_delay <= sample_val;
132 END IF;
133 END IF;
133 END PROCESS;
134 END PROCESS;
134
135
135 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
136 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
137 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
137 SampleLoop : FOR j IN 0 TO 15 GENERATE
138 SampleLoop : FOR j IN 0 TO 15 GENERATE
138 sample_filter_in(i, j) <= sample(i)(j);
139 sample_filter_in(i, j) <= sample(i)(j);
139 END GENERATE;
140 END GENERATE;
140
141
141 sample_filter_in(i, 16) <= sample(i)(15);
142 sample_filter_in(i, 16) <= sample(i)(15);
142 sample_filter_in(i, 17) <= sample(i)(15);
143 sample_filter_in(i, 17) <= sample(i)(15);
143 END GENERATE;
144 END GENERATE;
144
145
145 coefs_v2 <= CoefsInitValCst_v2;
146 coefs_v2 <= CoefsInitValCst_v2;
146
147
147 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
148 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
148 GENERIC MAP (
149 GENERIC MAP (
149 tech => 0,
150 tech => 0,
150 Mem_use => Mem_use, -- use_RAM
151 Mem_use => Mem_use, -- use_RAM
151 Sample_SZ => 18,
152 Sample_SZ => 18,
152 Coef_SZ => Coef_SZ,
153 Coef_SZ => Coef_SZ,
153 Coef_Nb => 25,
154 Coef_Nb => 25,
154 Coef_sel_SZ => 5,
155 Coef_sel_SZ => 5,
155 Cels_count => Cels_count,
156 Cels_count => Cels_count,
156 ChanelsCount => ChanelCount)
157 ChanelsCount => ChanelCount)
157 PORT MAP (
158 PORT MAP (
158 rstn => rstn,
159 rstn => rstn,
159 clk => clk,
160 clk => clk,
160 virg_pos => 7,
161 virg_pos => 7,
161 coefs => coefs_v2,
162 coefs => coefs_v2,
162 sample_in_val => sample_val_delay,
163 sample_in_val => sample_val_delay,
163 sample_in => sample_filter_in,
164 sample_in => sample_filter_in,
164 sample_out_val => sample_filter_v2_out_val,
165 sample_out_val => sample_filter_v2_out_val,
165 sample_out => sample_filter_v2_out);
166 sample_out => sample_filter_v2_out);
166
167
167 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
168 -- DATA_SHAPING
169 -- DATA_SHAPING
169 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
170 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
171 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
171 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
172 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
172 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
173 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
173 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
174 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
174 END GENERATE all_data_shaping_in_loop;
175 END GENERATE all_data_shaping_in_loop;
175
176
176 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
177 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
177 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
178 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
178
179
179 PROCESS (clk, rstn)
180 PROCESS (clk, rstn)
180 BEGIN -- PROCESS
181 BEGIN -- PROCESS
181 IF rstn = '0' THEN -- asynchronous reset (active low)
182 IF rstn = '0' THEN -- asynchronous reset (active low)
182 sample_data_shaping_out_val <= '0';
183 sample_data_shaping_out_val <= '0';
183 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
184 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
184 sample_data_shaping_out_val <= sample_filter_v2_out_val;
185 sample_data_shaping_out_val <= sample_filter_v2_out_val;
185 END IF;
186 END IF;
186 END PROCESS;
187 END PROCESS;
187
188
188 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
189 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
189 PROCESS (clk, rstn)
190 PROCESS (clk, rstn)
190 BEGIN
191 BEGIN
191 IF rstn = '0' THEN
192 IF rstn = '0' THEN
192 sample_data_shaping_out(0, j) <= '0';
193 sample_data_shaping_out(0, j) <= '0';
193 sample_data_shaping_out(1, j) <= '0';
194 sample_data_shaping_out(1, j) <= '0';
194 sample_data_shaping_out(2, j) <= '0';
195 sample_data_shaping_out(2, j) <= '0';
195 sample_data_shaping_out(3, j) <= '0';
196 sample_data_shaping_out(3, j) <= '0';
196 sample_data_shaping_out(4, j) <= '0';
197 sample_data_shaping_out(4, j) <= '0';
197 sample_data_shaping_out(5, j) <= '0';
198 sample_data_shaping_out(5, j) <= '0';
198 sample_data_shaping_out(6, j) <= '0';
199 sample_data_shaping_out(6, j) <= '0';
199 sample_data_shaping_out(7, j) <= '0';
200 sample_data_shaping_out(7, j) <= '0';
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
202 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
202 IF data_shaping_SP0 = '1' THEN
203 IF data_shaping_SP0 = '1' THEN
203 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
204 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
204 ELSE
205 ELSE
205 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
206 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
206 END IF;
207 END IF;
207 IF data_shaping_SP1 = '1' THEN
208 IF data_shaping_SP1 = '1' THEN
208 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
209 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
209 ELSE
210 ELSE
210 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
211 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
211 END IF;
212 END IF;
212 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
213 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
213 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
214 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
214 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
215 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
215 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
216 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
216 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
217 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
217 END IF;
218 END IF;
218 END PROCESS;
219 END PROCESS;
219 END GENERATE;
220 END GENERATE;
220
221
221 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
222 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
222 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
223 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
223 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
224 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
224 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
225 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
225 END GENERATE;
226 END GENERATE;
226 END GENERATE;
227 END GENERATE;
227 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
228 -- F0 -- @24.576 kHz
229 -- F0 -- @24.576 kHz
229 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
230 Downsampling_f0 : Downsampling
231 Downsampling_f0 : Downsampling
231 GENERIC MAP (
232 GENERIC MAP (
232 ChanelCount => 8,
233 ChanelCount => 8,
233 SampleSize => 16,
234 SampleSize => 16,
234 DivideParam => 4)
235 DivideParam => 4)
235 PORT MAP (
236 PORT MAP (
236 clk => clk,
237 clk => clk,
237 rstn => rstn,
238 rstn => rstn,
238 sample_in_val => sample_filter_v2_out_val_s,
239 sample_in_val => sample_filter_v2_out_val_s,
239 sample_in => sample_filter_v2_out_s,
240 sample_in => sample_filter_v2_out_s,
240 sample_out_val => sample_f0_val_s,
241 sample_out_val => sample_f0_val_s,
241 sample_out => sample_f0);
242 sample_out => sample_f0);
242
243
243 sample_f0_val <= sample_f0_val_s;
244 sample_f0_val <= sample_f0_val_s;
244
245
245 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
246 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
246 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
247 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
247 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
248 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
248 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
249 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
249 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
250 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
250 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
251 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
251 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
252 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
252 END GENERATE all_bit_sample_f0;
253 END GENERATE all_bit_sample_f0;
253
254
254 --sample_f0_wen <= NOT(sample_f0_val) &
255 --sample_f0_wen <= NOT(sample_f0_val) &
255 -- NOT(sample_f0_val) &
256 -- NOT(sample_f0_val) &
256 -- NOT(sample_f0_val) &
257 -- NOT(sample_f0_val) &
257 -- NOT(sample_f0_val) &
258 -- NOT(sample_f0_val) &
258 -- NOT(sample_f0_val) &
259 -- NOT(sample_f0_val) &
259 -- NOT(sample_f0_val);
260 -- NOT(sample_f0_val);
260
261
261 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
262 -- F1 -- @4096 Hz
263 -- F1 -- @4096 Hz
263 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
264 Downsampling_f1 : Downsampling
265 Downsampling_f1 : Downsampling
265 GENERIC MAP (
266 GENERIC MAP (
266 ChanelCount => 8,
267 ChanelCount => 8,
267 SampleSize => 16,
268 SampleSize => 16,
268 DivideParam => 6)
269 DivideParam => 6)
269 PORT MAP (
270 PORT MAP (
270 clk => clk,
271 clk => clk,
271 rstn => rstn,
272 rstn => rstn,
272 sample_in_val => sample_f0_val_s ,
273 sample_in_val => sample_f0_val_s ,
273 sample_in => sample_f0,
274 sample_in => sample_f0,
274 sample_out_val => sample_f1_val_s,
275 sample_out_val => sample_f1_val_s,
275 sample_out => sample_f1);
276 sample_out => sample_f1);
276
277
277 sample_f1_val <= sample_f1_val_s;
278 sample_f1_val <= sample_f1_val_s;
278
279
279 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
280 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
280 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
281 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
281 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
282 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
282 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
283 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
283 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
284 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
284 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
285 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
285 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
286 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
286 END GENERATE all_bit_sample_f1;
287 END GENERATE all_bit_sample_f1;
287
288
288 --sample_f1_wen <= NOT(sample_f1_val) &
289 --sample_f1_wen <= NOT(sample_f1_val) &
289 -- NOT(sample_f1_val) &
290 -- NOT(sample_f1_val) &
290 -- NOT(sample_f1_val) &
291 -- NOT(sample_f1_val) &
291 -- NOT(sample_f1_val) &
292 -- NOT(sample_f1_val) &
292 -- NOT(sample_f1_val) &
293 -- NOT(sample_f1_val) &
293 -- NOT(sample_f1_val);
294 -- NOT(sample_f1_val);
294
295
295 -----------------------------------------------------------------------------
296 -----------------------------------------------------------------------------
296 -- F2 -- @256 Hz
297 -- F2 -- @256 Hz
297 -----------------------------------------------------------------------------
298 -----------------------------------------------------------------------------
298 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
299 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
299 sample_f0_s(0, I) <= sample_f0(0, I); -- V
300 sample_f0_s(0, I) <= sample_f0(0, I); -- V
300 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
301 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
301 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
302 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
302 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
303 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
303 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
304 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
304 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
305 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
305 END GENERATE all_bit_sample_f0_s;
306 END GENERATE all_bit_sample_f0_s;
306
307
307 Downsampling_f2 : Downsampling
308 Downsampling_f2 : Downsampling
308 GENERIC MAP (
309 GENERIC MAP (
309 ChanelCount => 6,
310 ChanelCount => 6,
310 SampleSize => 16,
311 SampleSize => 16,
311 DivideParam => 96)
312 DivideParam => 96)
312 PORT MAP (
313 PORT MAP (
313 clk => clk,
314 clk => clk,
314 rstn => rstn,
315 rstn => rstn,
315 sample_in_val => sample_f0_val_s ,
316 sample_in_val => sample_f0_val_s ,
316 sample_in => sample_f0_s,
317 sample_in => sample_f0_s,
317 sample_out_val => sample_f2_val,
318 sample_out_val => sample_f2_val,
318 sample_out => sample_f2);
319 sample_out => sample_f2);
319
320
320 --sample_f2_wen <= NOT(sample_f2_val) &
321 --sample_f2_wen <= NOT(sample_f2_val) &
321 -- NOT(sample_f2_val) &
322 -- NOT(sample_f2_val) &
322 -- NOT(sample_f2_val) &
323 -- NOT(sample_f2_val) &
323 -- NOT(sample_f2_val) &
324 -- NOT(sample_f2_val) &
324 -- NOT(sample_f2_val) &
325 -- NOT(sample_f2_val) &
325 -- NOT(sample_f2_val);
326 -- NOT(sample_f2_val);
326
327
327 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
328 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
328 sample_f2_wdata_s(I) <= sample_f2(0, I);
329 sample_f2_wdata_s(I) <= sample_f2(0, I);
329 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
330 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(3, I);;
330 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
331 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I) WHEN data_shaping_R2 = '1' ELSE sample_f1(4, I);;
331 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
332 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
332 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
333 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
333 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
334 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
334 END GENERATE all_bit_sample_f2;
335 END GENERATE all_bit_sample_f2;
335
336
336 -----------------------------------------------------------------------------
337 -----------------------------------------------------------------------------
337 -- F3 -- @16 Hz
338 -- F3 -- @16 Hz
338 -----------------------------------------------------------------------------
339 -----------------------------------------------------------------------------
339 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
340 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
340 sample_f1_s(0, I) <= sample_f1(0, I); -- V
341 sample_f1_s(0, I) <= sample_f1(0, I); -- V
341 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
342 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
342 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
343 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
343 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
344 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
344 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
345 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
345 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
346 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
346 END GENERATE all_bit_sample_f1_s;
347 END GENERATE all_bit_sample_f1_s;
347
348
348 Downsampling_f3 : Downsampling
349 Downsampling_f3 : Downsampling
349 GENERIC MAP (
350 GENERIC MAP (
350 ChanelCount => 6,
351 ChanelCount => 6,
351 SampleSize => 16,
352 SampleSize => 16,
352 DivideParam => 256)
353 DivideParam => 256)
353 PORT MAP (
354 PORT MAP (
354 clk => clk,
355 clk => clk,
355 rstn => rstn,
356 rstn => rstn,
356 sample_in_val => sample_f1_val_s ,
357 sample_in_val => sample_f1_val_s ,
357 sample_in => sample_f1_s,
358 sample_in => sample_f1_s,
358 sample_out_val => sample_f3_val,
359 sample_out_val => sample_f3_val,
359 sample_out => sample_f3);
360 sample_out => sample_f3);
360
361
361 --sample_f3_wen <= (NOT sample_f3_val) &
362 --sample_f3_wen <= (NOT sample_f3_val) &
362 -- (NOT sample_f3_val) &
363 -- (NOT sample_f3_val) &
363 -- (NOT sample_f3_val) &
364 -- (NOT sample_f3_val) &
364 -- (NOT sample_f3_val) &
365 -- (NOT sample_f3_val) &
365 -- (NOT sample_f3_val) &
366 -- (NOT sample_f3_val) &
366 -- (NOT sample_f3_val);
367 -- (NOT sample_f3_val);
367
368
368 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
369 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
369 sample_f3_wdata_s(I) <= sample_f3(0, I);
370 sample_f3_wdata_s(I) <= sample_f3(0, I);
370 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
371 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
371 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
372 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
372 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
373 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
373 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
374 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
374 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
375 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
375 END GENERATE all_bit_sample_f3;
376 END GENERATE all_bit_sample_f3;
376
377
377 -----------------------------------------------------------------------------
378 -----------------------------------------------------------------------------
378 --
379 --
379 -----------------------------------------------------------------------------
380 -----------------------------------------------------------------------------
380 sample_f0_wdata <= sample_f0_wdata_s;
381 sample_f0_wdata <= sample_f0_wdata_s;
381 sample_f1_wdata <= sample_f1_wdata_s;
382 sample_f1_wdata <= sample_f1_wdata_s;
382 sample_f2_wdata <= sample_f2_wdata_s;
383 sample_f2_wdata <= sample_f2_wdata_s;
383 sample_f3_wdata <= sample_f3_wdata_s;
384 sample_f3_wdata <= sample_f3_wdata_s;
384
385
385 END tb; No newline at end of file
386 END tb;
Show file before | Show file after | Hide comments
@@ -1,1035 +1,1042
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 ---------------------------------------------------------------------------
25 ---------------------------------------------------------------------------
26 -- DATA INPUT
26 -- DATA INPUT
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- TIME
28 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
31 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- DMA
42 -- DMA
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
58
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63
63
64 -- Reg In
64 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC;
65 status_ready_matrix_f0 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
68
68
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78
78
79 );
79 );
80 END;
80 END;
81
81
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83
83
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89
89
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
95
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
102
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL error_wen_f0 : STD_LOGIC;
108 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
111
111
112 SIGNAL one_sample_f1_full : STD_LOGIC;
112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 -- FSM / SWITCH SELECT CHANNEL
118 -- FSM / SWITCH SELECT CHANNEL
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123
123
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128
128
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 -- FSM LOAD FFT
130 -- FSM LOAD FFT
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135
135
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_load : STD_LOGIC;
137 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141
141
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- FFT
144 -- FFT
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL fft_read : STD_LOGIC;
146 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_valid : STD_LOGIC;
150 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL current_fifo_empty : STD_LOGIC;
158 SIGNAL current_fifo_empty : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176
176
177 SIGNAL SM_correlation_start : STD_LOGIC;
177 SIGNAL SM_correlation_start : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
184
184
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188
188
189 SIGNAL current_matrix_write : STD_LOGIC;
189 SIGNAL current_matrix_write : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL fifo_0_ready : STD_LOGIC;
192 SIGNAL fifo_0_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
195
195
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
207
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 -- TIME REG & INFOs
209 -- TIME REG & INFOs
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212
212
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217
217
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222
222
223 --SIGNAL time_update_f0_A : STD_LOGIC;
223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
227 --
227 --
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231
231
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
237 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
238
238
239 SIGNAL fft_ready_reg : STD_LOGIC;
239 SIGNAL fft_ready_reg : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
240 SIGNAL fft_ready_rising_down : STD_LOGIC;
241
241
242 SIGNAL sample_load_reg : STD_LOGIC;
242 SIGNAL sample_load_reg : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
243 SIGNAL sample_load_rising_down : STD_LOGIC;
244
244
245 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
246 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
246 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
247 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
247 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
248 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
248 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
249 SIGNAL sample_f1_full_head_in : STD_LOGIC;
249 SIGNAL sample_f1_full_head_in : STD_LOGIC;
250 SIGNAL sample_f1_full_head_out : STD_LOGIC;
250 SIGNAL sample_f1_full_head_out : STD_LOGIC;
251 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
251 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
252
252
253 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
253 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
254
254
255 BEGIN
255 BEGIN
256
256
257
257
258 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
258 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
259
259
260
260
261 switch_f0_inst : spectral_matrix_switch_f0
261 switch_f0_inst : spectral_matrix_switch_f0
262 PORT MAP (
262 PORT MAP (
263 clk => clk,
263 clk => clk,
264 rstn => rstn,
264 rstn => rstn,
265
265
266 sample_wen => sample_f0_wen,
266 sample_wen => sample_f0_wen,
267
267
268 fifo_A_empty => sample_f0_A_empty,
268 fifo_A_empty => sample_f0_A_empty,
269 fifo_A_full => sample_f0_A_full,
269 fifo_A_full => sample_f0_A_full,
270 fifo_A_wen => sample_f0_A_wen,
270 fifo_A_wen => sample_f0_A_wen,
271
271
272 fifo_B_empty => sample_f0_B_empty,
272 fifo_B_empty => sample_f0_B_empty,
273 fifo_B_full => sample_f0_B_full,
273 fifo_B_full => sample_f0_B_full,
274 fifo_B_wen => sample_f0_B_wen,
274 fifo_B_wen => sample_f0_B_wen,
275
275
276 error_wen => error_wen_f0); -- TODO
276 error_wen => error_wen_f0); -- TODO
277
277
278 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
279 -- FIFO IN
279 -- FIFO IN
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 lppFIFOxN_f0_a : lppFIFOxN
281 lppFIFOxN_f0_a : lppFIFOxN
282 GENERIC MAP (
282 GENERIC MAP (
283 tech => 0,
283 tech => 0,
284 Mem_use => Mem_use,
284 Mem_use => Mem_use,
285 Data_sz => 16,
285 Data_sz => 16,
286 Addr_sz => 8,
286 Addr_sz => 8,
287 FifoCnt => 5)
287 FifoCnt => 5)
288 PORT MAP (
288 PORT MAP (
289 clk => clk,
289 clk => clk,
290 rstn => rstn,
290 rstn => rstn,
291
291
292 ReUse => (OTHERS => '0'),
292 ReUse => (OTHERS => '0'),
293
293
294 run => (OTHERS => '1'),
295
294 wen => sample_f0_A_wen,
296 wen => sample_f0_A_wen,
295 wdata => sample_f0_wdata,
297 wdata => sample_f0_wdata,
296
298
297 ren => sample_f0_A_ren,
299 ren => sample_f0_A_ren,
298 rdata => sample_f0_A_rdata,
300 rdata => sample_f0_A_rdata,
299
301
300 empty => sample_f0_A_empty,
302 empty => sample_f0_A_empty,
301 full => sample_f0_A_full,
303 full => sample_f0_A_full,
302 almost_full => OPEN);
304 almost_full => OPEN);
303
305
304 lppFIFOxN_f0_b : lppFIFOxN
306 lppFIFOxN_f0_b : lppFIFOxN
305 GENERIC MAP (
307 GENERIC MAP (
306 tech => 0,
308 tech => 0,
307 Mem_use => Mem_use,
309 Mem_use => Mem_use,
308 Data_sz => 16,
310 Data_sz => 16,
309 Addr_sz => 8,
311 Addr_sz => 8,
310 FifoCnt => 5)
312 FifoCnt => 5)
311 PORT MAP (
313 PORT MAP (
312 clk => clk,
314 clk => clk,
313 rstn => rstn,
315 rstn => rstn,
314
316
315 ReUse => (OTHERS => '0'),
317 ReUse => (OTHERS => '0'),
318 run => (OTHERS => '1'),
316
319
317 wen => sample_f0_B_wen,
320 wen => sample_f0_B_wen,
318 wdata => sample_f0_wdata,
321 wdata => sample_f0_wdata,
319 ren => sample_f0_B_ren,
322 ren => sample_f0_B_ren,
320 rdata => sample_f0_B_rdata,
323 rdata => sample_f0_B_rdata,
321 empty => sample_f0_B_empty,
324 empty => sample_f0_B_empty,
322 full => sample_f0_B_full,
325 full => sample_f0_B_full,
323 almost_full => OPEN);
326 almost_full => OPEN);
324
327
325 -----------------------------------------------------------------------------
328 -----------------------------------------------------------------------------
326 -- sample_f1_wen in
329 -- sample_f1_wen in
327 -- sample_f1_wdata in
330 -- sample_f1_wdata in
328 -- sample_f1_full OUT
331 -- sample_f1_full OUT
329
332
330 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
333 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
331 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
334 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
332 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
335 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
333
336
334 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
337 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
335 PORT MAP (
338 PORT MAP (
336 clk => clk,
339 clk => clk,
337 rstn => rstn,
340 rstn => rstn,
338 in_wen => sample_f1_wen_head_in,
341 in_wen => sample_f1_wen_head_in,
339 in_data => sample_f1_wdata,
342 in_data => sample_f1_wdata,
340 in_full => sample_f1_full_head_in,
343 in_full => sample_f1_full_head_in,
341 in_empty => sample_f1_empty_head_in,
344 in_empty => sample_f1_empty_head_in,
342 out_wen => sample_f1_wen_head_out,
345 out_wen => sample_f1_wen_head_out,
343 out_data => sample_f1_wdata_head,
346 out_data => sample_f1_wdata_head,
344 out_full => sample_f1_full_head_out);
347 out_full => sample_f1_full_head_out);
345
348
346 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
349 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
347
350
348
351
349 lppFIFOxN_f1 : lppFIFOxN
352 lppFIFOxN_f1 : lppFIFOxN
350 GENERIC MAP (
353 GENERIC MAP (
351 tech => 0,
354 tech => 0,
352 Mem_use => Mem_use,
355 Mem_use => Mem_use,
353 Data_sz => 16,
356 Data_sz => 16,
354 Addr_sz => 8,
357 Addr_sz => 8,
355 FifoCnt => 5)
358 FifoCnt => 5)
356 PORT MAP (
359 PORT MAP (
357 clk => clk,
360 clk => clk,
358 rstn => rstn,
361 rstn => rstn,
359
362
360 ReUse => (OTHERS => '0'),
363 ReUse => (OTHERS => '0'),
364 run => (OTHERS => '1'),
361
365
362 wen => sample_f1_wen_head,
366 wen => sample_f1_wen_head,
363 wdata => sample_f1_wdata_head,
367 wdata => sample_f1_wdata_head,
364 ren => sample_f1_ren,
368 ren => sample_f1_ren,
365 rdata => sample_f1_rdata,
369 rdata => sample_f1_rdata,
366 empty => sample_f1_empty,
370 empty => sample_f1_empty,
367 full => sample_f1_full,
371 full => sample_f1_full,
368 almost_full => sample_f1_almost_full);
372 almost_full => sample_f1_almost_full);
369
373
370
374
371 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
375 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
372
376
373 PROCESS (clk, rstn)
377 PROCESS (clk, rstn)
374 BEGIN -- PROCESS
378 BEGIN -- PROCESS
375 IF rstn = '0' THEN -- asynchronous reset (active low)
379 IF rstn = '0' THEN -- asynchronous reset (active low)
376 one_sample_f1_full <= '0';
380 one_sample_f1_full <= '0';
377 error_wen_f1 <= '0';
381 error_wen_f1 <= '0';
378 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
382 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
379 IF sample_f1_full_head_out = '0' THEN
383 IF sample_f1_full_head_out = '0' THEN
380 one_sample_f1_full <= '0';
384 one_sample_f1_full <= '0';
381 ELSE
385 ELSE
382 one_sample_f1_full <= '1';
386 one_sample_f1_full <= '1';
383 END IF;
387 END IF;
384 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
388 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
385 END IF;
389 END IF;
386 END PROCESS;
390 END PROCESS;
387
391
388 -----------------------------------------------------------------------------
392 -----------------------------------------------------------------------------
389
393
390
394
391 lppFIFOxN_f2 : lppFIFOxN
395 lppFIFOxN_f2 : lppFIFOxN
392 GENERIC MAP (
396 GENERIC MAP (
393 tech => 0,
397 tech => 0,
394 Mem_use => Mem_use,
398 Mem_use => Mem_use,
395 Data_sz => 16,
399 Data_sz => 16,
396 Addr_sz => 8,
400 Addr_sz => 8,
397 FifoCnt => 5)
401 FifoCnt => 5)
398 PORT MAP (
402 PORT MAP (
399 clk => clk,
403 clk => clk,
400 rstn => rstn,
404 rstn => rstn,
401
405
402 ReUse => (OTHERS => '0'),
406 ReUse => (OTHERS => '0'),
407 run => (OTHERS => '1'),
403
408
404 wen => sample_f2_wen,
409 wen => sample_f2_wen,
405 wdata => sample_f2_wdata,
410 wdata => sample_f2_wdata,
406 ren => sample_f2_ren,
411 ren => sample_f2_ren,
407 rdata => sample_f2_rdata,
412 rdata => sample_f2_rdata,
408 empty => sample_f2_empty,
413 empty => sample_f2_empty,
409 full => sample_f2_full,
414 full => sample_f2_full,
410 almost_full => OPEN);
415 almost_full => OPEN);
411
416
412
417
413 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
418 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
414
419
415 PROCESS (clk, rstn)
420 PROCESS (clk, rstn)
416 BEGIN -- PROCESS
421 BEGIN -- PROCESS
417 IF rstn = '0' THEN -- asynchronous reset (active low)
422 IF rstn = '0' THEN -- asynchronous reset (active low)
418 one_sample_f2_full <= '0';
423 one_sample_f2_full <= '0';
419 error_wen_f2 <= '0';
424 error_wen_f2 <= '0';
420 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
425 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
421 IF sample_f2_full = "00000" THEN
426 IF sample_f2_full = "00000" THEN
422 one_sample_f2_full <= '0';
427 one_sample_f2_full <= '0';
423 ELSE
428 ELSE
424 one_sample_f2_full <= '1';
429 one_sample_f2_full <= '1';
425 END IF;
430 END IF;
426 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
431 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
427 END IF;
432 END IF;
428 END PROCESS;
433 END PROCESS;
429
434
430 -----------------------------------------------------------------------------
435 -----------------------------------------------------------------------------
431 -- FSM SELECT CHANNEL
436 -- FSM SELECT CHANNEL
432 -----------------------------------------------------------------------------
437 -----------------------------------------------------------------------------
433 PROCESS (clk, rstn)
438 PROCESS (clk, rstn)
434 BEGIN
439 BEGIN
435 IF rstn = '0' THEN
440 IF rstn = '0' THEN
436 state_fsm_select_channel <= IDLE;
441 state_fsm_select_channel <= IDLE;
437 ELSIF clk'EVENT AND clk = '1' THEN
442 ELSIF clk'EVENT AND clk = '1' THEN
438 CASE state_fsm_select_channel IS
443 CASE state_fsm_select_channel IS
439 WHEN IDLE =>
444 WHEN IDLE =>
440 IF sample_f1_full = "11111" THEN
445 IF sample_f1_full = "11111" THEN
441 state_fsm_select_channel <= SWITCH_F1;
446 state_fsm_select_channel <= SWITCH_F1;
442 ELSIF sample_f1_almost_full = "00000" THEN
447 ELSIF sample_f1_almost_full = "00000" THEN
443 IF sample_f0_A_full = "11111" THEN
448 IF sample_f0_A_full = "11111" THEN
444 state_fsm_select_channel <= SWITCH_F0_A;
449 state_fsm_select_channel <= SWITCH_F0_A;
445 ELSIF sample_f0_B_full = "11111" THEN
450 ELSIF sample_f0_B_full = "11111" THEN
446 state_fsm_select_channel <= SWITCH_F0_B;
451 state_fsm_select_channel <= SWITCH_F0_B;
447 ELSIF sample_f2_full = "11111" THEN
452 ELSIF sample_f2_full = "11111" THEN
448 state_fsm_select_channel <= SWITCH_F2;
453 state_fsm_select_channel <= SWITCH_F2;
449 END IF;
454 END IF;
450 END IF;
455 END IF;
451
456
452 WHEN SWITCH_F0_A =>
457 WHEN SWITCH_F0_A =>
453 IF sample_f0_A_empty = "11111" THEN
458 IF sample_f0_A_empty = "11111" THEN
454 state_fsm_select_channel <= IDLE;
459 state_fsm_select_channel <= IDLE;
455 END IF;
460 END IF;
456 WHEN SWITCH_F0_B =>
461 WHEN SWITCH_F0_B =>
457 IF sample_f0_B_empty = "11111" THEN
462 IF sample_f0_B_empty = "11111" THEN
458 state_fsm_select_channel <= IDLE;
463 state_fsm_select_channel <= IDLE;
459 END IF;
464 END IF;
460 WHEN SWITCH_F1 =>
465 WHEN SWITCH_F1 =>
461 IF sample_f1_empty = "11111" THEN
466 IF sample_f1_empty = "11111" THEN
462 state_fsm_select_channel <= IDLE;
467 state_fsm_select_channel <= IDLE;
463 END IF;
468 END IF;
464 WHEN SWITCH_F2 =>
469 WHEN SWITCH_F2 =>
465 IF sample_f2_empty = "11111" THEN
470 IF sample_f2_empty = "11111" THEN
466 state_fsm_select_channel <= IDLE;
471 state_fsm_select_channel <= IDLE;
467 END IF;
472 END IF;
468 WHEN OTHERS => NULL;
473 WHEN OTHERS => NULL;
469 END CASE;
474 END CASE;
470
475
471 END IF;
476 END IF;
472 END PROCESS;
477 END PROCESS;
473
478
474 PROCESS (clk, rstn)
479 PROCESS (clk, rstn)
475 BEGIN
480 BEGIN
476 IF rstn = '0' THEN
481 IF rstn = '0' THEN
477 pre_state_fsm_select_channel <= IDLE;
482 pre_state_fsm_select_channel <= IDLE;
478 ELSIF clk'EVENT AND clk = '1' THEN
483 ELSIF clk'EVENT AND clk = '1' THEN
479 pre_state_fsm_select_channel <= state_fsm_select_channel;
484 pre_state_fsm_select_channel <= state_fsm_select_channel;
480 END IF;
485 END IF;
481 END PROCESS;
486 END PROCESS;
482
487
483
488
484 -----------------------------------------------------------------------------
489 -----------------------------------------------------------------------------
485 -- SWITCH SELECT CHANNEL
490 -- SWITCH SELECT CHANNEL
486 -----------------------------------------------------------------------------
491 -----------------------------------------------------------------------------
487 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
492 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
488 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
493 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
489 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
494 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
490 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
495 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
491 (OTHERS => '1');
496 (OTHERS => '1');
492
497
493 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
498 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
494 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
499 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
495 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
500 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
496 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
501 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
497 (OTHERS => '0');
502 (OTHERS => '0');
498
503
499 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
504 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
500 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
505 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
501 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
506 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
502 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
507 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
503
508
504
509
505 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
510 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
506 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
511 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
507 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
512 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
508 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
513 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
509
514
510
515
511 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
516 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
512 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
517 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
513 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
518 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
514 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
519 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
515
520
516 -----------------------------------------------------------------------------
521 -----------------------------------------------------------------------------
517 -- FSM LOAD FFT
522 -- FSM LOAD FFT
518 -----------------------------------------------------------------------------
523 -----------------------------------------------------------------------------
519
524
520 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
525 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
521 sample_ren_s WHEN sample_load = '1' ELSE
526 sample_ren_s WHEN sample_load = '1' ELSE
522 (OTHERS => '1');
527 (OTHERS => '1');
523
528
524 PROCESS (clk, rstn)
529 PROCESS (clk, rstn)
525 BEGIN
530 BEGIN
526 IF rstn = '0' THEN
531 IF rstn = '0' THEN
527 sample_ren_s <= (OTHERS => '1');
532 sample_ren_s <= (OTHERS => '1');
528 state_fsm_load_FFT <= IDLE;
533 state_fsm_load_FFT <= IDLE;
529 status_MS_input <= (OTHERS => '0');
534 status_MS_input <= (OTHERS => '0');
530 --next_state_fsm_load_FFT <= IDLE;
535 --next_state_fsm_load_FFT <= IDLE;
531 --sample_valid <= '0';
536 --sample_valid <= '0';
532 ELSIF clk'EVENT AND clk = '1' THEN
537 ELSIF clk'EVENT AND clk = '1' THEN
533 CASE state_fsm_load_FFT IS
538 CASE state_fsm_load_FFT IS
534 WHEN IDLE =>
539 WHEN IDLE =>
535 --sample_valid <= '0';
540 --sample_valid <= '0';
536 sample_ren_s <= (OTHERS => '1');
541 sample_ren_s <= (OTHERS => '1');
537 IF sample_full = "11111" AND sample_load = '1' THEN
542 IF sample_full = "11111" AND sample_load = '1' THEN
538 state_fsm_load_FFT <= FIFO_1;
543 state_fsm_load_FFT <= FIFO_1;
539 status_MS_input <= status_channel;
544 status_MS_input <= status_channel;
540 END IF;
545 END IF;
541
546
542 WHEN FIFO_1 =>
547 WHEN FIFO_1 =>
543 sample_ren_s <= "1111" & NOT(sample_load);
548 sample_ren_s <= "1111" & NOT(sample_load);
544 IF sample_empty(0) = '1' THEN
549 IF sample_empty(0) = '1' THEN
545 sample_ren_s <= (OTHERS => '1');
550 sample_ren_s <= (OTHERS => '1');
546 state_fsm_load_FFT <= FIFO_2;
551 state_fsm_load_FFT <= FIFO_2;
547 END IF;
552 END IF;
548
553
549 WHEN FIFO_2 =>
554 WHEN FIFO_2 =>
550 sample_ren_s <= "111" & NOT(sample_load) & '1';
555 sample_ren_s <= "111" & NOT(sample_load) & '1';
551 IF sample_empty(1) = '1' THEN
556 IF sample_empty(1) = '1' THEN
552 sample_ren_s <= (OTHERS => '1');
557 sample_ren_s <= (OTHERS => '1');
553 state_fsm_load_FFT <= FIFO_3;
558 state_fsm_load_FFT <= FIFO_3;
554 END IF;
559 END IF;
555
560
556 WHEN FIFO_3 =>
561 WHEN FIFO_3 =>
557 sample_ren_s <= "11" & NOT(sample_load) & "11";
562 sample_ren_s <= "11" & NOT(sample_load) & "11";
558 IF sample_empty(2) = '1' THEN
563 IF sample_empty(2) = '1' THEN
559 sample_ren_s <= (OTHERS => '1');
564 sample_ren_s <= (OTHERS => '1');
560 state_fsm_load_FFT <= FIFO_4;
565 state_fsm_load_FFT <= FIFO_4;
561 END IF;
566 END IF;
562
567
563 WHEN FIFO_4 =>
568 WHEN FIFO_4 =>
564 sample_ren_s <= '1' & NOT(sample_load) & "111";
569 sample_ren_s <= '1' & NOT(sample_load) & "111";
565 IF sample_empty(3) = '1' THEN
570 IF sample_empty(3) = '1' THEN
566 sample_ren_s <= (OTHERS => '1');
571 sample_ren_s <= (OTHERS => '1');
567 state_fsm_load_FFT <= FIFO_5;
572 state_fsm_load_FFT <= FIFO_5;
568 END IF;
573 END IF;
569
574
570 WHEN FIFO_5 =>
575 WHEN FIFO_5 =>
571 sample_ren_s <= NOT(sample_load) & "1111";
576 sample_ren_s <= NOT(sample_load) & "1111";
572 IF sample_empty(4) = '1' THEN
577 IF sample_empty(4) = '1' THEN
573 sample_ren_s <= (OTHERS => '1');
578 sample_ren_s <= (OTHERS => '1');
574 state_fsm_load_FFT <= IDLE;
579 state_fsm_load_FFT <= IDLE;
575 END IF;
580 END IF;
576 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
577 END CASE;
582 END CASE;
578 END IF;
583 END IF;
579 END PROCESS;
584 END PROCESS;
580
585
581 PROCESS (clk, rstn)
586 PROCESS (clk, rstn)
582 BEGIN
587 BEGIN
583 IF rstn = '0' THEN
588 IF rstn = '0' THEN
584 sample_valid_r <= '0';
589 sample_valid_r <= '0';
585 next_state_fsm_load_FFT <= IDLE;
590 next_state_fsm_load_FFT <= IDLE;
586 ELSIF clk'EVENT AND clk = '1' THEN
591 ELSIF clk'EVENT AND clk = '1' THEN
587 next_state_fsm_load_FFT <= state_fsm_load_FFT;
592 next_state_fsm_load_FFT <= state_fsm_load_FFT;
588 IF sample_ren_s = "11111" THEN
593 IF sample_ren_s = "11111" THEN
589 sample_valid_r <= '0';
594 sample_valid_r <= '0';
590 ELSE
595 ELSE
591 sample_valid_r <= '1';
596 sample_valid_r <= '1';
592 END IF;
597 END IF;
593 END IF;
598 END IF;
594 END PROCESS;
599 END PROCESS;
595
600
596 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
601 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
597
602
598 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
603 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
599 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
604 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
600 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
605 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
601 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
606 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
602 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
607 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
603
608
604 -----------------------------------------------------------------------------
609 -----------------------------------------------------------------------------
605 -- FFT
610 -- FFT
606 -----------------------------------------------------------------------------
611 -----------------------------------------------------------------------------
607 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
612 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
608 PORT MAP (
613 PORT MAP (
609 clk => clk,
614 clk => clk,
610 rstn => rstn,
615 rstn => rstn,
611 sample_valid => sample_valid,
616 sample_valid => sample_valid,
612 fft_read => fft_read,
617 fft_read => fft_read,
613 sample_data => sample_data,
618 sample_data => sample_data,
614 sample_load => sample_load,
619 sample_load => sample_load,
615 fft_pong => fft_pong,
620 fft_pong => fft_pong,
616 fft_data_im => fft_data_im,
621 fft_data_im => fft_data_im,
617 fft_data_re => fft_data_re,
622 fft_data_re => fft_data_re,
618 fft_data_valid => fft_data_valid,
623 fft_data_valid => fft_data_valid,
619 fft_ready => fft_ready);
624 fft_ready => fft_ready);
620
625
621 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
626 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
622 fft_ongoing_counter & --9 8
627 fft_ongoing_counter & --9 8
623 sample_load_rising_down & --7
628 sample_load_rising_down & --7
624 fft_ready_rising_down & --6
629 fft_ready_rising_down & --6
625 fft_ready & --5
630 fft_ready & --5
626 fft_data_valid & --4
631 fft_data_valid & --4
627 fft_pong & --3
632 fft_pong & --3
628 sample_load & --2
633 sample_load & --2
629 fft_read & --1
634 fft_read & --1
630 sample_valid; --0
635 sample_valid; --0
631
636
632 -----------------------------------------------------------------------------
637 -----------------------------------------------------------------------------
633 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
638 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
634 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
639 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
635
640
636 PROCESS (clk, rstn)
641 PROCESS (clk, rstn)
637 BEGIN
642 BEGIN
638 IF rstn = '0' THEN
643 IF rstn = '0' THEN
639 fft_ready_reg <= '0';
644 fft_ready_reg <= '0';
640 sample_load_reg <= '0';
645 sample_load_reg <= '0';
641
646
642 fft_ongoing_counter <= '0';
647 fft_ongoing_counter <= '0';
643 ELSIF clk'event AND clk = '1' THEN
648 ELSIF clk'event AND clk = '1' THEN
644 fft_ready_reg <= fft_ready;
649 fft_ready_reg <= fft_ready;
645 sample_load_reg <= sample_load;
650 sample_load_reg <= sample_load;
646
651
647 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
652 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
648 fft_ongoing_counter <= '0';
653 fft_ongoing_counter <= '0';
649
654
650 -- CASE fft_ongoing_counter IS
655 -- CASE fft_ongoing_counter IS
651 -- WHEN "01" => fft_ongoing_counter <= "00";
656 -- WHEN "01" => fft_ongoing_counter <= "00";
652 ---- WHEN "10" => fft_ongoing_counter <= "01";
657 ---- WHEN "10" => fft_ongoing_counter <= "01";
653 -- WHEN OTHERS => NULL;
658 -- WHEN OTHERS => NULL;
654 -- END CASE;
659 -- END CASE;
655 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
660 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
656 fft_ongoing_counter <= '1';
661 fft_ongoing_counter <= '1';
657 -- CASE fft_ongoing_counter IS
662 -- CASE fft_ongoing_counter IS
658 -- WHEN "00" => fft_ongoing_counter <= "01";
663 -- WHEN "00" => fft_ongoing_counter <= "01";
659 ---- WHEN "01" => fft_ongoing_counter <= "10";
664 ---- WHEN "01" => fft_ongoing_counter <= "10";
660 -- WHEN OTHERS => NULL;
665 -- WHEN OTHERS => NULL;
661 -- END CASE;
666 -- END CASE;
662 END IF;
667 END IF;
663
668
664 END IF;
669 END IF;
665 END PROCESS;
670 END PROCESS;
666
671
667 -----------------------------------------------------------------------------
672 -----------------------------------------------------------------------------
668 PROCESS (clk, rstn)
673 PROCESS (clk, rstn)
669 BEGIN
674 BEGIN
670 IF rstn = '0' THEN
675 IF rstn = '0' THEN
671 state_fsm_load_MS_memory <= IDLE;
676 state_fsm_load_MS_memory <= IDLE;
672 current_fifo_load <= "00001";
677 current_fifo_load <= "00001";
673 ELSIF clk'EVENT AND clk = '1' THEN
678 ELSIF clk'EVENT AND clk = '1' THEN
674 CASE state_fsm_load_MS_memory IS
679 CASE state_fsm_load_MS_memory IS
675 WHEN IDLE =>
680 WHEN IDLE =>
676 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
681 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
677 state_fsm_load_MS_memory <= LOAD_FIFO;
682 state_fsm_load_MS_memory <= LOAD_FIFO;
678 END IF;
683 END IF;
679 WHEN LOAD_FIFO =>
684 WHEN LOAD_FIFO =>
680 IF current_fifo_full = '1' THEN
685 IF current_fifo_full = '1' THEN
681 state_fsm_load_MS_memory <= TRASH_FFT;
686 state_fsm_load_MS_memory <= TRASH_FFT;
682 END IF;
687 END IF;
683 WHEN TRASH_FFT =>
688 WHEN TRASH_FFT =>
684 IF fft_ready = '0' THEN
689 IF fft_ready = '0' THEN
685 state_fsm_load_MS_memory <= IDLE;
690 state_fsm_load_MS_memory <= IDLE;
686 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
691 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
687 END IF;
692 END IF;
688 WHEN OTHERS => NULL;
693 WHEN OTHERS => NULL;
689 END CASE;
694 END CASE;
690
695
691 END IF;
696 END IF;
692 END PROCESS;
697 END PROCESS;
693
698
694 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
699 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
695 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
700 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
696 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
701 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
697 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
702 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
698 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
703 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
699
704
700 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
705 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
701 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
706 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
702 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
707 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
703 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
708 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
704 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
709 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
705
710
706 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
711 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
707 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
712 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
708 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
713 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
709 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
714 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
710 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
715 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
711
716
712 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
717 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
713
718
714 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
719 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
715 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
720 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
716 AND state_fsm_load_MS_memory = LOAD_FIFO
721 AND state_fsm_load_MS_memory = LOAD_FIFO
717 AND current_fifo_load(I) = '1'
722 AND current_fifo_load(I) = '1'
718 ELSE '1';
723 ELSE '1';
719 END GENERATE all_fifo;
724 END GENERATE all_fifo;
720
725
721 PROCESS (clk, rstn)
726 PROCESS (clk, rstn)
722 BEGIN
727 BEGIN
723 IF rstn = '0' THEN
728 IF rstn = '0' THEN
724 MEM_IN_SM_wen <= (OTHERS => '1');
729 MEM_IN_SM_wen <= (OTHERS => '1');
725 ELSIF clk'EVENT AND clk = '1' THEN
730 ELSIF clk'EVENT AND clk = '1' THEN
726 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
731 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
727 END IF;
732 END IF;
728 END PROCESS;
733 END PROCESS;
729
734
730 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
735 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
731 (fft_data_im & fft_data_re) &
736 (fft_data_im & fft_data_re) &
732 (fft_data_im & fft_data_re) &
737 (fft_data_im & fft_data_re) &
733 (fft_data_im & fft_data_re) &
738 (fft_data_im & fft_data_re) &
734 (fft_data_im & fft_data_re);
739 (fft_data_im & fft_data_re);
735 -----------------------------------------------------------------------------
740 -----------------------------------------------------------------------------
736
741
737
742
738 -----------------------------------------------------------------------------
743 -----------------------------------------------------------------------------
739 Mem_In_SpectralMatrix : lppFIFOxN
744 Mem_In_SpectralMatrix : lppFIFOxN
740 GENERIC MAP (
745 GENERIC MAP (
741 tech => 0,
746 tech => 0,
742 Mem_use => Mem_use,
747 Mem_use => Mem_use,
743 Data_sz => 32, --16,
748 Data_sz => 32, --16,
744 Addr_sz => 7, --8
749 Addr_sz => 7, --8
745 FifoCnt => 5)
750 FifoCnt => 5)
746 PORT MAP (
751 PORT MAP (
747 clk => clk,
752 clk => clk,
748 rstn => rstn,
753 rstn => rstn,
749
754
750 ReUse => MEM_IN_SM_ReUse,
755 ReUse => MEM_IN_SM_ReUse,
756 run => (OTHERS => '1'),
751
757
752 wen => MEM_IN_SM_wen,
758 wen => MEM_IN_SM_wen,
753 wdata => MEM_IN_SM_wData,
759 wdata => MEM_IN_SM_wData,
754
760
755 ren => MEM_IN_SM_ren,
761 ren => MEM_IN_SM_ren,
756 rdata => MEM_IN_SM_rData,
762 rdata => MEM_IN_SM_rData,
757 full => MEM_IN_SM_Full,
763 full => MEM_IN_SM_Full,
758 empty => MEM_IN_SM_Empty,
764 empty => MEM_IN_SM_Empty,
759 almost_full => OPEN);
765 almost_full => OPEN);
760
766
761 -----------------------------------------------------------------------------
767 -----------------------------------------------------------------------------
762
768
763 observation_vector_1(11 DOWNTO 0) <= '0' &
769 observation_vector_1(11 DOWNTO 0) <= '0' &
764 SM_correlation_done & --4
770 SM_correlation_done & --4
765 SM_correlation_auto & --3
771 SM_correlation_auto & --3
766 SM_correlation_start &
772 SM_correlation_start &
767 SM_correlation_start & --7
773 SM_correlation_start & --7
768 status_MS_input(1 DOWNTO 0)& --6..5
774 status_MS_input(1 DOWNTO 0)& --6..5
769 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
775 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
770
776
771 -----------------------------------------------------------------------------
777 -----------------------------------------------------------------------------
772 MS_control_1 : MS_control
778 MS_control_1 : MS_control
773 PORT MAP (
779 PORT MAP (
774 clk => clk,
780 clk => clk,
775 rstn => rstn,
781 rstn => rstn,
776
782
777 current_status_ms => status_MS_input,
783 current_status_ms => status_MS_input,
778
784
779 fifo_in_lock => MEM_IN_SM_locked,
785 fifo_in_lock => MEM_IN_SM_locked,
780 fifo_in_data => MEM_IN_SM_rdata,
786 fifo_in_data => MEM_IN_SM_rdata,
781 fifo_in_full => MEM_IN_SM_Full,
787 fifo_in_full => MEM_IN_SM_Full,
782 fifo_in_empty => MEM_IN_SM_Empty,
788 fifo_in_empty => MEM_IN_SM_Empty,
783 fifo_in_ren => MEM_IN_SM_ren,
789 fifo_in_ren => MEM_IN_SM_ren,
784 fifo_in_reuse => MEM_IN_SM_ReUse,
790 fifo_in_reuse => MEM_IN_SM_ReUse,
785
791
786 fifo_out_data => SM_in_data,
792 fifo_out_data => SM_in_data,
787 fifo_out_ren => SM_in_ren,
793 fifo_out_ren => SM_in_ren,
788 fifo_out_empty => SM_in_empty,
794 fifo_out_empty => SM_in_empty,
789
795
790 current_status_component => status_component,
796 current_status_component => status_component,
791
797
792 correlation_start => SM_correlation_start,
798 correlation_start => SM_correlation_start,
793 correlation_auto => SM_correlation_auto,
799 correlation_auto => SM_correlation_auto,
794 correlation_done => SM_correlation_done);
800 correlation_done => SM_correlation_done);
795
801
796
802
797 MS_calculation_1 : MS_calculation
803 MS_calculation_1 : MS_calculation
798 PORT MAP (
804 PORT MAP (
799 clk => clk,
805 clk => clk,
800 rstn => rstn,
806 rstn => rstn,
801
807
802 fifo_in_data => SM_in_data,
808 fifo_in_data => SM_in_data,
803 fifo_in_ren => SM_in_ren,
809 fifo_in_ren => SM_in_ren,
804 fifo_in_empty => SM_in_empty,
810 fifo_in_empty => SM_in_empty,
805
811
806 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
812 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
807 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
813 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
808 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
814 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
809
815
810 correlation_start => SM_correlation_start,
816 correlation_start => SM_correlation_start,
811 correlation_auto => SM_correlation_auto,
817 correlation_auto => SM_correlation_auto,
812 correlation_begin => SM_correlation_begin,
818 correlation_begin => SM_correlation_begin,
813 correlation_done => SM_correlation_done);
819 correlation_done => SM_correlation_done);
814
820
815 -----------------------------------------------------------------------------
821 -----------------------------------------------------------------------------
816 PROCESS (clk, rstn)
822 PROCESS (clk, rstn)
817 BEGIN -- PROCESS
823 BEGIN -- PROCESS
818 IF rstn = '0' THEN -- asynchronous reset (active low)
824 IF rstn = '0' THEN -- asynchronous reset (active low)
819 current_matrix_write <= '0';
825 current_matrix_write <= '0';
820 current_matrix_wait_empty <= '1';
826 current_matrix_wait_empty <= '1';
821 status_component_fifo_0 <= (OTHERS => '0');
827 status_component_fifo_0 <= (OTHERS => '0');
822 status_component_fifo_1 <= (OTHERS => '0');
828 status_component_fifo_1 <= (OTHERS => '0');
823 status_component_fifo_0_end <= '0';
829 status_component_fifo_0_end <= '0';
824 status_component_fifo_1_end <= '0';
830 status_component_fifo_1_end <= '0';
825 SM_correlation_done_reg1 <= '0';
831 SM_correlation_done_reg1 <= '0';
826 SM_correlation_done_reg2 <= '0';
832 SM_correlation_done_reg2 <= '0';
827 SM_correlation_done_reg3 <= '0';
833 SM_correlation_done_reg3 <= '0';
828
834
829 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
835 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
830 SM_correlation_done_reg1 <= SM_correlation_done;
836 SM_correlation_done_reg1 <= SM_correlation_done;
831 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
837 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
832 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
838 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
833 status_component_fifo_0_end <= '0';
839 status_component_fifo_0_end <= '0';
834 status_component_fifo_1_end <= '0';
840 status_component_fifo_1_end <= '0';
835 IF SM_correlation_begin = '1' THEN
841 IF SM_correlation_begin = '1' THEN
836 IF current_matrix_write = '0' THEN
842 IF current_matrix_write = '0' THEN
837 status_component_fifo_0 <= status_component;
843 status_component_fifo_0 <= status_component;
838 ELSE
844 ELSE
839 status_component_fifo_1 <= status_component;
845 status_component_fifo_1 <= status_component;
840 END IF;
846 END IF;
841 END IF;
847 END IF;
842
848
843 IF SM_correlation_done_reg3 = '1' THEN
849 IF SM_correlation_done_reg3 = '1' THEN
844 IF current_matrix_write = '0' THEN
850 IF current_matrix_write = '0' THEN
845 status_component_fifo_0_end <= '1';
851 status_component_fifo_0_end <= '1';
846 ELSE
852 ELSE
847 status_component_fifo_1_end <= '1';
853 status_component_fifo_1_end <= '1';
848 END IF;
854 END IF;
849 current_matrix_wait_empty <= '1';
855 current_matrix_wait_empty <= '1';
850 current_matrix_write <= NOT current_matrix_write;
856 current_matrix_write <= NOT current_matrix_write;
851 END IF;
857 END IF;
852
858
853 IF current_matrix_wait_empty <= '1' THEN
859 IF current_matrix_wait_empty <= '1' THEN
854 IF current_matrix_write = '0' THEN
860 IF current_matrix_write = '0' THEN
855 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
861 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
856 ELSE
862 ELSE
857 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
863 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
858 END IF;
864 END IF;
859 END IF;
865 END IF;
860
866
861 END IF;
867 END IF;
862 END PROCESS;
868 END PROCESS;
863
869
864 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
870 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
865 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
871 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
866 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
872 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
867 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
873 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
868 '1' WHEN current_matrix_wait_empty = '1' ELSE
874 '1' WHEN current_matrix_wait_empty = '1' ELSE
869 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
875 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
870 MEM_OUT_SM_Full(1);
876 MEM_OUT_SM_Full(1);
871
877
872 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
878 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
873 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
879 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
874
880
875 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
881 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
876 -----------------------------------------------------------------------------
882 -----------------------------------------------------------------------------
877
883
878 Mem_Out_SpectralMatrix : lppFIFOxN
884 Mem_Out_SpectralMatrix : lppFIFOxN
879 GENERIC MAP (
885 GENERIC MAP (
880 tech => 0,
886 tech => 0,
881 Mem_use => Mem_use,
887 Mem_use => Mem_use,
882 Data_sz => 32,
888 Data_sz => 32,
883 Addr_sz => 8,
889 Addr_sz => 8,
884 FifoCnt => 2)
890 FifoCnt => 2)
885 PORT MAP (
891 PORT MAP (
886 clk => clk,
892 clk => clk,
887 rstn => rstn,
893 rstn => rstn,
888
894
889 ReUse => (OTHERS => '0'),
895 ReUse => (OTHERS => '0'),
896 run => (OTHERS => '1'),
890
897
891 wen => MEM_OUT_SM_Write,
898 wen => MEM_OUT_SM_Write,
892 wdata => MEM_OUT_SM_Data_in,
899 wdata => MEM_OUT_SM_Data_in,
893
900
894 ren => MEM_OUT_SM_Read,
901 ren => MEM_OUT_SM_Read,
895 rdata => MEM_OUT_SM_Data_out,
902 rdata => MEM_OUT_SM_Data_out,
896
903
897 full => MEM_OUT_SM_Full,
904 full => MEM_OUT_SM_Full,
898 empty => MEM_OUT_SM_Empty,
905 empty => MEM_OUT_SM_Empty,
899 almost_full => OPEN);
906 almost_full => OPEN);
900
907
901 -----------------------------------------------------------------------------
908 -----------------------------------------------------------------------------
902 -- MEM_OUT_SM_Read <= "00";
909 -- MEM_OUT_SM_Read <= "00";
903 PROCESS (clk, rstn)
910 PROCESS (clk, rstn)
904 BEGIN
911 BEGIN
905 IF rstn = '0' THEN
912 IF rstn = '0' THEN
906 fifo_0_ready <= '0';
913 fifo_0_ready <= '0';
907 fifo_1_ready <= '0';
914 fifo_1_ready <= '0';
908 fifo_ongoing <= '0';
915 fifo_ongoing <= '0';
909 ELSIF clk'EVENT AND clk = '1' THEN
916 ELSIF clk'EVENT AND clk = '1' THEN
910 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
917 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
911 fifo_ongoing <= '1';
918 fifo_ongoing <= '1';
912 fifo_0_ready <= '0';
919 fifo_0_ready <= '0';
913 ELSIF status_component_fifo_0_end = '1' THEN
920 ELSIF status_component_fifo_0_end = '1' THEN
914 fifo_0_ready <= '1';
921 fifo_0_ready <= '1';
915 END IF;
922 END IF;
916
923
917 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
924 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
918 fifo_ongoing <= '0';
925 fifo_ongoing <= '0';
919 fifo_1_ready <= '0';
926 fifo_1_ready <= '0';
920 ELSIF status_component_fifo_1_end = '1' THEN
927 ELSIF status_component_fifo_1_end = '1' THEN
921 fifo_1_ready <= '1';
928 fifo_1_ready <= '1';
922 END IF;
929 END IF;
923
930
924 END IF;
931 END IF;
925 END PROCESS;
932 END PROCESS;
926
933
927 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
934 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
928 '1' WHEN fifo_0_ready = '0' ELSE
935 '1' WHEN fifo_0_ready = '0' ELSE
929 FSM_DMA_fifo_ren;
936 FSM_DMA_fifo_ren;
930
937
931 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
938 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
932 '1' WHEN fifo_1_ready = '0' ELSE
939 '1' WHEN fifo_1_ready = '0' ELSE
933 FSM_DMA_fifo_ren;
940 FSM_DMA_fifo_ren;
934
941
935 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
942 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
936 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
943 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
937 '1';
944 '1';
938
945
939 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
946 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
940 status_component_fifo_1;
947 status_component_fifo_1;
941
948
942 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
949 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
943 MEM_OUT_SM_Data_out(63 DOWNTO 32);
950 MEM_OUT_SM_Data_out(63 DOWNTO 32);
944
951
945 -----------------------------------------------------------------------------
952 -----------------------------------------------------------------------------
946 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
953 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
947 PORT MAP (
954 PORT MAP (
948 HCLK => clk,
955 HCLK => clk,
949 HRESETn => rstn,
956 HRESETn => rstn,
950
957
951 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
958 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
952 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
959 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
953 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
960 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
954 fifo_data => FSM_DMA_fifo_data,
961 fifo_data => FSM_DMA_fifo_data,
955 fifo_empty => FSM_DMA_fifo_empty,
962 fifo_empty => FSM_DMA_fifo_empty,
956 fifo_ren => FSM_DMA_fifo_ren,
963 fifo_ren => FSM_DMA_fifo_ren,
957
964
958 dma_addr => dma_addr,
965 dma_addr => dma_addr,
959 dma_data => dma_data,
966 dma_data => dma_data,
960 dma_valid => dma_valid,
967 dma_valid => dma_valid,
961 dma_valid_burst => dma_valid_burst,
968 dma_valid_burst => dma_valid_burst,
962 dma_ren => dma_ren,
969 dma_ren => dma_ren,
963 dma_done => dma_done,
970 dma_done => dma_done,
964
971
965 ready_matrix_f0 => ready_matrix_f0,
972 ready_matrix_f0 => ready_matrix_f0,
966 ready_matrix_f1 => ready_matrix_f1,
973 ready_matrix_f1 => ready_matrix_f1,
967 ready_matrix_f2 => ready_matrix_f2,
974 ready_matrix_f2 => ready_matrix_f2,
968
975
969 error_bad_component_error => error_bad_component_error,
976 error_bad_component_error => error_bad_component_error,
970 error_buffer_full => error_buffer_full,
977 error_buffer_full => error_buffer_full,
971
978
972 debug_reg => debug_reg,
979 debug_reg => debug_reg,
973 status_ready_matrix_f0 => status_ready_matrix_f0,
980 status_ready_matrix_f0 => status_ready_matrix_f0,
974 status_ready_matrix_f1 => status_ready_matrix_f1,
981 status_ready_matrix_f1 => status_ready_matrix_f1,
975 status_ready_matrix_f2 => status_ready_matrix_f2,
982 status_ready_matrix_f2 => status_ready_matrix_f2,
976
983
977 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
984 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
978 config_active_interruption_onError => config_active_interruption_onError,
985 config_active_interruption_onError => config_active_interruption_onError,
979
986
980 addr_matrix_f0 => addr_matrix_f0,
987 addr_matrix_f0 => addr_matrix_f0,
981 addr_matrix_f1 => addr_matrix_f1,
988 addr_matrix_f1 => addr_matrix_f1,
982 addr_matrix_f2 => addr_matrix_f2,
989 addr_matrix_f2 => addr_matrix_f2,
983
990
984 matrix_time_f0 => matrix_time_f0,
991 matrix_time_f0 => matrix_time_f0,
985 matrix_time_f1 => matrix_time_f1,
992 matrix_time_f1 => matrix_time_f1,
986 matrix_time_f2 => matrix_time_f2
993 matrix_time_f2 => matrix_time_f2
987 );
994 );
988 -----------------------------------------------------------------------------
995 -----------------------------------------------------------------------------
989
996
990
997
991
998
992
999
993
1000
994 -----------------------------------------------------------------------------
1001 -----------------------------------------------------------------------------
995 -- TIME MANAGMENT
1002 -- TIME MANAGMENT
996 -----------------------------------------------------------------------------
1003 -----------------------------------------------------------------------------
997 all_time <= coarse_time & fine_time;
1004 all_time <= coarse_time & fine_time;
998 --
1005 --
999 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1006 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1000 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1007 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1001 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1008 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1002 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1009 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1003
1010
1004 all_time_reg: FOR I IN 0 TO 3 GENERATE
1011 all_time_reg: FOR I IN 0 TO 3 GENERATE
1005
1012
1006 PROCESS (clk, rstn)
1013 PROCESS (clk, rstn)
1007 BEGIN
1014 BEGIN
1008 IF rstn = '0' THEN
1015 IF rstn = '0' THEN
1009 f_empty_reg(I) <= '1';
1016 f_empty_reg(I) <= '1';
1010 ELSIF clk'event AND clk = '1' THEN
1017 ELSIF clk'event AND clk = '1' THEN
1011 f_empty_reg(I) <= f_empty(I);
1018 f_empty_reg(I) <= f_empty(I);
1012 END IF;
1019 END IF;
1013 END PROCESS;
1020 END PROCESS;
1014
1021
1015 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1022 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1016
1023
1017 s_m_t_m_f0_A : spectral_matrix_time_managment
1024 s_m_t_m_f0_A : spectral_matrix_time_managment
1018 PORT MAP (
1025 PORT MAP (
1019 clk => clk,
1026 clk => clk,
1020 rstn => rstn,
1027 rstn => rstn,
1021 time_in => all_time,
1028 time_in => all_time,
1022 update_1 => time_update_f(I),
1029 update_1 => time_update_f(I),
1023 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1030 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1024 );
1031 );
1025
1032
1026 END GENERATE all_time_reg;
1033 END GENERATE all_time_reg;
1027
1034
1028 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1035 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1029 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1036 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1030 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1037 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1031 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1038 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1032
1039
1033 -----------------------------------------------------------------------------
1040 -----------------------------------------------------------------------------
1034
1041
1035 END Behavioral;
1042 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,429 +1,431
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER
72 Mem_use : INTEGER
73 );
73 );
74 PORT (
74 PORT (
75 clk : IN STD_LOGIC;
75 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
77
77
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
80
80
81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83
83
84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86
86
87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89
89
90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 dma_valid : OUT STD_LOGIC;
92 dma_valid : OUT STD_LOGIC;
93 dma_valid_burst : OUT STD_LOGIC;
93 dma_valid_burst : OUT STD_LOGIC;
94 dma_ren : IN STD_LOGIC;
94 dma_ren : IN STD_LOGIC;
95 dma_done : IN STD_LOGIC;
95 dma_done : IN STD_LOGIC;
96
96
97 ready_matrix_f0 : OUT STD_LOGIC;
97 ready_matrix_f0 : OUT STD_LOGIC;
98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
99 ready_matrix_f1 : OUT STD_LOGIC;
99 ready_matrix_f1 : OUT STD_LOGIC;
100 ready_matrix_f2 : OUT STD_LOGIC;
100 ready_matrix_f2 : OUT STD_LOGIC;
101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
102 error_bad_component_error : OUT STD_LOGIC;
102 error_bad_component_error : OUT STD_LOGIC;
103 error_buffer_full : OUT STD_LOGIC;
103 error_buffer_full : OUT STD_LOGIC;
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --
106 --
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
109 -------------------------------------------------------------------------
109 -------------------------------------------------------------------------
110 status_ready_matrix_f0 : IN STD_LOGIC;
110 status_ready_matrix_f0 : IN STD_LOGIC;
111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
112 status_ready_matrix_f1 : IN STD_LOGIC;
112 status_ready_matrix_f1 : IN STD_LOGIC;
113 status_ready_matrix_f2 : IN STD_LOGIC;
113 status_ready_matrix_f2 : IN STD_LOGIC;
114 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
114 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
115 -- status_error_bad_component_error : IN STD_LOGIC;
115 -- status_error_bad_component_error : IN STD_LOGIC;
116 config_active_interruption_onNewMatrix : IN STD_LOGIC;
116 config_active_interruption_onNewMatrix : IN STD_LOGIC;
117 config_active_interruption_onError : IN STD_LOGIC;
117 config_active_interruption_onError : IN STD_LOGIC;
118 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122
122
123 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
123 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
124 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
124 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
125 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
125 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
126 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
126 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
127 END COMPONENT;
127 END COMPONENT;
128
128
129 COMPONENT lpp_lfr_ms_fsmdma
129 COMPONENT lpp_lfr_ms_fsmdma
130 PORT (
130 PORT (
131 HCLK : IN STD_ULOGIC;
131 HCLK : IN STD_ULOGIC;
132 HRESETn : IN STD_ULOGIC;
132 HRESETn : IN STD_ULOGIC;
133 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
133 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
134 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
135 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
135 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
136 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fifo_empty : IN STD_LOGIC;
137 fifo_empty : IN STD_LOGIC;
138 fifo_ren : OUT STD_LOGIC;
138 fifo_ren : OUT STD_LOGIC;
139 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
139 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
140 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 --fifo_empty : IN STD_LOGIC;
141 --fifo_empty : IN STD_LOGIC;
142 --fifo_ren : OUT STD_LOGIC;
142 --fifo_ren : OUT STD_LOGIC;
143 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
143 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 --header_val : IN STD_LOGIC;
144 --header_val : IN STD_LOGIC;
145 --header_ack : OUT STD_LOGIC;
145 --header_ack : OUT STD_LOGIC;
146 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
146 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 dma_valid : OUT STD_LOGIC;
148 dma_valid : OUT STD_LOGIC;
149 dma_valid_burst : OUT STD_LOGIC;
149 dma_valid_burst : OUT STD_LOGIC;
150 dma_ren : IN STD_LOGIC;
150 dma_ren : IN STD_LOGIC;
151 dma_done : IN STD_LOGIC;
151 dma_done : IN STD_LOGIC;
152 ready_matrix_f0 : OUT STD_LOGIC;
152 ready_matrix_f0 : OUT STD_LOGIC;
153 -- ready_matrix_f0_1 : OUT STD_LOGIC;
153 -- ready_matrix_f0_1 : OUT STD_LOGIC;
154 ready_matrix_f1 : OUT STD_LOGIC;
154 ready_matrix_f1 : OUT STD_LOGIC;
155 ready_matrix_f2 : OUT STD_LOGIC;
155 ready_matrix_f2 : OUT STD_LOGIC;
156 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
156 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
157 error_bad_component_error : OUT STD_LOGIC;
157 error_bad_component_error : OUT STD_LOGIC;
158 error_buffer_full : OUT STD_LOGIC;
158 error_buffer_full : OUT STD_LOGIC;
159 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 status_ready_matrix_f0 : IN STD_LOGIC;
160 status_ready_matrix_f0 : IN STD_LOGIC;
161 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
161 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
162 status_ready_matrix_f1 : IN STD_LOGIC;
162 status_ready_matrix_f1 : IN STD_LOGIC;
163 status_ready_matrix_f2 : IN STD_LOGIC;
163 status_ready_matrix_f2 : IN STD_LOGIC;
164 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
164 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
165 -- status_error_bad_component_error : IN STD_LOGIC;
165 -- status_error_bad_component_error : IN STD_LOGIC;
166 config_active_interruption_onNewMatrix : IN STD_LOGIC;
166 config_active_interruption_onNewMatrix : IN STD_LOGIC;
167 config_active_interruption_onError : IN STD_LOGIC;
167 config_active_interruption_onError : IN STD_LOGIC;
168 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
172
172
173 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
173 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
174 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
174 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
175 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
175 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
176 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
176 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
177 );
177 );
178 END COMPONENT;
178 END COMPONENT;
179
179
180 COMPONENT lpp_lfr_ms_FFT
180 COMPONENT lpp_lfr_ms_FFT
181 PORT (
181 PORT (
182 clk : IN STD_LOGIC;
182 clk : IN STD_LOGIC;
183 rstn : IN STD_LOGIC;
183 rstn : IN STD_LOGIC;
184 sample_valid : IN STD_LOGIC;
184 sample_valid : IN STD_LOGIC;
185 fft_read : IN STD_LOGIC;
185 fft_read : IN STD_LOGIC;
186 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
186 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
187 sample_load : OUT STD_LOGIC;
187 sample_load : OUT STD_LOGIC;
188 fft_pong : OUT STD_LOGIC;
188 fft_pong : OUT STD_LOGIC;
189 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
189 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
190 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
190 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
191 fft_data_valid : OUT STD_LOGIC;
191 fft_data_valid : OUT STD_LOGIC;
192 fft_ready : OUT STD_LOGIC);
192 fft_ready : OUT STD_LOGIC);
193 END COMPONENT;
193 END COMPONENT;
194
194
195 COMPONENT lpp_lfr_filter
195 COMPONENT lpp_lfr_filter
196 GENERIC (
196 GENERIC (
197 Mem_use : INTEGER);
197 Mem_use : INTEGER);
198 PORT (
198 PORT (
199 sample : IN Samples(7 DOWNTO 0);
199 sample : IN Samples(7 DOWNTO 0);
200 sample_val : IN STD_LOGIC;
200 sample_val : IN STD_LOGIC;
201 clk : IN STD_LOGIC;
201 clk : IN STD_LOGIC;
202 rstn : IN STD_LOGIC;
202 rstn : IN STD_LOGIC;
203 data_shaping_SP0 : IN STD_LOGIC;
203 data_shaping_SP0 : IN STD_LOGIC;
204 data_shaping_SP1 : IN STD_LOGIC;
204 data_shaping_SP1 : IN STD_LOGIC;
205 data_shaping_R0 : IN STD_LOGIC;
205 data_shaping_R0 : IN STD_LOGIC;
206 data_shaping_R1 : IN STD_LOGIC;
206 data_shaping_R1 : IN STD_LOGIC;
207 data_shaping_R2 : IN STD_LOGIC;
207 sample_f0_val : OUT STD_LOGIC;
208 sample_f0_val : OUT STD_LOGIC;
208 sample_f1_val : OUT STD_LOGIC;
209 sample_f1_val : OUT STD_LOGIC;
209 sample_f2_val : OUT STD_LOGIC;
210 sample_f2_val : OUT STD_LOGIC;
210 sample_f3_val : OUT STD_LOGIC;
211 sample_f3_val : OUT STD_LOGIC;
211 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
212 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
212 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
213 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
213 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
214 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
214 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
215 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
215 END COMPONENT;
216 END COMPONENT;
216
217
217 COMPONENT lpp_lfr
218 COMPONENT lpp_lfr
218 GENERIC (
219 GENERIC (
219 Mem_use : INTEGER;
220 Mem_use : INTEGER;
220 nb_data_by_buffer_size : INTEGER;
221 nb_data_by_buffer_size : INTEGER;
221 nb_word_by_buffer_size : INTEGER;
222 nb_word_by_buffer_size : INTEGER;
222 nb_snapshot_param_size : INTEGER;
223 nb_snapshot_param_size : INTEGER;
223 delta_vector_size : INTEGER;
224 delta_vector_size : INTEGER;
224 delta_vector_size_f0_2 : INTEGER;
225 delta_vector_size_f0_2 : INTEGER;
225 pindex : INTEGER;
226 pindex : INTEGER;
226 paddr : INTEGER;
227 paddr : INTEGER;
227 pmask : INTEGER;
228 pmask : INTEGER;
228 pirq_ms : INTEGER;
229 pirq_ms : INTEGER;
229 pirq_wfp : INTEGER;
230 pirq_wfp : INTEGER;
230 hindex : INTEGER;
231 hindex : INTEGER;
231 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
232 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
232 );
233 );
233 PORT (
234 PORT (
234 clk : IN STD_LOGIC;
235 clk : IN STD_LOGIC;
235 rstn : IN STD_LOGIC;
236 rstn : IN STD_LOGIC;
236 sample_B : IN Samples(2 DOWNTO 0);
237 sample_B : IN Samples(2 DOWNTO 0);
237 sample_E : IN Samples(4 DOWNTO 0);
238 sample_E : IN Samples(4 DOWNTO 0);
238 sample_val : IN STD_LOGIC;
239 sample_val : IN STD_LOGIC;
239 apbi : IN apb_slv_in_type;
240 apbi : IN apb_slv_in_type;
240 apbo : OUT apb_slv_out_type;
241 apbo : OUT apb_slv_out_type;
241 ahbi : IN AHB_Mst_In_Type;
242 ahbi : IN AHB_Mst_In_Type;
242 ahbo : OUT AHB_Mst_Out_Type;
243 ahbo : OUT AHB_Mst_Out_Type;
243 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
245 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
245 data_shaping_BW : OUT STD_LOGIC;
246 data_shaping_BW : OUT STD_LOGIC;
246 --
247 --
247 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
248 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
248 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
249 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
249 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
250 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
250 );
251 );
251 END COMPONENT;
252 END COMPONENT;
252
253
253 -----------------------------------------------------------------------------
254 -----------------------------------------------------------------------------
254 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
255 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
255 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
256 COMPONENT lpp_lfr_WFP_nMS
257 COMPONENT lpp_lfr_WFP_nMS
257 GENERIC (
258 GENERIC (
258 Mem_use : INTEGER;
259 Mem_use : INTEGER;
259 nb_data_by_buffer_size : INTEGER;
260 nb_data_by_buffer_size : INTEGER;
260 nb_word_by_buffer_size : INTEGER;
261 nb_word_by_buffer_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
262 nb_snapshot_param_size : INTEGER;
262 delta_vector_size : INTEGER;
263 delta_vector_size : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
264 delta_vector_size_f0_2 : INTEGER;
264 pindex : INTEGER;
265 pindex : INTEGER;
265 paddr : INTEGER;
266 paddr : INTEGER;
266 pmask : INTEGER;
267 pmask : INTEGER;
267 pirq_ms : INTEGER;
268 pirq_ms : INTEGER;
268 pirq_wfp : INTEGER;
269 pirq_wfp : INTEGER;
269 hindex : INTEGER;
270 hindex : INTEGER;
270 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
271 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
271 PORT (
272 PORT (
272 clk : IN STD_LOGIC;
273 clk : IN STD_LOGIC;
273 rstn : IN STD_LOGIC;
274 rstn : IN STD_LOGIC;
274 sample_B : IN Samples(2 DOWNTO 0);
275 sample_B : IN Samples(2 DOWNTO 0);
275 sample_E : IN Samples(4 DOWNTO 0);
276 sample_E : IN Samples(4 DOWNTO 0);
276 sample_val : IN STD_LOGIC;
277 sample_val : IN STD_LOGIC;
277 apbi : IN apb_slv_in_type;
278 apbi : IN apb_slv_in_type;
278 apbo : OUT apb_slv_out_type;
279 apbo : OUT apb_slv_out_type;
279 ahbi : IN AHB_Mst_In_Type;
280 ahbi : IN AHB_Mst_In_Type;
280 ahbo : OUT AHB_Mst_Out_Type;
281 ahbo : OUT AHB_Mst_Out_Type;
281 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
283 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
283 data_shaping_BW : OUT STD_LOGIC;
284 data_shaping_BW : OUT STD_LOGIC;
284 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
285 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
285 END COMPONENT;
286 END COMPONENT;
286 -----------------------------------------------------------------------------
287 -----------------------------------------------------------------------------
287 COMPONENT lpp_lfr_apbreg
288 COMPONENT lpp_lfr_apbreg
288 GENERIC (
289 GENERIC (
289 nb_data_by_buffer_size : INTEGER;
290 nb_data_by_buffer_size : INTEGER;
290 nb_word_by_buffer_size : INTEGER;
291 nb_word_by_buffer_size : INTEGER;
291 nb_snapshot_param_size : INTEGER;
292 nb_snapshot_param_size : INTEGER;
292 delta_vector_size : INTEGER;
293 delta_vector_size : INTEGER;
293 delta_vector_size_f0_2 : INTEGER;
294 delta_vector_size_f0_2 : INTEGER;
294 pindex : INTEGER;
295 pindex : INTEGER;
295 paddr : INTEGER;
296 paddr : INTEGER;
296 pmask : INTEGER;
297 pmask : INTEGER;
297 pirq_ms : INTEGER;
298 pirq_ms : INTEGER;
298 pirq_wfp : INTEGER;
299 pirq_wfp : INTEGER;
299 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
300 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
300 PORT (
301 PORT (
301 HCLK : IN STD_ULOGIC;
302 HCLK : IN STD_ULOGIC;
302 HRESETn : IN STD_ULOGIC;
303 HRESETn : IN STD_ULOGIC;
303 apbi : IN apb_slv_in_type;
304 apbi : IN apb_slv_in_type;
304 apbo : OUT apb_slv_out_type;
305 apbo : OUT apb_slv_out_type;
305 run_ms : OUT STD_LOGIC;
306 run_ms : OUT STD_LOGIC;
306 ready_matrix_f0 : IN STD_LOGIC;
307 ready_matrix_f0 : IN STD_LOGIC;
307 ready_matrix_f1 : IN STD_LOGIC;
308 ready_matrix_f1 : IN STD_LOGIC;
308 ready_matrix_f2 : IN STD_LOGIC;
309 ready_matrix_f2 : IN STD_LOGIC;
309 error_bad_component_error : IN STD_LOGIC;
310 error_bad_component_error : IN STD_LOGIC;
310 error_buffer_full : in STD_LOGIC;
311 error_buffer_full : in STD_LOGIC;
311 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
312 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
312 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
313 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
313 status_ready_matrix_f0 : OUT STD_LOGIC;
314 status_ready_matrix_f0 : OUT STD_LOGIC;
314 status_ready_matrix_f1 : OUT STD_LOGIC;
315 status_ready_matrix_f1 : OUT STD_LOGIC;
315 status_ready_matrix_f2 : OUT STD_LOGIC;
316 status_ready_matrix_f2 : OUT STD_LOGIC;
316 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
317 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
317 config_active_interruption_onError : OUT STD_LOGIC;
318 config_active_interruption_onError : OUT STD_LOGIC;
318 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
319 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
319 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
323 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
323 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
325 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
325 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
326 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
326 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
328 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
328 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 data_shaping_BW : OUT STD_LOGIC;
331 data_shaping_BW : OUT STD_LOGIC;
331 data_shaping_SP0 : OUT STD_LOGIC;
332 data_shaping_SP0 : OUT STD_LOGIC;
332 data_shaping_SP1 : OUT STD_LOGIC;
333 data_shaping_SP1 : OUT STD_LOGIC;
333 data_shaping_R0 : OUT STD_LOGIC;
334 data_shaping_R0 : OUT STD_LOGIC;
334 data_shaping_R1 : OUT STD_LOGIC;
335 data_shaping_R1 : OUT STD_LOGIC;
336 data_shaping_R2 : OUT STD_LOGIC;
335 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
337 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
336 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
338 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
337 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
339 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
338 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
340 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
339 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
341 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
340 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
342 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
341 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
343 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
342 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
344 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
343 enable_f0 : OUT STD_LOGIC;
345 enable_f0 : OUT STD_LOGIC;
344 enable_f1 : OUT STD_LOGIC;
346 enable_f1 : OUT STD_LOGIC;
345 enable_f2 : OUT STD_LOGIC;
347 enable_f2 : OUT STD_LOGIC;
346 enable_f3 : OUT STD_LOGIC;
348 enable_f3 : OUT STD_LOGIC;
347 burst_f0 : OUT STD_LOGIC;
349 burst_f0 : OUT STD_LOGIC;
348 burst_f1 : OUT STD_LOGIC;
350 burst_f1 : OUT STD_LOGIC;
349 burst_f2 : OUT STD_LOGIC;
351 burst_f2 : OUT STD_LOGIC;
350 run : OUT STD_LOGIC;
352 run : OUT STD_LOGIC;
351 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
356 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
357 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
356
358
357 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
359 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
358
360
359 );
361 );
360 END COMPONENT;
362 END COMPONENT;
361
363
362
364
363
365
364 COMPONENT lpp_top_ms
366 COMPONENT lpp_top_ms
365 GENERIC (
367 GENERIC (
366 Mem_use : INTEGER;
368 Mem_use : INTEGER;
367 nb_burst_available_size : INTEGER;
369 nb_burst_available_size : INTEGER;
368 nb_snapshot_param_size : INTEGER;
370 nb_snapshot_param_size : INTEGER;
369 delta_snapshot_size : INTEGER;
371 delta_snapshot_size : INTEGER;
370 delta_f2_f0_size : INTEGER;
372 delta_f2_f0_size : INTEGER;
371 delta_f2_f1_size : INTEGER;
373 delta_f2_f1_size : INTEGER;
372 pindex : INTEGER;
374 pindex : INTEGER;
373 paddr : INTEGER;
375 paddr : INTEGER;
374 pmask : INTEGER;
376 pmask : INTEGER;
375 pirq_ms : INTEGER;
377 pirq_ms : INTEGER;
376 pirq_wfp : INTEGER;
378 pirq_wfp : INTEGER;
377 hindex_wfp : INTEGER;
379 hindex_wfp : INTEGER;
378 hindex_ms : INTEGER);
380 hindex_ms : INTEGER);
379 PORT (
381 PORT (
380 clk : IN STD_LOGIC;
382 clk : IN STD_LOGIC;
381 rstn : IN STD_LOGIC;
383 rstn : IN STD_LOGIC;
382 sample_B : IN Samples14v(2 DOWNTO 0);
384 sample_B : IN Samples14v(2 DOWNTO 0);
383 sample_E : IN Samples14v(4 DOWNTO 0);
385 sample_E : IN Samples14v(4 DOWNTO 0);
384 sample_val : IN STD_LOGIC;
386 sample_val : IN STD_LOGIC;
385 apbi : IN apb_slv_in_type;
387 apbi : IN apb_slv_in_type;
386 apbo : OUT apb_slv_out_type;
388 apbo : OUT apb_slv_out_type;
387 ahbi_ms : IN AHB_Mst_In_Type;
389 ahbi_ms : IN AHB_Mst_In_Type;
388 ahbo_ms : OUT AHB_Mst_Out_Type;
390 ahbo_ms : OUT AHB_Mst_Out_Type;
389 data_shaping_BW : OUT STD_LOGIC;
391 data_shaping_BW : OUT STD_LOGIC;
390 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
392 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
391 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
393 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
392 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
394 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
393 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
395 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
394
396
395 );
397 );
396 END COMPONENT;
398 END COMPONENT;
397
399
398 COMPONENT lpp_apbreg_ms_pointer
400 COMPONENT lpp_apbreg_ms_pointer
399 PORT (
401 PORT (
400 clk : IN STD_LOGIC;
402 clk : IN STD_LOGIC;
401 rstn : IN STD_LOGIC;
403 rstn : IN STD_LOGIC;
402 reg0_status_ready_matrix : IN STD_LOGIC;
404 reg0_status_ready_matrix : IN STD_LOGIC;
403 reg0_ready_matrix : OUT STD_LOGIC;
405 reg0_ready_matrix : OUT STD_LOGIC;
404 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
406 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
405 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
407 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
406 reg1_status_ready_matrix : IN STD_LOGIC;
408 reg1_status_ready_matrix : IN STD_LOGIC;
407 reg1_ready_matrix : OUT STD_LOGIC;
409 reg1_ready_matrix : OUT STD_LOGIC;
408 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
410 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
409 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
411 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
410 ready_matrix : IN STD_LOGIC;
412 ready_matrix : IN STD_LOGIC;
411 status_ready_matrix : OUT STD_LOGIC;
413 status_ready_matrix : OUT STD_LOGIC;
412 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
414 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
413 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
415 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
414 END COMPONENT;
416 END COMPONENT;
415
417
416 COMPONENT lpp_lfr_ms_reg_head
418 COMPONENT lpp_lfr_ms_reg_head
417 PORT (
419 PORT (
418 clk : IN STD_LOGIC;
420 clk : IN STD_LOGIC;
419 rstn : IN STD_LOGIC;
421 rstn : IN STD_LOGIC;
420 in_wen : IN STD_LOGIC;
422 in_wen : IN STD_LOGIC;
421 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
423 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
422 in_full : IN STD_LOGIC;
424 in_full : IN STD_LOGIC;
423 in_empty : IN STD_LOGIC;
425 in_empty : IN STD_LOGIC;
424 out_wen : OUT STD_LOGIC;
426 out_wen : OUT STD_LOGIC;
425 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
427 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
426 out_full : OUT STD_LOGIC);
428 out_full : OUT STD_LOGIC);
427 END COMPONENT;
429 END COMPONENT;
428
430
429 END lpp_lfr_pkg;
431 END lpp_lfr_pkg;
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@@ -1,558 +1,597
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.lpp_memory.ALL;
35
37
36 LIBRARY techmap;
38 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
38
40
39 ENTITY lpp_waveform IS
41 ENTITY lpp_waveform IS
40
42
41 GENERIC (
43 GENERIC (
42 tech : INTEGER := inferred;
44 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
45 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
46 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
47 nb_word_by_buffer_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
48 nb_snapshot_param_size : INTEGER := 11;
47 delta_vector_size : INTEGER := 20;
49 delta_vector_size : INTEGER := 20;
48 delta_vector_size_f0_2 : INTEGER := 3);
50 delta_vector_size_f0_2 : INTEGER := 3);
49
51
50 PORT (
52 PORT (
51 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
53
55
54 ---- AMBA AHB Master Interface
56 ---- AMBA AHB Master Interface
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57
59
58 --config
60 --config
59 reg_run : IN STD_LOGIC;
61 reg_run : IN STD_LOGIC;
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
68
67 enable_f0 : IN STD_LOGIC;
69 enable_f0 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
70 enable_f1 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
71 enable_f2 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
72 enable_f3 : IN STD_LOGIC;
71
73
72 burst_f0 : IN STD_LOGIC;
74 burst_f0 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
75 burst_f1 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
76 burst_f2 : IN STD_LOGIC;
75
77
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
84 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
84 -- INPUT
86 -- INPUT
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
88 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
89
88 --f0
90 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
92 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
93 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
94 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
95 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
96 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
97 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
98 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
100 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
102 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
104 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104
106
105 ---------------------------------------------------------------------------
107 ---------------------------------------------------------------------------
106 -- OUTPUT
108 -- OUTPUT
107 --f0
109 --f0
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
111 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
112 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
113 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
114 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
115 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
118 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
119 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
120 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
121 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
124 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
125 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
126 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
127 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
130 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
131 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
132 data_f3_data_out_ren : IN STD_LOGIC;
131
133
132 ---------------------------------------------------------------------------
134 ---------------------------------------------------------------------------
133 --
135 --
134 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
136 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
135
137
136
138
137 ----debug SNAPSHOT OUT
139 ----debug SNAPSHOT OUT
138 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 --debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 --debug_f0_data_valid : OUT STD_LOGIC;
141 --debug_f0_data_valid : OUT STD_LOGIC;
140 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 --debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 --debug_f1_data_valid : OUT STD_LOGIC;
143 --debug_f1_data_valid : OUT STD_LOGIC;
142 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 --debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 --debug_f2_data_valid : OUT STD_LOGIC;
145 --debug_f2_data_valid : OUT STD_LOGIC;
144 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 --debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 --debug_f3_data_valid : OUT STD_LOGIC;
147 --debug_f3_data_valid : OUT STD_LOGIC;
146
148
147 ----debug FIFO IN
149 ----debug FIFO IN
148 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
151 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
150 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
153 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
152 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
154 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
153 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
155 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
154 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
157 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC
156
158
157 );
159 );
158
160
159 END lpp_waveform;
161 END lpp_waveform;
160
162
161 ARCHITECTURE beh OF lpp_waveform IS
163 ARCHITECTURE beh OF lpp_waveform IS
162 SIGNAL start_snapshot_f0 : STD_LOGIC;
164 SIGNAL start_snapshot_f0 : STD_LOGIC;
163 SIGNAL start_snapshot_f1 : STD_LOGIC;
165 SIGNAL start_snapshot_f1 : STD_LOGIC;
164 SIGNAL start_snapshot_f2 : STD_LOGIC;
166 SIGNAL start_snapshot_f2 : STD_LOGIC;
165
167
166 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
168 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
167 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
168 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
169 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
171 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170
172
171 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175
177
176 SIGNAL data_f0_out_valid : STD_LOGIC;
178 SIGNAL data_f0_out_valid : STD_LOGIC;
177 SIGNAL data_f1_out_valid : STD_LOGIC;
179 SIGNAL data_f1_out_valid : STD_LOGIC;
178 SIGNAL data_f2_out_valid : STD_LOGIC;
180 SIGNAL data_f2_out_valid : STD_LOGIC;
179 SIGNAL data_f3_out_valid : STD_LOGIC;
181 SIGNAL data_f3_out_valid : STD_LOGIC;
180 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
182 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
181 --
183 --
182 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
191 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
190 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
196 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
195 --
197 --
196 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
198 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
197 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
198 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 --
202 --
201 SIGNAL run : STD_LOGIC;
203 SIGNAL run : STD_LOGIC;
202 --
204 --
203 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
205 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
204 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
206 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
205 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
207 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
206 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
208 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
207 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
209 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
208 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
210 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
210 --
212 --
211
213
212 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
214 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
213 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
216
219
217 --
220 --
218
221
219 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
223 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
224
221
225
222 BEGIN -- beh
226 BEGIN -- beh
223
227
228
224 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
225 -- DEBUG
230 -- DEBUG
226 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
227 PROCESS (clk, rstn)
232 PROCESS (clk, rstn)
228 BEGIN -- PROCESS
233 BEGIN -- PROCESS
229 IF rstn = '0' THEN -- asynchronous reset (active low)
234 IF rstn = '0' THEN -- asynchronous reset (active low)
230 observation_reg <= (OTHERS => '0');
235 observation_reg <= (OTHERS => '0');
231 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
236 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
232 observation_reg <= observation_reg_s;
237 observation_reg <= observation_reg_s;
233 END IF;
238 END IF;
234 END PROCESS;
239 END PROCESS;
235 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
240 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
236 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
241 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
237 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
242 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
238 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
243 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
239 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
244 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
240 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
245 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
241 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
242
247
243 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
248 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
244 GENERIC MAP (
249 GENERIC MAP (
245 delta_vector_size => delta_vector_size,
250 delta_vector_size => delta_vector_size,
246 delta_vector_size_f0_2 => delta_vector_size_f0_2
251 delta_vector_size_f0_2 => delta_vector_size_f0_2
247 )
252 )
248 PORT MAP (
253 PORT MAP (
249 clk => clk,
254 clk => clk,
250 rstn => rstn,
255 rstn => rstn,
251 reg_run => reg_run,
256 reg_run => reg_run,
252 reg_start_date => reg_start_date,
257 reg_start_date => reg_start_date,
253 reg_delta_snapshot => reg_delta_snapshot,
258 reg_delta_snapshot => reg_delta_snapshot,
254 reg_delta_f0 => reg_delta_f0,
259 reg_delta_f0 => reg_delta_f0,
255 reg_delta_f0_2 => reg_delta_f0_2,
260 reg_delta_f0_2 => reg_delta_f0_2,
256 reg_delta_f1 => reg_delta_f1,
261 reg_delta_f1 => reg_delta_f1,
257 reg_delta_f2 => reg_delta_f2,
262 reg_delta_f2 => reg_delta_f2,
258 coarse_time => coarse_time(30 DOWNTO 0),
263 coarse_time => coarse_time(30 DOWNTO 0),
259 data_f0_valid => data_f0_in_valid,
264 data_f0_valid => data_f0_in_valid,
260 data_f2_valid => data_f2_in_valid,
265 data_f2_valid => data_f2_in_valid,
261 start_snapshot_f0 => start_snapshot_f0,
266 start_snapshot_f0 => start_snapshot_f0,
262 start_snapshot_f1 => start_snapshot_f1,
267 start_snapshot_f1 => start_snapshot_f1,
263 start_snapshot_f2 => start_snapshot_f2,
268 start_snapshot_f2 => start_snapshot_f2,
264 wfp_on => run);
269 wfp_on => run);
265
270
266 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
271 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
267 GENERIC MAP (
272 GENERIC MAP (
268 data_size => data_size,
273 data_size => data_size,
269 nb_snapshot_param_size => nb_snapshot_param_size)
274 nb_snapshot_param_size => nb_snapshot_param_size)
270 PORT MAP (
275 PORT MAP (
271 clk => clk,
276 clk => clk,
272 rstn => rstn,
277 rstn => rstn,
273 run => run,
278 run => run,
274 enable => enable_f0,
279 enable => enable_f0,
275 burst_enable => burst_f0,
280 burst_enable => burst_f0,
276 nb_snapshot_param => nb_snapshot_param,
281 nb_snapshot_param => nb_snapshot_param,
277 start_snapshot => start_snapshot_f0,
282 start_snapshot => start_snapshot_f0,
278 data_in => data_f0_in,
283 data_in => data_f0_in,
279 data_in_valid => data_f0_in_valid,
284 data_in_valid => data_f0_in_valid,
280 data_out => data_f0_out,
285 data_out => data_f0_out,
281 data_out_valid => data_f0_out_valid);
286 data_out_valid => data_f0_out_valid);
282
287
283 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
288 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
284
289
285 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
290 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
286 GENERIC MAP (
291 GENERIC MAP (
287 data_size => data_size,
292 data_size => data_size,
288 nb_snapshot_param_size => nb_snapshot_param_size+1)
293 nb_snapshot_param_size => nb_snapshot_param_size+1)
289 PORT MAP (
294 PORT MAP (
290 clk => clk,
295 clk => clk,
291 rstn => rstn,
296 rstn => rstn,
292 run => run,
297 run => run,
293 enable => enable_f1,
298 enable => enable_f1,
294 burst_enable => burst_f1,
299 burst_enable => burst_f1,
295 nb_snapshot_param => nb_snapshot_param_more_one,
300 nb_snapshot_param => nb_snapshot_param_more_one,
296 start_snapshot => start_snapshot_f1,
301 start_snapshot => start_snapshot_f1,
297 data_in => data_f1_in,
302 data_in => data_f1_in,
298 data_in_valid => data_f1_in_valid,
303 data_in_valid => data_f1_in_valid,
299 data_out => data_f1_out,
304 data_out => data_f1_out,
300 data_out_valid => data_f1_out_valid);
305 data_out_valid => data_f1_out_valid);
301
306
302 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
307 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
303 GENERIC MAP (
308 GENERIC MAP (
304 data_size => data_size,
309 data_size => data_size,
305 nb_snapshot_param_size => nb_snapshot_param_size+1)
310 nb_snapshot_param_size => nb_snapshot_param_size+1)
306 PORT MAP (
311 PORT MAP (
307 clk => clk,
312 clk => clk,
308 rstn => rstn,
313 rstn => rstn,
309 run => run,
314 run => run,
310 enable => enable_f2,
315 enable => enable_f2,
311 burst_enable => burst_f2,
316 burst_enable => burst_f2,
312 nb_snapshot_param => nb_snapshot_param_more_one,
317 nb_snapshot_param => nb_snapshot_param_more_one,
313 start_snapshot => start_snapshot_f2,
318 start_snapshot => start_snapshot_f2,
314 data_in => data_f2_in,
319 data_in => data_f2_in,
315 data_in_valid => data_f2_in_valid,
320 data_in_valid => data_f2_in_valid,
316 data_out => data_f2_out,
321 data_out => data_f2_out,
317 data_out_valid => data_f2_out_valid);
322 data_out_valid => data_f2_out_valid);
318
323
319 lpp_waveform_burst_f3 : lpp_waveform_burst
324 lpp_waveform_burst_f3 : lpp_waveform_burst
320 GENERIC MAP (
325 GENERIC MAP (
321 data_size => data_size)
326 data_size => data_size)
322 PORT MAP (
327 PORT MAP (
323 clk => clk,
328 clk => clk,
324 rstn => rstn,
329 rstn => rstn,
325 run => run,
330 run => run,
326 enable => enable_f3,
331 enable => enable_f3,
327 data_in => data_f3_in,
332 data_in => data_f3_in,
328 data_in_valid => data_f3_in_valid,
333 data_in_valid => data_f3_in_valid,
329 data_out => data_f3_out,
334 data_out => data_f3_out,
330 data_out_valid => data_f3_out_valid);
335 data_out_valid => data_f3_out_valid);
331
336
332 -----------------------------------------------------------------------------
337 -----------------------------------------------------------------------------
333 -- DEBUG -- SNAPSHOT OUT
338 -- DEBUG -- SNAPSHOT OUT
334 --debug_f0_data_valid <= data_f0_out_valid;
339 --debug_f0_data_valid <= data_f0_out_valid;
335 --debug_f0_data <= data_f0_out;
340 --debug_f0_data <= data_f0_out;
336 --debug_f1_data_valid <= data_f1_out_valid;
341 --debug_f1_data_valid <= data_f1_out_valid;
337 --debug_f1_data <= data_f1_out;
342 --debug_f1_data <= data_f1_out;
338 --debug_f2_data_valid <= data_f2_out_valid;
343 --debug_f2_data_valid <= data_f2_out_valid;
339 --debug_f2_data <= data_f2_out;
344 --debug_f2_data <= data_f2_out;
340 --debug_f3_data_valid <= data_f3_out_valid;
345 --debug_f3_data_valid <= data_f3_out_valid;
341 --debug_f3_data <= data_f3_out;
346 --debug_f3_data <= data_f3_out;
342 -----------------------------------------------------------------------------
347 -----------------------------------------------------------------------------
343
348
344 PROCESS (clk, rstn)
349 PROCESS (clk, rstn)
345 BEGIN -- PROCESS
350 BEGIN -- PROCESS
346 IF rstn = '0' THEN -- asynchronous reset (active low)
351 IF rstn = '0' THEN -- asynchronous reset (active low)
347 time_reg1 <= (OTHERS => '0');
352 time_reg1 <= (OTHERS => '0');
348 time_reg2 <= (OTHERS => '0');
353 time_reg2 <= (OTHERS => '0');
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
354 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 time_reg1 <= fine_time & coarse_time;
355 time_reg1 <= fine_time & coarse_time;
351 time_reg2 <= time_reg1;
356 time_reg2 <= time_reg1;
352 END IF;
357 END IF;
353 END PROCESS;
358 END PROCESS;
354
359
355 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
360 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
356 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
361 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
357 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
362 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
358 PORT MAP (
363 PORT MAP (
359 HCLK => clk,
364 HCLK => clk,
360 HRESETn => rstn,
365 HRESETn => rstn,
361 run => run,
366 run => run,
362 valid_in => valid_in(I),
367 valid_in => valid_in(I),
363 ack_in => valid_ack(I),
368 ack_in => valid_ack(I),
364 time_in => time_reg2, -- Todo
369 time_in => time_reg2, -- Todo
365 valid_out => valid_out(I),
370 valid_out => valid_out(I),
366 time_out => time_out(I), -- Todo
371 time_out => time_out(I), -- Todo
367 error => status_new_err(I));
372 error => status_new_err(I));
368 END GENERATE all_input_valid;
373 END GENERATE all_input_valid;
369
374
370 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
375 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
371 data_f0_out((16*6)-1 DOWNTO 16*5) &
376 data_f0_out((16*6)-1 DOWNTO 16*5) &
372 data_f0_out((16*3)-1 DOWNTO 16*2) &
377 data_f0_out((16*3)-1 DOWNTO 16*2) &
373 data_f0_out((16*4)-1 DOWNTO 16*3) &
378 data_f0_out((16*4)-1 DOWNTO 16*3) &
374 data_f0_out((16*1)-1 DOWNTO 16*0) &
379 data_f0_out((16*1)-1 DOWNTO 16*0) &
375 data_f0_out((16*2)-1 DOWNTO 16*1) ;
380 data_f0_out((16*2)-1 DOWNTO 16*1) ;
376
381
377 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
382 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
378 data_f1_out((16*6)-1 DOWNTO 16*5) &
383 data_f1_out((16*6)-1 DOWNTO 16*5) &
379 data_f1_out((16*3)-1 DOWNTO 16*2) &
384 data_f1_out((16*3)-1 DOWNTO 16*2) &
380 data_f1_out((16*4)-1 DOWNTO 16*3) &
385 data_f1_out((16*4)-1 DOWNTO 16*3) &
381 data_f1_out((16*1)-1 DOWNTO 16*0) &
386 data_f1_out((16*1)-1 DOWNTO 16*0) &
382 data_f1_out((16*2)-1 DOWNTO 16*1) ;
387 data_f1_out((16*2)-1 DOWNTO 16*1) ;
383
388
384 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
389 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
385 data_f2_out((16*6)-1 DOWNTO 16*5) &
390 data_f2_out((16*6)-1 DOWNTO 16*5) &
386 data_f2_out((16*3)-1 DOWNTO 16*2) &
391 data_f2_out((16*3)-1 DOWNTO 16*2) &
387 data_f2_out((16*4)-1 DOWNTO 16*3) &
392 data_f2_out((16*4)-1 DOWNTO 16*3) &
388 data_f2_out((16*1)-1 DOWNTO 16*0) &
393 data_f2_out((16*1)-1 DOWNTO 16*0) &
389 data_f2_out((16*2)-1 DOWNTO 16*1) ;
394 data_f2_out((16*2)-1 DOWNTO 16*1) ;
390
395
391 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
396 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
392 data_f3_out((16*6)-1 DOWNTO 16*5) &
397 data_f3_out((16*6)-1 DOWNTO 16*5) &
393 data_f3_out((16*3)-1 DOWNTO 16*2) &
398 data_f3_out((16*3)-1 DOWNTO 16*2) &
394 data_f3_out((16*4)-1 DOWNTO 16*3) &
399 data_f3_out((16*4)-1 DOWNTO 16*3) &
395 data_f3_out((16*1)-1 DOWNTO 16*0) &
400 data_f3_out((16*1)-1 DOWNTO 16*0) &
396 data_f3_out((16*2)-1 DOWNTO 16*1) ;
401 data_f3_out((16*2)-1 DOWNTO 16*1) ;
397
402
398 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
403 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
399 data_out(0, I) <= data_f0_out_swap(I);
404 data_out(0, I) <= data_f0_out_swap(I);
400 data_out(1, I) <= data_f1_out_swap(I);
405 data_out(1, I) <= data_f1_out_swap(I);
401 data_out(2, I) <= data_f2_out_swap(I);
406 data_out(2, I) <= data_f2_out_swap(I);
402 data_out(3, I) <= data_f3_out_swap(I);
407 data_out(3, I) <= data_f3_out_swap(I);
403 END GENERATE all_bit_of_data_out;
408 END GENERATE all_bit_of_data_out;
404
409
405 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
406 -- TODO : debug
411 -- TODO : debug
407 -----------------------------------------------------------------------------
412 -----------------------------------------------------------------------------
408 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
413 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
409 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
414 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
410 time_out_2(J, I) <= time_out(J)(I);
415 time_out_2(J, I) <= time_out(J)(I);
411 END GENERATE all_sample_of_time_out;
416 END GENERATE all_sample_of_time_out;
412 END GENERATE all_bit_of_time_out;
417 END GENERATE all_bit_of_time_out;
413
418
414 -- DEBUG --
419 -- DEBUG --
415 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
420 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
416 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
421 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
417 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
422 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
418 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
423 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
419
424
420 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
425 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
421 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
426 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
422 -- time_out_2(J, I) <= time_out_debug(J)(I);
427 -- time_out_2(J, I) <= time_out_debug(J)(I);
423 -- END GENERATE all_sample_of_time_out;
428 -- END GENERATE all_sample_of_time_out;
424 --END GENERATE all_bit_of_time_out;
429 --END GENERATE all_bit_of_time_out;
425 -- DEBUG --
430 -- DEBUG --
426
431
427 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
432 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
428 GENERIC MAP (tech => tech,
433 GENERIC MAP (tech => tech,
429 nb_data_by_buffer_size => nb_data_by_buffer_size)
434 nb_data_by_buffer_size => nb_data_by_buffer_size)
430 PORT MAP (
435 PORT MAP (
431 clk => clk,
436 clk => clk,
432 rstn => rstn,
437 rstn => rstn,
433 run => run,
438 run => run,
434 nb_data_by_buffer => nb_data_by_buffer,
439 nb_data_by_buffer => nb_data_by_buffer,
435 data_in_valid => valid_out,
440 data_in_valid => valid_out,
436 data_in_ack => valid_ack,
441 data_in_ack => valid_ack,
437 data_in => data_out,
442 data_in => data_out,
438 time_in => time_out_2,
443 time_in => time_out_2,
439
444
440 data_out => wdata,
445 data_out => wdata,
441 data_out_wen => data_wen,
446 data_out_wen => data_wen,
442 full_almost => full_almost,
447 full_almost => full_almost,
443 full => full);
448 full => full);
444
449
445 -----------------------------------------------------------------------------
450 -----------------------------------------------------------------------------
446 -- DEBUG -- SNAPSHOT IN
451 -- DEBUG -- SNAPSHOT IN
447 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
452 --debug_f0_data_fifo_in_valid <= NOT data_wen(0);
448 --debug_f0_data_fifo_in <= wdata;
453 --debug_f0_data_fifo_in <= wdata;
449 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
454 --debug_f1_data_fifo_in_valid <= NOT data_wen(1);
450 --debug_f1_data_fifo_in <= wdata;
455 --debug_f1_data_fifo_in <= wdata;
451 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
456 --debug_f2_data_fifo_in_valid <= NOT data_wen(2);
452 --debug_f2_data_fifo_in <= wdata;
457 --debug_f2_data_fifo_in <= wdata;
453 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
458 --debug_f3_data_fifo_in_valid <= NOT data_wen(3);
454 --debug_f3_data_fifo_in <= wdata;s
459 --debug_f3_data_fifo_in <= wdata;s
455 -----------------------------------------------------------------------------
460 -----------------------------------------------------------------------------
456
461
457 lpp_waveform_fifo_1 : lpp_waveform_fifo
462
458 GENERIC MAP (tech => tech)
463 -- lpp_fifo_4_shared_1: lpp_fifo_4_shared
459 PORT MAP (
464 -- GENERIC MAP (
460 clk => clk,
465 -- tech => tech,
461 rstn => rstn,
466 -- Mem_use => use_RAM,
462 run => run,
467 -- EMPTY_ALMOST_LIMIT => 16,
468 -- FULL_ALMOST_LIMIT => 5,
469 -- DataSz => 32,
470 -- AddrSz => 7
471 -- )
472 -- PORT MAP (
473 -- clk => clk,
474 -- rstn => rstn,
475 -- run => run,
476 -- empty_almost => s_empty_almost,
477 -- empty => s_empty,
478 -- r_en => s_data_ren,
479 -- r_data => s_rdata,
480 -- full_almost => full_almost,
481 -- full => full,
482 -- w_en => data_wen,
483 -- w_data => wdata);
463
484
464 empty => s_empty,
485 --lpp_waveform_fifo_headreg_1 : lpp_fifo_4_shared_headreg_latency_1
465 empty_almost => s_empty_almost,
486 -- PORT MAP (
466 data_ren => s_data_ren,
487 -- clk => clk,
467 rdata => s_rdata,
488 -- rstn => rstn,
489 -- run => run,
490 -- o_empty_almost => empty_almost,
491 -- o_empty => empty,
468
492
469
493 -- o_data_ren => data_ren,
470 full_almost => full_almost,
494 -- o_rdata_0 => data_f0_data_out,
471 full => full,
495 -- o_rdata_1 => data_f1_data_out,
472 data_wen => data_wen,
496 -- o_rdata_2 => data_f2_data_out,
473 wdata => wdata);
497 -- o_rdata_3 => data_f3_data_out,
474
498
475 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
499 -- i_empty_almost => s_empty_almost,
476 GENERIC MAP (tech => tech)
500 -- i_empty => s_empty,
477 PORT MAP (
501 -- i_data_ren => s_data_ren,
478 clk => clk,
502 -- i_rdata => s_rdata);
479 rstn => rstn,
480 run => run,
481 o_empty_almost => empty_almost,
482 o_empty => empty,
483
503
484 o_data_ren => data_ren,
504 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
485 o_rdata_0 => data_f0_data_out,
505 lpp_fifo_1: lpp_fifo
486 o_rdata_1 => data_f1_data_out,
506 GENERIC MAP (
487 o_rdata_2 => data_f2_data_out,
507 tech => tech,
488 o_rdata_3 => data_f3_data_out,
508 Mem_use => use_RAM,
509 EMPTY_THRESHOLD_LIMIT => 16,
510 FULL_THRESHOLD_LIMIT => 5,
511 DataSz => 32,
512 AddrSz => 7)
513 PORT MAP (
514 clk => clk,
515 rstn => rstn,
516 reUse => '0',
517 run => run,
518 ren => data_ren(I),
519 rdata => s_rdata_v((I+1)*32-1 downto I*32),
520 wen => data_wen(I),
521 wdata => wdata,
522 empty => empty(I),
523 full => full(I),
524 full_almost => OPEN,
525 empty_threshold => empty_almost(I),
526 full_threshold => full_almost(I) );
527
528 END GENERATE generate_all_fifo;
489
529
490 i_empty_almost => s_empty_almost,
530
491 i_empty => s_empty,
531 --empty <= s_empty;
492 i_data_ren => s_data_ren,
532 --empty_almost <= s_empty_almost;
493 i_rdata => s_rdata);
533 --s_data_ren <= data_ren;
494
534
495
535 data_f0_data_out <= s_rdata_v(31 downto 0);
496 --data_f0_data_out <= rdata;
536 data_f1_data_out <= s_rdata_v(31+32 downto 0+32);
497 --data_f1_data_out <= rdata;
537 data_f2_data_out <= s_rdata_v(31+32*2 downto 32*2);
498 --data_f2_data_out <= rdata;
538 data_f3_data_out <= s_rdata_v(31+32*3 downto 32*3);
499 --data_f3_data_out <= rdata;
500
539
501 data_ren <= data_f3_data_out_ren &
540 data_ren <= data_f3_data_out_ren &
502 data_f2_data_out_ren &
541 data_f2_data_out_ren &
503 data_f1_data_out_ren &
542 data_f1_data_out_ren &
504 data_f0_data_out_ren;
543 data_f0_data_out_ren;
505
544
506 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
545 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
507 GENERIC MAP (
546 GENERIC MAP (
508 nb_data_by_buffer_size => nb_word_by_buffer_size)
547 nb_data_by_buffer_size => nb_word_by_buffer_size)
509 PORT MAP (
548 PORT MAP (
510 clk => clk,
549 clk => clk,
511 rstn => rstn,
550 rstn => rstn,
512 run => run,
551 run => run,
513
552
514 -------------------------------------------------------------------------
553 -------------------------------------------------------------------------
515 -- CONFIG
554 -- CONFIG
516 -------------------------------------------------------------------------
555 -------------------------------------------------------------------------
517 nb_data_by_buffer => nb_word_by_buffer,
556 nb_data_by_buffer => nb_word_by_buffer,
518
557
519 addr_data_f0 => addr_data_f0,
558 addr_data_f0 => addr_data_f0,
520 addr_data_f1 => addr_data_f1,
559 addr_data_f1 => addr_data_f1,
521 addr_data_f2 => addr_data_f2,
560 addr_data_f2 => addr_data_f2,
522 addr_data_f3 => addr_data_f3,
561 addr_data_f3 => addr_data_f3,
523 -------------------------------------------------------------------------
562 -------------------------------------------------------------------------
524 -- CTRL
563 -- CTRL
525 -------------------------------------------------------------------------
564 -------------------------------------------------------------------------
526 -- IN
565 -- IN
527 empty => empty,
566 empty => empty,
528 empty_almost => empty_almost,
567 empty_almost => empty_almost,
529 data_ren => data_ren,
568 data_ren => data_ren,
530
569
531 -------------------------------------------------------------------------
570 -------------------------------------------------------------------------
532 -- STATUS
571 -- STATUS
533 -------------------------------------------------------------------------
572 -------------------------------------------------------------------------
534 status_full => status_full_s,
573 status_full => status_full_s,
535 status_full_ack => status_full_ack,
574 status_full_ack => status_full_ack,
536 status_full_err => status_full_err,
575 status_full_err => status_full_err,
537
576
538 -------------------------------------------------------------------------
577 -------------------------------------------------------------------------
539 -- ADDR DATA OUT
578 -- ADDR DATA OUT
540 -------------------------------------------------------------------------
579 -------------------------------------------------------------------------
541 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
580 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
542 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
581 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
543 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
582 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
544 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
583 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
545
584
546 data_f0_data_out_valid => data_f0_data_out_valid,
585 data_f0_data_out_valid => data_f0_data_out_valid,
547 data_f1_data_out_valid => data_f1_data_out_valid,
586 data_f1_data_out_valid => data_f1_data_out_valid,
548 data_f2_data_out_valid => data_f2_data_out_valid,
587 data_f2_data_out_valid => data_f2_data_out_valid,
549 data_f3_data_out_valid => data_f3_data_out_valid,
588 data_f3_data_out_valid => data_f3_data_out_valid,
550
589
551 data_f0_addr_out => data_f0_addr_out,
590 data_f0_addr_out => data_f0_addr_out,
552 data_f1_addr_out => data_f1_addr_out,
591 data_f1_addr_out => data_f1_addr_out,
553 data_f2_addr_out => data_f2_addr_out,
592 data_f2_addr_out => data_f2_addr_out,
554 data_f3_addr_out => data_f3_addr_out
593 data_f3_addr_out => data_f3_addr_out
555 );
594 );
556 status_full <= status_full_s;
595 status_full <= status_full_s;
557
596
558 END beh;
597 END beh;
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