HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r373:8b7232d194b4

update APB_REG

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r373:8b7232d194b4 JC

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r373:8b7232d194b4

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designs/Validation_LFR_SpectralMatrix/Makefile +3 0

             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=TB
             CMD_VLIB=vlib
             CMD_VMAP=vmap
             CMD_VCOM=@vcom -quiet -93 -work
             ##################  project specific targets ##########################
             all:
             	@echo "make vsim"
             	@echo "make libs"
             	@echo "make clean"
             	@echo "make vcom_grlib vcom_lpp vcom_tb"
             run:
             	@vsim work.TB -do run.do
             #	@vsim work.TB
             #	@vsim lpp.lpp_lfr_ms
             vsim:   libs vcom run
             libs:
             	@$(CMD_VLIB) modelsim
             	@$(CMD_VMAP) modelsim modelsim
             	@$(CMD_VLIB) modelsim/techmap
             	@$(CMD_VMAP) techmap modelsim/techmap
             	@$(CMD_VLIB) modelsim/grlib
             	@$(CMD_VMAP) grlib modelsim/grlib
             	@$(CMD_VLIB) modelsim/gaisler
             	@$(CMD_VMAP) gaisler modelsim/gaisler
             	@$(CMD_VLIB) modelsim/work
             	@$(CMD_VMAP) work modelsim/work
             	@$(CMD_VLIB) modelsim/lpp
             	@$(CMD_VMAP) lpp modelsim/lpp
             	@echo "libs done"
             clean:
             	@rm -Rf modelsim
             	@rm -Rf modelsim.ini
             	@rm -Rf *~
             	@rm -Rf transcript
             	@rm -Rf wlft*
             	@rm -Rf *.wlf
             	@rm -Rf vish_stacktrace.vstf
             	@rm -Rf libs.do
             vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
             vcom_tb:
             ##	$(CMD_VCOM) lpp  lpp_memory.vhd
             ##	$(CMD_VCOM) lpp  lppFIFOxN.vhd
             ##	$(CMD_VCOM) lpp  lpp_FIFO.vhd
             ##	$(CMD_VCOM) lpp  lpp_lfr_ms.vhd
             	$(CMD_VCOM) work TB.vhd
             	@echo "vcom done"
             vcom_grlib:
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
             	@echo "vcom grlib done"
             vcom_gaisler:
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
             ##	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
             	@echo "vcom gaisler done"
             vcom_techmap:
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
             	@echo "vcom techmap done"
             vcom_lpp:
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
             	@echo "vcom lpp done"
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
             # 	@echo "vcom lpp done"
             #include Makefile_vcom_lpp

designs/Validation_LFR_SpectralMatrix/TB.vhd +122 -21

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY lpp;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             use lpp.lpp_fft.all;
             use lpp.fft_components.all;
+            LIBRARY grlib;
+            USE grlib.amba.ALL;
+            USE grlib.stdlib.ALL;
+            USE grlib.devices.ALL;
+            USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY TB IS
             END TB;
             ARCHITECTURE beh OF TB IS
               -----------------------------------------------------------------------------
               SIGNAL clk25MHz : STD_LOGIC := '0';
               SIGNAL rstn     : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time                            : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time                              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL sample_f0_wen                          : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_wdata                        : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wen                          : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wdata                        : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wen                          : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wdata                        : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL dma_addr                               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data                               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_valid                              : STD_LOGIC;
               SIGNAL dma_valid_burst                        : STD_LOGIC;
               SIGNAL dma_ren                                : STD_LOGIC;
               SIGNAL dma_done                               : STD_LOGIC;
               SIGNAL ready_matrix_f0                      : STD_LOGIC;
             --  SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
             --  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
               SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0               : STD_LOGIC;
             --  SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
             --  SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
             --  SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL matrix_time_f0                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1                         : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2                         : STD_LOGIC_VECTOR(47 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL clk49_152MHz : STD_LOGIC := '0';
               SIGNAL sample_counter_24k : INTEGER;
               SIGNAL s_24576Hz : STD_LOGIC;
               SIGNAL s_24_sync_reg_0 : STD_LOGIC;
               SIGNAL s_24_sync_reg_1 : STD_LOGIC;
               SIGNAL s_24576Hz_sync : STD_LOGIC;
               SIGNAL sample_counter_f1 : INTEGER;
               SIGNAL sample_counter_f2 : INTEGER;
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL ren_counter : INTEGER;
+              SIGNAL error_buffer_full         :  STD_LOGIC;
+              SIGNAL error_input_fifo_write    :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+              -----------------------------------------------------------------------------
+              SIGNAL apbi :  apb_slv_in_type;
+              SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
+              SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
+              SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
+              SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
             BEGIN  -- beh
               clk25MHz      <= NOT clk25MHz     AFTER 20 ns;
               clk25MHz      <= NOT clk25MHz     AFTER 20 ns;
               clk49_152MHz  <= NOT clk49_152MHz AFTER 10173 ps;  -- 49.152/2 MHz
               PROCESS
               BEGIN  -- PROCESS
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT UNTIL clk25MHz = '1';
                 rstn <= '1';
                 WAIT UNTIL clk25MHz = '1';
                 WAIT FOR 100 ms;
                 REPORT "*** END simulation ***" SEVERITY failure;
                 WAIT;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk49_152MHz, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_counter_24k <= 0;
                   s_24576Hz          <= '0';
                 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN  -- rising clock edge
                   IF sample_counter_24k = 0 THEN
                     sample_counter_24k <= 2000;
                     s_24576Hz <= NOT s_24576Hz;
                   ELSE
                     sample_counter_24k <= sample_counter_24k - 1;
                   END IF;
                 END IF;
               END PROCESS;
               PROCESS (clk25MHz, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   s_24_sync_reg_0 <= '0';
                   s_24_sync_reg_1 <= '0';
                   s_24576Hz_sync  <= '0';
                 ELSIF clk25MHz'event AND clk25MHz = '1' THEN  -- rising clock edge
                   s_24_sync_reg_0 <= s_24576Hz;
                   s_24_sync_reg_1 <= s_24_sync_reg_0;
                   s_24576Hz_sync  <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
                 END IF;
               END PROCESS;
               PROCESS (clk25MHz, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_f0_val <= '0';
                   sample_f1_val <= '0';
                   sample_f2_val <= '0';
                   sample_counter_f1 <= 0;
                   sample_counter_f2 <= 0;
                 ELSIF clk25MHz'event AND clk25MHz = '1' THEN  -- rising clock edge
                   IF s_24576Hz_sync = '1' THEN
                     sample_f0_val <= '1';
                     IF sample_counter_f1 = 0 THEN
                       sample_f1_val <= '1';
                       sample_counter_f1 <= 5;
                     ELSE
                       sample_f1_val <= '0';
                       sample_counter_f1 <= sample_counter_f1 -1;
                     END IF;
                     IF sample_counter_f2 = 0 THEN
                       sample_f2_val <= '1';
                       sample_counter_f2 <= 95;
                     ELSE
                       sample_f2_val <= '0';
                       sample_counter_f2 <= sample_counter_f2 -1;
                     END IF;
                   ELSE
                     sample_f0_val <= '0';
                     sample_f1_val <= '0';
                     sample_f2_val <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               coarse_time <= (OTHERS => '0');
               fine_time   <= (OTHERS => '0');
               sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
               sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
               sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1: lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => use_CEL)
                 PORT MAP (
                   clk                                    => clk25MHz,
                   rstn                                   => rstn,
                   --
                   coarse_time                            => coarse_time,
                   fine_time                              => fine_time,
                   --
                   sample_f0_wen                          => sample_f0_wen,
                   sample_f0_wdata                        => sample_f0_wdata,
                   sample_f1_wen                          => sample_f1_wen,
                   sample_f1_wdata                        => sample_f1_wdata,
                   sample_f2_wen                          => sample_f2_wen,
                   sample_f2_wdata                        => sample_f2_wdata,
                   --
                   dma_addr                               => dma_addr,
                   dma_data                               => dma_data,
                   dma_valid                              => dma_valid,
                   dma_valid_burst                        => dma_valid_burst,
                   dma_ren                                => dma_ren,
                   dma_done                               => dma_done,
                   ready_matrix_f0                      => ready_matrix_f0,
             --      ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
             --      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
-                  error_buffer_full                      => OPEN,
+                  error_buffer_full                      => error_buffer_full,
-                  error_input_fifo_write                 => OPEN,
+                  error_input_fifo_write                 => error_input_fifo_write,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0               => status_ready_matrix_f0,
             --      status_ready_matrix_f0               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
             --      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
             --      status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0                       => addr_matrix_f0,
             --      addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
                   matrix_time_f0                       => matrix_time_f0,
             --      matrix_time_f0_1                       => matrix_time_f0_1,
                   matrix_time_f1                         => matrix_time_f1,
                   matrix_time_f2                         => matrix_time_f2);
+              lpp_lfr_apbreg_1 : lpp_lfr_apbreg
+                GENERIC MAP (
+                  nb_data_by_buffer_size => 11,
+                  nb_word_by_buffer_size => 11,
+                  nb_snapshot_param_size => 11,
+                  delta_vector_size      => 20,
+                  delta_vector_size_f0_2 => 7,
+                  pindex                 => 4,
+                  paddr                  => 4,
+                  pmask                  => 16#fff#,
+                  pirq_ms                => 0,
+                  pirq_wfp               => 1,
+                  top_lfr_version        => (OTHERS => '0')
+                  )
+                PORT MAP (
+                  HCLK    => clk25MHz,
+                  HRESETn => rstn,
+                  apbi    => apbi,
+                  apbo    => OPEN,
-              PROCESS (clk25MHz, rstn)
+                  run_ms => OPEN,
-              BEGIN  -- PROCESS
-                IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                  ready_matrix_f0                        => ready_matrix_f0,
-                  status_ready_matrix_f0             <= '0';
+                  ready_matrix_f1                        => ready_matrix_f1,
-            --      status_ready_matrix_f0_1             <= '0';
+                  ready_matrix_f2                        => ready_matrix_f2,
-                  status_ready_matrix_f1               <= '0';
+                  error_bad_component_error              => error_bad_component_error,
-                  status_ready_matrix_f2               <= '0';
+                  error_buffer_full                      => error_buffer_full,      -- TODO
-                ELSIF clk25MHz'event AND clk25MHz = '1' THEN  -- rising clock edge
+                  error_input_fifo_write                 => error_input_fifo_write, -- TODO
-                  status_ready_matrix_f0             <= status_ready_matrix_f0 OR ready_matrix_f0;
+                  status_ready_matrix_f0                 => status_ready_matrix_f0,
-            --      status_ready_matrix_f0_1             <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
+                  status_ready_matrix_f1                 => status_ready_matrix_f1,
-                  status_ready_matrix_f1               <= status_ready_matrix_f1 OR ready_matrix_f1;
+                  status_ready_matrix_f2                 => status_ready_matrix_f2,
-                  status_ready_matrix_f2               <= status_ready_matrix_f2 OR ready_matrix_f2;
+                  config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
-                END IF;
+                  config_active_interruption_onError     => config_active_interruption_onError,
-              END PROCESS;
+                  matrix_time_f0    => matrix_time_f0,
+                  matrix_time_f1    => matrix_time_f1,
+                  matrix_time_f2     => matrix_time_f2,
+                  addr_matrix_f0    => addr_matrix_f0,
+                  addr_matrix_f1    => addr_matrix_f1,
+                  addr_matrix_f2    => addr_matrix_f2,
+                  -------------------------------------------------------------------------
+                  status_full       => status_full,
+                  status_full_ack   => status_full_ack,
+                  status_full_err   => status_full_err,
+                  status_new_err    => status_new_err,
+                  data_shaping_BW   => OPEN,
+                  data_shaping_SP0  => OPEN,
+                  data_shaping_SP1  => OPEN,
+                  data_shaping_R0   => OPEN,
+                  data_shaping_R1   => OPEN,
+                  delta_snapshot    => OPEN,
+                  delta_f0          => OPEN,
+                  delta_f0_2        => OPEN,
+                  delta_f1          => OPEN,
+                  delta_f2          => OPEN,
+                  nb_data_by_buffer => OPEN,
+                  nb_word_by_buffer => OPEN,
+                  nb_snapshot_param => OPEN,
+                  enable_f0         => OPEN,
+                  enable_f1         => OPEN,
+                  enable_f2         => OPEN,
+                  enable_f3         => OPEN,
+                  burst_f0          => OPEN,
+                  burst_f1          => OPEN,
+                  burst_f2          => OPEN,
+                  run               => OPEN,
+                  addr_data_f0      => OPEN,
+                  addr_data_f1      => OPEN,
+                  addr_data_f2      => OPEN,
+                  addr_data_f3      => OPEN,
+                  start_date        => OPEN);
+            --  PROCESS (clk25MHz, rstn)
+            --  BEGIN  -- PROCESS
+            --    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+            --      status_ready_matrix_f0             <= '0';
+            ----      status_ready_matrix_f0_1             <= '0';
+            --      status_ready_matrix_f1               <= '0';
+            --      status_ready_matrix_f2               <= '0';
+            --    ELSIF clk25MHz'event AND clk25MHz = '1' THEN  -- rising clock edge
+            --      status_ready_matrix_f0             <= status_ready_matrix_f0 OR ready_matrix_f0;
+            ----      status_ready_matrix_f0_1             <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
+            --      status_ready_matrix_f1               <= status_ready_matrix_f1 OR ready_matrix_f1;
+            --      status_ready_matrix_f2               <= status_ready_matrix_f2 OR ready_matrix_f2;
+            --    END IF;
+            --  END PROCESS;
             --  status_error_anticipating_empty_fifo <= '0';
             --  status_error_bad_component_error     <= '0';
-              config_active_interruption_onNewMatrix <= '0';
+            --  config_active_interruption_onNewMatrix <= '0';
-              config_active_interruption_onError     <= '0';
+            --  config_active_interruption_onError     <= '0';
-              addr_matrix_f0                         <= (OTHERS => '0');
+            --  addr_matrix_f0                         <= (OTHERS => '0');
             --  addr_matrix_f0_1                       <= (OTHERS => '0');
-              addr_matrix_f1                         <= (OTHERS => '0');
+            --  addr_matrix_f1                         <= (OTHERS => '0');
-              addr_matrix_f2                         <= (OTHERS => '0');
+            --  addr_matrix_f2                         <= (OTHERS => '0');
               PROCESS (clk25MHz, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   dma_ren  <= '1';
                   dma_done <= '0';
                   ren_counter <= 0;
                 ELSIF clk25MHz'event AND clk25MHz = '1' THEN  -- rising clock edge
                   dma_ren  <= '1';
                   dma_done <= '0';
                   IF dma_valid_burst = '1' THEN
                     ren_counter <= 17;
                   END IF;
                   IF ren_counter > 1 THEN
                     ren_counter <= ren_counter - 1;
                     dma_ren <= '0';
                   END IF;
                   IF ren_counter = 1 THEN
                     ren_counter <= 0;
                     dma_done <= '1';
                   END IF;
                 END IF;
               END PROCESS;
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +7 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
                 sample_B        : IN  Samples(2 DOWNTO 0);
                 sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 --debug
                 --debug_f0_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f0_data_valid : OUT STD_LOGIC;
                 --debug_f1_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f1_data_valid : OUT STD_LOGIC;
                 --debug_f2_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f2_data_valid : OUT STD_LOGIC;
                 --debug_f3_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
                 --debug_f3_data_valid : OUT STD_LOGIC;
                 ---- debug FIFO_IN
                 --debug_f0_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f1_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f2_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
                 --debug_f3_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
                 ----debug FIFO OUT
                 --debug_f0_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f1_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f2_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
                 --debug_f3_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
                 ----debug DMA IN
                 --debug_f0_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f1_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f2_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
                 --debug_f3_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
               --SIGNAL sample           : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
             --  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
             --  SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
             --  SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
             --  SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
             --  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -- WFP
               SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               SIGNAL addr_data_f0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_data_f3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               SIGNAL data_f0_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f0_data_out_ren         : STD_LOGIC;
               --f1
               SIGNAL data_f1_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f1_data_out_ren         : STD_LOGIC;
               --f2
               SIGNAL data_f2_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f2_data_out_ren         : STD_LOGIC;
               --f3
               SIGNAL data_f3_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
               SIGNAL data_f3_data_out_ren         : STD_LOGIC;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
               SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
               SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
               SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
               SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
               SIGNAL dma_sel_valid   : STD_LOGIC;
               SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
               SIGNAL ongoing_reg         : STD_LOGIC;
               SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL dma_send_reg        : STD_LOGIC;
               SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               SIGNAL dma_send        : STD_LOGIC;
               SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
               SIGNAL dma_done        : STD_LOGIC;
               SIGNAL dma_ren         : STD_LOGIC;
               SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
               SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL data_ms_valid       : STD_LOGIC;
               SIGNAL data_ms_valid_burst : STD_LOGIC;
               SIGNAL data_ms_ren         : STD_LOGIC;
               SIGNAL data_ms_done        : STD_LOGIC;
               SIGNAL run_ms              : STD_LOGIC;
               SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0    : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1      : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2      : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_buffer_full         :  STD_LOGIC;
               SIGNAL error_input_fifo_write    :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+              SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
               --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
               --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
               --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data);
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_word_by_buffer_size => nb_word_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => run_ms,
                   ready_matrix_f0                      => ready_matrix_f0,
             --      ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
             --      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   error_buffer_full                      => error_buffer_full,      -- TODO
                   error_input_fifo_write                 => error_input_fifo_write, -- TODO
             --      debug_reg                              => debug_reg,
                   status_ready_matrix_f0               => status_ready_matrix_f0,
             --      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
             --      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
             --      status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   matrix_time_f0 => matrix_time_f0,
             --      matrix_time_f0_1 => matrix_time_f0_1,
                   matrix_time_f1   => matrix_time_f1,
                   matrix_time_f2   => matrix_time_f2,
                   addr_matrix_f0  => addr_matrix_f0,
             --      addr_matrix_f0_1  => addr_matrix_f0_1,
                   addr_matrix_f1    => addr_matrix_f1,
                   addr_matrix_f2    => addr_matrix_f2,
                   -------------------------------------------------------------------------
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_word_by_buffer => nb_word_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => run,
                   addr_data_f0      => addr_data_f0,
                   addr_data_f1      => addr_data_f1,
                   addr_data_f2      => addr_data_f2,
                   addr_data_f3      => addr_data_f3,
                   start_date        => start_date);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => inferred,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_word_by_buffer_size => nb_word_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_word_by_buffer => nb_word_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
                   status_new_err    => status_new_err,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   --f0
                   addr_data_f0                 => addr_data_f0,
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
                   --f1
                   addr_data_f1                 => addr_data_f1,
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
                   --f2
                   addr_data_f2                 => addr_data_f2,
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
                   --f3
                   addr_data_f3                 => addr_data_f3,
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
                   -- OUTPUT -- DMA interface
                   --f0
                   data_f0_addr_out             => data_f0_addr_out_s,
                   data_f0_data_out             => data_f0_data_out,
                   data_f0_data_out_valid       => data_f0_data_out_valid_s,
                   data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
                   data_f0_data_out_ren         => data_f0_data_out_ren,
                   --f1
                   data_f1_addr_out             => data_f1_addr_out_s,
                   data_f1_data_out             => data_f1_data_out,
                   data_f1_data_out_valid       => data_f1_data_out_valid_s,
                   data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
                   data_f1_data_out_ren         => data_f1_data_out_ren,
                   --f2
                   data_f2_addr_out             => data_f2_addr_out_s,
                   data_f2_data_out             => data_f2_data_out,
                   data_f2_data_out_valid       => data_f2_data_out_valid_s,
                   data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
                   data_f2_data_out_ren         => data_f2_data_out_ren,
                   --f3
                   data_f3_addr_out             => data_f3_addr_out_s,
                   data_f3_data_out             => data_f3_data_out,
                   data_f3_data_out_valid       => data_f3_data_out_valid_s,
                   data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
                   data_f3_data_out_ren         => data_f3_data_out_ren ,
                   -------------------------------------------------------------------------
                   observation_reg => OPEN
                   );
               -----------------------------------------------------------------------------
               -- TEMP
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_f0_data_out_valid       <= '0';
                   data_f0_data_out_valid_burst <= '0';
                   data_f1_data_out_valid       <= '0';
                   data_f1_data_out_valid_burst <= '0';
                   data_f2_data_out_valid       <= '0';
                   data_f2_data_out_valid_burst <= '0';
                   data_f3_data_out_valid       <= '0';
                   data_f3_data_out_valid_burst <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   data_f0_data_out_valid       <= data_f0_data_out_valid_s;
                   data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
                   data_f1_data_out_valid       <= data_f1_data_out_valid_s;
                   data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
                   data_f2_data_out_valid       <= data_f2_data_out_valid_s;
                   data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
                   data_f3_data_out_valid       <= data_f3_data_out_valid_s;
                   data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
                 END IF;
               END PROCESS;
               data_f0_addr_out <= data_f0_addr_out_s;
               data_f1_addr_out <= data_f1_addr_out_s;
               data_f2_addr_out <= data_f2_addr_out_s;
               data_f3_addr_out <= data_f3_addr_out_s;
               -----------------------------------------------------------------------------
               -- RoundRobin Selection For DMA
               -----------------------------------------------------------------------------
               dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
               dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
               dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
               dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
               RR_Arbiter_4_1 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid,
                   out_grant => dma_rr_grant_s);
               dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
               dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
               dma_rr_valid_ms(2) <= '0';
               dma_rr_valid_ms(3) <= '0';
               RR_Arbiter_4_2 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => dma_rr_valid_ms,
                   out_grant => dma_rr_grant_ms);
               dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
               -----------------------------------------------------------------------------
               -- in  : dma_rr_grant
               --       send
               -- out : dma_sel
               --       dma_valid_burst
               --       dma_sel_valid
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   dma_sel         <= (OTHERS => '0');
                   dma_send        <= '0';
                   dma_valid_burst <= '0';
                   data_ms_done    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF run = '1' THEN
                     data_ms_done <= '0';
                     IF dma_sel = "00000" OR dma_done = '1' THEN
                       dma_sel <= dma_rr_grant;
                       IF dma_rr_grant(0) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f0_data_out_valid_burst;
                         dma_sel_valid   <= data_f0_data_out_valid;
                       ELSIF dma_rr_grant(1) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f1_data_out_valid_burst;
                         dma_sel_valid   <= data_f1_data_out_valid;
                       ELSIF dma_rr_grant(2) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f2_data_out_valid_burst;
                         dma_sel_valid   <= data_f2_data_out_valid;
                       ELSIF dma_rr_grant(3) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_f3_data_out_valid_burst;
                         dma_sel_valid   <= data_f3_data_out_valid;
                       ELSIF dma_rr_grant(4) = '1' THEN
                         dma_send        <= '1';
                         dma_valid_burst <= data_ms_valid_burst;
                         dma_sel_valid   <= data_ms_valid;
                       END IF;
                       IF dma_sel(4) = '1' THEN
                         data_ms_done <= '1';
                       END IF;
                     ELSE
                       dma_sel  <= dma_sel;
                       dma_send <= '0';
                     END IF;
                   ELSE
                     data_ms_done    <= '0';
                     dma_sel         <= (OTHERS => '0');
                     dma_send        <= '0';
                     dma_valid_burst <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
                              data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
                              data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
                              data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
                              data_ms_addr;
               dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
                           data_f1_data_out WHEN dma_sel(1) = '1' ELSE
                           data_f2_data_out WHEN dma_sel(2) = '1' ELSE
                           data_f3_data_out WHEN dma_sel(3) = '1' ELSE
                           data_ms_data;
               data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
               data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
               data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
               data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
               data_ms_ren          <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
               dma_data_2 <= dma_data;
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
               lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
                 GENERIC MAP (
                   tech   => inferred,
                   hindex => hindex)
                 PORT MAP (
                   HCLK           => clk,
                   HRESETn        => rstn,
                   run            => run,
                   AHB_Master_In  => ahbi,
                   AHB_Master_Out => ahbo,
                   send        => dma_send,
                   valid_burst => dma_valid_burst,
                   done        => dma_done,
                   ren         => dma_ren,
                   address     => dma_address,
                   data        => dma_data_2);
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
                                NOT(sample_f3_val) & NOT(sample_f3_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
               -------------------------------------------------------------------------------
               ms_softandhard_rstn <= rstn AND run_ms AND run;
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   clk  => clk,
                   rstn => ms_softandhard_rstn,      --rstn,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f2_wen   => sample_f3_wen,  -- TODO
                   sample_f2_wdata => sample_f3_wdata,-- TODO
                   dma_addr        => data_ms_addr,         --
                   dma_data        => data_ms_data,         --
                   dma_valid       => data_ms_valid,        --
                   dma_valid_burst => data_ms_valid_burst,  --
                   dma_ren         => data_ms_ren,          --
                   dma_done        => data_ms_done,         --
                   ready_matrix_f0                        => ready_matrix_f0,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_bad_component_error              => error_bad_component_error,
                   error_buffer_full                      => error_buffer_full,
                   error_input_fifo_write                 => error_input_fifo_write,
-                  debug_reg                              => observation_reg,
+                  debug_reg                              => debug_ms,--observation_reg,
                   status_ready_matrix_f0                 => status_ready_matrix_f0,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0                         => addr_matrix_f0,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
                   matrix_time_f0                         => matrix_time_f0,
                   matrix_time_f1                         => matrix_time_f1,
                   matrix_time_f2                         => matrix_time_f2);
+              -----------------------------------------------------------------------------
+              observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +20 -28

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.lpp_lfr_pkg.ALL;
-            USE lpp.lpp_amba.ALL;
+            --USE lpp.lpp_amba.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_lfr_apbreg IS
               GENERIC (
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 3;
                 pindex          : INTEGER                       := 4;
                 paddr           : INTEGER                       := 4;
                 pmask           : INTEGER                       := 16#fff#;
                 pirq_ms         : INTEGER                       := 0;
                 pirq_wfp        : INTEGER                       := 1;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
               PORT (
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
                 -- AMBA APB Slave Interface
                 apbi : IN  apb_slv_in_type;
                 apbo : OUT apb_slv_out_type;
                 ---------------------------------------------------------------------------
                 -- Spectral Matrix Reg
                 run_ms          : OUT STD_LOGIC;
                 -- IN
                 ready_matrix_f0 : IN  STD_LOGIC;
                 ready_matrix_f1 : IN  STD_LOGIC;
                 ready_matrix_f2 : IN  STD_LOGIC;
                 error_bad_component_error : IN STD_LOGIC;
                 error_buffer_full         : IN STD_LOGIC;                     --  TODO
                 error_input_fifo_write    : IN STD_LOGIC_VECTOR(2 DOWNTO 0);  --  TODO
             --    debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 -- OUT
                 status_ready_matrix_f0 : OUT STD_LOGIC;
                 status_ready_matrix_f1 : OUT STD_LOGIC;
                 status_ready_matrix_f2 : OUT STD_LOGIC;
                 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                 config_active_interruption_onError     : OUT STD_LOGIC;
                 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 ---------------------------------------------------------------------------
                 -- WaveForm picker Reg
                 status_full     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_err : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 -- OUT
                 data_shaping_BW  : OUT STD_LOGIC;
                 data_shaping_SP0 : OUT STD_LOGIC;
                 data_shaping_SP1 : OUT STD_LOGIC;
                 data_shaping_R0  : OUT STD_LOGIC;
                 data_shaping_R1  : OUT STD_LOGIC;
                 delta_snapshot    : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0_2        : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 delta_f1          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f2          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 enable_f0 : OUT STD_LOGIC;
                 enable_f1 : OUT STD_LOGIC;
                 enable_f2 : OUT STD_LOGIC;
                 enable_f3 : OUT STD_LOGIC;
                 burst_f0 : OUT STD_LOGIC;
                 burst_f1 : OUT STD_LOGIC;
                 burst_f2 : OUT STD_LOGIC;
                 run : OUT STD_LOGIC;
                 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
                 ---------------------------------------------------------------------------
                 );
             END lpp_lfr_apbreg;
             ARCHITECTURE beh OF lpp_lfr_apbreg IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
 => apb_iobar(paddr, pmask));
               TYPE lpp_SpectralMatrix_regs IS RECORD
                 config_active_interruption_onNewMatrix : STD_LOGIC;
                 config_active_interruption_onError     : STD_LOGIC;
                 config_ms_run                          : STD_LOGIC;
                 status_ready_matrix_f0_0               : STD_LOGIC;
                 status_ready_matrix_f1_0               : STD_LOGIC;
                 status_ready_matrix_f2_0               : STD_LOGIC;
                 status_ready_matrix_f0_1               : STD_LOGIC;
                 status_ready_matrix_f1_1               : STD_LOGIC;
                 status_ready_matrix_f2_1               : STD_LOGIC;
                 status_error_bad_component_error       : STD_LOGIC;
                 status_error_buffer_full               : STD_LOGIC;
                 status_error_input_fifo_write          : STD_LOGIC_VECTOR(2 DOWNTO 0);
                 addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 time_matrix_f0_0                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f0_1                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f1_0                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f1_1                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f2_0                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f2_1                       : STD_LOGIC_VECTOR(47 DOWNTO 0);
               END RECORD;
               SIGNAL reg_sp : lpp_SpectralMatrix_regs;
               TYPE lpp_WaveformPicker_regs IS RECORD
                 status_full       : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_full_err   : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err    : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 data_shaping_BW   : STD_LOGIC;
                 data_shaping_SP0  : STD_LOGIC;
                 data_shaping_SP1  : STD_LOGIC;
                 data_shaping_R0   : STD_LOGIC;
                 data_shaping_R1   : STD_LOGIC;
                 delta_snapshot    : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0          : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0_2        : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 delta_f1          : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f2          : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 enable_f0         : STD_LOGIC;
                 enable_f1         : STD_LOGIC;
                 enable_f2         : STD_LOGIC;
                 enable_f3         : STD_LOGIC;
                 burst_f0          : STD_LOGIC;
                 burst_f1          : STD_LOGIC;
                 burst_f2          : STD_LOGIC;
                 run               : STD_LOGIC;
                 addr_data_f0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 start_date        : STD_LOGIC_VECTOR(30 DOWNTO 0);
               END RECORD;
               SIGNAL reg_wp : lpp_WaveformPicker_regs;
               SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               CONSTANT IRQ_WFP_SIZE  : INTEGER := 12;
               SIGNAL   irq_wfp_ZERO  : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   irq_wfp_reg   : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   irq_wfp       : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   ored_irq_wfp  : STD_LOGIC;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
               SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
               SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
               SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
               SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
               SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
               SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN  -- beh
             --  status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
             --  status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
             --  status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
               config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
               config_active_interruption_onError     <= reg_sp.config_active_interruption_onError;
             --  addr_matrix_f0                         <= reg_sp.addr_matrix_f0;
             --  addr_matrix_f1                         <= reg_sp.addr_matrix_f1;
             --  addr_matrix_f2                         <= reg_sp.addr_matrix_f2;
               data_shaping_BW  <= NOT reg_wp.data_shaping_BW;
               data_shaping_SP0 <= reg_wp.data_shaping_SP0;
               data_shaping_SP1 <= reg_wp.data_shaping_SP1;
               data_shaping_R0  <= reg_wp.data_shaping_R0;
               data_shaping_R1  <= reg_wp.data_shaping_R1;
               delta_snapshot    <= reg_wp.delta_snapshot;
               delta_f0          <= reg_wp.delta_f0;
               delta_f0_2        <= reg_wp.delta_f0_2;
               delta_f1          <= reg_wp.delta_f1;
               delta_f2          <= reg_wp.delta_f2;
               nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
               nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
               nb_snapshot_param <= reg_wp.nb_snapshot_param;
               enable_f0 <= reg_wp.enable_f0;
               enable_f1 <= reg_wp.enable_f1;
               enable_f2 <= reg_wp.enable_f2;
               enable_f3 <= reg_wp.enable_f3;
               burst_f0 <= reg_wp.burst_f0;
               burst_f1 <= reg_wp.burst_f1;
               burst_f2 <= reg_wp.burst_f2;
               run <= reg_wp.run;
               addr_data_f0 <= reg_wp.addr_data_f0;
               addr_data_f1 <= reg_wp.addr_data_f1;
               addr_data_f2 <= reg_wp.addr_data_f2;
               addr_data_f3 <= reg_wp.addr_data_f3;
               start_date <= reg_wp.start_date;
               lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN  -- PROCESS lpp_dma_top
                 IF HRESETn = '0' THEN               -- asynchronous reset (active low)
                   reg_sp.config_active_interruption_onNewMatrix <= '0';
                   reg_sp.config_active_interruption_onError     <= '0';
                   reg_sp.config_ms_run                          <= '1';
                   reg_sp.status_ready_matrix_f0_0               <= '0';
                   reg_sp.status_ready_matrix_f1_0               <= '0';
                   reg_sp.status_ready_matrix_f2_0               <= '0';
                   reg_sp.status_ready_matrix_f0_1               <= '0';
                   reg_sp.status_ready_matrix_f1_1               <= '0';
                   reg_sp.status_ready_matrix_f2_1               <= '0';
                   reg_sp.status_error_bad_component_error       <= '0';
                   reg_sp.status_error_buffer_full               <= '0';
                   reg_sp.status_error_input_fifo_write          <= (OTHERS => '0');
                   reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
-                  reg_sp.time_matrix_f0_0 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f0_0 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f1_0 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f1_0 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f2_0 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f2_0 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f0_1 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f0_1 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f1_1 <= (OTHERS => '0');  -- ok
+                  --reg_sp.time_matrix_f1_1 <= (OTHERS => '0');  -- ok
-                  reg_sp.time_matrix_f2_1 <= (OTHERS => '0');  -- ok
+            --      reg_sp.time_matrix_f2_1 <= (OTHERS => '0');  -- ok
                   prdata <= (OTHERS => '0');
                   apbo.pirq <= (OTHERS => '0');
                   status_full_ack <= (OTHERS => '0');
                   reg_wp.data_shaping_BW   <= '0';
                   reg_wp.data_shaping_SP0  <= '0';
                   reg_wp.data_shaping_SP1  <= '0';
                   reg_wp.data_shaping_R0   <= '0';
                   reg_wp.data_shaping_R1   <= '0';
                   reg_wp.enable_f0         <= '0';
                   reg_wp.enable_f1         <= '0';
                   reg_wp.enable_f2         <= '0';
                   reg_wp.enable_f3         <= '0';
                   reg_wp.burst_f0          <= '0';
                   reg_wp.burst_f1          <= '0';
                   reg_wp.burst_f2          <= '0';
                   reg_wp.run               <= '0';
                   reg_wp.addr_data_f0      <= (OTHERS => '0');
                   reg_wp.addr_data_f1      <= (OTHERS => '0');
                   reg_wp.addr_data_f2      <= (OTHERS => '0');
                   reg_wp.addr_data_f3      <= (OTHERS => '0');
                   reg_wp.status_full       <= (OTHERS => '0');
                   reg_wp.status_full_err   <= (OTHERS => '0');
                   reg_wp.status_new_err    <= (OTHERS => '0');
                   reg_wp.delta_snapshot    <= (OTHERS => '0');
                   reg_wp.delta_f0          <= (OTHERS => '0');
                   reg_wp.delta_f0_2        <= (OTHERS => '0');
                   reg_wp.delta_f1          <= (OTHERS => '0');
                   reg_wp.delta_f2          <= (OTHERS => '0');
                   reg_wp.nb_data_by_buffer <= (OTHERS => '0');
                   reg_wp.nb_snapshot_param <= (OTHERS => '0');
                   reg_wp.start_date        <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
-                  reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0;  -- ok
-                  reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1;  -- ok
-                  reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2;  -- ok
-                  reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0;  -- ok
-                  reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1;  -- ok
-                  reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2;  -- ok
                   status_full_ack <= (OTHERS => '0');
                   reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
                   reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
                   reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
                   reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
                   reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
                   reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
                   reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
                   reg_sp.status_error_buffer_full         <= reg_sp.status_error_buffer_full OR error_buffer_full;
                   reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
                   reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
                   reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
                   all_status : FOR I IN 3 DOWNTO 0 LOOP
                     reg_wp.status_full(I)     <= status_full(I) AND reg_wp.run;
                     reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
                     reg_wp.status_new_err(I)  <= status_new_err(I) AND reg_wp.run;
                   END LOOP all_status;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   prdata            <= (OTHERS => '0');
                   IF apbi.psel(pindex) = '1' THEN
                     -- APB DMA READ  --
                     CASE paddr(7 DOWNTO 2) IS
                                        --0
                       WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
                                        prdata(1) <= reg_sp.config_active_interruption_onError;
                                        prdata(2) <= reg_sp.config_ms_run;
                                        --1
                       WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
                                        prdata(1) <= reg_sp.status_ready_matrix_f0_1;
                                        prdata(2) <= reg_sp.status_ready_matrix_f1_0;
                                        prdata(3) <= reg_sp.status_ready_matrix_f1_1;
                                        prdata(4) <= reg_sp.status_ready_matrix_f2_0;
                                        prdata(5) <= reg_sp.status_ready_matrix_f2_1;
                                        prdata(6) <= reg_sp.status_error_bad_component_error;
                                        prdata(7) <= reg_sp.status_error_buffer_full;
                                        prdata(8) <= reg_sp.status_error_input_fifo_write(0);
                                        prdata(9) <= reg_sp.status_error_input_fifo_write(1);
                                        prdata(10) <= reg_sp.status_error_input_fifo_write(2);
                                        --2
                       WHEN "000010" => prdata              <= reg_sp.addr_matrix_f0_0;
                                        --3
                       WHEN "000011" => prdata              <= reg_sp.addr_matrix_f0_1;
                                        --4
                       WHEN "000100" => prdata              <= reg_sp.addr_matrix_f1_0;
                                        --5
                       WHEN "000101" => prdata              <= reg_sp.addr_matrix_f1_1;
                                        --6
                       WHEN "000110" => prdata              <= reg_sp.addr_matrix_f2_0;
                                        --7
                       WHEN "000111" => prdata              <= reg_sp.addr_matrix_f2_1;
                                        --8
                       WHEN "001000" => prdata              <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
                                        --9
                       WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO  0);
                                        --10
                       WHEN "001010" => prdata              <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
                                        --11
                       WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO  0);
                                        --12
                       WHEN "001100" => prdata              <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
                                        --13
                       WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO  0);
                                        --14
                       WHEN "001110" => prdata              <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
                                        --15
                       WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO  0);
                                        --16
                       WHEN "010000" => prdata              <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
                                        --17
                       WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO  0);
                                        --18
                       WHEN "010010" => prdata              <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
                                        --19
                       WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO  0);
                                        ---------------------------------------------------------------------
                                        --20
                       WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
                                        prdata(1) <= reg_wp.data_shaping_SP0;
                                        prdata(2) <= reg_wp.data_shaping_SP1;
                                        prdata(3) <= reg_wp.data_shaping_R0;
                                        prdata(4) <= reg_wp.data_shaping_R1;
                                        --21
                       WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
                                        prdata(1) <= reg_wp.enable_f1;
                                        prdata(2) <= reg_wp.enable_f2;
                                        prdata(3) <= reg_wp.enable_f3;
                                        prdata(4) <= reg_wp.burst_f0;
                                        prdata(5) <= reg_wp.burst_f1;
                                        prdata(6) <= reg_wp.burst_f2;
                                        prdata(7) <= reg_wp.run;
                                        --22
                       WHEN "010110" => prdata             <= reg_wp.addr_data_f0;
                                        --23
                       WHEN "010111" => prdata             <= reg_wp.addr_data_f1;
                                        --24
                       WHEN "011000" => prdata             <= reg_wp.addr_data_f2;
                                        --25
                       WHEN "011001" => prdata             <= reg_wp.addr_data_f3;
                                        --26
                       WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
                                        prdata(7 DOWNTO 4)  <= reg_wp.status_full_err;
                                        prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
                                        --27
                       WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_snapshot;
                                        --28
                       WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_f0;
                                        --29
                       WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
                                        --30
                       WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_f1;
                                        --31
                       WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_f2;
                                        --32
                       WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
                                        --33
                       WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
                                        --34
                       WHEN "100010" => prdata(30 DOWNTO 0)                       <= reg_wp.start_date;
                                        --35
                       WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
                                        ----------------------------------------------------
                       WHEN "111100" => prdata(23 DOWNTO 0)                       <= top_lfr_version(23 DOWNTO 0);
                       WHEN OTHERS   => NULL;
                     END CASE;
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       -- APB DMA WRITE --
                       CASE paddr(7 DOWNTO 2) IS
                         --
                         WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
                                          reg_sp.config_active_interruption_onError     <= apbi.pwdata(1);
                                          reg_sp.config_ms_run                          <= apbi.pwdata(2);
                         WHEN "000001" => reg_sp.status_ready_matrix_f0_0               <= apbi.pwdata(0);
                                          reg_sp.status_ready_matrix_f0_1               <= apbi.pwdata(1);
                                          reg_sp.status_ready_matrix_f1_0               <= apbi.pwdata(2);
                                          reg_sp.status_ready_matrix_f1_1               <= apbi.pwdata(3);
                                          reg_sp.status_ready_matrix_f2_0               <= apbi.pwdata(4);
                                          reg_sp.status_ready_matrix_f2_1           <= apbi.pwdata(5);
                                          reg_sp.status_error_bad_component_error   <= apbi.pwdata(6);
                                          reg_sp.status_error_buffer_full           <= apbi.pwdata(7);
                                          reg_sp.status_error_input_fifo_write(0)   <= apbi.pwdata(8);
                                          reg_sp.status_error_input_fifo_write(1)   <= apbi.pwdata(9);
                                          reg_sp.status_error_input_fifo_write(2)   <= apbi.pwdata(10);
                                          --2
                         WHEN "000010" => reg_sp.addr_matrix_f0_0  <= apbi.pwdata;
                         WHEN "000011" => reg_sp.addr_matrix_f0_1  <= apbi.pwdata;
                         WHEN "000100" => reg_sp.addr_matrix_f1_0  <= apbi.pwdata;
                         WHEN "000101" => reg_sp.addr_matrix_f1_1  <= apbi.pwdata;
                         WHEN "000110" => reg_sp.addr_matrix_f2_0  <= apbi.pwdata;
                         WHEN "000111" => reg_sp.addr_matrix_f2_1  <= apbi.pwdata;
                                          --8 to 19
                                          --20
                         WHEN "010100" => reg_wp.data_shaping_BW  <= apbi.pwdata(0);
                                          reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
                                          reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
                                          reg_wp.data_shaping_R0  <= apbi.pwdata(3);
                                          reg_wp.data_shaping_R1  <= apbi.pwdata(4);
                         WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
                                          reg_wp.enable_f1 <= apbi.pwdata(1);
                                          reg_wp.enable_f2 <= apbi.pwdata(2);
                                          reg_wp.enable_f3 <= apbi.pwdata(3);
                                          reg_wp.burst_f0  <= apbi.pwdata(4);
                                          reg_wp.burst_f1  <= apbi.pwdata(5);
                                          reg_wp.burst_f2  <= apbi.pwdata(6);
                                          reg_wp.run       <= apbi.pwdata(7);
                                          --22
                         WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
                         WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
                         WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
                         WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
                                          --26
                         WHEN "011010" => reg_wp.status_full  <= apbi.pwdata(3 DOWNTO 0);
                                          reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
                                          reg_wp.status_new_err  <= apbi.pwdata(11 DOWNTO 8);
                                          status_full_ack(0)     <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
                                          status_full_ack(1)     <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
                                          status_full_ack(2)     <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
                                          status_full_ack(3)     <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
                         WHEN "011011" => reg_wp.delta_snapshot    <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "011100" => reg_wp.delta_f0          <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "011101" => reg_wp.delta_f0_2        <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
                         WHEN "011110" => reg_wp.delta_f1          <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "011111" => reg_wp.delta_f2          <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
                         WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
                         WHEN "100010" => reg_wp.start_date        <= apbi.pwdata(30 DOWNTO 0);
                         WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
                                          --
                         WHEN OTHERS   => NULL;
                       END CASE;
                     END IF;
                   END IF;
                   apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
                                                                                              ready_matrix_f1 OR
                                                                                              ready_matrix_f2)
                                           )
                                          OR
                                          (reg_sp.config_active_interruption_onError AND (
                                            error_bad_component_error
                                            OR error_buffer_full
                                            OR error_input_fifo_write(0)
                                            OR error_input_fifo_write(1)
                                            OR error_input_fifo_write(2))
                                           ));
                   apbo.pirq(pirq_wfp) <= ored_irq_wfp;
                 END IF;
               END PROCESS lpp_lfr_apbreg;
               apbo.pindex  <= pindex;
               apbo.pconfig <= pconfig;
               apbo.prdata  <= prdata;
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
               PROCESS (HCLK, HRESETn)
               BEGIN  -- PROCESS
                 IF HRESETn = '0' THEN                 -- asynchronous reset (active low)
                   irq_wfp_reg <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
                   irq_wfp_reg <= irq_wfp_reg_s;
                 END IF;
               END PROCESS;
               all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
                 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
               END GENERATE all_irq_wfp;
               irq_wfp_ZERO <= (OTHERS => '0');
               ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
               run_ms <= reg_sp.config_ms_run;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
                 PORT MAP (
                   clk  => HCLK,
                   rstn => HRESETn,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f0,
-                  reg0_addr_matrix         => reg0_addr_matrix_f0,
+                  reg0_addr_matrix         => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0,
-                  reg0_matrix_time         => reg0_matrix_time_f0,
+                  reg0_matrix_time         => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f0,
-                  reg1_addr_matrix         => reg1_addr_matrix_f0,
+                  reg1_addr_matrix         => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0,
-                  reg1_matrix_time         => reg1_matrix_time_f0,
+                  reg1_matrix_time         => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0,
                   ready_matrix              => ready_matrix_f0,
                   status_ready_matrix       => status_ready_matrix_f0,
                   addr_matrix               => addr_matrix_f0,
                   matrix_time               => matrix_time_f0);
               lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
                 PORT MAP (
                   clk  => HCLK,
                   rstn => HRESETn,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f1,
-                  reg0_addr_matrix         => reg0_addr_matrix_f1,
+                  reg0_addr_matrix         => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1,
-                  reg0_matrix_time         => reg0_matrix_time_f1,
+                  reg0_matrix_time         => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f1,
-                  reg1_addr_matrix         => reg1_addr_matrix_f1,
+                  reg1_addr_matrix         => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1,
-                  reg1_matrix_time         => reg1_matrix_time_f1,
+                  reg1_matrix_time         => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1,
                   ready_matrix              => ready_matrix_f1,
                   status_ready_matrix       => status_ready_matrix_f1,
                   addr_matrix               => addr_matrix_f1,
                   matrix_time               => matrix_time_f1);
               lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
                 PORT MAP (
                   clk  => HCLK,
                   rstn => HRESETn,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f2,
-                  reg0_addr_matrix         => reg0_addr_matrix_f2,
+                  reg0_addr_matrix         => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2,
-                  reg0_matrix_time         => reg0_matrix_time_f2,
+                  reg0_matrix_time         => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f2,
-                  reg1_addr_matrix         => reg1_addr_matrix_f2,
+                  reg1_addr_matrix         => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2,
-                  reg1_matrix_time         => reg1_matrix_time_f2,
+                  reg1_matrix_time         => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2,
                   ready_matrix              => ready_matrix_f2,
                   status_ready_matrix       => status_ready_matrix_f2,
                   addr_matrix               => addr_matrix_f2,
                   matrix_time               => matrix_time_f2);
-            END beh;
  No newline at end of file
+            END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd +13 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             ENTITY lpp_apbreg_ms_pointer IS
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 -- REG 0
                 reg0_status_ready_matrix : IN  STD_LOGIC;
                 reg0_ready_matrix        : OUT STD_LOGIC;
                 reg0_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 reg0_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 -- REG 1
                 reg1_status_ready_matrix : IN  STD_LOGIC;
                 reg1_ready_matrix        : OUT STD_LOGIC;
                 reg1_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 reg1_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 -- SpectralMatrix
                 ready_matrix        : IN  STD_LOGIC;
                 status_ready_matrix : OUT STD_LOGIC;
                 addr_matrix         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 matrix_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0)
                 );
             END lpp_apbreg_ms_pointer;
             ARCHITECTURE beh OF lpp_apbreg_ms_pointer IS
               SIGNAL current_reg : STD_LOGIC;
             BEGIN  -- beh
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_reg <= '0';
+                  reg0_matrix_time <= (OTHERS => '0');
+                  reg1_matrix_time <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF ready_matrix = '1' THEN
                     current_reg <= NOT current_reg;
                   END IF;
+                  IF current_reg = '0' THEN
+                    reg0_matrix_time <= matrix_time;
+                  END IF;
+                  IF current_reg = '1' THEN
+                    reg1_matrix_time <= matrix_time;
+                  END IF;
                 END IF;
               END PROCESS;
               addr_matrix <= reg0_addr_matrix WHEN current_reg = '0' ELSE
                              reg1_addr_matrix;
               status_ready_matrix <= reg0_status_ready_matrix WHEN current_reg = '0' ELSE
                                      reg1_status_ready_matrix;
               reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
               reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
-            END beh;
  No newline at end of file
+            END beh;

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