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update APB_REG
pellion -
r373:8b7232d194b4 JC
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@@ -393,8 +393,11 vcom_lpp:
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
395 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
395 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
396 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
396 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
398 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
398 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
401 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
402 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
403 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
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@@ -32,6 +32,12 USE lpp.spectral_matrix_package.ALL;
32 use lpp.lpp_fft.all;
32 use lpp.lpp_fft.all;
33 use lpp.fft_components.all;
33 use lpp.fft_components.all;
34
34
35 LIBRARY grlib;
36 USE grlib.amba.ALL;
37 USE grlib.stdlib.ALL;
38 USE grlib.devices.ALL;
39 USE GRLIB.DMA2AHB_Package.ALL;
40
35 ENTITY TB IS
41 ENTITY TB IS
36
42
37
43
@@ -103,6 +109,15 ARCHITECTURE beh OF TB IS
103 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
104 SIGNAL ren_counter : INTEGER;
110 SIGNAL ren_counter : INTEGER;
105
111
112 SIGNAL error_buffer_full : STD_LOGIC;
113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
114 -----------------------------------------------------------------------------
115 SIGNAL apbi : apb_slv_in_type;
116 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120
106 BEGIN -- beh
121 BEGIN -- beh
107
122
108 clk25MHz <= NOT clk25MHz AFTER 20 ns;
123 clk25MHz <= NOT clk25MHz AFTER 20 ns;
@@ -234,8 +249,8 BEGIN -- beh
234 ready_matrix_f2 => ready_matrix_f2,
249 ready_matrix_f2 => ready_matrix_f2,
235 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
250 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
236 error_bad_component_error => error_bad_component_error,
251 error_bad_component_error => error_bad_component_error,
237 error_buffer_full => OPEN,
252 error_buffer_full => error_buffer_full,
238 error_input_fifo_write => OPEN,
253 error_input_fifo_write => error_input_fifo_write,
239
254
240 debug_reg => debug_reg,
255 debug_reg => debug_reg,
241 status_ready_matrix_f0 => status_ready_matrix_f0,
256 status_ready_matrix_f0 => status_ready_matrix_f0,
@@ -255,37 +270,123 BEGIN -- beh
255 matrix_time_f1 => matrix_time_f1,
270 matrix_time_f1 => matrix_time_f1,
256 matrix_time_f2 => matrix_time_f2);
271 matrix_time_f2 => matrix_time_f2);
257
272
273
274
275
276 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
277 GENERIC MAP (
278 nb_data_by_buffer_size => 11,
279 nb_word_by_buffer_size => 11,
280 nb_snapshot_param_size => 11,
281 delta_vector_size => 20,
282 delta_vector_size_f0_2 => 7,
283 pindex => 4,
284 paddr => 4,
285 pmask => 16#fff#,
286 pirq_ms => 0,
287 pirq_wfp => 1,
288 top_lfr_version => (OTHERS => '0')
289 )
290 PORT MAP (
291 HCLK => clk25MHz,
292 HRESETn => rstn,
293 apbi => apbi,
294 apbo => OPEN,
295
296 run_ms => OPEN,
297
298 ready_matrix_f0 => ready_matrix_f0,
299 ready_matrix_f1 => ready_matrix_f1,
300 ready_matrix_f2 => ready_matrix_f2,
301 error_bad_component_error => error_bad_component_error,
302 error_buffer_full => error_buffer_full, -- TODO
303 error_input_fifo_write => error_input_fifo_write, -- TODO
304 status_ready_matrix_f0 => status_ready_matrix_f0,
305 status_ready_matrix_f1 => status_ready_matrix_f1,
306 status_ready_matrix_f2 => status_ready_matrix_f2,
307 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
308 config_active_interruption_onError => config_active_interruption_onError,
309
310 matrix_time_f0 => matrix_time_f0,
311 matrix_time_f1 => matrix_time_f1,
312 matrix_time_f2 => matrix_time_f2,
313
314 addr_matrix_f0 => addr_matrix_f0,
315 addr_matrix_f1 => addr_matrix_f1,
316 addr_matrix_f2 => addr_matrix_f2,
317 -------------------------------------------------------------------------
318 status_full => status_full,
319 status_full_ack => status_full_ack,
320 status_full_err => status_full_err,
321 status_new_err => status_new_err,
322 data_shaping_BW => OPEN,
323 data_shaping_SP0 => OPEN,
324 data_shaping_SP1 => OPEN,
325 data_shaping_R0 => OPEN,
326 data_shaping_R1 => OPEN,
327 delta_snapshot => OPEN,
328 delta_f0 => OPEN,
329 delta_f0_2 => OPEN,
330 delta_f1 => OPEN,
331 delta_f2 => OPEN,
332 nb_data_by_buffer => OPEN,
333 nb_word_by_buffer => OPEN,
334 nb_snapshot_param => OPEN,
335 enable_f0 => OPEN,
336 enable_f1 => OPEN,
337 enable_f2 => OPEN,
338 enable_f3 => OPEN,
339 burst_f0 => OPEN,
340 burst_f1 => OPEN,
341 burst_f2 => OPEN,
342 run => OPEN,
343 addr_data_f0 => OPEN,
344 addr_data_f1 => OPEN,
345 addr_data_f2 => OPEN,
346 addr_data_f3 => OPEN,
347 start_date => OPEN);
348
349
350
351
352
353
354
355
356
357
258
358
259
359
260
360
261
361
262 PROCESS (clk25MHz, rstn)
362
263 BEGIN -- PROCESS
363
264 IF rstn = '0' THEN -- asynchronous reset (active low)
364 -- PROCESS (clk25MHz, rstn)
265 status_ready_matrix_f0 <= '0';
365 -- BEGIN -- PROCESS
266 -- status_ready_matrix_f0_1 <= '0';
366 -- IF rstn = '0' THEN -- asynchronous reset (active low)
267 status_ready_matrix_f1 <= '0';
367 -- status_ready_matrix_f0 <= '0';
268 status_ready_matrix_f2 <= '0';
368 ---- status_ready_matrix_f0_1 <= '0';
269 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
369 -- status_ready_matrix_f1 <= '0';
270 status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
370 -- status_ready_matrix_f2 <= '0';
271 -- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
371 -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
272 status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
372 -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
273 status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
373 ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
274 END IF;
374 -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
275 END PROCESS;
375 -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
276
376 -- END IF;
377 -- END PROCESS;
277
378
278
379
279
380
280 -- status_error_anticipating_empty_fifo <= '0';
381 -- status_error_anticipating_empty_fifo <= '0';
281 -- status_error_bad_component_error <= '0';
382 -- status_error_bad_component_error <= '0';
282
383
283 config_active_interruption_onNewMatrix <= '0';
384 -- config_active_interruption_onNewMatrix <= '0';
284 config_active_interruption_onError <= '0';
385 -- config_active_interruption_onError <= '0';
285 addr_matrix_f0 <= (OTHERS => '0');
386 -- addr_matrix_f0 <= (OTHERS => '0');
286 -- addr_matrix_f0_1 <= (OTHERS => '0');
387 -- addr_matrix_f0_1 <= (OTHERS => '0');
287 addr_matrix_f1 <= (OTHERS => '0');
388 -- addr_matrix_f1 <= (OTHERS => '0');
288 addr_matrix_f2 <= (OTHERS => '0');
389 -- addr_matrix_f2 <= (OTHERS => '0');
289
390
290
391
291 PROCESS (clk25MHz, rstn)
392 PROCESS (clk25MHz, rstn)
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@@ -281,7 +281,9 ARCHITECTURE beh OF lpp_lfr IS
281
281
282 SIGNAL error_buffer_full : STD_LOGIC;
282 SIGNAL error_buffer_full : STD_LOGIC;
283 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
283 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
284
284
285 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
286
285 BEGIN
287 BEGIN
286
288
287 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
289 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -698,7 +700,7 BEGIN
698 error_buffer_full => error_buffer_full,
700 error_buffer_full => error_buffer_full,
699 error_input_fifo_write => error_input_fifo_write,
701 error_input_fifo_write => error_input_fifo_write,
700
702
701 debug_reg => observation_reg,
703 debug_reg => debug_ms,--observation_reg,
702
704
703 status_ready_matrix_f0 => status_ready_matrix_f0,
705 status_ready_matrix_f0 => status_ready_matrix_f0,
704 status_ready_matrix_f1 => status_ready_matrix_f1,
706 status_ready_matrix_f1 => status_ready_matrix_f1,
@@ -713,4 +715,8 BEGIN
713 matrix_time_f1 => matrix_time_f1,
715 matrix_time_f1 => matrix_time_f1,
714 matrix_time_f2 => matrix_time_f2);
716 matrix_time_f2 => matrix_time_f2);
715
717
718 -----------------------------------------------------------------------------
719 observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
720
721
716 END beh;
722 END beh;
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@@ -29,7 +29,7 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
@@ -136,11 +136,11 END lpp_lfr_apbreg;
136 ARCHITECTURE beh OF lpp_lfr_apbreg IS
136 ARCHITECTURE beh OF lpp_lfr_apbreg IS
137
137
138 CONSTANT REVISION : INTEGER := 1;
138 CONSTANT REVISION : INTEGER := 1;
139
139
140 CONSTANT pconfig : apb_config_type := (
140 CONSTANT pconfig : apb_config_type := (
141 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
141 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
142 1 => apb_iobar(paddr, pmask));
142 1 => apb_iobar(paddr, pmask));
143
143
144 TYPE lpp_SpectralMatrix_regs IS RECORD
144 TYPE lpp_SpectralMatrix_regs IS RECORD
145 config_active_interruption_onNewMatrix : STD_LOGIC;
145 config_active_interruption_onNewMatrix : STD_LOGIC;
146 config_active_interruption_onError : STD_LOGIC;
146 config_active_interruption_onError : STD_LOGIC;
@@ -316,13 +316,13 BEGIN -- beh
316 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
316 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
317 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
317 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
318
318
319 reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
319 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
320 reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
320 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
321 reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
321 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
322
322
323 reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
323 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
324 reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
324 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
325 reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
326
326
327 prdata <= (OTHERS => '0');
327 prdata <= (OTHERS => '0');
328
328
@@ -360,14 +360,6 BEGIN -- beh
360 reg_wp.start_date <= (OTHERS => '0');
360 reg_wp.start_date <= (OTHERS => '0');
361
361
362 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
362 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
363
364 reg_sp.time_matrix_f0_0 <= reg0_matrix_time_f0; -- ok
365 reg_sp.time_matrix_f1_0 <= reg0_matrix_time_f1; -- ok
366 reg_sp.time_matrix_f2_0 <= reg0_matrix_time_f2; -- ok
367
368 reg_sp.time_matrix_f0_1 <= reg1_matrix_time_f0; -- ok
369 reg_sp.time_matrix_f1_1 <= reg1_matrix_time_f1; -- ok
370 reg_sp.time_matrix_f2_1 <= reg1_matrix_time_f2; -- ok
371
363
372 status_full_ack <= (OTHERS => '0');
364 status_full_ack <= (OTHERS => '0');
373
365
@@ -626,13 +618,13 BEGIN -- beh
626
618
627 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
619 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
628 reg0_ready_matrix => reg0_ready_matrix_f0,
620 reg0_ready_matrix => reg0_ready_matrix_f0,
629 reg0_addr_matrix => reg0_addr_matrix_f0,
621 reg0_addr_matrix => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0,
630 reg0_matrix_time => reg0_matrix_time_f0,
622 reg0_matrix_time => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0,
631
623
632 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
624 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
633 reg1_ready_matrix => reg1_ready_matrix_f0,
625 reg1_ready_matrix => reg1_ready_matrix_f0,
634 reg1_addr_matrix => reg1_addr_matrix_f0,
626 reg1_addr_matrix => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0,
635 reg1_matrix_time => reg1_matrix_time_f0,
627 reg1_matrix_time => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0,
636
628
637 ready_matrix => ready_matrix_f0,
629 ready_matrix => ready_matrix_f0,
638 status_ready_matrix => status_ready_matrix_f0,
630 status_ready_matrix => status_ready_matrix_f0,
@@ -646,13 +638,13 BEGIN -- beh
646
638
647 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
639 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
648 reg0_ready_matrix => reg0_ready_matrix_f1,
640 reg0_ready_matrix => reg0_ready_matrix_f1,
649 reg0_addr_matrix => reg0_addr_matrix_f1,
641 reg0_addr_matrix => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1,
650 reg0_matrix_time => reg0_matrix_time_f1,
642 reg0_matrix_time => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1,
651
643
652 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
644 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
653 reg1_ready_matrix => reg1_ready_matrix_f1,
645 reg1_ready_matrix => reg1_ready_matrix_f1,
654 reg1_addr_matrix => reg1_addr_matrix_f1,
646 reg1_addr_matrix => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1,
655 reg1_matrix_time => reg1_matrix_time_f1,
647 reg1_matrix_time => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1,
656
648
657 ready_matrix => ready_matrix_f1,
649 ready_matrix => ready_matrix_f1,
658 status_ready_matrix => status_ready_matrix_f1,
650 status_ready_matrix => status_ready_matrix_f1,
@@ -666,13 +658,13 BEGIN -- beh
666
658
667 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
659 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
668 reg0_ready_matrix => reg0_ready_matrix_f2,
660 reg0_ready_matrix => reg0_ready_matrix_f2,
669 reg0_addr_matrix => reg0_addr_matrix_f2,
661 reg0_addr_matrix => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2,
670 reg0_matrix_time => reg0_matrix_time_f2,
662 reg0_matrix_time => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2,
671
663
672 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
664 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
673 reg1_ready_matrix => reg1_ready_matrix_f2,
665 reg1_ready_matrix => reg1_ready_matrix_f2,
674 reg1_addr_matrix => reg1_addr_matrix_f2,
666 reg1_addr_matrix => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2,
675 reg1_matrix_time => reg1_matrix_time_f2,
667 reg1_matrix_time => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2,
676
668
677 ready_matrix => ready_matrix_f2,
669 ready_matrix => ready_matrix_f2,
678 status_ready_matrix => status_ready_matrix_f2,
670 status_ready_matrix => status_ready_matrix_f2,
@@ -680,4 +672,4 BEGIN -- beh
680 matrix_time => matrix_time_f2);
672 matrix_time => matrix_time_f2);
681
673
682
674
683 END beh; No newline at end of file
675 END beh;
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@@ -61,11 +61,20 BEGIN -- beh
61 BEGIN -- PROCESS
61 BEGIN -- PROCESS
62 IF rstn = '0' THEN -- asynchronous reset (active low)
62 IF rstn = '0' THEN -- asynchronous reset (active low)
63 current_reg <= '0';
63 current_reg <= '0';
64 reg0_matrix_time <= (OTHERS => '0');
65 reg1_matrix_time <= (OTHERS => '0');
64
66
65 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
66 IF ready_matrix = '1' THEN
68 IF ready_matrix = '1' THEN
67 current_reg <= NOT current_reg;
69 current_reg <= NOT current_reg;
68 END IF;
70 END IF;
71 IF current_reg = '0' THEN
72 reg0_matrix_time <= matrix_time;
73 END IF;
74 IF current_reg = '1' THEN
75 reg1_matrix_time <= matrix_time;
76 END IF;
77
69 END IF;
78 END IF;
70 END PROCESS;
79 END PROCESS;
71
80
@@ -78,4 +87,7 BEGIN -- beh
78 reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
87 reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
79 reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
88 reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
80
89
81 END beh; No newline at end of file
90
91
92
93 END beh;
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