@@ -0,0 +1,63 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------ | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------ | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.std_logic_1164.all; | |||
|
24 | use IEEE.numeric_std.all; | |||
|
25 | ||||
|
26 | ENTITY ramp_generator IS | |||
|
27 | ||||
|
28 | GENERIC ( | |||
|
29 | DATA_SIZE : INTEGER := 16; | |||
|
30 | VALUE_UNSIGNED_INIT : INTEGER := 0; | |||
|
31 | VALUE_UNSIGNED_INCR : INTEGER := 1; | |||
|
32 | VALUE_UNSIGNED_MASK : INTEGER := 16#FFFF#); | |||
|
33 | ||||
|
34 | PORT ( | |||
|
35 | clk : IN STD_LOGIC; | |||
|
36 | rstn : IN STD_LOGIC; | |||
|
37 | new_data : IN STD_LOGIC; | |||
|
38 | output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); | |||
|
39 | ||||
|
40 | END ramp_generator; | |||
|
41 | ||||
|
42 | ARCHITECTURE beh OF ramp_generator IS | |||
|
43 | ||||
|
44 | SIGNAL data : STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0); | |||
|
45 | ||||
|
46 | BEGIN -- beh | |||
|
47 | ||||
|
48 | PROCESS (clk, rstn) | |||
|
49 | BEGIN -- PROCESS | |||
|
50 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
51 | data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INIT,DATA_SIZE)) | |||
|
52 | AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK,DATA_SIZE)); | |||
|
53 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
54 | IF new_data = '1' THEN | |||
|
55 | data <= STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_INCR + to_integer(UNSIGNED(data)),DATA_SIZE)) | |||
|
56 | AND STD_LOGIC_VECTOR(to_unsigned(VALUE_UNSIGNED_MASK ,DATA_SIZE)); | |||
|
57 | END IF; | |||
|
58 | END IF; | |||
|
59 | END PROCESS; | |||
|
60 | ||||
|
61 | output_data <= data; | |||
|
62 | ||||
|
63 | END beh; |
@@ -1,520 +1,566 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
31 | USE gaisler.sim.ALL; |
|
31 | USE gaisler.sim.ALL; | |
32 | USE gaisler.memctrl.ALL; |
|
32 | USE gaisler.memctrl.ALL; | |
33 | USE gaisler.leon3.ALL; |
|
33 | USE gaisler.leon3.ALL; | |
34 | USE gaisler.uart.ALL; |
|
34 | USE gaisler.uart.ALL; | |
35 | USE gaisler.misc.ALL; |
|
35 | USE gaisler.misc.ALL; | |
36 | USE gaisler.spacewire.ALL; |
|
36 | USE gaisler.spacewire.ALL; | |
37 | LIBRARY esa; |
|
37 | LIBRARY esa; | |
38 | USE esa.memoryctrl.ALL; |
|
38 | USE esa.memoryctrl.ALL; | |
39 | LIBRARY lpp; |
|
39 | LIBRARY lpp; | |
40 | USE lpp.lpp_memory.ALL; |
|
40 | USE lpp.lpp_memory.ALL; | |
41 | USE lpp.lpp_ad_conv.ALL; |
|
41 | USE lpp.lpp_ad_conv.ALL; | |
42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
44 | USE lpp.iir_filter.ALL; |
|
44 | USE lpp.iir_filter.ALL; | |
45 | USE lpp.general_purpose.ALL; |
|
45 | USE lpp.general_purpose.ALL; | |
46 | USE lpp.lpp_lfr_management.ALL; |
|
46 | USE lpp.lpp_lfr_management.ALL; | |
47 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
48 | USE lpp.lpp_bootloader_pkg.ALL; |
|
48 | USE lpp.lpp_bootloader_pkg.ALL; | |
49 |
|
49 | |||
50 | --library proasic3l; |
|
50 | --library proasic3l; | |
51 | --use proasic3l.all; |
|
51 | --use proasic3l.all; | |
52 |
|
52 | |||
53 | ENTITY LFR_EQM IS |
|
53 | ENTITY LFR_EQM IS | |
54 | GENERIC ( |
|
54 | GENERIC ( | |
55 | Mem_use : INTEGER := use_RAM; |
|
55 | Mem_use : INTEGER := use_RAM; | |
56 | USE_BOOTLOADER : INTEGER := 0 |
|
56 | USE_BOOTLOADER : INTEGER := 0; | |
|
57 | USE_ADCDRIVER : INTEGER := 0; | |||
|
58 | tech : INTEGER := apa3e; | |||
|
59 | tech_leon : INTEGER := apa3e | |||
57 | ); |
|
60 | ); | |
58 |
|
61 | |||
59 | PORT ( |
|
62 | PORT ( | |
60 | clk50MHz : IN STD_ULOGIC; |
|
63 | clk50MHz : IN STD_ULOGIC; | |
61 | clk49_152MHz : IN STD_ULOGIC; |
|
64 | clk49_152MHz : IN STD_ULOGIC; | |
62 | reset : IN STD_ULOGIC; |
|
65 | reset : IN STD_ULOGIC; | |
63 |
|
66 | |||
64 | -- TAG -------------------------------------------------------------------- |
|
67 | -- TAG -------------------------------------------------------------------- | |
65 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
|
68 | TAG1 : IN STD_ULOGIC; -- DSU rx data | |
66 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
|
69 | TAG3 : OUT STD_ULOGIC; -- DSU tx data | |
67 | -- UART APB --------------------------------------------------------------- |
|
70 | -- UART APB --------------------------------------------------------------- | |
68 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
|
71 | TAG2 : IN STD_ULOGIC; -- UART1 rx data | |
69 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
|
72 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data | |
70 | -- RAM -------------------------------------------------------------------- |
|
73 | -- RAM -------------------------------------------------------------------- | |
71 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
74 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); | |
72 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
73 |
|
76 | |||
74 | nSRAM_MBE : INOUT STD_LOGIC; -- new |
|
77 | nSRAM_MBE : INOUT STD_LOGIC; -- new | |
75 | nSRAM_E1 : OUT STD_LOGIC; -- new |
|
78 | nSRAM_E1 : OUT STD_LOGIC; -- new | |
76 | nSRAM_E2 : OUT STD_LOGIC; -- new |
|
79 | nSRAM_E2 : OUT STD_LOGIC; -- new | |
77 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new |
|
80 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new | |
78 | nSRAM_W : OUT STD_LOGIC; -- new |
|
81 | nSRAM_W : OUT STD_LOGIC; -- new | |
79 | nSRAM_G : OUT STD_LOGIC; -- new |
|
82 | nSRAM_G : OUT STD_LOGIC; -- new | |
80 | nSRAM_BUSY : IN STD_LOGIC; -- new |
|
83 | nSRAM_BUSY : IN STD_LOGIC; -- new | |
81 | -- SPW -------------------------------------------------------------------- |
|
84 | -- SPW -------------------------------------------------------------------- | |
82 | spw1_en : OUT STD_LOGIC; -- new |
|
85 | spw1_en : OUT STD_LOGIC; -- new | |
83 | spw1_din : IN STD_LOGIC; |
|
86 | spw1_din : IN STD_LOGIC; | |
84 | spw1_sin : IN STD_LOGIC; |
|
87 | spw1_sin : IN STD_LOGIC; | |
85 | spw1_dout : OUT STD_LOGIC; |
|
88 | spw1_dout : OUT STD_LOGIC; | |
86 | spw1_sout : OUT STD_LOGIC; |
|
89 | spw1_sout : OUT STD_LOGIC; | |
87 | spw2_en : OUT STD_LOGIC; -- new |
|
90 | spw2_en : OUT STD_LOGIC; -- new | |
88 | spw2_din : IN STD_LOGIC; |
|
91 | spw2_din : IN STD_LOGIC; | |
89 | spw2_sin : IN STD_LOGIC; |
|
92 | spw2_sin : IN STD_LOGIC; | |
90 | spw2_dout : OUT STD_LOGIC; |
|
93 | spw2_dout : OUT STD_LOGIC; | |
91 | spw2_sout : OUT STD_LOGIC; |
|
94 | spw2_sout : OUT STD_LOGIC; | |
92 | -- ADC -------------------------------------------------------------------- |
|
95 | -- ADC -------------------------------------------------------------------- | |
93 | bias_fail_sw : OUT STD_LOGIC; |
|
96 | bias_fail_sw : OUT STD_LOGIC; | |
94 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
97 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
95 | ADC_smpclk : OUT STD_LOGIC; |
|
98 | ADC_smpclk : OUT STD_LOGIC; | |
96 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
99 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
97 | -- DAC -------------------------------------------------------------------- |
|
100 | -- DAC -------------------------------------------------------------------- | |
98 | DAC_SDO : OUT STD_LOGIC; |
|
101 | DAC_SDO : OUT STD_LOGIC; | |
99 | DAC_SCK : OUT STD_LOGIC; |
|
102 | DAC_SCK : OUT STD_LOGIC; | |
100 | DAC_SYNC : OUT STD_LOGIC; |
|
103 | DAC_SYNC : OUT STD_LOGIC; | |
101 | DAC_CAL_EN : OUT STD_LOGIC; |
|
104 | DAC_CAL_EN : OUT STD_LOGIC; | |
102 | -- HK --------------------------------------------------------------------- |
|
105 | -- HK --------------------------------------------------------------------- | |
103 | HK_smpclk : OUT STD_LOGIC; |
|
106 | HK_smpclk : OUT STD_LOGIC; | |
104 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
|
107 | ADC_OEB_bar_HK : OUT STD_LOGIC; | |
105 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
108 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
106 | --------------------------------------------------------------------------- |
|
109 | --------------------------------------------------------------------------- | |
107 | TAG8 : OUT STD_LOGIC |
|
110 | TAG8 : OUT STD_LOGIC | |
108 | ); |
|
111 | ); | |
109 |
|
112 | |||
110 | END LFR_EQM; |
|
113 | END LFR_EQM; | |
111 |
|
114 | |||
112 |
|
115 | |||
113 | ARCHITECTURE beh OF LFR_EQM IS |
|
116 | ARCHITECTURE beh OF LFR_EQM IS | |
114 |
|
117 | |||
115 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
118 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
116 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
119 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
117 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
118 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
122 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
120 |
|
123 | |||
121 | -- CONSTANTS |
|
124 | -- CONSTANTS | |
122 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
125 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
123 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
126 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
124 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
127 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
125 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
128 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
126 |
|
129 | |||
127 | SIGNAL apbi_ext : apb_slv_in_type; |
|
130 | SIGNAL apbi_ext : apb_slv_in_type; | |
128 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
131 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
129 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
132 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
130 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
133 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
131 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
134 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
132 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
135 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
133 |
|
136 | |||
134 | -- Spacewire signals |
|
137 | -- Spacewire signals | |
135 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
138 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
136 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
139 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
137 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
140 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
138 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
141 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
139 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
142 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
140 | SIGNAL spw_clk : STD_LOGIC; |
|
143 | SIGNAL spw_clk : STD_LOGIC; | |
141 | SIGNAL swni : grspw_in_type; |
|
144 | SIGNAL swni : grspw_in_type; | |
142 | SIGNAL swno : grspw_out_type; |
|
145 | SIGNAL swno : grspw_out_type; | |
143 |
|
146 | |||
144 | --GPIO |
|
147 | --GPIO | |
145 | SIGNAL gpioi : gpio_in_type; |
|
148 | SIGNAL gpioi : gpio_in_type; | |
146 | SIGNAL gpioo : gpio_out_type; |
|
149 | SIGNAL gpioo : gpio_out_type; | |
147 |
|
150 | |||
148 | -- AD Converter ADS7886 |
|
151 | -- AD Converter ADS7886 | |
149 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
|
152 | SIGNAL sample : Samples14v(8 DOWNTO 0); | |
150 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
|
153 | SIGNAL sample_s : Samples(8 DOWNTO 0); | |
151 | SIGNAL sample_val : STD_LOGIC; |
|
154 | SIGNAL sample_val : STD_LOGIC; | |
152 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
|
155 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); | |
153 |
|
156 | |||
154 | ----------------------------------------------------------------------------- |
|
157 | ----------------------------------------------------------------------------- | |
155 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
158 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
156 |
|
159 | |||
157 | ----------------------------------------------------------------------------- |
|
160 | ----------------------------------------------------------------------------- | |
158 | SIGNAL rstn_25 : STD_LOGIC; |
|
161 | SIGNAL rstn_25 : STD_LOGIC; | |
159 | SIGNAL rstn_24 : STD_LOGIC; |
|
162 | SIGNAL rstn_24 : STD_LOGIC; | |
160 |
|
163 | |||
161 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
|
164 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
162 | SIGNAL LFR_rstn : STD_LOGIC; |
|
165 | SIGNAL LFR_rstn : STD_LOGIC; | |
163 |
|
166 | |||
164 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
|
167 | SIGNAL ADC_smpclk_s : STD_LOGIC; | |
165 |
|
168 | |||
166 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
169 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
167 |
|
170 | |||
168 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; |
|
171 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; | |
169 | SIGNAL clk_25_int : STD_LOGIC := '0'; |
|
172 | SIGNAL clk_25_int : STD_LOGIC := '0'; | |
170 |
|
173 | |||
171 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; |
|
174 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; | |
172 |
|
175 | |||
173 | SIGNAL rstn_50 : STD_LOGIC; |
|
176 | SIGNAL rstn_50 : STD_LOGIC; | |
174 | SIGNAL clk_lock : STD_LOGIC; |
|
177 | SIGNAL clk_lock : STD_LOGIC; | |
175 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
178 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
176 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; |
|
179 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; | |
177 | BEGIN -- beh |
|
180 | BEGIN -- beh | |
178 |
|
181 | |||
179 | ----------------------------------------------------------------------------- |
|
182 | ----------------------------------------------------------------------------- | |
180 | -- CLK_LOCK |
|
183 | -- CLK_LOCK | |
181 | ----------------------------------------------------------------------------- |
|
184 | ----------------------------------------------------------------------------- | |
182 |
rst_gen_global : rstgen PORT MAP (reset, clk |
|
185 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); | |
183 |
|
186 | |||
184 | PROCESS (clk50MHz_int, rstn_50) |
|
187 | PROCESS (clk50MHz_int, rstn_50) | |
185 | BEGIN -- PROCESS |
|
188 | BEGIN -- PROCESS | |
186 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
189 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
187 | clk_lock <= '0'; |
|
190 | clk_lock <= '0'; | |
188 | clk_busy_counter <= (OTHERS => '0'); |
|
191 | clk_busy_counter <= (OTHERS => '0'); | |
189 | nSRAM_BUSY_reg <= '0'; |
|
192 | nSRAM_BUSY_reg <= '0'; | |
190 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge |
|
193 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge | |
191 | nSRAM_BUSY_reg <= nSRAM_BUSY; |
|
194 | nSRAM_BUSY_reg <= nSRAM_BUSY; | |
192 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN |
|
195 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN | |
193 | IF clk_busy_counter = "1111" THEN |
|
196 | IF clk_busy_counter = "1111" THEN | |
194 | clk_lock = '1'; |
|
197 | clk_lock <= '1'; | |
195 | ELSE |
|
198 | ELSE | |
196 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); |
|
199 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); | |
197 | END IF; |
|
200 | END IF; | |
198 | END IF; |
|
201 | END IF; | |
199 | END IF; |
|
202 | END IF; | |
200 | END PROCESS; |
|
203 | END PROCESS; | |
201 |
|
204 | |||
202 | ----------------------------------------------------------------------------- |
|
205 | ----------------------------------------------------------------------------- | |
203 | -- CLK |
|
206 | -- CLK | |
204 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
205 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); |
|
208 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); | |
206 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); |
|
209 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); | |
207 |
|
210 | |||
208 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); |
|
211 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); | |
209 | clk50MHz_int <= clk50MHz; |
|
212 | clk50MHz_int <= clk50MHz; | |
210 |
|
213 | |||
211 | PROCESS(clk50MHz_int) |
|
214 | PROCESS(clk50MHz_int) | |
212 | BEGIN |
|
215 | BEGIN | |
213 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN |
|
216 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN | |
214 | --clk_25_int <= NOT clk_25_int; |
|
217 | --clk_25_int <= NOT clk_25_int; | |
215 | clk_25 <= NOT clk_25; |
|
218 | clk_25 <= NOT clk_25; | |
216 | END IF; |
|
219 | END IF; | |
217 | END PROCESS; |
|
220 | END PROCESS; | |
218 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); |
|
221 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); | |
219 |
|
222 | |||
220 | PROCESS(clk49_152MHz) |
|
223 | PROCESS(clk49_152MHz) | |
221 | BEGIN |
|
224 | BEGIN | |
222 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
|
225 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN | |
223 | clk_24 <= NOT clk_24; |
|
226 | clk_24 <= NOT clk_24; | |
224 | END IF; |
|
227 | END IF; | |
225 | END PROCESS; |
|
228 | END PROCESS; | |
226 |
|
229 | |||
227 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
228 | -- |
|
231 | -- | |
229 | leon3_soc_1 : leon3_soc |
|
232 | leon3_soc_1 : leon3_soc | |
230 | GENERIC MAP ( |
|
233 | GENERIC MAP ( | |
231 |
fabtech => |
|
234 | fabtech => tech_leon, | |
232 |
memtech => |
|
235 | memtech => tech_leon, | |
233 | padtech => inferred, |
|
236 | padtech => inferred, | |
234 | clktech => inferred, |
|
237 | clktech => inferred, | |
235 | disas => 0, |
|
238 | disas => 0, | |
236 | dbguart => 0, |
|
239 | dbguart => 0, | |
237 | pclow => 2, |
|
240 | pclow => 2, | |
238 | clk_freq => 25000, |
|
241 | clk_freq => 25000, | |
239 | IS_RADHARD => 0, |
|
242 | IS_RADHARD => 0, | |
240 | NB_CPU => 1, |
|
243 | NB_CPU => 1, | |
241 | ENABLE_FPU => 1, |
|
244 | ENABLE_FPU => 1, | |
242 | FPU_NETLIST => 0, |
|
245 | FPU_NETLIST => 0, | |
243 | ENABLE_DSU => 1, |
|
246 | ENABLE_DSU => 1, | |
244 | ENABLE_AHB_UART => 1, |
|
247 | ENABLE_AHB_UART => 1, | |
245 | ENABLE_APB_UART => 1, |
|
248 | ENABLE_APB_UART => 1, | |
246 | ENABLE_IRQMP => 1, |
|
249 | ENABLE_IRQMP => 1, | |
247 | ENABLE_GPT => 1, |
|
250 | ENABLE_GPT => 1, | |
248 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
251 | NB_AHB_MASTER => NB_AHB_MASTER, | |
249 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
252 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
250 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
253 | NB_APB_SLAVE => NB_APB_SLAVE, | |
251 | ADDRESS_SIZE => 19, |
|
254 | ADDRESS_SIZE => 19, | |
252 | USES_IAP_MEMCTRLR => 1, |
|
255 | USES_IAP_MEMCTRLR => 1, | |
253 | BYPASS_EDAC_MEMCTRLR => '0', |
|
256 | BYPASS_EDAC_MEMCTRLR => '0', | |
254 | SRBANKSZ => 8) |
|
257 | SRBANKSZ => 8) | |
255 | PORT MAP ( |
|
258 | PORT MAP ( | |
256 | clk => clk_25, |
|
259 | clk => clk_25, | |
257 | reset => rstn_25, |
|
260 | reset => rstn_25, | |
258 | errorn => OPEN, |
|
261 | errorn => OPEN, | |
259 |
|
262 | |||
260 | ahbrxd => TAG1, |
|
263 | ahbrxd => TAG1, | |
261 | ahbtxd => TAG3, |
|
264 | ahbtxd => TAG3, | |
262 | urxd1 => TAG2, |
|
265 | urxd1 => TAG2, | |
263 | utxd1 => TAG4, |
|
266 | utxd1 => TAG4, | |
264 |
|
267 | |||
265 | address => address, |
|
268 | address => address, | |
266 | data => data, |
|
269 | data => data, | |
267 | nSRAM_BE0 => OPEN, |
|
270 | nSRAM_BE0 => OPEN, | |
268 | nSRAM_BE1 => OPEN, |
|
271 | nSRAM_BE1 => OPEN, | |
269 | nSRAM_BE2 => OPEN, |
|
272 | nSRAM_BE2 => OPEN, | |
270 | nSRAM_BE3 => OPEN, |
|
273 | nSRAM_BE3 => OPEN, | |
271 | nSRAM_WE => nSRAM_W, |
|
274 | nSRAM_WE => nSRAM_W, | |
272 | nSRAM_CE => nSRAM_CE, |
|
275 | nSRAM_CE => nSRAM_CE, | |
273 | nSRAM_OE => nSRAM_G, |
|
276 | nSRAM_OE => nSRAM_G, | |
274 | nSRAM_READY => nSRAM_BUSY, |
|
277 | nSRAM_READY => nSRAM_BUSY, | |
275 | SRAM_MBE => nSRAM_MBE, |
|
278 | SRAM_MBE => nSRAM_MBE, | |
276 |
|
279 | |||
277 | apbi_ext => apbi_ext, |
|
280 | apbi_ext => apbi_ext, | |
278 | apbo_ext => apbo_ext, |
|
281 | apbo_ext => apbo_ext, | |
279 | ahbi_s_ext => ahbi_s_ext, |
|
282 | ahbi_s_ext => ahbi_s_ext, | |
280 | ahbo_s_ext => ahbo_s_ext, |
|
283 | ahbo_s_ext => ahbo_s_ext, | |
281 | ahbi_m_ext => ahbi_m_ext, |
|
284 | ahbi_m_ext => ahbi_m_ext, | |
282 | ahbo_m_ext => ahbo_m_ext); |
|
285 | ahbo_m_ext => ahbo_m_ext); | |
283 |
|
286 | |||
284 |
|
287 | |||
285 | nSRAM_E1 <= nSRAM_CE(0); |
|
288 | nSRAM_E1 <= nSRAM_CE(0); | |
286 | nSRAM_E2 <= nSRAM_CE(1); |
|
289 | nSRAM_E2 <= nSRAM_CE(1); | |
287 |
|
290 | |||
288 | ------------------------------------------------------------------------------- |
|
291 | ------------------------------------------------------------------------------- | |
289 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
292 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
290 | ------------------------------------------------------------------------------- |
|
293 | ------------------------------------------------------------------------------- | |
291 | apb_lfr_management_1 : apb_lfr_management |
|
294 | apb_lfr_management_1 : apb_lfr_management | |
292 | GENERIC MAP ( |
|
295 | GENERIC MAP ( | |
293 |
tech => |
|
296 | tech => tech, | |
294 | pindex => 6, |
|
297 | pindex => 6, | |
295 | paddr => 6, |
|
298 | paddr => 6, | |
296 | pmask => 16#fff#, |
|
299 | pmask => 16#fff#, | |
297 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
300 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
298 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
301 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
299 | PORT MAP ( |
|
302 | PORT MAP ( | |
300 | clk25MHz => clk_25, |
|
303 | clk25MHz => clk_25, | |
301 | resetn_25MHz => rstn_25, -- TODO |
|
304 | resetn_25MHz => rstn_25, -- TODO | |
302 | --clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
305 | --clk24_576MHz => clk_24, -- 49.152MHz/2 | |
303 | --resetn_24_576MHz => rstn_24, -- TODO |
|
306 | --resetn_24_576MHz => rstn_24, -- TODO | |
304 |
|
307 | |||
305 | grspw_tick => swno.tickout, |
|
308 | grspw_tick => swno.tickout, | |
306 | apbi => apbi_ext, |
|
309 | apbi => apbi_ext, | |
307 | apbo => apbo_ext(6), |
|
310 | apbo => apbo_ext(6), | |
308 |
|
311 | |||
309 | HK_sample => sample_s(8), |
|
312 | HK_sample => sample_s(8), | |
310 | HK_val => sample_val, |
|
313 | HK_val => sample_val, | |
311 | HK_sel => HK_SEL, |
|
314 | HK_sel => HK_SEL, | |
312 |
|
315 | |||
313 | DAC_SDO => DAC_SDO, |
|
316 | DAC_SDO => DAC_SDO, | |
314 | DAC_SCK => DAC_SCK, |
|
317 | DAC_SCK => DAC_SCK, | |
315 | DAC_SYNC => DAC_SYNC, |
|
318 | DAC_SYNC => DAC_SYNC, | |
316 | DAC_CAL_EN => DAC_CAL_EN, |
|
319 | DAC_CAL_EN => DAC_CAL_EN, | |
317 |
|
320 | |||
318 | coarse_time => coarse_time, |
|
321 | coarse_time => coarse_time, | |
319 | fine_time => fine_time, |
|
322 | fine_time => fine_time, | |
320 | LFR_soft_rstn => LFR_soft_rstn |
|
323 | LFR_soft_rstn => LFR_soft_rstn | |
321 | ); |
|
324 | ); | |
322 |
|
325 | |||
323 | ----------------------------------------------------------------------- |
|
326 | ----------------------------------------------------------------------- | |
324 | --- SpaceWire -------------------------------------------------------- |
|
327 | --- SpaceWire -------------------------------------------------------- | |
325 | ----------------------------------------------------------------------- |
|
328 | ----------------------------------------------------------------------- | |
326 |
|
329 | |||
327 | ------------------------------------------------------------------------------ |
|
330 | ------------------------------------------------------------------------------ | |
328 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ |
|
331 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ | |
329 | ------------------------------------------------------------------------------ |
|
332 | ------------------------------------------------------------------------------ | |
330 | spw1_en <= '1'; |
|
333 | spw1_en <= '1'; | |
331 | spw2_en <= '1'; |
|
334 | spw2_en <= '1'; | |
332 | ------------------------------------------------------------------------------ |
|
335 | ------------------------------------------------------------------------------ | |
333 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ |
|
336 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ | |
334 | ------------------------------------------------------------------------------ |
|
337 | ------------------------------------------------------------------------------ | |
335 |
|
338 | |||
336 | --spw_clk <= clk50MHz; |
|
339 | --spw_clk <= clk50MHz; | |
337 | --spw_rxtxclk <= spw_clk; |
|
340 | --spw_rxtxclk <= spw_clk; | |
338 | --spw_rxclkn <= NOT spw_rxtxclk; |
|
341 | --spw_rxclkn <= NOT spw_rxtxclk; | |
339 |
|
342 | |||
340 | -- PADS for SPW1 |
|
343 | -- PADS for SPW1 | |
341 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
344 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
342 | PORT MAP (spw1_din, dtmp(0)); |
|
345 | PORT MAP (spw1_din, dtmp(0)); | |
343 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
346 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
344 | PORT MAP (spw1_sin, stmp(0)); |
|
347 | PORT MAP (spw1_sin, stmp(0)); | |
345 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
348 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
346 | PORT MAP (spw1_dout, swno.d(0)); |
|
349 | PORT MAP (spw1_dout, swno.d(0)); | |
347 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
350 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
348 | PORT MAP (spw1_sout, swno.s(0)); |
|
351 | PORT MAP (spw1_sout, swno.s(0)); | |
349 | -- PADS FOR SPW2 |
|
352 | -- PADS FOR SPW2 | |
350 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
353 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
351 | PORT MAP (spw2_din, dtmp(1)); |
|
354 | PORT MAP (spw2_din, dtmp(1)); | |
352 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
355 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
353 | PORT MAP (spw2_sin, stmp(1)); |
|
356 | PORT MAP (spw2_sin, stmp(1)); | |
354 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
357 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
355 | PORT MAP (spw2_dout, swno.d(1)); |
|
358 | PORT MAP (spw2_dout, swno.d(1)); | |
356 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
359 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
357 | PORT MAP (spw2_sout, swno.s(1)); |
|
360 | PORT MAP (spw2_sout, swno.s(1)); | |
358 |
|
361 | |||
359 | -- GRSPW PHY |
|
362 | -- GRSPW PHY | |
360 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
363 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
361 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
364 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
362 | spw_phy0 : grspw_phy |
|
365 | spw_phy0 : grspw_phy | |
363 | GENERIC MAP( |
|
366 | GENERIC MAP( | |
364 |
tech => |
|
367 | tech => tech_leon, | |
365 | rxclkbuftype => 1, |
|
368 | rxclkbuftype => 1, | |
366 | scantest => 0) |
|
369 | scantest => 0) | |
367 | PORT MAP( |
|
370 | PORT MAP( | |
368 | rxrst => swno.rxrst, |
|
371 | rxrst => swno.rxrst, | |
369 | di => dtmp(j), |
|
372 | di => dtmp(j), | |
370 | si => stmp(j), |
|
373 | si => stmp(j), | |
371 | rxclko => spw_rxclk(j), |
|
374 | rxclko => spw_rxclk(j), | |
372 | do => swni.d(j), |
|
375 | do => swni.d(j), | |
373 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
376 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
374 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
377 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
375 | END GENERATE spw_inputloop; |
|
378 | END GENERATE spw_inputloop; | |
376 |
|
379 | |||
377 | -- SPW core |
|
380 | -- SPW core | |
378 | sw0 : grspwm GENERIC MAP( |
|
381 | sw0 : grspwm GENERIC MAP( | |
379 |
tech => |
|
382 | tech => tech_leon, | |
380 | hindex => 1, |
|
383 | hindex => 1, | |
381 | pindex => 5, |
|
384 | pindex => 5, | |
382 | paddr => 5, |
|
385 | paddr => 5, | |
383 | pirq => 11, |
|
386 | pirq => 11, | |
384 | sysfreq => 25000, -- CPU_FREQ |
|
387 | sysfreq => 25000, -- CPU_FREQ | |
385 | rmap => 1, |
|
388 | rmap => 1, | |
386 | rmapcrc => 1, |
|
389 | rmapcrc => 1, | |
387 | fifosize1 => 16, |
|
390 | fifosize1 => 16, | |
388 | fifosize2 => 16, |
|
391 | fifosize2 => 16, | |
389 | rxclkbuftype => 1, |
|
392 | rxclkbuftype => 1, | |
390 | rxunaligned => 0, |
|
393 | rxunaligned => 0, | |
391 | rmapbufs => 4, |
|
394 | rmapbufs => 4, | |
392 | ft => 0, |
|
395 | ft => 0, | |
393 | netlist => 0, |
|
396 | netlist => 0, | |
394 | ports => 2, |
|
397 | ports => 2, | |
395 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
398 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
396 |
memtech => |
|
399 | memtech => tech_leon, | |
397 | destkey => 2, |
|
400 | destkey => 2, | |
398 | spwcore => 1 |
|
401 | spwcore => 1 | |
399 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
402 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
400 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
403 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
401 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
404 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
402 | ) |
|
405 | ) | |
403 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
406 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
404 | spw_rxclk(1), |
|
407 | spw_rxclk(1), | |
405 | clk50MHz_int, |
|
408 | clk50MHz_int, | |
406 | clk50MHz_int, |
|
409 | clk50MHz_int, | |
407 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, |
|
410 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, | |
408 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
411 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
409 | swni, swno); |
|
412 | swni, swno); | |
410 |
|
413 | |||
411 | swni.tickin <= '0'; |
|
414 | swni.tickin <= '0'; | |
412 | swni.rmapen <= '1'; |
|
415 | swni.rmapen <= '1'; | |
413 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
|
416 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz | |
414 | swni.tickinraw <= '0'; |
|
417 | swni.tickinraw <= '0'; | |
415 | swni.timein <= (OTHERS => '0'); |
|
418 | swni.timein <= (OTHERS => '0'); | |
416 | swni.dcrstval <= (OTHERS => '0'); |
|
419 | swni.dcrstval <= (OTHERS => '0'); | |
417 | swni.timerrstval <= (OTHERS => '0'); |
|
420 | swni.timerrstval <= (OTHERS => '0'); | |
418 |
|
421 | |||
419 | ------------------------------------------------------------------------------- |
|
422 | ------------------------------------------------------------------------------- | |
420 | -- LFR ------------------------------------------------------------------------ |
|
423 | -- LFR ------------------------------------------------------------------------ | |
421 | ------------------------------------------------------------------------------- |
|
424 | ------------------------------------------------------------------------------- | |
422 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
425 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
423 |
|
426 | |||
424 | lpp_lfr_1 : lpp_lfr |
|
427 | lpp_lfr_1 : lpp_lfr | |
425 | GENERIC MAP ( |
|
428 | GENERIC MAP ( | |
426 | Mem_use => Mem_use, |
|
429 | Mem_use => Mem_use, | |
427 | nb_data_by_buffer_size => 32, |
|
430 | nb_data_by_buffer_size => 32, | |
428 | --nb_word_by_buffer_size => 30, |
|
431 | --nb_word_by_buffer_size => 30, | |
429 | nb_snapshot_param_size => 32, |
|
432 | nb_snapshot_param_size => 32, | |
430 | delta_vector_size => 32, |
|
433 | delta_vector_size => 32, | |
431 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
434 | delta_vector_size_f0_2 => 7, -- log2(96) | |
432 | pindex => 15, |
|
435 | pindex => 15, | |
433 | paddr => 15, |
|
436 | paddr => 15, | |
434 | pmask => 16#fff#, |
|
437 | pmask => 16#fff#, | |
435 | pirq_ms => 6, |
|
438 | pirq_ms => 6, | |
436 | pirq_wfp => 14, |
|
439 | pirq_wfp => 14, | |
437 | hindex => 2, |
|
440 | hindex => 2, | |
438 | top_lfr_version => X"020147") -- aa.bb.cc version |
|
441 | top_lfr_version => X"020147") -- aa.bb.cc version | |
439 | -- AA : BOARD NUMBER |
|
442 | -- AA : BOARD NUMBER | |
440 | -- 0 => MINI_LFR |
|
443 | -- 0 => MINI_LFR | |
441 | -- 1 => EM |
|
444 | -- 1 => EM | |
442 | -- 2 => EQM (with A3PE3000) |
|
445 | -- 2 => EQM (with A3PE3000) | |
443 | PORT MAP ( |
|
446 | PORT MAP ( | |
444 | clk => clk_25, |
|
447 | clk => clk_25, | |
445 | rstn => LFR_rstn, |
|
448 | rstn => LFR_rstn, | |
446 | sample_B => sample_s(2 DOWNTO 0), |
|
449 | sample_B => sample_s(2 DOWNTO 0), | |
447 | sample_E => sample_s(7 DOWNTO 3), |
|
450 | sample_E => sample_s(7 DOWNTO 3), | |
448 | sample_val => sample_val, |
|
451 | sample_val => sample_val, | |
449 | apbi => apbi_ext, |
|
452 | apbi => apbi_ext, | |
450 | apbo => apbo_ext(15), |
|
453 | apbo => apbo_ext(15), | |
451 | ahbi => ahbi_m_ext, |
|
454 | ahbi => ahbi_m_ext, | |
452 | ahbo => ahbo_m_ext(2), |
|
455 | ahbo => ahbo_m_ext(2), | |
453 | coarse_time => coarse_time, |
|
456 | coarse_time => coarse_time, | |
454 | fine_time => fine_time, |
|
457 | fine_time => fine_time, | |
455 | data_shaping_BW => bias_fail_sw, |
|
458 | data_shaping_BW => bias_fail_sw, | |
456 | debug_vector => OPEN, |
|
459 | debug_vector => OPEN, | |
457 | debug_vector_ms => OPEN); --, |
|
460 | debug_vector_ms => OPEN); --, | |
458 | --observation_vector_0 => OPEN, |
|
461 | --observation_vector_0 => OPEN, | |
459 | --observation_vector_1 => OPEN, |
|
462 | --observation_vector_1 => OPEN, | |
460 | --observation_reg => observation_reg); |
|
463 | --observation_reg => observation_reg); | |
461 |
|
464 | |||
462 |
|
465 | |||
463 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
466 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
464 | sample_s(I) <= sample(I) & '0' & '0'; |
|
467 | sample_s(I) <= sample(I) & '0' & '0'; | |
465 | END GENERATE all_sample; |
|
468 | END GENERATE all_sample; | |
466 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
469 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); | |
467 |
|
470 | |||
468 | ----------------------------------------------------------------------------- |
|
471 | ----------------------------------------------------------------------------- | |
469 | -- |
|
472 | -- | |
470 | ----------------------------------------------------------------------------- |
|
473 | ----------------------------------------------------------------------------- | |
471 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
474 | USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE | |
472 | GENERIC MAP ( |
|
475 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
473 | ChanelCount => 9, |
|
476 | GENERIC MAP ( | |
474 | ncycle_cnv_high => 13, |
|
477 | ChanelCount => 9, | |
475 |
ncycle_cnv |
|
478 | ncycle_cnv_high => 13, | |
476 | FILTER_ENABLED => 16#FF#) |
|
479 | ncycle_cnv => 25, | |
477 | PORT MAP ( |
|
480 | FILTER_ENABLED => 16#FF#) | |
478 | cnv_clk => clk_24, |
|
481 | PORT MAP ( | |
479 |
|
|
482 | cnv_clk => clk_24, | |
480 | cnv => ADC_smpclk_s, |
|
483 | cnv_rstn => rstn_24, | |
481 |
|
|
484 | cnv => ADC_smpclk_s, | |
482 |
|
|
485 | clk => clk_25, | |
483 | ADC_data => ADC_data, |
|
486 | rstn => rstn_25, | |
484 |
|
|
487 | ADC_data => ADC_data, | |
485 | sample => sample, |
|
488 | ADC_nOE => ADC_OEB_bar_CH_s, | |
486 |
sample |
|
489 | sample => sample, | |
|
490 | sample_val => sample_val); | |||
|
491 | ||||
|
492 | END GENERATE USE_ADCDRIVER_true; | |||
|
493 | ||||
|
494 | USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE | |||
|
495 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |||
|
496 | GENERIC MAP ( | |||
|
497 | ChanelCount => 9, | |||
|
498 | ncycle_cnv_high => 13, | |||
|
499 | ncycle_cnv => 25, | |||
|
500 | FILTER_ENABLED => 16#FF#) | |||
|
501 | PORT MAP ( | |||
|
502 | cnv_clk => clk_24, | |||
|
503 | cnv_rstn => rstn_24, | |||
|
504 | cnv => ADC_smpclk_s, | |||
|
505 | clk => clk_25, | |||
|
506 | rstn => rstn_25, | |||
|
507 | ADC_data => ADC_data, | |||
|
508 | ADC_nOE => OPEN, | |||
|
509 | sample => OPEN, | |||
|
510 | sample_val => sample_val); | |||
|
511 | ||||
|
512 | ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); | |||
487 |
|
513 | |||
|
514 | all_sample: FOR I IN 8 DOWNTO 0 GENERATE | |||
|
515 | ramp_generator_1: ramp_generator | |||
|
516 | GENERIC MAP ( | |||
|
517 | DATA_SIZE => 14, | |||
|
518 | VALUE_UNSIGNED_INIT => 2**I, | |||
|
519 | VALUE_UNSIGNED_INCR => 0, | |||
|
520 | VALUE_UNSIGNED_MASK => 16#3FFF#) | |||
|
521 | PORT MAP ( | |||
|
522 | clk => clk_25, | |||
|
523 | rstn => rstn_25, | |||
|
524 | new_data => sample_val, | |||
|
525 | output_data => sample(I) ); | |||
|
526 | END GENERATE all_sample; | |||
|
527 | ||||
|
528 | ||||
|
529 | END GENERATE USE_ADCDRIVER_false; | |||
|
530 | ||||
|
531 | ||||
|
532 | ||||
|
533 | ||||
488 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
534 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); | |
489 |
|
535 | |||
490 | ADC_smpclk <= ADC_smpclk_s; |
|
536 | ADC_smpclk <= ADC_smpclk_s; | |
491 | HK_smpclk <= ADC_smpclk_s; |
|
537 | HK_smpclk <= ADC_smpclk_s; | |
492 |
|
538 | |||
493 | TAG8 <= nSRAM_BUSY; |
|
539 | TAG8 <= nSRAM_BUSY; | |
494 |
|
540 | |||
495 | ----------------------------------------------------------------------------- |
|
541 | ----------------------------------------------------------------------------- | |
496 | -- HK |
|
542 | -- HK | |
497 | ----------------------------------------------------------------------------- |
|
543 | ----------------------------------------------------------------------------- | |
498 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
544 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); | |
499 |
|
545 | |||
500 | ----------------------------------------------------------------------------- |
|
546 | ----------------------------------------------------------------------------- | |
501 | -- |
|
547 | -- | |
502 | ----------------------------------------------------------------------------- |
|
548 | ----------------------------------------------------------------------------- | |
503 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE |
|
549 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE | |
504 | lpp_bootloader_1: lpp_bootloader |
|
550 | lpp_bootloader_1: lpp_bootloader | |
505 | GENERIC MAP ( |
|
551 | GENERIC MAP ( | |
506 | pindex => 13, |
|
552 | pindex => 13, | |
507 | paddr => 13, |
|
553 | paddr => 13, | |
508 | pmask => 16#fff#, |
|
554 | pmask => 16#fff#, | |
509 | hindex => 3, |
|
555 | hindex => 3, | |
510 | haddr => 0, |
|
556 | haddr => 0, | |
511 | hmask => 16#fff#) |
|
557 | hmask => 16#fff#) | |
512 | PORT MAP ( |
|
558 | PORT MAP ( | |
513 | HCLK => clk_25, |
|
559 | HCLK => clk_25, | |
514 | HRESETn => rstn_25, |
|
560 | HRESETn => rstn_25, | |
515 | apbi => apbi_ext, |
|
561 | apbi => apbi_ext, | |
516 | apbo => apbo_ext(13), |
|
562 | apbo => apbo_ext(13), | |
517 | ahbsi => ahbi_s_ext, |
|
563 | ahbsi => ahbi_s_ext, | |
518 | ahbso => ahbo_s_ext(3)); |
|
564 | ahbso => ahbo_s_ext(3)); | |
519 | END GENERATE inst_bootloader; |
|
565 | END GENERATE inst_bootloader; | |
520 | END beh; |
|
566 | END beh; |
@@ -1,54 +1,54 | |||||
1 | #GRLIB=../.. |
|
1 | #GRLIB=../.. | |
2 | VHDLIB=../.. |
|
2 | VHDLIB=../.. | |
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=LFR_EQM |
|
5 | TOP=LFR_EQM | |
6 | BOARD=LFR-EQM |
|
6 | BOARD=LFR-EQM | |
7 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc |
|
7 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc | |
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf |
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf |
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |
11 | EFFORT=high |
|
11 | EFFORT=high | |
12 | XSTOPT= |
|
12 | XSTOPT= | |
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
15 | #VHDLSYNFILES=config.vhd leon3mp.vhd |
|
15 | #VHDLSYNFILES=config.vhd leon3mp.vhd | |
16 | VHDLSYNFILES=LFR-EQM.vhd |
|
16 | VHDLSYNFILES=LFR-EQM.vhd | |
17 | VHDLSIMFILES=testbench.vhd |
|
17 | VHDLSIMFILES=testbench.vhd | |
18 | #SIMTOP=testbench |
|
18 | #SIMTOP=testbench | |
19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc |
|
19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000_NoADC.pdc | |
20 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc |
|
20 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc | |
21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc |
|
21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc | |
22 |
|
22 | |||
23 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
|
23 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | |
24 | CLEAN=soft-clean |
|
24 | CLEAN=soft-clean | |
25 |
|
25 | |||
26 | TECHLIBS = proasic3e |
|
26 | TECHLIBS = proasic3e | |
27 |
|
27 | |||
28 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
28 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |
29 | tmtc openchip hynix ihp gleichmann micron usbhc |
|
29 | tmtc openchip hynix ihp gleichmann micron usbhc | |
30 |
|
30 | |||
31 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
|
31 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |
32 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
|
32 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |
33 | ./amba_lcd_16x2_ctrlr \ |
|
33 | ./amba_lcd_16x2_ctrlr \ | |
34 | ./general_purpose/lpp_AMR \ |
|
34 | ./general_purpose/lpp_AMR \ | |
35 | ./general_purpose/lpp_balise \ |
|
35 | ./general_purpose/lpp_balise \ | |
36 | ./general_purpose/lpp_delay \ |
|
36 | ./general_purpose/lpp_delay \ | |
37 | ./dsp/lpp_fft_rtax \ |
|
37 | ./dsp/lpp_fft_rtax \ | |
38 | ./lpp_uart \ |
|
38 | ./lpp_uart \ | |
39 | ./lpp_usb \ |
|
39 | ./lpp_usb \ | |
40 | ./lpp_sim/CY7C1061DV33 \ |
|
40 | ./lpp_sim/CY7C1061DV33 \ | |
41 |
|
41 | |||
42 | FILESKIP = i2cmst.vhd \ |
|
42 | FILESKIP = i2cmst.vhd \ | |
43 | APB_MULTI_DIODE.vhd \ |
|
43 | APB_MULTI_DIODE.vhd \ | |
44 | APB_MULTI_DIODE.vhd \ |
|
44 | APB_MULTI_DIODE.vhd \ | |
45 | Top_MatrixSpec.vhd \ |
|
45 | Top_MatrixSpec.vhd \ | |
46 | APB_FFT.vhd\ |
|
46 | APB_FFT.vhd\ | |
47 | CoreFFT_simu.vhd \ |
|
47 | CoreFFT_simu.vhd \ | |
48 | lpp_lfr_apbreg_simu.vhd |
|
48 | lpp_lfr_apbreg_simu.vhd | |
49 |
|
49 | |||
50 | include $(GRLIB)/bin/Makefile |
|
50 | include $(GRLIB)/bin/Makefile | |
51 | include $(GRLIB)/software/leon3/Makefile |
|
51 | include $(GRLIB)/software/leon3/Makefile | |
52 |
|
52 | |||
53 | ################## project specific targets ########################## |
|
53 | ################## project specific targets ########################## | |
54 |
|
54 |
@@ -1,657 +1,672 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 |
|
22 | |||
23 | LIBRARY IEEE; |
|
23 | LIBRARY IEEE; | |
24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
24 | USE IEEE.STD_LOGIC_1164.ALL; | |
25 | USE IEEE.NUMERIC_STD.ALL; |
|
25 | USE IEEE.NUMERIC_STD.ALL; | |
26 |
|
26 | |||
|
27 | LIBRARY techmap; | |||
|
28 | USE techmap.gencomp.ALL; | |||
27 |
|
29 | |||
28 | LIBRARY lpp; |
|
30 | LIBRARY lpp; | |
29 | USE lpp.lpp_sim_pkg.ALL; |
|
31 | USE lpp.lpp_sim_pkg.ALL; | |
30 | USE lpp.lpp_lfr_sim_pkg.ALL; |
|
32 | USE lpp.lpp_lfr_sim_pkg.ALL; | |
31 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
33 | USE lpp.lpp_lfr_apbreg_pkg.ALL; | |
32 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
34 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; | |
33 | USE lpp.iir_filter.ALL; |
|
35 | USE lpp.iir_filter.ALL; | |
34 | USE lpp.FILTERcfg.ALL; |
|
36 | USE lpp.FILTERcfg.ALL; | |
35 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
36 | USE lpp.lpp_waveform_pkg.ALL; |
|
38 | USE lpp.lpp_waveform_pkg.ALL; | |
37 | USE lpp.lpp_dma_pkg.ALL; |
|
39 | USE lpp.lpp_dma_pkg.ALL; | |
38 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
40 | USE lpp.lpp_top_lfr_pkg.ALL; | |
39 | USE lpp.lpp_lfr_pkg.ALL; |
|
41 | USE lpp.lpp_lfr_pkg.ALL; | |
40 | USE lpp.general_purpose.ALL; |
|
42 | USE lpp.general_purpose.ALL; | |
41 | --LIBRARY lpp; |
|
43 | --LIBRARY lpp; | |
42 | USE lpp.lpp_ad_conv.ALL; |
|
44 | USE lpp.lpp_ad_conv.ALL; | |
43 | --USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
45 | --USE lpp.lpp_lfr_management_apbreg_pkg.ALL; | |
44 | --USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
46 | --USE lpp.lpp_lfr_apbreg_pkg.ALL; | |
45 |
|
47 | |||
46 | --USE work.debug.ALL; |
|
48 | --USE work.debug.ALL; | |
47 |
|
49 | |||
48 | LIBRARY gaisler; |
|
50 | LIBRARY gaisler; | |
49 | USE gaisler.libdcom.ALL; |
|
51 | USE gaisler.libdcom.ALL; | |
50 | USE gaisler.sim.ALL; |
|
52 | USE gaisler.sim.ALL; | |
51 | USE gaisler.memctrl.ALL; |
|
53 | USE gaisler.memctrl.ALL; | |
52 | USE gaisler.leon3.ALL; |
|
54 | USE gaisler.leon3.ALL; | |
53 | USE gaisler.uart.ALL; |
|
55 | USE gaisler.uart.ALL; | |
54 | USE gaisler.misc.ALL; |
|
56 | USE gaisler.misc.ALL; | |
55 | USE gaisler.spacewire.ALL; |
|
57 | USE gaisler.spacewire.ALL; | |
56 |
|
58 | |||
57 | ENTITY TB IS |
|
59 | ENTITY TB IS | |
58 |
|
60 | |||
59 | END TB; |
|
61 | END TB; | |
60 |
|
62 | |||
61 | ARCHITECTURE beh OF TB IS |
|
63 | ARCHITECTURE beh OF TB IS | |
62 |
|
64 | |||
63 | CONSTANT USE_ESA_MEMCTRL : INTEGER := 0; |
|
65 | CONSTANT USE_ESA_MEMCTRL : INTEGER := 0; | |
64 |
|
66 | |||
65 | COMPONENT LFR_EQM |
|
67 | COMPONENT LFR_EQM | |
66 | GENERIC ( |
|
68 | GENERIC ( | |
67 | Mem_use : INTEGER; |
|
69 | Mem_use : INTEGER; | |
68 |
USE_BOOTLOADER : INTEGER |
|
70 | USE_BOOTLOADER : INTEGER; | |
|
71 | USE_ADCDRIVER : INTEGER; | |||
|
72 | tech : INTEGER; | |||
|
73 | tech_leon : INTEGER); | |||
69 | PORT ( |
|
74 | PORT ( | |
70 | clk50MHz : IN STD_ULOGIC; |
|
75 | clk50MHz : IN STD_ULOGIC; | |
71 | clk49_152MHz : IN STD_ULOGIC; |
|
76 | clk49_152MHz : IN STD_ULOGIC; | |
72 | reset : IN STD_ULOGIC; |
|
77 | reset : IN STD_ULOGIC; | |
73 | TAG1 : IN STD_ULOGIC; |
|
78 | TAG1 : IN STD_ULOGIC; | |
74 | TAG3 : OUT STD_ULOGIC; |
|
79 | TAG3 : OUT STD_ULOGIC; | |
75 | TAG2 : IN STD_ULOGIC; |
|
80 | TAG2 : IN STD_ULOGIC; | |
76 | TAG4 : OUT STD_ULOGIC; |
|
81 | TAG4 : OUT STD_ULOGIC; | |
77 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
82 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); | |
78 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
79 | nSRAM_MBE : INOUT STD_LOGIC; |
|
84 | nSRAM_MBE : INOUT STD_LOGIC; | |
80 | nSRAM_E1 : OUT STD_LOGIC; |
|
85 | nSRAM_E1 : OUT STD_LOGIC; | |
81 | nSRAM_E2 : OUT STD_LOGIC; |
|
86 | nSRAM_E2 : OUT STD_LOGIC; | |
82 | nSRAM_W : OUT STD_LOGIC; |
|
87 | nSRAM_W : OUT STD_LOGIC; | |
83 | nSRAM_G : OUT STD_LOGIC; |
|
88 | nSRAM_G : OUT STD_LOGIC; | |
84 | nSRAM_BUSY : IN STD_LOGIC; |
|
89 | nSRAM_BUSY : IN STD_LOGIC; | |
85 | spw1_en : OUT STD_LOGIC; |
|
90 | spw1_en : OUT STD_LOGIC; | |
86 | spw1_din : IN STD_LOGIC; |
|
91 | spw1_din : IN STD_LOGIC; | |
87 | spw1_sin : IN STD_LOGIC; |
|
92 | spw1_sin : IN STD_LOGIC; | |
88 | spw1_dout : OUT STD_LOGIC; |
|
93 | spw1_dout : OUT STD_LOGIC; | |
89 | spw1_sout : OUT STD_LOGIC; |
|
94 | spw1_sout : OUT STD_LOGIC; | |
90 | spw2_en : OUT STD_LOGIC; |
|
95 | spw2_en : OUT STD_LOGIC; | |
91 | spw2_din : IN STD_LOGIC; |
|
96 | spw2_din : IN STD_LOGIC; | |
92 | spw2_sin : IN STD_LOGIC; |
|
97 | spw2_sin : IN STD_LOGIC; | |
93 | spw2_dout : OUT STD_LOGIC; |
|
98 | spw2_dout : OUT STD_LOGIC; | |
94 | spw2_sout : OUT STD_LOGIC; |
|
99 | spw2_sout : OUT STD_LOGIC; | |
95 | bias_fail_sw : OUT STD_LOGIC; |
|
100 | bias_fail_sw : OUT STD_LOGIC; | |
96 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
97 | ADC_smpclk : OUT STD_LOGIC; |
|
102 | ADC_smpclk : OUT STD_LOGIC; | |
98 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
103 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
99 | DAC_SDO : OUT STD_LOGIC; |
|
104 | DAC_SDO : OUT STD_LOGIC; | |
100 | DAC_SCK : OUT STD_LOGIC; |
|
105 | DAC_SCK : OUT STD_LOGIC; | |
101 | DAC_SYNC : OUT STD_LOGIC; |
|
106 | DAC_SYNC : OUT STD_LOGIC; | |
102 | DAC_CAL_EN : OUT STD_LOGIC; |
|
107 | DAC_CAL_EN : OUT STD_LOGIC; | |
103 | HK_smpclk : OUT STD_LOGIC; |
|
108 | HK_smpclk : OUT STD_LOGIC; | |
104 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
|
109 | ADC_OEB_bar_HK : OUT STD_LOGIC; | |
105 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
110 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
106 | TAG8 : OUT STD_LOGIC); |
|
111 | TAG8 : OUT STD_LOGIC); | |
107 | END COMPONENT; |
|
112 | END COMPONENT; | |
108 |
|
113 | |||
109 | SIGNAL clk50MHz : STD_ULOGIC := '0'; |
|
114 | SIGNAL clk50MHz : STD_ULOGIC := '0'; | |
110 | SIGNAL clk49_152MHz : STD_ULOGIC := '0'; |
|
115 | SIGNAL clk49_152MHz : STD_ULOGIC := '0'; | |
111 | SIGNAL reset : STD_ULOGIC; |
|
116 | SIGNAL reset : STD_ULOGIC; | |
112 | SIGNAL TAG1 : STD_ULOGIC := '1'; |
|
117 | SIGNAL TAG1 : STD_ULOGIC := '1'; | |
113 | SIGNAL TAG3 : STD_ULOGIC; |
|
118 | SIGNAL TAG3 : STD_ULOGIC; | |
114 | SIGNAL TAG2 : STD_ULOGIC := '1'; |
|
119 | SIGNAL TAG2 : STD_ULOGIC := '1'; | |
115 | SIGNAL TAG4 : STD_ULOGIC; |
|
120 | SIGNAL TAG4 : STD_ULOGIC; | |
116 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
121 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); | |
117 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
122 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
118 | SIGNAL nSRAM_MBE : STD_LOGIC; |
|
123 | SIGNAL nSRAM_MBE : STD_LOGIC; | |
119 | SIGNAL nSRAM_E1 : STD_LOGIC; |
|
124 | SIGNAL nSRAM_E1 : STD_LOGIC; | |
120 | SIGNAL nSRAM_E2 : STD_LOGIC; |
|
125 | SIGNAL nSRAM_E2 : STD_LOGIC; | |
121 | SIGNAL nSRAM_W : STD_LOGIC; |
|
126 | SIGNAL nSRAM_W : STD_LOGIC; | |
122 | SIGNAL nSRAM_G : STD_LOGIC; |
|
127 | SIGNAL nSRAM_G : STD_LOGIC; | |
123 | SIGNAL nSRAM_BUSY : STD_LOGIC; |
|
128 | SIGNAL nSRAM_BUSY : STD_LOGIC; | |
124 | SIGNAL spw1_en : STD_LOGIC; |
|
129 | SIGNAL spw1_en : STD_LOGIC; | |
125 | SIGNAL spw1_din : STD_LOGIC := '1'; |
|
130 | SIGNAL spw1_din : STD_LOGIC := '1'; | |
126 | SIGNAL spw1_sin : STD_LOGIC := '1'; |
|
131 | SIGNAL spw1_sin : STD_LOGIC := '1'; | |
127 | SIGNAL spw1_dout : STD_LOGIC; |
|
132 | SIGNAL spw1_dout : STD_LOGIC; | |
128 | SIGNAL spw1_sout : STD_LOGIC; |
|
133 | SIGNAL spw1_sout : STD_LOGIC; | |
129 | SIGNAL spw2_en : STD_LOGIC; |
|
134 | SIGNAL spw2_en : STD_LOGIC; | |
130 | SIGNAL spw2_din : STD_LOGIC := '1'; |
|
135 | SIGNAL spw2_din : STD_LOGIC := '1'; | |
131 | SIGNAL spw2_sin : STD_LOGIC := '1'; |
|
136 | SIGNAL spw2_sin : STD_LOGIC := '1'; | |
132 | SIGNAL spw2_dout : STD_LOGIC; |
|
137 | SIGNAL spw2_dout : STD_LOGIC; | |
133 | SIGNAL spw2_sout : STD_LOGIC; |
|
138 | SIGNAL spw2_sout : STD_LOGIC; | |
134 | SIGNAL bias_fail_sw : STD_LOGIC; |
|
139 | SIGNAL bias_fail_sw : STD_LOGIC; | |
135 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
140 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
136 | SIGNAL ADC_smpclk : STD_LOGIC; |
|
141 | SIGNAL ADC_smpclk : STD_LOGIC; | |
137 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
142 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); | |
138 | SIGNAL DAC_SDO : STD_LOGIC; |
|
143 | SIGNAL DAC_SDO : STD_LOGIC; | |
139 | SIGNAL DAC_SCK : STD_LOGIC; |
|
144 | SIGNAL DAC_SCK : STD_LOGIC; | |
140 | SIGNAL DAC_SYNC : STD_LOGIC; |
|
145 | SIGNAL DAC_SYNC : STD_LOGIC; | |
141 | SIGNAL DAC_CAL_EN : STD_LOGIC; |
|
146 | SIGNAL DAC_CAL_EN : STD_LOGIC; | |
142 | SIGNAL HK_smpclk : STD_LOGIC; |
|
147 | SIGNAL HK_smpclk : STD_LOGIC; | |
143 | SIGNAL ADC_OEB_bar_HK : STD_LOGIC; |
|
148 | SIGNAL ADC_OEB_bar_HK : STD_LOGIC; | |
144 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
149 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
145 | SIGNAL TAG8 : STD_LOGIC; |
|
150 | SIGNAL TAG8 : STD_LOGIC; | |
146 |
|
151 | |||
147 | CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20; |
|
152 | CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20; | |
148 | CONSTANT SCRUB_PERIOD : INTEGER := 200/20; |
|
153 | CONSTANT SCRUB_PERIOD : INTEGER := 200/20; | |
149 | CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20; |
|
154 | CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20; | |
150 | CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20; |
|
155 | CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20; | |
151 | SIGNAL counter_scrub_period : INTEGER; |
|
156 | SIGNAL counter_scrub_period : INTEGER; | |
152 |
|
157 | |||
153 |
|
158 | |||
154 | --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800"; |
|
159 | --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800"; | |
155 | --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006"; |
|
160 | --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006"; | |
156 | --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F"; |
|
161 | --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F"; | |
157 |
|
162 | |||
158 | CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90"; |
|
163 | CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90"; | |
159 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; |
|
164 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; | |
160 | CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E"; |
|
165 | CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E"; | |
161 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; |
|
166 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; | |
162 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; |
|
167 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; | |
163 | CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000"; |
|
168 | CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000"; | |
164 |
|
169 | |||
165 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; |
|
170 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; | |
166 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; |
|
171 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; | |
167 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); |
|
172 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); | |
168 | SIGNAL TXD1 : STD_LOGIC; |
|
173 | SIGNAL TXD1 : STD_LOGIC; | |
169 | SIGNAL RXD1 : STD_LOGIC; |
|
174 | SIGNAL RXD1 : STD_LOGIC; | |
170 |
|
175 | |||
171 | ----------------------------------------------------------------------------- |
|
176 | ----------------------------------------------------------------------------- | |
172 | CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000"; |
|
177 | CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000"; | |
173 | CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000"; |
|
178 | CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000"; | |
174 | CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000"; |
|
179 | CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000"; | |
175 | CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000"; |
|
180 | CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000"; | |
176 | CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000"; |
|
181 | CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000"; | |
177 | CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000"; |
|
182 | CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000"; | |
178 | CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000"; |
|
183 | CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000"; | |
179 | CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000"; |
|
184 | CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000"; | |
180 | CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000"; |
|
185 | CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000"; | |
181 | CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000"; |
|
186 | CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000"; | |
182 | CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000"; |
|
187 | CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000"; | |
183 | CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000"; |
|
188 | CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000"; | |
184 | CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000"; |
|
189 | CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000"; | |
185 | CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000"; |
|
190 | CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000"; | |
186 |
|
191 | |||
187 |
|
192 | |||
188 | TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
193 | TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |
189 | SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0); |
|
194 | SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0); | |
190 |
|
195 | |||
191 | TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; |
|
196 | TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |
192 | SIGNAL sample_counter : counter_vector( 2 DOWNTO 0); |
|
197 | SIGNAL sample_counter : counter_vector( 2 DOWNTO 0); | |
193 |
|
198 | |||
194 | SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
199 | SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
195 | SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
200 | SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
196 | SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
201 | SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
197 | SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
202 | SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
198 |
|
203 | |||
199 | SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
204 | SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0); | |
200 | SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
205 | SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0); | |
201 | SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
206 | SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0); | |
202 |
|
207 | |||
203 |
|
208 | |||
204 | SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
209 | SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
205 | ----------------------------------------------------------------------------- |
|
210 | ----------------------------------------------------------------------------- | |
206 | CONSTANT srambanks : INTEGER := 2; |
|
211 | CONSTANT srambanks : INTEGER := 2; | |
207 | CONSTANT sramwidth : INTEGER := 32; |
|
212 | CONSTANT sramwidth : INTEGER := 32; | |
208 | CONSTANT sramdepth : INTEGER := 19; |
|
213 | CONSTANT sramdepth : INTEGER := 19; | |
209 | CONSTANT sramfile : STRING := "prom.srec"; |
|
214 | CONSTANT sramfile : STRING := "prom.srec"; | |
210 | SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0); |
|
215 | SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0); | |
211 | ----------------------------------------------------------------------------- |
|
216 | ----------------------------------------------------------------------------- | |
212 |
|
217 | |||
213 | BEGIN -- beh |
|
218 | BEGIN -- beh | |
214 |
|
219 | |||
215 | LFR_EQM_1 : LFR_EQM |
|
220 | LFR_EQM_1 : LFR_EQM | |
216 | GENERIC MAP ( |
|
221 | GENERIC MAP ( | |
217 | Mem_use => use_RAM, |
|
222 | Mem_use => use_RAM, | |
218 |
USE_BOOTLOADER => 0 |
|
223 | USE_BOOTLOADER => 0, | |
|
224 | USE_ADCDRIVER => 0, | |||
|
225 | tech => apa3e, | |||
|
226 | tech_leon => inferred) | |||
219 | PORT MAP ( |
|
227 | PORT MAP ( | |
220 | clk50MHz => clk50MHz, --IN --ok |
|
228 | clk50MHz => clk50MHz, --IN --ok | |
221 | clk49_152MHz => clk49_152MHz, --in --ok |
|
229 | clk49_152MHz => clk49_152MHz, --in --ok | |
222 | reset => reset, --IN --ok |
|
230 | reset => reset, --IN --ok | |
223 |
|
231 | |||
224 | TAG1 => TAG1, --in |
|
232 | TAG1 => TAG1, --in | |
225 | TAG3 => TAG3, --out |
|
233 | TAG3 => TAG3, --out | |
226 | TAG2 => TAG2, --IN --ok |
|
234 | TAG2 => TAG2, --IN --ok | |
227 | TAG4 => TAG4, --out --ok |
|
235 | TAG4 => TAG4, --out --ok | |
228 |
|
236 | |||
229 | address => address, --out |
|
237 | address => address, --out | |
230 | data => data, --inout |
|
238 | data => data, --inout | |
231 | nSRAM_MBE => nSRAM_MBE, --inout |
|
239 | nSRAM_MBE => nSRAM_MBE, --inout | |
232 | nSRAM_E1 => nSRAM_E1, --out |
|
240 | nSRAM_E1 => nSRAM_E1, --out | |
233 | nSRAM_E2 => nSRAM_E2, --out |
|
241 | nSRAM_E2 => nSRAM_E2, --out | |
234 | nSRAM_W => nSRAM_W, --out |
|
242 | nSRAM_W => nSRAM_W, --out | |
235 | nSRAM_G => nSRAM_G, --out |
|
243 | nSRAM_G => nSRAM_G, --out | |
236 | nSRAM_BUSY => nSRAM_BUSY, --in |
|
244 | nSRAM_BUSY => nSRAM_BUSY, --in | |
237 |
|
245 | |||
238 | spw1_en => spw1_en, --out --ok |
|
246 | spw1_en => spw1_en, --out --ok | |
239 | spw1_din => spw1_din, --in --ok |
|
247 | spw1_din => spw1_din, --in --ok | |
240 | spw1_sin => spw1_sin, --in --ok |
|
248 | spw1_sin => spw1_sin, --in --ok | |
241 | spw1_dout => spw1_dout, --out --ok |
|
249 | spw1_dout => spw1_dout, --out --ok | |
242 | spw1_sout => spw1_sout, --out --ok |
|
250 | spw1_sout => spw1_sout, --out --ok | |
243 |
|
251 | |||
244 | spw2_en => spw2_en, --out --ok |
|
252 | spw2_en => spw2_en, --out --ok | |
245 | spw2_din => spw2_din, --in --ok |
|
253 | spw2_din => spw2_din, --in --ok | |
246 | spw2_sin => spw2_sin, --in --ok |
|
254 | spw2_sin => spw2_sin, --in --ok | |
247 | spw2_dout => spw2_dout, --out --ok |
|
255 | spw2_dout => spw2_dout, --out --ok | |
248 | spw2_sout => spw2_sout, --out --ok |
|
256 | spw2_sout => spw2_sout, --out --ok | |
249 |
|
257 | |||
250 | bias_fail_sw => bias_fail_sw, --OUT --ok |
|
258 | bias_fail_sw => bias_fail_sw, --OUT --ok | |
251 |
|
259 | |||
252 | ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok |
|
260 | ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok | |
253 | ADC_smpclk => ADC_smpclk, --out --ok |
|
261 | ADC_smpclk => ADC_smpclk, --out --ok | |
254 | ADC_data => ADC_data, --IN --ok |
|
262 | ADC_data => ADC_data, --IN --ok | |
255 |
|
263 | |||
256 | DAC_SDO => DAC_SDO, --out --ok |
|
264 | DAC_SDO => DAC_SDO, --out --ok | |
257 | DAC_SCK => DAC_SCK, --out --ok |
|
265 | DAC_SCK => DAC_SCK, --out --ok | |
258 | DAC_SYNC => DAC_SYNC, --out --ok |
|
266 | DAC_SYNC => DAC_SYNC, --out --ok | |
259 | DAC_CAL_EN => DAC_CAL_EN, --out --ok |
|
267 | DAC_CAL_EN => DAC_CAL_EN, --out --ok | |
260 |
|
268 | |||
261 | HK_smpclk => HK_smpclk, --out --ok |
|
269 | HK_smpclk => HK_smpclk, --out --ok | |
262 | ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok |
|
270 | ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok | |
263 | HK_SEL => HK_SEL, --out --ok |
|
271 | HK_SEL => HK_SEL, --out --ok | |
264 | TAG8 => TAG8); --out --ok |
|
272 | TAG8 => TAG8); --out --ok | |
265 |
|
273 | |||
266 |
|
274 | |||
267 | ----------------------------------------------------------------------------- |
|
275 | ----------------------------------------------------------------------------- | |
268 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
276 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |
269 | clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz |
|
277 | clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz | |
270 | ----------------------------------------------------------------------------- |
|
278 | ----------------------------------------------------------------------------- | |
271 |
|
279 | |||
272 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE |
|
280 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE | |
273 | TestModule_RHF1401_1 : TestModule_RHF1401 |
|
281 | TestModule_RHF1401_1 : TestModule_RHF1401 | |
274 | GENERIC MAP ( |
|
282 | GENERIC MAP ( | |
275 | freq => 24*(I+1), |
|
283 | freq => 24*(I+1), | |
276 | amplitude => 8000/(I+1), |
|
284 | amplitude => 8000/(I+1), | |
277 | impulsion => 0) |
|
285 | impulsion => 0) | |
278 | PORT MAP ( |
|
286 | PORT MAP ( | |
279 | ADC_smpclk => ADC_smpclk, |
|
287 | ADC_smpclk => ADC_smpclk, | |
280 | ADC_OEB_bar => ADC_OEB_bar_CH(I), |
|
288 | ADC_OEB_bar => ADC_OEB_bar_CH(I), | |
281 | ADC_data => ADC_data); |
|
289 | ADC_data => ADC_data); | |
282 | END GENERATE MODULE_RHF1401; |
|
290 | END GENERATE MODULE_RHF1401; | |
283 |
|
291 | |||
284 | ----------------------------------------------------------------------------- |
|
292 | ----------------------------------------------------------------------------- | |
285 | PROCESS (clk50MHz, reset) |
|
293 | PROCESS (clk50MHz, reset) | |
286 | BEGIN -- PROCESS |
|
294 | BEGIN -- PROCESS | |
287 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
295 | IF reset = '0' THEN -- asynchronous reset (active low) | |
288 | nSRAM_BUSY <= '1'; |
|
296 | nSRAM_BUSY <= '1'; | |
289 | counter_scrub_period <= 0; |
|
297 | counter_scrub_period <= 0; | |
290 | ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge |
|
298 | ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge | |
291 | IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN |
|
299 | IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN | |
292 | counter_scrub_period <= 0; |
|
300 | counter_scrub_period <= 0; | |
293 | ELSE |
|
301 | ELSE | |
294 | counter_scrub_period <= counter_scrub_period + 1; |
|
302 | counter_scrub_period <= counter_scrub_period + 1; | |
295 | END IF; |
|
303 | END IF; | |
296 |
|
304 | |||
297 | IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN |
|
305 | IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN | |
298 | nSRAM_BUSY <= '1'; |
|
306 | nSRAM_BUSY <= '1'; | |
299 | ELSE |
|
307 | ELSE | |
300 | nSRAM_BUSY <= '0'; |
|
308 | nSRAM_BUSY <= '0'; | |
301 | END IF; |
|
309 | END IF; | |
302 | END IF; |
|
310 | END IF; | |
303 | END PROCESS; |
|
311 | END PROCESS; | |
304 |
|
312 | |||
305 | ----------------------------------------------------------------------------- |
|
313 | ----------------------------------------------------------------------------- | |
306 | -- TB |
|
314 | -- TB | |
307 | ----------------------------------------------------------------------------- |
|
315 | ----------------------------------------------------------------------------- | |
308 | TAG1 <= TXD1; |
|
316 | TAG1 <= TXD1; | |
309 | RXD1 <= TAG3; |
|
317 | RXD1 <= TAG3; | |
310 |
|
318 | |||
311 | PROCESS |
|
319 | PROCESS | |
312 | CONSTANT txp : TIME := 320 ns; |
|
320 | CONSTANT txp : TIME := 320 ns; | |
313 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
321 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
314 | BEGIN -- PROCESS |
|
322 | BEGIN -- PROCESS | |
315 | TXD1 <= '1'; |
|
323 | TXD1 <= '1'; | |
316 | reset <= '0'; |
|
324 | reset <= '0'; | |
317 | WAIT FOR 500 ns; |
|
325 | WAIT FOR 500 ns; | |
318 | reset <= '1'; |
|
326 | reset <= '1'; | |
319 |
WAIT FOR 100 |
|
327 | WAIT FOR 100 us; | |
320 | message_simu <= "0 - UART init "; |
|
328 | message_simu <= "0 - UART init "; | |
321 | UART_INIT(TXD1, txp); |
|
329 | UART_INIT(TXD1, txp); | |
322 |
|
330 | |||
323 | --------------------------------------------------------------------------- |
|
331 | --------------------------------------------------------------------------- | |
324 | -- LAUNCH leon 3 software |
|
332 | -- LAUNCH leon 3 software | |
325 | --------------------------------------------------------------------------- |
|
333 | --------------------------------------------------------------------------- | |
326 | message_simu <= "2- GO Leon3...."; |
|
334 | message_simu <= "2- GO Leon3...."; | |
327 |
|
335 | |||
328 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- |
|
336 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- | |
329 | --Force a debug break |
|
337 | --Force a debug break | |
330 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); |
|
338 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); | |
331 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20); |
|
339 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20); | |
332 | --Clear time tag counter |
|
340 | --Clear time tag counter | |
333 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8); |
|
341 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8); | |
334 | --Clear ASR registers |
|
342 | --Clear ASR registers | |
335 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
|
343 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040); | |
336 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000"); |
|
344 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000"); | |
337 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000"); |
|
345 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000"); | |
338 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024); |
|
346 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024); | |
339 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
|
347 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); | |
340 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
|
348 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); | |
341 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
349 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); | |
342 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
350 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); | |
343 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000"); |
|
351 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000"); | |
344 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000"); |
|
352 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000"); | |
345 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000"); |
|
353 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000"); | |
346 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000"); |
|
354 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000"); | |
347 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48); |
|
355 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48); | |
348 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C); |
|
356 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C); | |
349 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040); |
|
357 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040); | |
350 |
|
358 | |||
351 | IF USE_ESA_MEMCTRL = 1 THEN |
|
359 | IF USE_ESA_MEMCTRL = 1 THEN | |
352 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS); |
|
360 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS); | |
353 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60"); |
|
361 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60"); | |
354 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000"); |
|
362 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000"); | |
355 | END IF; |
|
363 | END IF; | |
356 |
|
364 | |||
357 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); |
|
365 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); | |
358 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); |
|
366 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); | |
359 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); |
|
367 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); | |
360 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); |
|
368 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); | |
361 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24); |
|
369 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24); | |
362 |
|
370 | |||
363 | --memSet(DSUBASEADDRESS+0x300000,0,1567); |
|
371 | --memSet(DSUBASEADDRESS+0x300000,0,1567); | |
364 |
|
372 | |||
365 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000); |
|
373 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000); | |
366 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0"); |
|
374 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0"); | |
367 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002"); |
|
375 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002"); | |
368 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000"); |
|
376 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000"); | |
369 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000"); |
|
377 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000"); | |
370 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004"); |
|
378 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004"); | |
371 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000"); |
|
379 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000"); | |
372 |
|
380 | |||
373 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020); |
|
381 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020); | |
374 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000"); |
|
382 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000"); | |
375 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000"); |
|
383 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000"); | |
376 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000"); |
|
384 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000"); | |
377 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000"); |
|
385 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000"); | |
378 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000"); |
|
386 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000"); | |
379 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0"); |
|
387 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0"); | |
380 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000"); |
|
388 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000"); | |
381 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000"); |
|
389 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000"); | |
382 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000"); |
|
390 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000"); | |
383 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000"); |
|
391 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000"); | |
384 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000"); |
|
392 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000"); | |
385 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000"); |
|
393 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000"); | |
386 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000"); |
|
394 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000"); | |
387 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000"); |
|
395 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000"); | |
388 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000"); |
|
396 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000"); | |
389 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000"); |
|
397 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000"); | |
390 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000"); |
|
398 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000"); | |
391 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000"); |
|
399 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000"); | |
392 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000"); |
|
400 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000"); | |
393 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000"); |
|
401 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000"); | |
394 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000"); |
|
402 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000"); | |
395 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000"); |
|
403 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000"); | |
396 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000"); |
|
404 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000"); | |
397 |
|
405 | |||
398 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS); |
|
406 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS); | |
399 |
|
407 | |||
400 | --//Disable interrupts |
|
408 | --//Disable interrupts | |
401 | --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0); |
|
409 | --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0); | |
402 | --if(APBIRQCTRLRBASEADD == (unsigned int)-1) |
|
410 | --if(APBIRQCTRLRBASEADD == (unsigned int)-1) | |
403 | -- return false; |
|
411 | -- return false; | |
404 | --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040); |
|
412 | --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040); | |
405 | --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080); |
|
413 | --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080); | |
406 | --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD); |
|
414 | --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD); | |
407 |
|
415 | |||
408 | -- //Set up timer |
|
416 | -- //Set up timer | |
409 | --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0); |
|
417 | --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0); | |
410 | --if(APBTIMERBASEADD == (unsigned int)-1) |
|
418 | --if(APBTIMERBASEADD == (unsigned int)-1) | |
411 | -- return false; |
|
419 | -- return false; | |
412 | --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014); |
|
420 | --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014); | |
413 | --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04); |
|
421 | --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04); | |
414 | --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018); |
|
422 | --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018); | |
415 |
|
423 | |||
416 |
|
424 | |||
417 | --------------------------------------------------------------------------- |
|
425 | --------------------------------------------------------------------------- | |
418 | --bool dsu3plugin::setCacheEnable(bool enabled) |
|
426 | --bool dsu3plugin::setCacheEnable(bool enabled) | |
419 | --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0); |
|
427 | --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0); | |
420 | --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000; |
|
428 | --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000; | |
421 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024); |
|
429 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024); | |
422 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000); |
|
430 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000); | |
423 | data_read <= data_read_v; |
|
431 | data_read <= data_read_v; | |
424 | --if(enabled){ |
|
432 | --if(enabled){ | |
425 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000); |
|
433 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000); | |
426 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000); |
|
434 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000); | |
427 | --}else{ |
|
435 | --}else{ | |
428 | --WriteRegs(uIntlist()<<((!0x0001000F)®),DSUBASEADDRESS+0x700000); |
|
436 | --WriteRegs(uIntlist()<<((!0x0001000F)®),DSUBASEADDRESS+0x700000); | |
429 | --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000); |
|
437 | --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000); | |
430 | --} |
|
438 | --} | |
431 |
|
439 | |||
432 |
|
440 | |||
433 | -- void dsu3plugin::run() --------------------------------------------------------------------------------------------------------------------------------------- |
|
441 | -- void dsu3plugin::run() --------------------------------------------------------------------------------------------------------------------------------------- | |
434 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020); |
|
442 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020); | |
435 |
|
443 | |||
436 | --------------------------------------------------------------------------- |
|
444 | --------------------------------------------------------------------------- | |
437 | --message_simu <= "1 - UART test "; |
|
445 | --message_simu <= "1 - UART test "; | |
438 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF"); |
|
446 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF"); | |
439 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A"); |
|
447 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A"); | |
440 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B"); |
|
448 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B"); | |
441 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v); |
|
449 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v); | |
442 | --data_read <= data_read_v; |
|
450 | --data_read <= data_read_v; | |
443 | --data_message <= "GPIO_data_write"; |
|
451 | --data_message <= "GPIO_data_write"; | |
444 |
|
452 | |||
445 | -- UNSET the LFR reset |
|
453 | -- UNSET the LFR reset | |
446 | message_simu <= "2 - LFR UNRESET"; |
|
454 | message_simu <= "2 - LFR UNRESET"; | |
447 | UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT); |
|
455 | UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT); | |
448 | -- |
|
456 | -- | |
449 | message_simu <= "3 - LFR CONFIG "; |
|
457 | message_simu <= "3 - LFR CONFIG "; | |
450 | LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR, |
|
458 | LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR, | |
451 | ADDR_BUFFER_MS_F0_0, |
|
459 | ADDR_BUFFER_MS_F0_0, | |
452 | ADDR_BUFFER_MS_F0_1, |
|
460 | ADDR_BUFFER_MS_F0_1, | |
453 | ADDR_BUFFER_MS_F1_0, |
|
461 | ADDR_BUFFER_MS_F1_0, | |
454 | ADDR_BUFFER_MS_F1_1, |
|
462 | ADDR_BUFFER_MS_F1_1, | |
455 | ADDR_BUFFER_MS_F2_0, |
|
463 | ADDR_BUFFER_MS_F2_0, | |
456 | ADDR_BUFFER_MS_F2_1); |
|
464 | ADDR_BUFFER_MS_F2_1); | |
457 |
|
465 | |||
458 |
|
466 | |||
459 | LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp, |
|
467 | LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp, | |
460 | LFR_MODE_SBM1, |
|
468 | LFR_MODE_SBM1, | |
461 | X"7FFFFFFF", -- START DATE |
|
469 | X"7FFFFFFF", -- START DATE | |
462 |
|
470 | |||
463 | "00000", --DATA_SHAPING ( 4 DOWNTO 0) |
|
471 | "00000", --DATA_SHAPING ( 4 DOWNTO 0) | |
464 | X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0) |
|
472 | X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0) | |
465 | X"0001280A", --DELTA_F0 (31 DOWNTO 0) |
|
473 | X"0001280A", --DELTA_F0 (31 DOWNTO 0) | |
466 | X"00000007", --DELTA_F0_2 (31 DOWNTO 0) |
|
474 | X"00000007", --DELTA_F0_2 (31 DOWNTO 0) | |
467 | X"0001283F", --DELTA_F1 (31 DOWNTO 0) |
|
475 | X"0001283F", --DELTA_F1 (31 DOWNTO 0) | |
468 | X"000127FF", --DELTA_F2 (31 DOWNTO 0) |
|
476 | X"000127FF", --DELTA_F2 (31 DOWNTO 0) | |
469 |
|
477 | |||
470 | ADDR_BASE_LFR, |
|
478 | ADDR_BASE_LFR, | |
471 | ADDR_BUFFER_WFP_F0_0, |
|
479 | ADDR_BUFFER_WFP_F0_0, | |
472 | ADDR_BUFFER_WFP_F0_1, |
|
480 | ADDR_BUFFER_WFP_F0_1, | |
473 | ADDR_BUFFER_WFP_F1_0, |
|
481 | ADDR_BUFFER_WFP_F1_0, | |
474 | ADDR_BUFFER_WFP_F1_1, |
|
482 | ADDR_BUFFER_WFP_F1_1, | |
475 | ADDR_BUFFER_WFP_F2_0, |
|
483 | ADDR_BUFFER_WFP_F2_0, | |
476 | ADDR_BUFFER_WFP_F2_1, |
|
484 | ADDR_BUFFER_WFP_F2_1, | |
477 | ADDR_BUFFER_WFP_F3_0, |
|
485 | ADDR_BUFFER_WFP_F3_0, | |
478 | ADDR_BUFFER_WFP_F3_1); |
|
486 | ADDR_BUFFER_WFP_F3_1); | |
479 |
|
487 | |||
480 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
488 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); | |
481 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
489 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); | |
482 |
|
490 | |||
483 |
|
491 | |||
484 | --------------------------------------------------------------------------- |
|
492 | --------------------------------------------------------------------------- | |
485 | -- CONFIG LFR 2 |
|
493 | -- CONFIG LFR 2 | |
486 | --------------------------------------------------------------------------- |
|
494 | --------------------------------------------------------------------------- | |
487 | --message_simu <= "3 - LFR2 CONFIG"; |
|
495 | --message_simu <= "3 - LFR2 CONFIG"; | |
488 | --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2, |
|
496 | --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2, | |
489 | -- X"40000000", |
|
497 | -- X"40000000", | |
490 | -- X"40001000", |
|
498 | -- X"40001000", | |
491 | -- X"40002000", |
|
499 | -- X"40002000", | |
492 | -- X"40003000", |
|
500 | -- X"40003000", | |
493 | -- X"40004000", |
|
501 | -- X"40004000", | |
494 | -- X"40005000"); |
|
502 | -- X"40005000"); | |
495 |
|
503 | |||
496 |
|
504 | |||
497 | --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, |
|
505 | --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, | |
498 | -- LFR_MODE_SBM1, |
|
506 | -- LFR_MODE_SBM1, | |
499 | -- X"7FFFFFFF", -- START DATE |
|
507 | -- X"7FFFFFFF", -- START DATE | |
500 |
|
508 | |||
501 | -- "00000",--DATA_SHAPING ( 4 DOWNTO 0) |
|
509 | -- "00000",--DATA_SHAPING ( 4 DOWNTO 0) | |
502 | -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) |
|
510 | -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) | |
503 | -- X"0001280A",--DELTA_F0 (31 DOWNTO 0) |
|
511 | -- X"0001280A",--DELTA_F0 (31 DOWNTO 0) | |
504 | -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0) |
|
512 | -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0) | |
505 | -- X"0001283F",--DELTA_F1 (31 DOWNTO 0) |
|
513 | -- X"0001283F",--DELTA_F1 (31 DOWNTO 0) | |
506 | -- X"000127FF",--DELTA_F2 (31 DOWNTO 0) |
|
514 | -- X"000127FF",--DELTA_F2 (31 DOWNTO 0) | |
507 |
|
515 | |||
508 | -- ADDR_BASE_LFR_2, |
|
516 | -- ADDR_BASE_LFR_2, | |
509 | -- X"40006000", |
|
517 | -- X"40006000", | |
510 | -- X"40007000", |
|
518 | -- X"40007000", | |
511 | -- X"40008000", |
|
519 | -- X"40008000", | |
512 | -- X"40009000", |
|
520 | -- X"40009000", | |
513 | -- X"4000A000", |
|
521 | -- X"4000A000", | |
514 | -- X"4000B000", |
|
522 | -- X"4000B000", | |
515 | -- X"4000C000", |
|
523 | -- X"4000C000", | |
516 | -- X"4000D000"); |
|
524 | -- X"4000D000"); | |
517 |
|
525 | |||
518 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F"); |
|
526 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F"); | |
519 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); |
|
527 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); | |
520 |
|
528 | |||
521 | --------------------------------------------------------------------------- |
|
529 | --------------------------------------------------------------------------- | |
522 | --------------------------------------------------------------------------- |
|
530 | --------------------------------------------------------------------------- | |
523 |
|
531 | |||
524 |
|
532 | |||
525 | message_simu <= "4 - GO GO GO !!"; |
|
533 | message_simu <= "4 - GO GO GO !!"; | |
|
534 | data_message <= "---------------"; | |||
526 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); |
|
535 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); | |
527 |
|
|
536 | -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); | |
528 |
|
537 | |||
|
538 | ||||
|
539 | data_read_v := (OTHERS => '1'); | |||
529 | READ_STATUS : LOOP |
|
540 | READ_STATUS : LOOP | |
|
541 | data_message <= "---------------"; | |||
530 | WAIT FOR 2 ms; |
|
542 | WAIT FOR 2 ms; | |
531 |
data_message <= "READ_ |
|
543 | data_message <= "READ_STATUS_SM_"; | |
532 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
544 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |
533 | data_read <= data_read_v; |
|
545 | --data_message <= "--------------r"; | |
|
546 | --data_read <= data_read_v; | |||
534 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); |
|
547 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |
535 |
|
548 | |||
536 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
549 | data_message <= "READ_STATUS_WF_"; | |
537 | data_read <= data_read_v; |
|
550 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |
|
551 | --data_message <= "--------------r"; | |||
|
552 | --data_read <= data_read_v; | |||
538 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); |
|
553 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |
539 | END LOOP READ_STATUS; |
|
554 | END LOOP READ_STATUS; | |
540 |
|
555 | |||
541 | WAIT; |
|
556 | WAIT; | |
542 | END PROCESS; |
|
557 | END PROCESS; | |
543 |
|
558 | |||
544 |
|
559 | |||
545 | ----------------------------------------------------------------------------- |
|
560 | ----------------------------------------------------------------------------- | |
546 | PROCESS (nSRAM_W, reset) |
|
561 | PROCESS (nSRAM_W, reset) | |
547 | BEGIN -- PROCESS |
|
562 | BEGIN -- PROCESS | |
548 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
563 | IF reset = '0' THEN -- asynchronous reset (active low) | |
549 | data_pre_f0 <= X"00020001"; |
|
564 | data_pre_f0 <= X"00020001"; | |
550 | data_pre_f1 <= X"00020001"; |
|
565 | data_pre_f1 <= X"00020001"; | |
551 | data_pre_f2 <= X"00020001"; |
|
566 | data_pre_f2 <= X"00020001"; | |
552 |
|
567 | |||
553 | addr_pre_f0 <= (OTHERS => '0'); |
|
568 | addr_pre_f0 <= (OTHERS => '0'); | |
554 | addr_pre_f1 <= (OTHERS => '0'); |
|
569 | addr_pre_f1 <= (OTHERS => '0'); | |
555 | addr_pre_f2 <= (OTHERS => '0'); |
|
570 | addr_pre_f2 <= (OTHERS => '0'); | |
556 |
|
571 | |||
557 | error_wfp <= "000"; |
|
572 | error_wfp <= "000"; | |
558 | error_wfp_addr <= "000"; |
|
573 | error_wfp_addr <= "000"; | |
559 |
|
574 | |||
560 | sample_counter <= (0,0,0); |
|
575 | sample_counter <= (0,0,0); | |
561 |
|
576 | |||
562 | ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge |
|
577 | ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge | |
563 | error_wfp <= "000"; |
|
578 | error_wfp <= "000"; | |
564 | error_wfp_addr <= "000"; |
|
579 | error_wfp_addr <= "000"; | |
565 | ------------------------------------------------------------------------- |
|
580 | ------------------------------------------------------------------------- | |
566 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR |
|
581 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR | |
567 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN |
|
582 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN | |
568 |
|
583 | |||
569 | addr_pre_f0 <= address(13 DOWNTO 0); |
|
584 | addr_pre_f0 <= address(13 DOWNTO 0); | |
570 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN |
|
585 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN | |
571 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
586 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN | |
572 | error_wfp_addr(0) <= '1'; |
|
587 | error_wfp_addr(0) <= '1'; | |
573 | END IF; |
|
588 | END IF; | |
574 | END IF; |
|
589 | END IF; | |
575 |
|
590 | |||
576 | data_pre_f0 <= data; |
|
591 | data_pre_f0 <= data; | |
577 | CASE data_pre_f0 IS |
|
592 | CASE data_pre_f0 IS | |
578 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF; |
|
593 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF; | |
579 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF; |
|
594 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF; | |
580 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF; |
|
595 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF; | |
581 | WHEN OTHERS => error_wfp(0) <= '1'; |
|
596 | WHEN OTHERS => error_wfp(0) <= '1'; | |
582 | END CASE; |
|
597 | END CASE; | |
583 |
|
598 | |||
584 |
|
599 | |||
585 | END IF; |
|
600 | END IF; | |
586 | ------------------------------------------------------------------------- |
|
601 | ------------------------------------------------------------------------- | |
587 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR |
|
602 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR | |
588 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN |
|
603 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN | |
589 |
|
604 | |||
590 | addr_pre_f1 <= address(13 DOWNTO 0); |
|
605 | addr_pre_f1 <= address(13 DOWNTO 0); | |
591 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN |
|
606 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN | |
592 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
607 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN | |
593 | error_wfp_addr(1) <= '1'; |
|
608 | error_wfp_addr(1) <= '1'; | |
594 | END IF; |
|
609 | END IF; | |
595 | END IF; |
|
610 | END IF; | |
596 |
|
611 | |||
597 | data_pre_f1 <= data; |
|
612 | data_pre_f1 <= data; | |
598 | CASE data_pre_f1 IS |
|
613 | CASE data_pre_f1 IS | |
599 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF; |
|
614 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF; | |
600 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF; |
|
615 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF; | |
601 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF; |
|
616 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF; | |
602 | WHEN OTHERS => error_wfp(1) <= '1'; |
|
617 | WHEN OTHERS => error_wfp(1) <= '1'; | |
603 | END CASE; |
|
618 | END CASE; | |
604 |
|
619 | |||
605 | sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16); |
|
620 | sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16); | |
606 | sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0); |
|
621 | sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0); | |
607 | sample_counter(1) <= (sample_counter(1) + 1) MOD 3; |
|
622 | sample_counter(1) <= (sample_counter(1) + 1) MOD 3; | |
608 |
|
623 | |||
609 | END IF; |
|
624 | END IF; | |
610 | ------------------------------------------------------------------------- |
|
625 | ------------------------------------------------------------------------- | |
611 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR |
|
626 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR | |
612 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN |
|
627 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN | |
613 |
|
628 | |||
614 | addr_pre_f2 <= address(13 DOWNTO 0); |
|
629 | addr_pre_f2 <= address(13 DOWNTO 0); | |
615 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN |
|
630 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN | |
616 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN |
|
631 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN | |
617 | error_wfp_addr(2) <= '1'; |
|
632 | error_wfp_addr(2) <= '1'; | |
618 | END IF; |
|
633 | END IF; | |
619 | END IF; |
|
634 | END IF; | |
620 |
|
635 | |||
621 | data_pre_f2 <= data; |
|
636 | data_pre_f2 <= data; | |
622 | CASE data_pre_f2 IS |
|
637 | CASE data_pre_f2 IS | |
623 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF; |
|
638 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF; | |
624 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF; |
|
639 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF; | |
625 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF; |
|
640 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF; | |
626 | WHEN OTHERS => error_wfp(2) <= '1'; |
|
641 | WHEN OTHERS => error_wfp(2) <= '1'; | |
627 | END CASE; |
|
642 | END CASE; | |
628 |
|
643 | |||
629 | sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16); |
|
644 | sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16); | |
630 | sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0); |
|
645 | sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0); | |
631 | sample_counter(2) <= (sample_counter(2) + 1) MOD 3; |
|
646 | sample_counter(2) <= (sample_counter(2) + 1) MOD 3; | |
632 |
|
647 | |||
633 | END IF; |
|
648 | END IF; | |
634 | END IF; |
|
649 | END IF; | |
635 | END PROCESS; |
|
650 | END PROCESS; | |
636 | ----------------------------------------------------------------------------- |
|
651 | ----------------------------------------------------------------------------- | |
637 | ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; |
|
652 | ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; | |
638 |
|
653 | |||
639 | sbanks : FOR k IN 0 TO srambanks-1 GENERATE |
|
654 | sbanks : FOR k IN 0 TO srambanks-1 GENERATE | |
640 | sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE |
|
655 | sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE | |
641 | sr0 : sram |
|
656 | sr0 : sram | |
642 | GENERIC MAP ( |
|
657 | GENERIC MAP ( | |
643 | index => i, |
|
658 | index => i, | |
644 | abits => sramdepth, |
|
659 | abits => sramdepth, | |
645 | fname => sramfile) |
|
660 | fname => sramfile) | |
646 | PORT MAP ( |
|
661 | PORT MAP ( | |
647 | address, |
|
662 | address, | |
648 | data(31-i*8 DOWNTO 24-i*8), |
|
663 | data(31-i*8 DOWNTO 24-i*8), | |
649 | ramsn(k), |
|
664 | ramsn(k), | |
650 | nSRAM_W, |
|
665 | nSRAM_W, | |
651 | nSRAM_G |
|
666 | nSRAM_G | |
652 | ); |
|
667 | ); | |
653 | END GENERATE; |
|
668 | END GENERATE; | |
654 | END GENERATE; |
|
669 | END GENERATE; | |
655 |
|
670 | |||
656 | END beh; |
|
671 | END beh; | |
657 |
|
672 |
@@ -1,199 +1,226 | |||||
1 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd |
|
1 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |
2 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd |
|
2 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |
3 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd |
|
3 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |
4 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
4 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
5 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd |
|
5 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd | |
6 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd |
|
6 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd | |
7 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd |
|
7 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd | |
8 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd |
|
8 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd | |
9 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd |
|
9 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd | |
10 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd |
|
10 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd | |
11 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd |
|
11 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd | |
12 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
|
12 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd | |
13 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd |
|
13 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd | |
14 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd |
|
14 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd | |
15 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd |
|
15 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd | |
16 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd |
|
16 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd | |
17 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd |
|
17 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd | |
18 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd |
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18 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd | |
19 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd |
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19 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd | |
20 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd |
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20 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd | |
21 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd |
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21 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd | |
22 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd |
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22 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd | |
23 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd |
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23 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd | |
24 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd |
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24 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd | |
25 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd |
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25 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd | |
26 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd |
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26 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd | |
27 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd |
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27 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd | |
28 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd |
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28 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd | |
29 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd |
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29 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd | |
30 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd |
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30 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd | |
31 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd |
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31 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd | |
32 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd |
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32 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd | |
33 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd |
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33 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd | |
34 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd |
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34 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd | |
35 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd |
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35 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd | |
36 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd |
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36 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd | |
37 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd |
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37 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd | |
38 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd |
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38 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd | |
39 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd |
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39 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd | |
40 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd |
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40 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd | |
41 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd |
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41 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd | |
42 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd |
|
42 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd | |
43 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd |
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43 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd | |
|
44 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd | |||
44 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd |
|
45 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd | |
45 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd |
|
46 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd | |
46 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd |
|
47 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd | |
47 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd |
|
48 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd | |
48 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd |
|
49 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |
49 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd |
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50 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd | |
50 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd |
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51 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd | |
51 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd |
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52 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |
52 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd |
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53 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd | |
53 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd |
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54 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |
54 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
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55 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
55 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd |
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56 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |
56 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd |
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57 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd | |
57 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd |
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58 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd | |
58 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd |
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59 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd | |
59 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd |
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60 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd | |
60 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd |
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61 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd | |
61 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd |
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62 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd | |
62 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd |
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63 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd | |
63 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd |
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64 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd | |
64 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd |
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65 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd | |
65 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd |
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66 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd | |
66 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd |
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67 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd | |
67 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd |
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68 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd | |
68 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd |
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69 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd | |
69 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd |
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70 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd | |
70 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd |
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71 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd | |
71 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd |
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72 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd | |
72 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd |
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73 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd | |
73 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd |
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74 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd | |
74 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd |
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75 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd | |
75 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd |
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76 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd | |
76 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd |
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77 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd | |
77 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd |
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78 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |
78 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd |
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79 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |
79 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd |
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80 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd | |
80 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd |
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81 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd | |
81 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd |
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82 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd | |
82 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd |
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83 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd | |
83 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd |
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84 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd | |
84 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd |
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85 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd | |
85 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd |
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86 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd | |
86 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd |
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87 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd | |
87 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd |
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88 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd | |
88 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd |
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89 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |
89 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd |
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90 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd | |
90 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd |
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91 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd | |
91 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd |
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92 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd | |
92 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd |
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93 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd | |
93 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd |
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94 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd | |
94 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd |
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95 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd | |
95 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd |
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96 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd | |
96 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd |
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97 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd | |
97 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd |
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98 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd | |
98 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd |
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99 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd | |
99 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd |
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100 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd | |
100 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd |
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101 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd | |
101 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd |
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102 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd | |
102 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd |
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103 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd | |
103 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd |
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104 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd | |
104 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd |
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105 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd | |
105 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd |
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106 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd | |
106 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd |
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107 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd | |
107 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd |
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108 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd | |
108 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd |
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109 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd | |
109 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd |
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110 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd | |
110 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd |
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111 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd | |
111 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd |
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112 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd | |
112 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd |
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113 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd | |
113 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd |
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114 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd | |
114 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd |
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115 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd | |
115 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd |
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116 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd | |
116 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd |
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117 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |
117 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd |
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118 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |
118 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd |
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119 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd | |
119 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd |
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120 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd | |
120 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd |
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121 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd | |
121 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
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122 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |
122 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd |
|
123 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd | |
123 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd |
|
124 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd | |
124 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd |
|
125 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd | |
125 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd |
|
126 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd | |
126 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd |
|
127 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd | |
127 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd |
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128 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd | |
128 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd |
|
129 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd | |
129 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd |
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130 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd | |
130 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd |
|
131 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd | |
131 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd |
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132 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd | |
132 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd |
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133 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd | |
133 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd |
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134 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd | |
134 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd |
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135 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd | |
135 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd |
|
136 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd | |
136 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd |
|
137 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd | |
137 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd |
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138 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |
138 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd |
|
139 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd | |
139 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd |
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140 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd | |
140 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd |
|
141 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd | |
141 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd |
|
142 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd | |
142 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd |
|
143 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd | |
143 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd |
|
144 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd | |
144 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd |
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145 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd | |
145 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd |
|
146 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd | |
146 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd |
|
147 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd | |
147 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd |
|
148 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd | |
148 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd |
|
149 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd | |
149 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd |
|
150 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd | |
150 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd |
|
151 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd | |
151 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd |
|
152 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd | |
152 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd |
|
153 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd | |
153 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd |
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154 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd | |
154 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd |
|
155 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd | |
155 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd |
|
156 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd | |
156 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd |
|
157 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd | |
157 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd |
|
158 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd | |
158 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd |
|
159 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd | |
159 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd |
|
160 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd | |
160 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd |
|
161 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |
161 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd |
|
162 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd | |
162 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd |
|
163 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd | |
163 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd |
|
164 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd | |
164 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd |
|
165 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd | |
165 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd |
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166 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |
166 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd |
|
167 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |
167 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd |
|
168 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |
168 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd |
|
169 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd | |
169 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd |
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170 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd | |
170 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd |
|
171 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd | |
171 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd |
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172 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd | |
172 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd |
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173 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |
173 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd |
|
174 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd | |
174 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd |
|
175 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd | |
175 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd |
|
176 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd | |
176 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd |
|
177 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd | |
177 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd |
|
178 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd | |
178 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd |
|
179 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd | |
179 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd |
|
180 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd | |
180 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd |
|
181 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd | |
181 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd |
|
182 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd | |
182 | vcom -quiet -93 -work work LFR-EQM.vhd |
|
183 | vcom -quiet -93 -work work LFR-EQM.vhd | |
183 | vcom -quiet -93 -work work TB.vhd |
|
184 | vcom -quiet -93 -work work TB.vhd | |
184 |
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185 | |||
185 | vsim work.tb |
|
186 | vsim work.tb | |
186 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0 |
|
187 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0 | |
187 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 |
|
188 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 | |
188 | #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 |
|
189 | #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 | |
189 |
|
190 | |||
190 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000 |
|
191 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
191 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 00 |
|
192 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
192 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 0 |
|
193 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
193 |
force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data |
|
194 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0 | |
|
195 | ||||
|
196 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |||
|
197 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |||
|
198 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |||
|
199 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd | |||
|
200 | ||||
|
201 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |||
|
202 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |||
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203 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd | |||
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204 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd | |||
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205 | ||||
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206 | mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd | |||
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207 | ||||
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208 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |||
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209 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |||
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210 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |||
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211 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |||
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212 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |||
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213 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |||
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214 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9 | |||
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215 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9 | |||
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216 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9 | |||
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217 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9 | |||
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218 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9 | |||
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219 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9 | |||
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220 | #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9 | |||
194 |
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221 | |||
195 | log -r *; |
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222 | log -r *; | |
196 | do wave.do ; |
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223 | do wave.do ; | |
197 | run -all |
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224 | run -all | |
198 |
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225 | |||
199 |
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226 |
@@ -1,116 +1,116 | |||||
1 | onerror {resume} |
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1 | onerror {resume} | |
2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc |
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2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc | |
3 | quietly WaveActivateNextPane {} 0 |
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3 | quietly WaveActivateNextPane {} 0 | |
4 | add wave -noupdate /tb/data_message |
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4 | add wave -noupdate /tb/data_message | |
5 | add wave -noupdate /tb/message_simu |
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5 | add wave -noupdate /tb/message_simu | |
6 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 |
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6 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 | |
7 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 |
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7 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 | |
8 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G |
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8 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G | |
9 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W |
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9 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W | |
10 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data |
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10 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data | |
11 | add wave -noupdate -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc |
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11 | add wave -noupdate -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc | |
12 | add wave -noupdate -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address |
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12 | add wave -noupdate -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address | |
13 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY |
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13 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |
14 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE |
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14 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE | |
15 | add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data |
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15 | add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data | |
16 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk |
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16 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk | |
17 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH |
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17 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH | |
18 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample |
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18 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
19 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val |
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19 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
20 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val |
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20 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
21 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata |
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21 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
22 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val |
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22 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
23 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata |
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23 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
24 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val |
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24 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
25 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata |
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25 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
26 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val |
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26 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
27 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata |
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27 | add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
28 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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28 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
29 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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29 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
30 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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30 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
31 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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31 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
32 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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32 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
33 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter |
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33 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |
34 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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34 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
35 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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35 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
36 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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36 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
37 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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37 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
38 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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38 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
39 | add wave -noupdate -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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39 | add wave -noupdate -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
40 | add wave -noupdate -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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40 | add wave -noupdate -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
41 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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41 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
42 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk |
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42 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk | |
43 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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43 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
44 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid |
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44 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid | |
45 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex |
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45 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex | |
46 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn |
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46 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn | |
47 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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47 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
48 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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48 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
49 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid |
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49 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid | |
50 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version |
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50 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version | |
51 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
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51 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
52 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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52 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
53 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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53 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
54 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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54 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
55 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter |
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55 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |
56 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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56 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
57 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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57 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |
58 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window |
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58 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |
59 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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59 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
60 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp |
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60 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |
61 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp |
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61 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |
62 | add wave -noupdate -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 |
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62 | add wave -noupdate -expand -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
63 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f1 |
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63 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f1 | |
64 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f2 |
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64 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f2 | |
65 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f0 |
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65 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
66 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f1 |
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66 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
67 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f2 |
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67 | add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
68 | add wave -noupdate /tb/error_wfp |
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68 | add wave -noupdate /tb/error_wfp | |
69 | add wave -noupdate /tb/error_wfp_addr |
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69 | add wave -noupdate /tb/error_wfp_addr | |
70 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a |
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70 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a | |
71 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 |
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71 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 | |
72 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe |
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72 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe | |
73 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we |
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73 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we | |
74 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a |
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74 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a | |
75 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 |
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75 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 | |
76 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe |
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76 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe | |
77 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we |
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77 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we | |
78 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi |
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78 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi | |
79 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo |
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79 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo | |
80 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi |
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80 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi | |
81 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso |
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81 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso | |
82 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbmi |
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82 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbmi | |
83 | add wave -noupdate -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo |
|
83 | add wave -noupdate -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo | |
84 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In |
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84 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
85 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out |
|
85 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
86 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address |
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86 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
87 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst |
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87 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
88 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data |
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88 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
89 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send |
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89 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
90 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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90 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
91 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg |
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91 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
92 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig |
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92 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
93 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window |
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93 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |
94 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window |
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94 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |
95 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done |
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95 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
96 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren |
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96 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
97 |
add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}} |
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97 | add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-height 15 -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} /tb/sample(2)(5) {-height 15 -radix decimal} /tb/sample(2)(4) {-height 15 -radix decimal} /tb/sample(2)(3) {-height 15 -radix decimal} /tb/sample(2)(2) {-height 15 -radix decimal} /tb/sample(2)(1) {-height 15 -radix decimal} /tb/sample(2)(0) {-height 15 -radix decimal} /tb/sample(1) {-height 15 -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -expand} /tb/sample(1)(5) {-format Analog-Step -height 74 -min -4.0 -radix decimal} /tb/sample(1)(4) {-format Analog-Step -height 74 -min -8.0 -radix decimal} /tb/sample(1)(3) {-format Analog-Step -height 74 -max 70.0 -radix decimal} /tb/sample(1)(2) {-format Analog-Step -height 74 -max 512.0 -radix decimal} /tb/sample(1)(1) {-format Analog-Step -height 74 -max 256.0 -radix decimal} /tb/sample(1)(0) {-format Analog-Step -height 74 -max 16.0 -radix decimal} /tb/sample(0) {-height 15 -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-height 15 -radix decimal} /tb/sample(0)(4) {-height 15 -radix decimal} /tb/sample(0)(3) {-height 15 -radix decimal} /tb/sample(0)(2) {-height 15 -radix decimal} /tb/sample(0)(1) {-height 15 -radix decimal} /tb/sample(0)(0) {-height 15 -radix decimal}} /tb/sample | |
98 |
add wave -noupdate |
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98 | add wave -noupdate /tb/sample_counter | |
99 | TreeUpdate [SetDefaultTree] |
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99 | TreeUpdate [SetDefaultTree] | |
100 |
WaveRestoreCursors {{Cursor 1} { |
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100 | WaveRestoreCursors {{Cursor 1} {14590425667 ps} 0} {{Cursor 2} {5525050896 ps} 0} {{Cursor 3} {24728625854 ps} 0} | |
101 |
quietly wave cursor active |
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101 | quietly wave cursor active 1 | |
102 | configure wave -namecolwidth 517 |
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102 | configure wave -namecolwidth 517 | |
103 | configure wave -valuecolwidth 347 |
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103 | configure wave -valuecolwidth 347 | |
104 | configure wave -justifyvalue left |
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104 | configure wave -justifyvalue left | |
105 | configure wave -signalnamewidth 0 |
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105 | configure wave -signalnamewidth 0 | |
106 | configure wave -snapdistance 10 |
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106 | configure wave -snapdistance 10 | |
107 | configure wave -datasetprefix 0 |
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107 | configure wave -datasetprefix 0 | |
108 | configure wave -rowmargin 4 |
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108 | configure wave -rowmargin 4 | |
109 | configure wave -childrowmargin 2 |
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109 | configure wave -childrowmargin 2 | |
110 | configure wave -gridoffset 0 |
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110 | configure wave -gridoffset 0 | |
111 | configure wave -gridperiod 1 |
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111 | configure wave -gridperiod 1 | |
112 | configure wave -griddelta 40 |
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112 | configure wave -griddelta 40 | |
113 | configure wave -timeline 0 |
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113 | configure wave -timeline 0 | |
114 | configure wave -timelineunits ns |
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114 | configure wave -timelineunits ns | |
115 | update |
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115 | update | |
116 |
WaveRestoreZoom {0 ps} { |
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116 | WaveRestoreZoom {0 ps} {40323664500 ps} |
@@ -1,407 +1,420 | |||||
1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
22 | --UPDATE |
|
22 | --UPDATE | |
23 | ------------------------------------------------------------------------------- |
|
23 | ------------------------------------------------------------------------------- | |
24 | -- 14-03-2013 - Jean-christophe Pellion |
|
24 | -- 14-03-2013 - Jean-christophe Pellion | |
25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) |
|
25 | -- ADD MUXN (a parametric multiplexor (N stage of MUX2)) | |
26 | ------------------------------------------------------------------------------- |
|
26 | ------------------------------------------------------------------------------- | |
27 |
|
27 | |||
28 | LIBRARY ieee; |
|
28 | LIBRARY ieee; | |
29 | USE ieee.std_logic_1164.ALL; |
|
29 | USE ieee.std_logic_1164.ALL; | |
30 | USE IEEE.NUMERIC_STD.ALL; |
|
30 | USE IEEE.NUMERIC_STD.ALL; | |
31 |
|
31 | |||
32 |
|
32 | |||
33 |
|
33 | |||
34 | PACKAGE general_purpose IS |
|
34 | PACKAGE general_purpose IS | |
35 |
|
35 | |||
36 | COMPONENT general_counter |
|
36 | COMPONENT general_counter | |
37 | GENERIC ( |
|
37 | GENERIC ( | |
38 | CYCLIC : STD_LOGIC; |
|
38 | CYCLIC : STD_LOGIC; | |
39 | NB_BITS_COUNTER : INTEGER; |
|
39 | NB_BITS_COUNTER : INTEGER; | |
40 | RST_VALUE : INTEGER); |
|
40 | RST_VALUE : INTEGER); | |
41 | PORT ( |
|
41 | PORT ( | |
42 | clk : IN STD_LOGIC; |
|
42 | clk : IN STD_LOGIC; | |
43 | rstn : IN STD_LOGIC; |
|
43 | rstn : IN STD_LOGIC; | |
44 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
|
44 | MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
45 | set : IN STD_LOGIC; |
|
45 | set : IN STD_LOGIC; | |
46 | set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
|
46 | set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
47 | add1 : IN STD_LOGIC; |
|
47 | add1 : IN STD_LOGIC; | |
48 | counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)); |
|
48 | counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)); | |
49 | END COMPONENT; |
|
49 | END COMPONENT; | |
50 |
|
50 | |||
51 | COMPONENT Clk_divider IS |
|
51 | COMPONENT Clk_divider IS | |
52 | GENERIC(OSC_freqHz : INTEGER := 50000000; |
|
52 | GENERIC(OSC_freqHz : INTEGER := 50000000; | |
53 | TargetFreq_Hz : INTEGER := 50000); |
|
53 | TargetFreq_Hz : INTEGER := 50000); | |
54 |
PORT (clk |
|
54 | PORT (clk : IN STD_LOGIC; | |
55 |
|
|
55 | reset : IN STD_LOGIC; | |
56 |
|
|
56 | clk_divided : OUT STD_LOGIC); | |
57 | END COMPONENT; |
|
57 | END COMPONENT; | |
58 |
|
58 | |||
59 |
|
59 | |||
60 | COMPONENT Clk_divider2 IS |
|
60 | COMPONENT Clk_divider2 IS | |
61 | generic(N : integer := 16); |
|
61 | GENERIC(N : INTEGER := 16); | |
62 | port( |
|
62 | PORT( | |
63 |
clk_in : |
|
63 | clk_in : IN STD_LOGIC; | |
64 | clk_out : out std_logic); |
|
64 | clk_out : OUT STD_LOGIC); | |
65 | END COMPONENT; |
|
65 | END COMPONENT; | |
66 |
|
66 | |||
67 | COMPONENT Adder IS |
|
67 | COMPONENT Adder IS | |
68 | GENERIC( |
|
68 | GENERIC( | |
69 | Input_SZ_A : INTEGER := 16; |
|
69 | Input_SZ_A : INTEGER := 16; | |
70 | Input_SZ_B : INTEGER := 16 |
|
70 | Input_SZ_B : INTEGER := 16 | |
71 |
|
71 | |||
72 | ); |
|
72 | ); | |
73 | PORT( |
|
73 | PORT( | |
74 | clk : IN STD_LOGIC; |
|
74 | clk : IN STD_LOGIC; | |
75 | reset : IN STD_LOGIC; |
|
75 | reset : IN STD_LOGIC; | |
76 | clr : IN STD_LOGIC; |
|
76 | clr : IN STD_LOGIC; | |
77 | load : IN STD_LOGIC; |
|
77 | load : IN STD_LOGIC; | |
78 | add : IN STD_LOGIC; |
|
78 | add : IN STD_LOGIC; | |
79 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
79 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
80 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
80 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
81 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) |
|
81 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |
82 | ); |
|
82 | ); | |
83 | END COMPONENT; |
|
83 | END COMPONENT; | |
84 |
|
84 | |||
85 |
COMPONENT Adder_V0 |
|
85 | COMPONENT Adder_V0 IS | |
86 | generic( |
|
86 | GENERIC( | |
87 |
Input_SZ_A |
|
87 | Input_SZ_A : INTEGER := 16; | |
88 |
Input_SZ_B |
|
88 | Input_SZ_B : INTEGER := 16 | |
89 |
|
89 | |||
90 | ); |
|
90 | ); | |
91 | port( |
|
91 | PORT( | |
92 | clk : in std_logic; |
|
92 | clk : IN STD_LOGIC; | |
93 | reset : in std_logic; |
|
93 | reset : IN STD_LOGIC; | |
94 | clr : in std_logic; |
|
94 | clr : IN STD_LOGIC; | |
95 | add : in std_logic; |
|
95 | add : IN STD_LOGIC; | |
96 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
96 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
97 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
97 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
98 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) |
|
98 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) | |
99 | ); |
|
99 | ); | |
100 |
|
|
100 | END COMPONENT; | |
101 |
|
101 | |||
102 | COMPONENT ADDRcntr IS |
|
102 | COMPONENT ADDRcntr IS | |
103 | PORT( |
|
103 | PORT( | |
104 | clk : IN STD_LOGIC; |
|
104 | clk : IN STD_LOGIC; | |
105 | reset : IN STD_LOGIC; |
|
105 | reset : IN STD_LOGIC; | |
106 | count : IN STD_LOGIC; |
|
106 | count : IN STD_LOGIC; | |
107 | clr : IN STD_LOGIC; |
|
107 | clr : IN STD_LOGIC; | |
108 | Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) |
|
108 | Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) | |
109 | ); |
|
109 | ); | |
110 | END COMPONENT; |
|
110 | END COMPONENT; | |
111 |
|
111 | |||
112 | COMPONENT ALU IS |
|
112 | COMPONENT ALU IS | |
113 | GENERIC( |
|
113 | GENERIC( | |
114 | Arith_en : INTEGER := 1; |
|
114 | Arith_en : INTEGER := 1; | |
115 | Logic_en : INTEGER := 1; |
|
115 | Logic_en : INTEGER := 1; | |
116 | Input_SZ_1 : INTEGER := 16; |
|
116 | Input_SZ_1 : INTEGER := 16; | |
117 | Input_SZ_2 : INTEGER := 9; |
|
117 | Input_SZ_2 : INTEGER := 9; | |
118 | COMP_EN : INTEGER := 0 -- 1 => No Comp |
|
118 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
119 |
|
119 | |||
120 | ); |
|
120 | ); | |
121 | PORT( |
|
121 | PORT( | |
122 | clk : IN STD_LOGIC; |
|
122 | clk : IN STD_LOGIC; | |
123 | reset : IN STD_LOGIC; |
|
123 | reset : IN STD_LOGIC; | |
124 |
ctrl : IN STD_LOGIC_VECTOR(2 |
|
124 | ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |
125 |
comp : IN STD_LOGIC_VECTOR(1 |
|
125 | comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
126 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |||
|
127 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |||
|
128 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |||
|
129 | ); | |||
|
130 | END COMPONENT; | |||
|
131 | ||||
|
132 | COMPONENT ALU_V0 IS | |||
|
133 | GENERIC( | |||
|
134 | Arith_en : INTEGER := 1; | |||
|
135 | Logic_en : INTEGER := 1; | |||
|
136 | Input_SZ_1 : INTEGER := 16; | |||
|
137 | Input_SZ_2 : INTEGER := 9 | |||
|
138 | ||||
|
139 | ); | |||
|
140 | PORT( | |||
|
141 | clk : IN STD_LOGIC; | |||
|
142 | reset : IN STD_LOGIC; | |||
|
143 | ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
126 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
|
144 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
127 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); |
|
145 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |
128 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) |
|
146 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |
129 | ); |
|
147 | ); | |
130 | END COMPONENT; |
|
148 | END COMPONENT; | |
131 |
|
149 | |||
132 |
COMPONENT |
|
150 | COMPONENT MAC_V0 IS | |
133 | GENERIC( |
|
151 | GENERIC( | |
134 |
|
|
152 | Input_SZ_A : INTEGER := 8; | |
135 |
|
|
153 | Input_SZ_B : INTEGER := 8 | |
136 | Input_SZ_1 : INTEGER := 16; |
|
|||
137 | Input_SZ_2 : INTEGER := 9 |
|
|||
138 |
|
154 | |||
139 | ); |
|
155 | ); | |
140 | PORT( |
|
156 | PORT( | |
141 | clk : IN STD_LOGIC; |
|
157 | clk : IN STD_LOGIC; | |
142 | reset : IN STD_LOGIC; |
|
158 | reset : IN STD_LOGIC; | |
143 |
|
|
159 | clr_MAC : IN STD_LOGIC; | |
144 |
|
|
160 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
145 |
|
|
161 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
146 |
|
|
162 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
147 | ); |
|
163 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
148 | END COMPONENT; |
|
164 | ); | |
149 |
|
165 | END COMPONENT; | ||
150 | COMPONENT MAC_V0 is |
|
|||
151 | generic( |
|
|||
152 | Input_SZ_A : integer := 8; |
|
|||
153 | Input_SZ_B : integer := 8 |
|
|||
154 |
|
||||
155 | ); |
|
|||
156 | port( |
|
|||
157 | clk : in std_logic; |
|
|||
158 | reset : in std_logic; |
|
|||
159 | clr_MAC : in std_logic; |
|
|||
160 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); |
|
|||
161 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
|||
162 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
|||
163 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
|||
164 | ); |
|
|||
165 | end COMPONENT; |
|
|||
166 |
|
166 | |||
167 | --------------------------------------------------------- |
|
167 | --------------------------------------------------------- | |
168 | -------- // Sélection grace a l'entrée "ctrl" \\ -------- |
|
168 | -------- // Sélection grace a l'entrée "ctrl" \\ -------- | |
169 | --------------------------------------------------------- |
|
169 | --------------------------------------------------------- | |
170 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; |
|
170 | CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; | |
171 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; |
|
171 | CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001"; | |
172 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; |
|
172 | CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010"; | |
173 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; |
|
173 | CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011"; | |
174 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; |
|
174 | CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100"; | |
175 |
|
175 | |||
176 |
|
176 | |||
177 | Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; |
|
177 | CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; | |
178 | Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; |
|
178 | CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001"; | |
179 | Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; |
|
179 | CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010"; | |
180 | Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; |
|
180 | CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011"; | |
181 | Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; |
|
181 | CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100"; | |
182 | --------------------------------------------------------- |
|
182 | --------------------------------------------------------- | |
183 |
|
183 | |||
184 | COMPONENT MAC IS |
|
184 | COMPONENT MAC IS | |
185 | GENERIC( |
|
185 | GENERIC( | |
186 | Input_SZ_A : INTEGER := 8; |
|
186 | Input_SZ_A : INTEGER := 8; | |
187 | Input_SZ_B : INTEGER := 8; |
|
187 | Input_SZ_B : INTEGER := 8; | |
188 | COMP_EN : INTEGER := 0 -- 1 => No Comp |
|
188 | COMP_EN : INTEGER := 0 -- 1 => No Comp | |
189 | ); |
|
189 | ); | |
190 | PORT( |
|
190 | PORT( | |
191 | clk : IN STD_LOGIC; |
|
191 | clk : IN STD_LOGIC; | |
192 | reset : IN STD_LOGIC; |
|
192 | reset : IN STD_LOGIC; | |
193 | clr_MAC : IN STD_LOGIC; |
|
193 | clr_MAC : IN STD_LOGIC; | |
194 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
194 | MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
195 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
195 | Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
196 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
196 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
197 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
197 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
198 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
198 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
199 | ); |
|
199 | ); | |
200 | END COMPONENT; |
|
200 | END COMPONENT; | |
201 |
|
201 | |||
202 |
COMPONENT TwoComplementer |
|
202 | COMPONENT TwoComplementer IS | |
203 | generic( |
|
203 | GENERIC( | |
204 |
Input_SZ : |
|
204 | Input_SZ : INTEGER := 16); | |
205 | port( |
|
205 | PORT( | |
206 |
clk : |
|
206 | clk : IN STD_LOGIC; --! Horloge du composant | |
207 |
reset : |
|
207 | reset : IN STD_LOGIC; --! Reset general du composant | |
208 |
clr : |
|
208 | clr : IN STD_LOGIC; --! Un reset spécifique au programme | |
209 |
TwoComp : |
|
209 | TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément | |
210 |
OP : |
|
210 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée | |
211 |
RES : |
|
211 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non | |
212 | ); |
|
212 | ); | |
213 |
|
|
213 | END COMPONENT; | |
214 |
|
214 | |||
215 | COMPONENT MAC_CONTROLER IS |
|
215 | COMPONENT MAC_CONTROLER IS | |
216 | PORT( |
|
216 | PORT( | |
217 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
217 | ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
218 | MULT : OUT STD_LOGIC; |
|
218 | MULT : OUT STD_LOGIC; | |
219 | ADD : OUT STD_LOGIC; |
|
219 | ADD : OUT STD_LOGIC; | |
220 | -- LOAD_ADDER : out std_logic; |
|
220 | -- LOAD_ADDER : out std_logic; | |
221 | MACMUX_sel : OUT STD_LOGIC; |
|
221 | MACMUX_sel : OUT STD_LOGIC; | |
222 | MACMUX2_sel : OUT STD_LOGIC |
|
222 | MACMUX2_sel : OUT STD_LOGIC | |
223 | ); |
|
223 | ); | |
224 | END COMPONENT; |
|
224 | END COMPONENT; | |
225 |
|
225 | |||
226 | COMPONENT MAC_MUX IS |
|
226 | COMPONENT MAC_MUX IS | |
227 | GENERIC( |
|
227 | GENERIC( | |
228 | Input_SZ_A : INTEGER := 16; |
|
228 | Input_SZ_A : INTEGER := 16; | |
229 | Input_SZ_B : INTEGER := 16 |
|
229 | Input_SZ_B : INTEGER := 16 | |
230 |
|
230 | |||
231 | ); |
|
231 | ); | |
232 | PORT( |
|
232 | PORT( | |
233 | sel : IN STD_LOGIC; |
|
233 | sel : IN STD_LOGIC; | |
234 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
234 | INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
235 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
235 | INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
236 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
236 | INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
237 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
237 | INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
238 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
238 | OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
239 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) |
|
239 | OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) | |
240 | ); |
|
240 | ); | |
241 | END COMPONENT; |
|
241 | END COMPONENT; | |
242 |
|
242 | |||
243 |
|
243 | |||
244 | COMPONENT MAC_MUX2 IS |
|
244 | COMPONENT MAC_MUX2 IS | |
245 | GENERIC(Input_SZ : INTEGER := 16); |
|
245 | GENERIC(Input_SZ : INTEGER := 16); | |
246 | PORT( |
|
246 | PORT( | |
247 | sel : IN STD_LOGIC; |
|
247 | sel : IN STD_LOGIC; | |
248 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
248 | RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
249 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
249 | RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
250 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
250 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |
251 | ); |
|
251 | ); | |
252 | END COMPONENT; |
|
252 | END COMPONENT; | |
253 |
|
253 | |||
254 |
|
254 | |||
255 | COMPONENT MAC_REG IS |
|
255 | COMPONENT MAC_REG IS | |
256 | GENERIC(size : INTEGER := 16); |
|
256 | GENERIC(size : INTEGER := 16); | |
257 | PORT( |
|
257 | PORT( | |
258 | reset : IN STD_LOGIC; |
|
258 | reset : IN STD_LOGIC; | |
259 | clk : IN STD_LOGIC; |
|
259 | clk : IN STD_LOGIC; | |
260 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
260 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
261 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
261 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) | |
262 | ); |
|
262 | ); | |
263 | END COMPONENT; |
|
263 | END COMPONENT; | |
264 |
|
264 | |||
265 |
|
265 | |||
266 | COMPONENT MUX2 IS |
|
266 | COMPONENT MUX2 IS | |
267 | GENERIC(Input_SZ : INTEGER := 16); |
|
267 | GENERIC(Input_SZ : INTEGER := 16); | |
268 | PORT( |
|
268 | PORT( | |
269 | sel : IN STD_LOGIC; |
|
269 | sel : IN STD_LOGIC; | |
270 | IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
270 | IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
271 | IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
271 | IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
272 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
272 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |
273 | ); |
|
273 | ); | |
274 | END COMPONENT; |
|
274 | END COMPONENT; | |
275 |
|
275 | |||
276 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; |
|
276 | TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; | |
277 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; |
|
277 | TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; | |
278 |
|
278 | |||
279 | COMPONENT MUXN |
|
279 | COMPONENT MUXN | |
280 | GENERIC ( |
|
280 | GENERIC ( | |
281 | Input_SZ : INTEGER; |
|
281 | Input_SZ : INTEGER; | |
282 | NbStage : INTEGER); |
|
282 | NbStage : INTEGER); | |
283 | PORT ( |
|
283 | PORT ( | |
284 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); |
|
284 | sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); | |
285 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0); |
|
285 | INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0); | |
286 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
286 | --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
287 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); |
|
287 | RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); | |
288 | END COMPONENT; |
|
288 | END COMPONENT; | |
289 |
|
289 | |||
290 |
|
290 | |||
291 |
|
291 | |||
292 | COMPONENT Multiplier IS |
|
292 | COMPONENT Multiplier IS | |
293 | GENERIC( |
|
293 | GENERIC( | |
294 | Input_SZ_A : INTEGER := 16; |
|
294 | Input_SZ_A : INTEGER := 16; | |
295 | Input_SZ_B : INTEGER := 16 |
|
295 | Input_SZ_B : INTEGER := 16 | |
296 |
|
296 | |||
297 | ); |
|
297 | ); | |
298 | PORT( |
|
298 | PORT( | |
299 | clk : IN STD_LOGIC; |
|
299 | clk : IN STD_LOGIC; | |
300 | reset : IN STD_LOGIC; |
|
300 | reset : IN STD_LOGIC; | |
301 | mult : IN STD_LOGIC; |
|
301 | mult : IN STD_LOGIC; | |
302 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); |
|
302 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); | |
303 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); |
|
303 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); | |
304 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) |
|
304 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) | |
305 | ); |
|
305 | ); | |
306 | END COMPONENT; |
|
306 | END COMPONENT; | |
307 |
|
307 | |||
308 | COMPONENT REG IS |
|
308 | COMPONENT REG IS | |
309 | GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0); |
|
309 | GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0); | |
310 | PORT( |
|
310 | PORT( | |
311 | reset : IN STD_LOGIC; |
|
311 | reset : IN STD_LOGIC; | |
312 | clk : IN STD_LOGIC; |
|
312 | clk : IN STD_LOGIC; | |
313 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); |
|
313 | D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); | |
314 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) |
|
314 | Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) | |
315 | ); |
|
315 | ); | |
316 | END COMPONENT; |
|
316 | END COMPONENT; | |
317 |
|
317 | |||
318 |
|
318 | |||
319 |
|
319 | |||
320 | COMPONENT RShifter IS |
|
320 | COMPONENT RShifter IS | |
321 | GENERIC( |
|
321 | GENERIC( | |
322 | Input_SZ : INTEGER := 16; |
|
322 | Input_SZ : INTEGER := 16; | |
323 | shift_SZ : INTEGER := 4 |
|
323 | shift_SZ : INTEGER := 4 | |
324 | ); |
|
324 | ); | |
325 | PORT( |
|
325 | PORT( | |
326 | clk : IN STD_LOGIC; |
|
326 | clk : IN STD_LOGIC; | |
327 | reset : IN STD_LOGIC; |
|
327 | reset : IN STD_LOGIC; | |
328 | shift : IN STD_LOGIC; |
|
328 | shift : IN STD_LOGIC; | |
329 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); |
|
329 | OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); | |
330 | cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0); |
|
330 | cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0); | |
331 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) |
|
331 | RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) | |
332 | ); |
|
332 | ); | |
333 | END COMPONENT; |
|
333 | END COMPONENT; | |
334 |
|
334 | |||
335 | COMPONENT SYNC_FF |
|
335 | COMPONENT SYNC_FF | |
336 | GENERIC ( |
|
336 | GENERIC ( | |
337 | NB_FF_OF_SYNC : INTEGER); |
|
337 | NB_FF_OF_SYNC : INTEGER); | |
338 | PORT ( |
|
338 | PORT ( | |
339 | clk : IN STD_LOGIC; |
|
339 | clk : IN STD_LOGIC; | |
340 | rstn : IN STD_LOGIC; |
|
340 | rstn : IN STD_LOGIC; | |
341 | A : IN STD_LOGIC; |
|
341 | A : IN STD_LOGIC; | |
342 | A_sync : OUT STD_LOGIC); |
|
342 | A_sync : OUT STD_LOGIC); | |
343 | END COMPONENT; |
|
343 | END COMPONENT; | |
344 |
|
344 | |||
345 | COMPONENT lpp_front_to_level |
|
345 | COMPONENT lpp_front_to_level | |
346 | PORT ( |
|
346 | PORT ( | |
347 | clk : IN STD_LOGIC; |
|
347 | clk : IN STD_LOGIC; | |
348 | rstn : IN STD_LOGIC; |
|
348 | rstn : IN STD_LOGIC; | |
349 | sin : IN STD_LOGIC; |
|
349 | sin : IN STD_LOGIC; | |
350 | sout : OUT STD_LOGIC); |
|
350 | sout : OUT STD_LOGIC); | |
351 | END COMPONENT; |
|
351 | END COMPONENT; | |
352 |
|
352 | |||
353 | COMPONENT lpp_front_detection |
|
353 | COMPONENT lpp_front_detection | |
354 | PORT ( |
|
354 | PORT ( | |
355 | clk : IN STD_LOGIC; |
|
355 | clk : IN STD_LOGIC; | |
356 | rstn : IN STD_LOGIC; |
|
356 | rstn : IN STD_LOGIC; | |
357 | sin : IN STD_LOGIC; |
|
357 | sin : IN STD_LOGIC; | |
358 | sout : OUT STD_LOGIC); |
|
358 | sout : OUT STD_LOGIC); | |
359 | END COMPONENT; |
|
359 | END COMPONENT; | |
360 |
|
360 | |||
361 | COMPONENT lpp_front_positive_detection |
|
361 | COMPONENT lpp_front_positive_detection | |
362 | PORT ( |
|
362 | PORT ( | |
363 | clk : IN STD_LOGIC; |
|
363 | clk : IN STD_LOGIC; | |
364 | rstn : IN STD_LOGIC; |
|
364 | rstn : IN STD_LOGIC; | |
365 | sin : IN STD_LOGIC; |
|
365 | sin : IN STD_LOGIC; | |
366 | sout : OUT STD_LOGIC); |
|
366 | sout : OUT STD_LOGIC); | |
367 | END COMPONENT; |
|
367 | END COMPONENT; | |
368 |
|
368 | |||
369 | --COMPONENT SYNC_VALID_BIT |
|
369 | --COMPONENT SYNC_VALID_BIT | |
370 | -- GENERIC ( |
|
370 | -- GENERIC ( | |
371 | -- NB_FF_OF_SYNC : INTEGER); |
|
371 | -- NB_FF_OF_SYNC : INTEGER); | |
372 | -- PORT ( |
|
372 | -- PORT ( | |
373 | -- clk_in : IN STD_LOGIC; |
|
373 | -- clk_in : IN STD_LOGIC; | |
374 | -- clk_out : IN STD_LOGIC; |
|
374 | -- clk_out : IN STD_LOGIC; | |
375 | -- rstn : IN STD_LOGIC; |
|
375 | -- rstn : IN STD_LOGIC; | |
376 | -- sin : IN STD_LOGIC; |
|
376 | -- sin : IN STD_LOGIC; | |
377 | -- sout : OUT STD_LOGIC); |
|
377 | -- sout : OUT STD_LOGIC); | |
378 | --END COMPONENT; |
|
378 | --END COMPONENT; | |
379 |
|
379 | |||
380 | COMPONENT SYNC_VALID_BIT |
|
380 | COMPONENT SYNC_VALID_BIT | |
381 | GENERIC ( |
|
381 | GENERIC ( | |
382 | NB_FF_OF_SYNC : INTEGER); |
|
382 | NB_FF_OF_SYNC : INTEGER); | |
383 | PORT ( |
|
383 | PORT ( | |
384 | clk_in : IN STD_LOGIC; |
|
384 | clk_in : IN STD_LOGIC; | |
385 | rstn_in : IN STD_LOGIC; |
|
385 | rstn_in : IN STD_LOGIC; | |
386 | clk_out : IN STD_LOGIC; |
|
386 | clk_out : IN STD_LOGIC; | |
387 | rstn_out : IN STD_LOGIC; |
|
387 | rstn_out : IN STD_LOGIC; | |
388 | sin : IN STD_LOGIC; |
|
388 | sin : IN STD_LOGIC; | |
389 | sout : OUT STD_LOGIC); |
|
389 | sout : OUT STD_LOGIC); | |
390 | END COMPONENT; |
|
390 | END COMPONENT; | |
391 |
|
391 | |||
392 | COMPONENT RR_Arbiter_4 |
|
392 | COMPONENT RR_Arbiter_4 | |
393 | PORT ( |
|
393 | PORT ( | |
394 | clk : IN STD_LOGIC; |
|
394 | clk : IN STD_LOGIC; | |
395 | rstn : IN STD_LOGIC; |
|
395 | rstn : IN STD_LOGIC; | |
396 | in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
396 | in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
397 | out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); |
|
397 | out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); | |
398 | END COMPONENT; |
|
398 | END COMPONENT; | |
399 |
|
399 | |||
400 |
COMPONENT Clock_Divider |
|
400 | COMPONENT Clock_Divider IS | |
401 | generic(N :integer := 10); |
|
401 | GENERIC(N : INTEGER := 10); | |
402 | port( |
|
402 | PORT( | |
403 | clk, rst : in std_logic; |
|
403 | clk, rst : IN STD_LOGIC; | |
404 | sclk : out std_logic); |
|
404 | sclk : OUT STD_LOGIC); | |
405 |
|
|
405 | END COMPONENT; | |
|
406 | ||||
|
407 | COMPONENT ramp_generator | |||
|
408 | GENERIC ( | |||
|
409 | DATA_SIZE : INTEGER; | |||
|
410 | VALUE_UNSIGNED_INIT : INTEGER; | |||
|
411 | VALUE_UNSIGNED_INCR : INTEGER; | |||
|
412 | VALUE_UNSIGNED_MASK : INTEGER); | |||
|
413 | PORT ( | |||
|
414 | clk : IN STD_LOGIC; | |||
|
415 | rstn : IN STD_LOGIC; | |||
|
416 | new_data : IN STD_LOGIC; | |||
|
417 | output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0)); | |||
|
418 | END COMPONENT; | |||
406 |
|
419 | |||
407 | END; |
|
420 | END; |
@@ -1,26 +1,27 | |||||
1 | data_type_pkg.vhd |
|
1 | data_type_pkg.vhd | |
2 | general_purpose.vhd |
|
2 | general_purpose.vhd | |
3 | ADDRcntr.vhd |
|
3 | ADDRcntr.vhd | |
4 | ALU.vhd |
|
4 | ALU.vhd | |
5 | Adder.vhd |
|
5 | Adder.vhd | |
6 | Clk_Divider2.vhd |
|
6 | Clk_Divider2.vhd | |
7 | Clk_divider.vhd |
|
7 | Clk_divider.vhd | |
8 | MAC.vhd |
|
8 | MAC.vhd | |
9 | MAC_CONTROLER.vhd |
|
9 | MAC_CONTROLER.vhd | |
10 | MAC_MUX.vhd |
|
10 | MAC_MUX.vhd | |
11 | MAC_MUX2.vhd |
|
11 | MAC_MUX2.vhd | |
12 | MAC_REG.vhd |
|
12 | MAC_REG.vhd | |
13 | MUX2.vhd |
|
13 | MUX2.vhd | |
14 | MUXN.vhd |
|
14 | MUXN.vhd | |
15 | Multiplier.vhd |
|
15 | Multiplier.vhd | |
16 | REG.vhd |
|
16 | REG.vhd | |
17 | SYNC_FF.vhd |
|
17 | SYNC_FF.vhd | |
18 | Shifter.vhd |
|
18 | Shifter.vhd | |
19 | TwoComplementer.vhd |
|
19 | TwoComplementer.vhd | |
20 | Clock_Divider.vhd |
|
20 | Clock_Divider.vhd | |
21 | lpp_front_to_level.vhd |
|
21 | lpp_front_to_level.vhd | |
22 | lpp_front_detection.vhd |
|
22 | lpp_front_detection.vhd | |
23 | lpp_front_positive_detection.vhd |
|
23 | lpp_front_positive_detection.vhd | |
24 | SYNC_VALID_BIT.vhd |
|
24 | SYNC_VALID_BIT.vhd | |
25 | RR_Arbiter_4.vhd |
|
25 | RR_Arbiter_4.vhd | |
26 | general_counter.vhd |
|
26 | general_counter.vhd | |
|
27 | ramp_generator.vhd |
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