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WaveForm Picker : Big Endian Correction
pellion -
r206:82098655f36b em-2013-07-24-vhdlib206 JC
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@@ -238,9 +238,6 BEGIN -- beh
238 data_wen => data_wen,
238 data_wen => data_wen,
239 wdata => wdata);
239 wdata => wdata);
240
240
241 --time_ren <= (OTHERS => '1');
242 --data_ren <= (OTHERS => '1');
243
244 pp_waveform_dma_1: lpp_waveform_dma
241 pp_waveform_dma_1: lpp_waveform_dma
245 GENERIC MAP (
242 GENERIC MAP (
246 data_size => data_size,
243 data_size => data_size,
@@ -256,14 +253,6 BEGIN -- beh
256 data => rdata,
253 data => rdata,
257 data_data_ren => data_ren,
254 data_data_ren => data_ren,
258 data_time_ren => time_ren,
255 data_time_ren => time_ren,
259 --data_f0_in => data_f0_out,
260 --data_f1_in => data_f1_out,
261 --data_f2_in => data_f2_out,
262 --data_f3_in => data_f3_out,
263 --data_f0_in_valid => data_f0_out_valid,
264 --data_f1_in_valid => data_f1_out_valid,
265 --data_f2_in_valid => data_f2_out_valid,
266 --data_f3_in_valid => data_f3_out_valid,
267 nb_burst_available => nb_burst_available,
256 nb_burst_available => nb_burst_available,
268 status_full => status_full,
257 status_full => status_full,
269 status_full_ack => status_full_ack,
258 status_full_ack => status_full_ack,
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@@ -122,6 +122,8 ARCHITECTURE Behavioral OF lpp_waveform_
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 SIGNAL send_16_3_time : STD_LOGIC;
123 SIGNAL send_16_3_time : STD_LOGIC;
124 SIGNAL count_send_time : INTEGER;
124 SIGNAL count_send_time : INTEGER;
125 -----------------------------------------------------------------------------
126 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
125 BEGIN
127 BEGIN
126
128
127 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
@@ -174,18 +176,6 BEGIN
174 time_already_send(2) WHEN data_ready(2) = '1' ELSE
176 time_already_send(2) WHEN data_ready(2) = '1' ELSE
175 time_already_send(3);
177 time_already_send(3);
176
178
177
178 --send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
179 -- send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
180 -- send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
181 -- send_16_3_time_reg(9) ;
182
183 --all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
184 -- send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
185 -- send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
186 -- send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
187 --END GENERATE all_send_16_3;
188
189 -- DMA control
179 -- DMA control
190 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
180 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
191 BEGIN -- PROCESS DMAWriteBurst_p
181 BEGIN -- PROCESS DMAWriteBurst_p
@@ -199,11 +189,6 BEGIN
199 data_send <= '0';
189 data_send <= '0';
200 time_send <= '0';
190 time_send <= '0';
201 time_write <= '0';
191 time_write <= '0';
202 --send_16_3_time <= "001";
203 --send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
204 --send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
205 --send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
206 --send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
207
192
208 count_send_time <= 0;
193 count_send_time <= 0;
209 ELSIF HCLK'EVENT AND HCLK = '1' THEN
194 ELSIF HCLK'EVENT AND HCLK = '1' THEN
@@ -223,56 +208,9 BEGIN
223 state <= IDLE;
208 state <= IDLE;
224 ELSE
209 ELSE
225 sel_data <= sel_data_s;
210 sel_data <= sel_data_s;
226 --send_16_3_time_reg <= send_16_3_time_reg_s;
227 --IF send_16_3_time = '1' THEN
228 -- state <= SEND_TIME_0;
229 --ELSE
230 -- state <= SEND_5_TIME;
231 --END IF;
232 state <= SEND_5_TIME;
211 state <= SEND_5_TIME;
233 END IF;
212 END IF;
234
213
235 --WHEN SEND_TIME_0 =>
236 -- time_select <= '1';
237 -- IF time_already_send_s = '0' THEN
238 -- time_send <= '1';
239 -- state <= WAIT_TIME_0;
240 -- ELSE
241 -- time_send <= '0';
242 -- state <= SEND_TIME_1;
243 -- END IF;
244 -- time_fifo_ren <= '0';
245
246 --WHEN WAIT_TIME_0 =>
247 -- time_fifo_ren <= '1';
248 -- update <= "00";
249 -- time_send <= '0';
250 -- IF time_send_ok = '1' OR time_send_ko = '1' THEN
251 -- update <= "01";
252 -- state <= SEND_TIME_1;
253 -- END IF;
254
255 --WHEN SEND_TIME_1 =>
256 -- time_select <= '1';
257 -- IF time_already_send_s = '0' THEN
258 -- time_send <= '1';
259 -- state <= WAIT_TIME_1;
260 -- ELSE
261 -- time_send <= '0';
262 -- state <= SEND_5_TIME;
263 -- END IF;
264 -- time_fifo_ren <= '0';
265
266 --WHEN WAIT_TIME_1 =>
267 -- time_fifo_ren <= '1';
268 -- update <= "00";
269 -- time_send <= '0';
270 -- IF time_send_ok = '1' OR time_send_ko = '1' THEN
271 -- time_write <= '1';
272 -- update <= "01";
273 -- state <= SEND_5_TIME;
274 -- END IF;
275
276 WHEN SEND_5_TIME =>
214 WHEN SEND_5_TIME =>
277 update <= "00";
215 update <= "00";
278 time_select <= '1';
216 time_select <= '1';
@@ -329,6 +267,8 BEGIN
329 -----------------------------------------------------------------------------
267 -----------------------------------------------------------------------------
330 -- SEND 16 word by DMA (in burst mode)
268 -- SEND 16 word by DMA (in burst mode)
331 -----------------------------------------------------------------------------
269 -----------------------------------------------------------------------------
270 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
271
332 lpp_dma_send_16word_1 : lpp_dma_send_16word
272 lpp_dma_send_16word_1 : lpp_dma_send_16word
333 PORT MAP (
273 PORT MAP (
334 HCLK => HCLK,
274 HCLK => HCLK,
@@ -338,7 +278,7 BEGIN
338
278
339 send => data_send,
279 send => data_send,
340 address => data_address,
280 address => data_address,
341 data => data,
281 data => data_2_halfword,
342 ren => data_fifo_ren,
282 ren => data_fifo_ren,
343 send_ok => data_send_ok,
283 send_ok => data_send_ok,
344 send_ko => data_send_ko);
284 send_ko => data_send_ko);
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