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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
48
49 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
51
52 ################## project specific targets ##########################
53
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1 vcom -quiet -93 -work work tb.vhd
2
3 vsim work.testbench
4
5 log -r *
6
7 do wave.do
8
9 run -all
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
6
7 LIBRARY lpp;
8 USE lpp.lpp_memory.ALL;
9 USE lpp.iir_filter.ALL;
10
11
12 ENTITY testbench IS
13 END;
14
15 ARCHITECTURE behav OF testbench IS
16
17 -----------------------------------------------------------------------------
18 -- Common signal
19 SIGNAL clk : STD_LOGIC := '0';
20 SIGNAL rstn : STD_LOGIC := '0';
21 SIGNAL run : STD_LOGIC := '0';
22
23 -----------------------------------------------------------------------------
24
25 SIGNAL full_almost : STD_LOGIC;
26 SIGNAL full : STD_LOGIC;
27 SIGNAL data_wen : STD_LOGIC;
28 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
29
30 SIGNAL empty : STD_LOGIC;
31 SIGNAL data_ren : STD_LOGIC;
32 SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
33 SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0);
34
35 SIGNAL empty_reg : STD_LOGIC;
36 SIGNAL full_reg : STD_LOGIC;
37
38 -----------------------------------------------------------------------------
39 TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL data_in : DATA_CHANNEL;
41
42 -----------------------------------------------------------------------------
43 CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE
44 CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0;
45 SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
46 --
47 SIGNAL rand_ren : STD_LOGIC;
48 SIGNAL rand_wen : STD_LOGIC;
49
50 SIGNAL pointer_read : INTEGER;
51 SIGNAL pointer_write : INTEGER := 0;
52
53 SIGNAL error_now : STD_LOGIC;
54 SIGNAL error_new : STD_LOGIC;
55
56 SIGNAL read_stop : STD_LOGIC;
57 BEGIN
58
59
60 all_J : FOR J IN 0 TO 127 GENERATE
61 data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32));
62 END GENERATE all_J;
63
64
65 -----------------------------------------------------------------------------
66 lpp_fifo_1 : lpp_fifo
67 GENERIC MAP (
68 tech => 0,
69 Mem_use => use_CEL,
70 DataSz => 32,
71 AddrSz => 8)
72 PORT MAP (
73 clk => clk,
74 rstn => rstn,
75 reUse => '0',
76 ren => data_ren,
77 rdata => data_out,
78 wen => data_wen,
79 wdata => wdata,
80 empty => empty,
81 full => full,
82 almost_full => full_almost);
83
84 -----------------------------------------------------------------------------
85
86
87
88 -----------------------------------------------------------------------------
89 -- READ
90 -----------------------------------------------------------------------------
91 PROCESS (clk, rstn)
92 BEGIN -- PROCESS
93 IF rstn = '0' THEN -- asynchronous reset (active low)
94 empty_reg <= '1';
95 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
96 empty_reg <= empty;
97 END IF;
98 END PROCESS;
99
100 PROCESS (clk, rstn)
101 BEGIN -- PROCESS
102 IF rstn = '0' THEN -- asynchronous reset (active low)
103 data_out_obs <= (OTHERS => '0');
104
105 pointer_read <= 0;
106 error_now <= '0';
107 error_new <= '0';
108
109 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
110 error_now <= '0';
111 IF empty_reg = '0' THEN
112 IF data_ren = '0' THEN
113 --IF data_ren_and_not_empty = '0' THEN
114 error_new <= '0';
115 data_out_obs <= data_out;
116
117 IF pointer_read < 127 THEN
118 pointer_read <= pointer_read + 1;
119 ELSE
120 pointer_read <= 0;
121 END IF;
122
123 IF data_out /= data_in(pointer_read) THEN
124 error_now <= '1';
125 error_new <= '1';
126 END IF;
127 END IF;
128
129 END IF;
130 END IF;
131 END PROCESS;
132 -----------------------------------------------------------------------------
133
134
135
136
137 -----------------------------------------------------------------------------
138 -- WRITE
139 -----------------------------------------------------------------------------
140 PROCESS (clk, rstn)
141 BEGIN -- PROCESS
142 IF rstn = '0' THEN -- asynchronous reset (active low)
143 full_reg <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
145 full_reg <= full;
146 END IF;
147 END PROCESS;
148
149 proc_verif : PROCESS (clk, rstn)
150 BEGIN -- PROCESS proc_verif
151 IF rstn = '0' THEN -- asynchronous reset (active low)
152 pointer_write <= 0;
153 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
154 IF data_wen = '0' THEN
155 IF full_reg = '0' THEN
156 IF pointer_write < 127 THEN
157 pointer_write <= pointer_write+1;
158 ELSE
159 pointer_write <= 0;
160 END IF;
161 END IF;
162 END IF;
163 END IF;
164 END PROCESS proc_verif;
165
166 wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X');
167 -----------------------------------------------------------------------------
168
169
170
171 -----------------------------------------------------------------------------
172 clk <= NOT clk AFTER 5 ns; -- 100 MHz
173 -----------------------------------------------------------------------------
174 WaveGen_Proc : PROCESS
175 BEGIN
176 -- insert signal assignments here
177 WAIT UNTIL clk = '1';
178 read_stop <= '0';
179 rstn <= '0';
180 run <= '0';
181 WAIT UNTIL clk = '1';
182 WAIT UNTIL clk = '1';
183 WAIT UNTIL clk = '1';
184 rstn <= '1';
185 WAIT UNTIL clk = '1';
186 WAIT UNTIL clk = '1';
187 WAIT UNTIL clk = '1';
188 WAIT UNTIL clk = '1';
189 WAIT UNTIL clk = '1';
190 run <= '1';
191 WAIT UNTIL clk = '1';
192 WAIT UNTIL clk = '1';
193 WAIT UNTIL clk = '1';
194 WAIT UNTIL clk = '1';
195 WAIT FOR 10 us;
196 read_stop <= '1';
197 WAIT FOR 10 us;
198 read_stop <= '0';
199 WAIT FOR 80 us;
200 REPORT "*** END simulation ***" SEVERITY failure;
201 WAIT;
202 END PROCESS WaveGen_Proc;
203 -----------------------------------------------------------------------------
204
205
206
207 -----------------------------------------------------------------------------
208 -- RANDOM GENERATOR
209 -----------------------------------------------------------------------------
210 PROCESS (clk, rstn)
211 VARIABLE seed1, seed2 : POSITIVE;
212 VARIABLE rand1 : REAL;
213 VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
214 BEGIN -- PROCESS
215 IF rstn = '0' THEN -- asynchronous reset (active low)
216 random_vector <= (OTHERS => '0');
217 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
218 UNIFORM(seed1, seed2, rand1);
219 RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
220 to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
221 RANDOM_VECTOR_VAR'LENGTH)
222 );
223 random_vector <= RANDOM_VECTOR_VAR;
224 END IF;
225 END PROCESS;
226 -----------------------------------------------------------------------------
227 rand_wen <= random_vector(1);
228 rand_ren <= random_vector(0);
229 -----------------------------------------------------------------------------
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 data_wen <= '1';
234 data_ren <= '1';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 data_wen <= rand_wen;
237 IF read_stop = '0' THEN
238 data_ren <= rand_ren;
239 ELSE
240 data_ren <= '1';
241 END IF;
242 END IF;
243 END PROCESS;
244 -----------------------------------------------------------------------------
245
246
247
248 END;
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1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group COMMON /testbench/clk
4 add wave -noupdate -expand -group COMMON /testbench/rstn
5 add wave -noupdate -expand -group COMMON /testbench/run
6 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost
7 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full
8 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen
9 add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata
10 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty
11 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren
12 add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out
13 add wave -noupdate -radix hexadecimal /testbench/data_out_obs
14 add wave -noupdate /testbench/pointer_read
15 add wave -noupdate /testbench/pointer_write
16 add wave -noupdate /testbench/error_now
17 add wave -noupdate /testbench/error_new
18 add wave -noupdate /testbench/read_stop
19 TreeUpdate [SetDefaultTree]
20 WaveRestoreCursors {{Cursor 1} {56085000 ps} 0}
21 configure wave -namecolwidth 510
22 configure wave -valuecolwidth 172
23 configure wave -justifyvalue left
24 configure wave -signalnamewidth 0
25 configure wave -snapdistance 10
26 configure wave -datasetprefix 0
27 configure wave -rowmargin 4
28 configure wave -childrowmargin 2
29 configure wave -gridoffset 0
30 configure wave -gridperiod 1
31 configure wave -griddelta 40
32 configure wave -timeline 0
33 configure wave -timelineunits ns
34 update
35 WaveRestoreZoom {0 ps} {105131250 ps}
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.std_logic_1164.ALL;
24 24 USE IEEE.numeric_std.ALL;
25 25 LIBRARY lpp;
26 26 USE lpp.lpp_memory.ALL;
27 27 USE lpp.iir_filter.ALL;
28 28 USE lpp.lpp_waveform_pkg.ALL;
29 29
30 30 LIBRARY techmap;
31 31 USE techmap.gencomp.ALL;
32 32
33 33 ENTITY lpp_waveform_fifo_headreg IS
34 34 GENERIC(
35 35 tech : INTEGER := 0
36 36 );
37 37 PORT(
38 38 clk : IN STD_LOGIC;
39 39 rstn : IN STD_LOGIC;
40 40 ---------------------------------------------------------------------------
41 41 run : IN STD_LOGIC;
42 42 ---------------------------------------------------------------------------
43 43 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
44 44 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 45 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 46 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
47 47 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
48 48 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
49 49 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
50 50 ---------------------------------------------------------------------------
51 51 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 52 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
53 53 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
54 54 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 55 );
56 56 END ENTITY;
57 57
58 58
59 59 ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS
60 60 SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
61 61 SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 62 SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 63 SIGNAL one_ren_and_notEmpty : STD_LOGIC;
64 64 SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 65 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
66 66 SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 67 SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 68 SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 BEGIN
71 71
72 72 -----------------------------------------------------------------------------
73 73 -- DATA_REN_FIFO
74 74 -----------------------------------------------------------------------------
75 75 i_data_ren <= s_ren;
76
76 77 PROCESS (clk, rstn)
77 78 BEGIN
78 79 IF rstn = '0' THEN
79 80 s_ren_reg <= (OTHERS => '1');
80 81 ELSIF clk'EVENT AND clk = '1' THEN
81 82 IF run = '1' THEN
82 83 s_ren_reg <= s_ren;
83 84 ELSE
84 85 s_ren_reg <= (OTHERS => '1');
85 86 END IF;
86 87 END IF;
87 88 END PROCESS;
88 89
89 90 s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE
90 91 NOT ((NOT i_empty(0)) AND (NOT reg_full(0)));
91 s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
92 '1' WHEN s_ren(0) = '0' ELSE
92 s_ren(1) <= '1' WHEN s_ren(0) = '0' ELSE
93 o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
93 94 NOT ((NOT i_empty(1)) AND (NOT reg_full(1)));
94 s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
95 '1' WHEN s_ren(0) = '0' ELSE
95 s_ren(2) <= '1' WHEN s_ren(0) = '0' ELSE
96 96 '1' WHEN s_ren(1) = '0' ELSE
97 o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
97 98 NOT ((NOT i_empty(2)) AND (NOT reg_full(2)));
98 s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
99 '1' WHEN s_ren(0) = '0' ELSE
99 s_ren(3) <= '1' WHEN s_ren(0) = '0' ELSE
100 100 '1' WHEN s_ren(1) = '0' ELSE
101 101 '1' WHEN s_ren(2) = '0' ELSE
102 o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
102 103 NOT ((NOT i_empty(3)) AND (NOT reg_full(3)));
103 104 -----------------------------------------------------------------------------
104 105 all_ren : FOR I IN 3 DOWNTO 0 GENERATE
105 106 ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I));
106 107 END GENERATE all_ren;
107 108 one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1';
108 109
109 110 -----------------------------------------------------------------------------
110 111 -- DATA
111 112 -----------------------------------------------------------------------------
112 113 o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0;
113 114 o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1;
114 115 o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2;
115 116 o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3;
116 117
117 118 PROCESS (clk, rstn)
118 119 BEGIN
119 120 IF rstn = '0' THEN
120 121 s_rdata_0 <= (OTHERS => '0');
121 122 s_rdata_1 <= (OTHERS => '0');
122 123 s_rdata_2 <= (OTHERS => '0');
123 124 s_rdata_3 <= (OTHERS => '0');
124 125 ELSIF clk'EVENT AND clk = '1' THEN
125 126 IF run = '1' THEN
126 127 IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
127 128 IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
128 129 IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
129 130 IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
130 131 ELSE
131 s_rdata_0 <= (OTHERS => '0');
132 s_rdata_1 <= (OTHERS => '0');
133 s_rdata_2 <= (OTHERS => '0');
134 s_rdata_3 <= (OTHERS => '0');
132 s_rdata_0 <= (OTHERS => '0');
133 s_rdata_1 <= (OTHERS => '0');
134 s_rdata_2 <= (OTHERS => '0');
135 s_rdata_3 <= (OTHERS => '0');
135 136 END IF;
136 137 END IF;
137 138 END PROCESS;
138 139
139 140 all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE
140 141 PROCESS (clk, rstn)
141 142 BEGIN
142 143 IF rstn = '0' THEN
143 144 reg_full(I) <= '0';
144 145 ELSIF clk'EVENT AND clk = '1' THEN
145 146 -- IF s_ren_reg(I) = '0' THEN
146 147 IF run = '1' THEN
147 148 IF s_ren(I) = '0' THEN
148 149 reg_full(I) <= '1';
149 150 ELSIF o_data_ren(I) = '0' THEN
150 151 reg_full(I) <= '0';
151 152 END IF;
152 153 ELSE
153 154 reg_full(I) <= '0';
154 155 END IF;
155 156 END IF;
156 157 END PROCESS;
157 158 END GENERATE all_reg_full;
158 159
159 160 -----------------------------------------------------------------------------
160 161 -- EMPTY
161 162 -----------------------------------------------------------------------------
162 163 o_empty <= NOT reg_full;
163 164
164 165 -----------------------------------------------------------------------------
165 166 -- EMPTY_ALMOST
166 167 -----------------------------------------------------------------------------
167 168 o_empty_almost <= s_empty_almost;
168 169
169 170 all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE
170 171 PROCESS (clk, rstn)
171 172 BEGIN -- PROCESS
172 173 IF rstn = '0' THEN -- asynchronous reset (active low)
173 174 s_empty_almost(I) <= '1';
174 175 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
175 176 IF run = '1' THEN
176 177 IF s_ren(I) = '0' THEN
177 178 s_empty_almost(I) <= i_empty_almost(I);
178 179 ELSIF o_data_ren(I) = '0' THEN
179 180 s_empty_almost(I) <= '1';
180 181 ELSE
181 182 IF i_empty_almost(I) = '0' THEN
182 183 s_empty_almost(I) <= '0';
183 184 END IF;
184 185 END IF;
185 186 ELSE
186 187 s_empty_almost(I) <= '1';
187 188 END IF;
188 189 END IF;
189 190 END PROCESS;
190 191 END GENERATE all_empty_almost;
191 192
192 193 END ARCHITECTURE;
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