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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY lpp;
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USE lpp.lpp_memory.ALL;
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USE lpp.iir_filter.ALL;
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ENTITY testbench IS
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END;
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ARCHITECTURE behav OF testbench IS
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-----------------------------------------------------------------------------
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-- Common signal
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL rstn : STD_LOGIC := '0';
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SIGNAL run : STD_LOGIC := '0';
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-----------------------------------------------------------------------------
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SIGNAL full_almost : STD_LOGIC;
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SIGNAL full : STD_LOGIC;
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SIGNAL data_wen : STD_LOGIC;
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SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL empty : STD_LOGIC;
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SIGNAL data_ren : STD_LOGIC;
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SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL empty_reg : STD_LOGIC;
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SIGNAL full_reg : STD_LOGIC;
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-----------------------------------------------------------------------------
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TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL data_in : DATA_CHANNEL;
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-----------------------------------------------------------------------------
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CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE
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CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0;
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SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
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--
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SIGNAL rand_ren : STD_LOGIC;
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SIGNAL rand_wen : STD_LOGIC;
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SIGNAL pointer_read : INTEGER;
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SIGNAL pointer_write : INTEGER := 0;
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SIGNAL error_now : STD_LOGIC;
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SIGNAL error_new : STD_LOGIC;
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SIGNAL read_stop : STD_LOGIC;
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BEGIN
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all_J : FOR J IN 0 TO 127 GENERATE
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data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32));
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END GENERATE all_J;
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-----------------------------------------------------------------------------
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lpp_fifo_1 : lpp_fifo
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GENERIC MAP (
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tech => 0,
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Mem_use => use_CEL,
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DataSz => 32,
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AddrSz => 8)
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PORT MAP (
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clk => clk,
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rstn => rstn,
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reUse => '0',
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ren => data_ren,
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rdata => data_out,
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wen => data_wen,
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wdata => wdata,
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empty => empty,
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full => full,
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almost_full => full_almost);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- READ
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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empty_reg <= '1';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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empty_reg <= empty;
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END IF;
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END PROCESS;
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data_out_obs <= (OTHERS => '0');
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pointer_read <= 0;
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error_now <= '0';
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error_new <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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error_now <= '0';
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IF empty_reg = '0' THEN
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IF data_ren = '0' THEN
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--IF data_ren_and_not_empty = '0' THEN
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error_new <= '0';
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data_out_obs <= data_out;
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IF pointer_read < 127 THEN
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pointer_read <= pointer_read + 1;
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ELSE
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pointer_read <= 0;
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END IF;
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IF data_out /= data_in(pointer_read) THEN
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error_now <= '1';
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error_new <= '1';
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- WRITE
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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full_reg <= '0';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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full_reg <= full;
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END IF;
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END PROCESS;
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proc_verif : PROCESS (clk, rstn)
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BEGIN -- PROCESS proc_verif
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IF rstn = '0' THEN -- asynchronous reset (active low)
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pointer_write <= 0;
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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IF data_wen = '0' THEN
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IF full_reg = '0' THEN
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IF pointer_write < 127 THEN
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pointer_write <= pointer_write+1;
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ELSE
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pointer_write <= 0;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS proc_verif;
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wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X');
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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clk <= NOT clk AFTER 5 ns; -- 100 MHz
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-----------------------------------------------------------------------------
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WaveGen_Proc : PROCESS
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BEGIN
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-- insert signal assignments here
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WAIT UNTIL clk = '1';
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read_stop <= '0';
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rstn <= '0';
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run <= '0';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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rstn <= '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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run <= '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT UNTIL clk = '1';
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WAIT FOR 10 us;
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read_stop <= '1';
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WAIT FOR 10 us;
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read_stop <= '0';
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WAIT FOR 80 us;
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REPORT "*** END simulation ***" SEVERITY failure;
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WAIT;
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END PROCESS WaveGen_Proc;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- RANDOM GENERATOR
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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VARIABLE seed1, seed2 : POSITIVE;
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VARIABLE rand1 : REAL;
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VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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random_vector <= (OTHERS => '0');
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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UNIFORM(seed1, seed2, rand1);
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RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
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to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
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RANDOM_VECTOR_VAR'LENGTH)
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);
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random_vector <= RANDOM_VECTOR_VAR;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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rand_wen <= random_vector(1);
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rand_ren <= random_vector(0);
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-----------------------------------------------------------------------------
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PROCESS (clk, rstn)
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BEGIN -- PROCESS
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IF rstn = '0' THEN -- asynchronous reset (active low)
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data_wen <= '1';
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data_ren <= '1';
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ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
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data_wen <= rand_wen;
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IF read_stop = '0' THEN
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data_ren <= rand_ren;
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ELSE
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data_ren <= '1';
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END IF;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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END;
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