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WF picker IP + Reg...
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r167:7b2690121175 merge JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity ReUse_CTRLR is
27 port(
28 clk : in std_logic;
29 reset : in std_logic;
30
31 SetReUse : in std_logic_vector(4 downto 0);
32 Statu : in std_logic_vector(3 downto 0);
33
34 ReUse : out std_logic_vector(4 downto 0)
35 );
36 end entity;
37
38
39 architecture ar_ReUse_CTRLR of ReUse_CTRLR is
40
41 signal ResetReUse : std_logic_vector(4 downto 0);
42 signal MatrixParam : integer;
43 signal MatrixParam_Reg : integer;
44
45 begin
46
47
48
49 process (clk,reset)
50 -- variable MatrixParam : integer;
51 begin
52 -- MatrixParam := to_integer(unsigned(Statu));
53
54 if(reset='0')then
55 ResetReUse <= (others => '1');
56 MatrixParam_Reg <= 0;
57
58
59 elsif(clk' event and clk='1')then
60 MatrixParam_Reg <= MatrixParam;
61
62 if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11
63 ResetReUse(0) <= '0';
64 elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12
65 ResetReUse(1) <= '0';
66 elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13
67 ResetReUse(2) <= '0';
68 elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14
69 ResetReUse(3) <= '0';
70 elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15
71 ResetReUse(4) <= '0';
72 end if;
73
74 end if;
75 end process;
76
77 MatrixParam <= to_integer(unsigned(Statu));
78 ReUse <= SetReUse and ResetReUse;
79
80 end architecture; No newline at end of file
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
15
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
22 ENTITY lpp_top_lfr_wf_picker IS
23 GENERIC (
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 4;
26 paddr : INTEGER := 4;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 0;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10
35 );
36 PORT (
37 -- ADS7886
38 cnv_run : IN STD_LOGIC;
39 cnv : OUT STD_LOGIC;
40 sck : OUT STD_LOGIC;
41 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
42 --
43 cnv_clk : IN STD_LOGIC;
44 cnv_rstn : IN STD_LOGIC;
45
46 -- AMBA AHB system signals
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49
50 -- AMBA APB Slave Interface
51 apbi : IN apb_slv_in_type;
52 apbo : OUT apb_slv_out_type;
53
54 -- AMBA AHB Master Interface
55 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57
58 --
59 coarse_time_0 : IN STD_LOGIC;
60
61 --
62 data_shaping_BW : OUT STD_LOGIC
63 );
64 END lpp_top_lfr_wf_picker;
65
66 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
67
68 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
69 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
72 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
79 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
80 SIGNAL status_error_bad_component_error : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
83 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
88 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92 SIGNAL data_shaping_SP0 : STD_LOGIC;
93 SIGNAL data_shaping_SP1 : STD_LOGIC;
94 SIGNAL data_shaping_R0 : STD_LOGIC;
95 SIGNAL data_shaping_R1 : STD_LOGIC;
96 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
99 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
100 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
101 SIGNAL enable_f0 : STD_LOGIC;
102 SIGNAL enable_f1 : STD_LOGIC;
103 SIGNAL enable_f2 : STD_LOGIC;
104 SIGNAL enable_f3 : STD_LOGIC;
105 SIGNAL burst_f0 : STD_LOGIC;
106 SIGNAL burst_f1 : STD_LOGIC;
107 SIGNAL burst_f2 : STD_LOGIC;
108 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112
113 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
114 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
116 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
120 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
121
122
123 BEGIN
124
125 lpp_top_apbreg_1: lpp_top_apbreg
126 GENERIC MAP (
127 nb_burst_available_size => nb_burst_available_size,
128 nb_snapshot_param_size => nb_snapshot_param_size,
129 delta_snapshot_size => delta_snapshot_size,
130 delta_f2_f0_size => delta_f2_f0_size,
131 delta_f2_f1_size => delta_f2_f1_size,
132 pindex => pindex,
133 paddr => paddr,
134 pmask => pmask,
135 pirq => pirq)
136 PORT MAP (
137 HCLK => HCLK,
138 HRESETn => HRESETn,
139 apbi => apbi,
140 apbo => apbo,
141
142 ready_matrix_f0_0 => ready_matrix_f0_0,
143 ready_matrix_f0_1 => ready_matrix_f0_1,
144 ready_matrix_f1 => ready_matrix_f1,
145 ready_matrix_f2 => ready_matrix_f2,
146 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
147 error_bad_component_error => error_bad_component_error,
148 debug_reg => debug_reg,
149 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
150 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
151 status_ready_matrix_f1 => status_ready_matrix_f1,
152 status_ready_matrix_f2 => status_ready_matrix_f2,
153 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
154 status_error_bad_component_error => status_error_bad_component_error,
155 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
156 config_active_interruption_onError => config_active_interruption_onError,
157 addr_matrix_f0_0 => addr_matrix_f0_0,
158 addr_matrix_f0_1 => addr_matrix_f0_1,
159 addr_matrix_f1 => addr_matrix_f1,
160 addr_matrix_f2 => addr_matrix_f2,
161
162 status_full => status_full,
163 status_full_ack => status_full_ack,
164 status_full_err => status_full_err,
165 status_new_err => status_new_err,
166 data_shaping_BW => data_shaping_BW,
167 data_shaping_SP0 => data_shaping_SP0,
168 data_shaping_SP1 => data_shaping_SP1,
169 data_shaping_R0 => data_shaping_R0,
170 data_shaping_R1 => data_shaping_R1,
171 delta_snapshot => delta_snapshot,
172 delta_f2_f1 => delta_f2_f1,
173 delta_f2_f0 => delta_f2_f0,
174 nb_burst_available => nb_burst_available,
175 nb_snapshot_param => nb_snapshot_param,
176 enable_f0 => enable_f0,
177 enable_f1 => enable_f1,
178 enable_f2 => enable_f2,
179 enable_f3 => enable_f3,
180 burst_f0 => burst_f0,
181 burst_f1 => burst_f1,
182 burst_f2 => burst_f2,
183 addr_data_f0 => addr_data_f0,
184 addr_data_f1 => addr_data_f1,
185 addr_data_f2 => addr_data_f2,
186 addr_data_f3 => addr_data_f3);
187
188 lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip
189 GENERIC MAP (
190 hindex => hindex,
191 nb_burst_available_size => nb_burst_available_size,
192 nb_snapshot_param_size => nb_snapshot_param_size,
193 delta_snapshot_size => delta_snapshot_size,
194 delta_f2_f0_size => delta_f2_f0_size,
195 delta_f2_f1_size => delta_f2_f1_size,
196 tech => tech)
197 PORT MAP (
198 cnv_run => cnv_run,
199 cnv => cnv,
200 sck => sck,
201 sdo => sdo,
202 cnv_clk => cnv_clk,
203 cnv_rstn => cnv_rstn,
204
205 clk => HCLK,
206 rstn => HRESETn,
207
208 sample_f0_wen => sample_f0_wen,
209 sample_f0_wdata => sample_f0_wdata,
210 sample_f1_wen => sample_f1_wen,
211 sample_f1_wdata => sample_f1_wdata,
212 sample_f2_wen => sample_f2_wen,
213 sample_f2_wdata => sample_f2_wdata,
214 sample_f3_wen => sample_f3_wen,
215 sample_f3_wdata => sample_f3_wdata,
216 AHB_Master_In => AHB_Master_In,
217 AHB_Master_Out => AHB_Master_Out,
218 coarse_time_0 => coarse_time_0,
219 data_shaping_SP0 => data_shaping_SP0,
220 data_shaping_SP1 => data_shaping_SP1,
221 data_shaping_R0 => data_shaping_R0,
222 data_shaping_R1 => data_shaping_R1,
223 delta_snapshot => delta_snapshot,
224 delta_f2_f1 => delta_f2_f1,
225 delta_f2_f0 => delta_f2_f0,
226 enable_f0 => enable_f0,
227 enable_f1 => enable_f1,
228 enable_f2 => enable_f2,
229 enable_f3 => enable_f3,
230 burst_f0 => burst_f0,
231 burst_f1 => burst_f1,
232 burst_f2 => burst_f2,
233 nb_burst_available => nb_burst_available,
234 nb_snapshot_param => nb_snapshot_param,
235 status_full => status_full,
236 status_full_ack => status_full_ack,
237 status_full_err => status_full_err,
238 status_new_err => status_new_err,
239 addr_data_f0 => addr_data_f0,
240 addr_data_f1 => addr_data_f1,
241 addr_data_f2 => addr_data_f2,
242 addr_data_f3 => addr_data_f3);
243 END tb;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
14
15 LIBRARY grlib;
16 USE grlib.amba.ALL;
17 USE grlib.stdlib.ALL;
18 USE grlib.devices.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
20
21 ENTITY lpp_top_lfr_wf_picker_ip IS
22 GENERIC(
23 hindex : INTEGER := 2;
24 nb_burst_available_size : INTEGER := 11;
25 nb_snapshot_param_size : INTEGER := 11;
26 delta_snapshot_size : INTEGER := 16;
27 delta_f2_f0_size : INTEGER := 10;
28 delta_f2_f1_size : INTEGER := 10;
29 tech : INTEGER := 0
30 );
31 PORT (
32 -- ADS7886
33 cnv_run : IN STD_LOGIC;
34 cnv : OUT STD_LOGIC;
35 sck : OUT STD_LOGIC;
36 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
37 --
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
41 clk : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
43 --
44 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
45 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
46 --
47 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
48 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
49 --
50 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
51 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
52 --
53 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
54 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59
60 coarse_time_0 : IN STD_LOGIC;
61
62 --config
63 data_shaping_SP0 : IN STD_LOGIC;
64 data_shaping_SP1 : IN STD_LOGIC;
65 data_shaping_R0 : IN STD_LOGIC;
66 data_shaping_R1 : IN STD_LOGIC;
67
68 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
69 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
70 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
71
72 enable_f0 : IN STD_LOGIC;
73 enable_f1 : IN STD_LOGIC;
74 enable_f2 : IN STD_LOGIC;
75 enable_f3 : IN STD_LOGIC;
76
77 burst_f0 : IN STD_LOGIC;
78 burst_f1 : IN STD_LOGIC;
79 burst_f2 : IN STD_LOGIC;
80
81 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
82 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
83 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
84 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
87
88 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 );
93 END lpp_top_lfr_wf_picker_ip;
94
95 ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
96
97 COMPONENT Downsampling
98 GENERIC (
99 ChanelCount : INTEGER;
100 SampleSize : INTEGER;
101 DivideParam : INTEGER);
102 PORT (
103 clk : IN STD_LOGIC;
104 rstn : IN STD_LOGIC;
105 sample_in_val : IN STD_LOGIC;
106 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
107 sample_out_val : OUT STD_LOGIC;
108 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
109 END COMPONENT;
110
111 -----------------------------------------------------------------------------
112 CONSTANT ChanelCount : INTEGER := 8;
113 CONSTANT ncycle_cnv_high : INTEGER := 79;
114 CONSTANT ncycle_cnv : INTEGER := 500;
115
116 -----------------------------------------------------------------------------
117 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
118 SIGNAL sample_val : STD_LOGIC;
119 SIGNAL sample_val_delay : STD_LOGIC;
120 -----------------------------------------------------------------------------
121 CONSTANT Coef_SZ : INTEGER := 9;
122 CONSTANT CoefCntPerCel : INTEGER := 6;
123 CONSTANT CoefPerCel : INTEGER := 5;
124 CONSTANT Cels_count : INTEGER := 5;
125
126 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
127 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
128 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
129 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
130 --
131 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
132 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
133 -----------------------------------------------------------------------------
134 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
135 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
137 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
138 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
139 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
140 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
141 -----------------------------------------------------------------------------
142 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
143 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
144 -----------------------------------------------------------------------------
145 SIGNAL sample_f0_val : STD_LOGIC;
146 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
147 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
148 --
149 SIGNAL sample_f1_val : STD_LOGIC;
150 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
151 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
152 --
153 SIGNAL sample_f2_val : STD_LOGIC;
154 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
155 --
156 SIGNAL sample_f3_val : STD_LOGIC;
157 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
158
159 -----------------------------------------------------------------------------
160 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
161 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
162 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
163 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
164 -----------------------------------------------------------------------------
165
166 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
169 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
170 BEGIN
171
172 -- component instantiation
173 -----------------------------------------------------------------------------
174 DIGITAL_acquisition : AD7688_drvr
175 GENERIC MAP (
176 ChanelCount => ChanelCount,
177 ncycle_cnv_high => ncycle_cnv_high,
178 ncycle_cnv => ncycle_cnv)
179 PORT MAP (
180 cnv_clk => cnv_clk, --
181 cnv_rstn => cnv_rstn, --
182 cnv_run => cnv_run, --
183 cnv => cnv, --
184 clk => clk, --
185 rstn => rstn, --
186 sck => sck, --
187 sdo => sdo(ChanelCount-1 DOWNTO 0), --
188 sample => sample,
189 sample_val => sample_val);
190
191 -----------------------------------------------------------------------------
192
193 PROCESS (clk, rstn)
194 BEGIN -- PROCESS
195 IF rstn = '0' THEN -- asynchronous reset (active low)
196 sample_val_delay <= '0';
197 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 sample_val_delay <= sample_val;
199 END IF;
200 END PROCESS;
201
202 -----------------------------------------------------------------------------
203 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
204 SampleLoop : FOR j IN 0 TO 15 GENERATE
205 sample_filter_in(i, j) <= sample(i)(j);
206 END GENERATE;
207
208 sample_filter_in(i, 16) <= sample(i)(15);
209 sample_filter_in(i, 17) <= sample(i)(15);
210 END GENERATE;
211
212 coefs_v2 <= CoefsInitValCst_v2;
213
214 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 GENERIC MAP (
216 tech => 0,
217 Mem_use => use_CEL, -- use_RAM
218 Sample_SZ => 18,
219 Coef_SZ => Coef_SZ,
220 Coef_Nb => 25,
221 Coef_sel_SZ => 5,
222 Cels_count => Cels_count,
223 ChanelsCount => ChanelCount)
224 PORT MAP (
225 rstn => rstn,
226 clk => clk,
227 virg_pos => 7,
228 coefs => coefs_v2,
229 sample_in_val => sample_val_delay,
230 sample_in => sample_filter_in,
231 sample_out_val => sample_filter_v2_out_val,
232 sample_out => sample_filter_v2_out);
233
234 -----------------------------------------------------------------------------
235 -- DATA_SHAPING
236 -----------------------------------------------------------------------------
237 all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE
238 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I);
239 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I);
240 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I);
241 END GENERATE all_data_shaping_in_loop;
242
243 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
244 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
245
246 PROCESS (clk, rstn)
247 BEGIN -- PROCESS
248 IF rstn = '0' THEN -- asynchronous reset (active low)
249 sample_data_shaping_out_val <= '0';
250 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
251 sample_data_shaping_out_val <= sample_filter_v2_out_val;
252 END IF;
253 END PROCESS;
254
255 SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE
256 PROCESS (clk, rstn)
257 BEGIN
258 IF rstn = '0' THEN
259 sample_data_shaping_out(0,j) <= '0';
260 sample_data_shaping_out(1,j) <= '0';
261 sample_data_shaping_out(2,j) <= '0';
262 sample_data_shaping_out(3,j) <= '0';
263 sample_data_shaping_out(4,j) <= '0';
264 sample_data_shaping_out(5,j) <= '0';
265 sample_data_shaping_out(6,j) <= '0';
266 sample_data_shaping_out(7,j) <= '0';
267 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
268 sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j);
269 IF data_shaping_SP0 = '1' THEN
270 sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j);
271 ELSE
272 sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j);
273 END IF;
274 IF data_shaping_SP1 = '1' THEN
275 sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j);
276 ELSE
277 sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j);
278 END IF;
279 sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j);
280 sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j);
281 sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j);
282 sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j);
283 END IF;
284 END PROCESS;
285 END GENERATE;
286
287 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
288 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
289 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
290 sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j);
291 END GENERATE;
292 END GENERATE;
293 -----------------------------------------------------------------------------
294 -- F0 -- @24.576 kHz
295 -----------------------------------------------------------------------------
296 Downsampling_f0 : Downsampling
297 GENERIC MAP (
298 ChanelCount => 8,
299 SampleSize => 16,
300 DivideParam => 4)
301 PORT MAP (
302 clk => clk,
303 rstn => rstn,
304 sample_in_val => sample_filter_v2_out_val_s,
305 sample_in => sample_filter_v2_out_s,
306 sample_out_val => sample_f0_val,
307 sample_out => sample_f0);
308
309 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
310 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
311 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
312 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
313 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
314 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
315 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
316 END GENERATE all_bit_sample_f0;
317
318 sample_f0_wen <= NOT(sample_f0_val) &
319 NOT(sample_f0_val) &
320 NOT(sample_f0_val) &
321 NOT(sample_f0_val) &
322 NOT(sample_f0_val) &
323 NOT(sample_f0_val);
324
325 -----------------------------------------------------------------------------
326 -- F1 -- @4096 Hz
327 -----------------------------------------------------------------------------
328 Downsampling_f1 : Downsampling
329 GENERIC MAP (
330 ChanelCount => 8,
331 SampleSize => 16,
332 DivideParam => 6)
333 PORT MAP (
334 clk => clk,
335 rstn => rstn,
336 sample_in_val => sample_f0_val ,
337 sample_in => sample_f0,
338 sample_out_val => sample_f1_val,
339 sample_out => sample_f1);
340
341 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
342 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
343 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
344 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
345 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
346 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
347 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
348 END GENERATE all_bit_sample_f1;
349
350 sample_f1_wen <= NOT(sample_f1_val) &
351 NOT(sample_f1_val) &
352 NOT(sample_f1_val) &
353 NOT(sample_f1_val) &
354 NOT(sample_f1_val) &
355 NOT(sample_f1_val);
356
357 -----------------------------------------------------------------------------
358 -- F2 -- @256 Hz
359 -----------------------------------------------------------------------------
360 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
361 sample_f0_s(0, I) <= sample_f0(0, I); -- V
362 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
363 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
364 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
365 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
366 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
367 END GENERATE all_bit_sample_f0_s;
368
369 Downsampling_f2 : Downsampling
370 GENERIC MAP (
371 ChanelCount => 6,
372 SampleSize => 16,
373 DivideParam => 96)
374 PORT MAP (
375 clk => clk,
376 rstn => rstn,
377 sample_in_val => sample_f0_val ,
378 sample_in => sample_f0_s,
379 sample_out_val => sample_f2_val,
380 sample_out => sample_f2);
381
382 sample_f2_wen <= NOT(sample_f2_val) &
383 NOT(sample_f2_val) &
384 NOT(sample_f2_val) &
385 NOT(sample_f2_val) &
386 NOT(sample_f2_val) &
387 NOT(sample_f2_val);
388
389 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
390 sample_f2_wdata_s(I) <= sample_f2(0, I);
391 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
392 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
393 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
394 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
395 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
396 END GENERATE all_bit_sample_f2;
397
398 -----------------------------------------------------------------------------
399 -- F3 -- @16 Hz
400 -----------------------------------------------------------------------------
401 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
402 sample_f1_s(0, I) <= sample_f1(0, I); -- V
403 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
404 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
405 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
406 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
407 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
408 END GENERATE all_bit_sample_f1_s;
409
410 Downsampling_f3 : Downsampling
411 GENERIC MAP (
412 ChanelCount => 6,
413 SampleSize => 16,
414 DivideParam => 256)
415 PORT MAP (
416 clk => clk,
417 rstn => rstn,
418 sample_in_val => sample_f1_val ,
419 sample_in => sample_f1_s,
420 sample_out_val => sample_f3_val,
421 sample_out => sample_f3);
422
423 sample_f3_wen <= (NOT sample_f3_val) &
424 (NOT sample_f3_val) &
425 (NOT sample_f3_val) &
426 (NOT sample_f3_val) &
427 (NOT sample_f3_val) &
428 (NOT sample_f3_val);
429
430 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
431 sample_f3_wdata_s(I) <= sample_f3(0, I);
432 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
433 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
434 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
435 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
436 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
437 END GENERATE all_bit_sample_f3;
438
439 lpp_waveform_1 : lpp_waveform
440 GENERIC MAP (
441 hindex => hindex,
442 tech => tech,
443 data_size => 160,
444 nb_burst_available_size => nb_burst_available_size,
445 nb_snapshot_param_size => nb_snapshot_param_size,
446 delta_snapshot_size => delta_snapshot_size,
447 delta_f2_f0_size => delta_f2_f0_size,
448 delta_f2_f1_size => delta_f2_f1_size)
449 PORT MAP (
450 clk => clk,
451 rstn => rstn,
452
453 AHB_Master_In => AHB_Master_In,
454 AHB_Master_Out => AHB_Master_Out,
455
456 coarse_time_0 => coarse_time_0, -- IN
457 delta_snapshot => delta_snapshot, -- IN
458 delta_f2_f1 => delta_f2_f1, -- IN
459 delta_f2_f0 => delta_f2_f0, -- IN
460 enable_f0 => enable_f0, -- IN
461 enable_f1 => enable_f1, -- IN
462 enable_f2 => enable_f2, -- IN
463 enable_f3 => enable_f3, -- IN
464 burst_f0 => burst_f0, -- IN
465 burst_f1 => burst_f1, -- IN
466 burst_f2 => burst_f2, -- IN
467 nb_burst_available => nb_burst_available,
468 nb_snapshot_param => nb_snapshot_param,
469 status_full => status_full,
470 status_full_ack => status_full_ack, -- IN
471 status_full_err => status_full_err,
472 status_new_err => status_new_err,
473
474 addr_data_f0 => addr_data_f0, -- IN
475 addr_data_f1 => addr_data_f1, -- IN
476 addr_data_f2 => addr_data_f2, -- IN
477 addr_data_f3 => addr_data_f3, -- IN
478
479 data_f0_in => data_f0_in_valid,
480 data_f1_in => data_f1_in_valid,
481 data_f2_in => data_f2_in_valid,
482 data_f3_in => data_f3_in_valid,
483 data_f0_in_valid => sample_f0_val,
484 data_f1_in_valid => sample_f1_val,
485 data_f2_in_valid => sample_f2_val,
486 data_f3_in_valid => sample_f3_val);
487
488 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
489 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
490 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
491 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
492
493 sample_f0_wdata <= sample_f0_wdata_s;
494 sample_f1_wdata <= sample_f1_wdata_s;
495 sample_f2_wdata <= sample_f2_wdata_s;
496 sample_f3_wdata <= sample_f3_wdata_s;
497
498 END tb;
Show file before | Show file after | Hide comments
@@ -1,328 +1,348
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_top_lfr_pkg.ALL;
6 USE lpp.lpp_top_lfr_pkg.ALL;
7 USE lpp.lpp_waveform_pkg.ALL;
7 USE lpp.lpp_waveform_pkg.ALL;
8
8
9 LIBRARY grlib;
9 LIBRARY grlib;
10 USE grlib.amba.ALL;
10 USE grlib.amba.ALL;
11 USE grlib.stdlib.ALL;
11 USE grlib.stdlib.ALL;
12 USE grlib.devices.ALL;
12 USE grlib.devices.ALL;
13 USE GRLIB.DMA2AHB_Package.ALL;
13 USE GRLIB.DMA2AHB_Package.ALL;
14
14
15 LIBRARY techmap;
15 LIBRARY techmap;
16 USE techmap.gencomp.ALL;
16 USE techmap.gencomp.ALL;
17
17
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19
19
20 ENTITY TB_Data_Acquisition IS
20 ENTITY TB_Data_Acquisition IS
21
21
22 END TB_Data_Acquisition;
22 END TB_Data_Acquisition;
23
23
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25
25
26 ARCHITECTURE tb OF TB_Data_Acquisition IS
26 ARCHITECTURE tb OF TB_Data_Acquisition IS
27
27
28 COMPONENT TestModule_ADS7886
28 COMPONENT TestModule_ADS7886
29 GENERIC (
29 GENERIC (
30 freq : INTEGER;
30 freq : INTEGER;
31 amplitude : INTEGER;
31 amplitude : INTEGER;
32 impulsion : INTEGER);
32 impulsion : INTEGER);
33 PORT (
33 PORT (
34 cnv_run : IN STD_LOGIC;
34 cnv_run : IN STD_LOGIC;
35 cnv : IN STD_LOGIC;
35 cnv : IN STD_LOGIC;
36 sck : IN STD_LOGIC;
36 sck : IN STD_LOGIC;
37 sdo : OUT STD_LOGIC);
37 sdo : OUT STD_LOGIC);
38 END COMPONENT;
38 END COMPONENT;
39
39
40 COMPONENT Top_Data_Acquisition
40 --COMPONENT Top_Data_Acquisition
41 GENERIC (
41 -- GENERIC (
42 hindex : INTEGER;
42 -- hindex : INTEGER;
43 nb_burst_available_size : INTEGER := 11;
43 -- nb_burst_available_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
44 -- nb_snapshot_param_size : INTEGER := 11;
45 delta_snapshot_size : INTEGER := 16;
45 -- delta_snapshot_size : INTEGER := 16;
46 delta_f2_f0_size : INTEGER := 10;
46 -- delta_f2_f0_size : INTEGER := 10;
47 delta_f2_f1_size : INTEGER := 10;
47 -- delta_f2_f1_size : INTEGER := 10;
48 tech : integer);
48 -- tech : integer);
49 PORT (
49 -- PORT (
50 cnv_run : IN STD_LOGIC;
50 -- cnv_run : IN STD_LOGIC;
51 cnv : OUT STD_LOGIC;
51 -- cnv : OUT STD_LOGIC;
52 sck : OUT STD_LOGIC;
52 -- sck : OUT STD_LOGIC;
53 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
53 -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
54 cnv_clk : IN STD_LOGIC;
54 -- cnv_clk : IN STD_LOGIC;
55 cnv_rstn : IN STD_LOGIC;
55 -- cnv_rstn : IN STD_LOGIC;
56 clk : IN STD_LOGIC;
56 -- clk : IN STD_LOGIC;
57 rstn : IN STD_LOGIC;
57 -- rstn : IN STD_LOGIC;
58 sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
58 -- sample_f0_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
59 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
59 -- sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
60 sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
60 -- sample_f1_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
61 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
61 -- sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
62 sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
62 -- sample_f2_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
63 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
63 -- sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
64 sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
64 -- sample_f3_wen : out STD_LOGIC_VECTOR(5 DOWNTO 0);
65 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
65 -- sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
66 AHB_Master_In : IN AHB_Mst_In_Type;
66 -- AHB_Master_In : IN AHB_Mst_In_Type;
67 AHB_Master_Out : OUT AHB_Mst_Out_Type;
67 -- AHB_Master_Out : OUT AHB_Mst_Out_Type;
68 coarse_time_0 : IN STD_LOGIC;
68 -- coarse_time_0 : IN STD_LOGIC;
69 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
69 -- data_shaping_SP0 : IN STD_LOGIC;
70 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
70 -- data_shaping_SP1 : IN STD_LOGIC;
71 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
71 -- data_shaping_R0 : IN STD_LOGIC;
72 enable_f0 : IN STD_LOGIC;
72 -- data_shaping_R1 : IN STD_LOGIC;
73 enable_f1 : IN STD_LOGIC;
73 -- delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
74 enable_f2 : IN STD_LOGIC;
74 -- delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
75 enable_f3 : IN STD_LOGIC;
75 -- delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
76 burst_f0 : IN STD_LOGIC;
76 -- enable_f0 : IN STD_LOGIC;
77 burst_f1 : IN STD_LOGIC;
77 -- enable_f1 : IN STD_LOGIC;
78 burst_f2 : IN STD_LOGIC;
78 -- enable_f2 : IN STD_LOGIC;
79 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
79 -- enable_f3 : IN STD_LOGIC;
80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 -- burst_f0 : IN STD_LOGIC;
81 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 -- burst_f1 : IN STD_LOGIC;
82 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 -- burst_f2 : IN STD_LOGIC;
83 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 -- nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
84 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
84 -- nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
85 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 -- status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 -- status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 -- status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
88 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 END COMPONENT;
89 -- addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 -- addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 -- addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 -- addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
93 --END COMPONENT;
90
94
91 -- component ports
95 -- component ports
92 SIGNAL cnv_rstn : STD_LOGIC;
96 SIGNAL cnv_rstn : STD_LOGIC;
93 SIGNAL cnv : STD_LOGIC;
97 SIGNAL cnv : STD_LOGIC;
94 SIGNAL rstn : STD_LOGIC;
98 SIGNAL rstn : STD_LOGIC;
95 SIGNAL sck : STD_LOGIC;
99 SIGNAL sck : STD_LOGIC;
96 SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
100 SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
97 SIGNAL run_cnv : STD_LOGIC;
101 SIGNAL run_cnv : STD_LOGIC;
98
102
99
103
100 -- clock
104 -- clock
101 signal Clk : STD_LOGIC := '1';
105 signal Clk : STD_LOGIC := '1';
102 SIGNAL cnv_clk : STD_LOGIC := '1';
106 SIGNAL cnv_clk : STD_LOGIC := '1';
103
107
104 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
105 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
109 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
106 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
110 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
107 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
108 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
112 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
109 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
113 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
110 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
111 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
112 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
113 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
114 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116
120
117 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
118 CONSTANT nb_burst_available_size : INTEGER := 11;
122 CONSTANT nb_burst_available_size : INTEGER := 11;
119 CONSTANT nb_snapshot_param_size : INTEGER := 11;
123 CONSTANT nb_snapshot_param_size : INTEGER := 11;
120 CONSTANT delta_snapshot_size : INTEGER := 16;
124 CONSTANT delta_snapshot_size : INTEGER := 16;
121 CONSTANT delta_f2_f0_size : INTEGER := 10;
125 CONSTANT delta_f2_f0_size : INTEGER := 10;
122 CONSTANT delta_f2_f1_size : INTEGER := 10;
126 CONSTANT delta_f2_f1_size : INTEGER := 10;
123
127
124 SIGNAL AHB_Master_In : AHB_Mst_In_Type;
128 SIGNAL AHB_Master_In : AHB_Mst_In_Type;
125 SIGNAL AHB_Master_Out : AHB_Mst_Out_Type;
129 SIGNAL AHB_Master_Out : AHB_Mst_Out_Type;
126
130
127 SIGNAL coarse_time_0 : STD_LOGIC;
131 SIGNAL coarse_time_0 : STD_LOGIC;
128 SIGNAL coarse_time_0_t : STD_LOGIC := '0';
132 SIGNAL coarse_time_0_t : STD_LOGIC := '0';
129 SIGNAL coarse_time_0_t2 : STD_LOGIC := '0';
133 SIGNAL coarse_time_0_t2 : STD_LOGIC := '0';
130
134
131 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
135 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
132 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
136 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
133 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
137 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
134
138
135 SIGNAL enable_f0 : STD_LOGIC;
139 SIGNAL enable_f0 : STD_LOGIC;
136 SIGNAL enable_f1 : STD_LOGIC;
140 SIGNAL enable_f1 : STD_LOGIC;
137 SIGNAL enable_f2 : STD_LOGIC;
141 SIGNAL enable_f2 : STD_LOGIC;
138 SIGNAL enable_f3 : STD_LOGIC;
142 SIGNAL enable_f3 : STD_LOGIC;
139
143
140 SIGNAL burst_f0 : STD_LOGIC;
144 SIGNAL burst_f0 : STD_LOGIC;
141 SIGNAL burst_f1 : STD_LOGIC;
145 SIGNAL burst_f1 : STD_LOGIC;
142 SIGNAL burst_f2 : STD_LOGIC;
146 SIGNAL burst_f2 : STD_LOGIC;
143
147
144 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
148 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
145 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
149 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
146
150
147 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
151
155
152 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160
156
161
162 SIGNAL data_shaping_SP0 : STD_LOGIC;
163 SIGNAL data_shaping_SP1 : STD_LOGIC;
164 SIGNAL data_shaping_R0 : STD_LOGIC;
165 SIGNAL data_shaping_R1 : STD_LOGIC;
157 BEGIN -- tb
166 BEGIN -- tb
158
167
159 MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
168 MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
160 TestModule_ADS7886_u: TestModule_ADS7886
169 TestModule_ADS7886_u: TestModule_ADS7886
161 GENERIC MAP (
170 GENERIC MAP (
162 freq => 24*(I+1),
171 freq => 24*(I+1),
163 amplitude => 30000/(I+1),
172 amplitude => 30000/(I+1),
164 impulsion => 0)
173 impulsion => 0)
165 PORT MAP (
174 PORT MAP (
166 cnv_run => run_cnv,
175 cnv_run => run_cnv,
167 cnv => cnv,
176 cnv => cnv,
168 sck => sck,
177 sck => sck,
169 sdo => sdo(I));
178 sdo => sdo(I));
170 END GENERATE MODULE_ADS7886;
179 END GENERATE MODULE_ADS7886;
171
180
172 TestModule_ADS7886_u: TestModule_ADS7886
181 TestModule_ADS7886_u: TestModule_ADS7886
173 GENERIC MAP (
182 GENERIC MAP (
174 freq => 0,
183 freq => 0,
175 amplitude => 30000,
184 amplitude => 30000,
176 impulsion => 1)
185 impulsion => 1)
177 PORT MAP (
186 PORT MAP (
178 cnv_run => run_cnv,
187 cnv_run => run_cnv,
179 cnv => cnv,
188 cnv => cnv,
180 sck => sck,
189 sck => sck,
181 sdo => sdo(7));
190 sdo => sdo(7));
182
191
183
192
184 -- clock generation
193 -- clock generation
185 Clk <= not Clk after 20 ns; -- 25 Mhz
194 Clk <= not Clk after 20 ns; -- 25 Mhz
186 cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
195 cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
187
196
188 -- waveform generation
197 -- waveform generation
189 WaveGen_Proc: process
198 WaveGen_Proc: process
190 begin
199 begin
191 -- insert signal assignments here
200 -- insert signal assignments here
192 wait until Clk = '1';
201 wait until Clk = '1';
193 rstn <= '0';
202 rstn <= '0';
194 cnv_rstn <= '0';
203 cnv_rstn <= '0';
195 run_cnv <= '0';
204 run_cnv <= '0';
196 wait until Clk = '1';
205 wait until Clk = '1';
197 wait until Clk = '1';
206 wait until Clk = '1';
198 wait until Clk = '1';
207 wait until Clk = '1';
199 rstn <= '1';
208 rstn <= '1';
200 cnv_rstn <= '1';
209 cnv_rstn <= '1';
201 wait until Clk = '1';
210 wait until Clk = '1';
202 wait until Clk = '1';
211 wait until Clk = '1';
203 wait until Clk = '1';
212 wait until Clk = '1';
204 wait until Clk = '1';
213 wait until Clk = '1';
205 wait until Clk = '1';
214 wait until Clk = '1';
206 wait until Clk = '1';
215 wait until Clk = '1';
207 run_cnv <= '1';
216 run_cnv <= '1';
208 wait;
217 wait;
209
218
210 end process WaveGen_Proc;
219 end process WaveGen_Proc;
211
220
212 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
213
222
214 Top_Data_Acquisition_2: Top_Data_Acquisition
223 Top_Data_Acquisition_2: lpp_top_lfr_wf_picker_ip
215 GENERIC MAP (
224 GENERIC MAP (
216 hindex => 2,
225 hindex => 2,
217 nb_burst_available_size => nb_burst_available_size,
226 nb_burst_available_size => nb_burst_available_size,
218 nb_snapshot_param_size => nb_snapshot_param_size,
227 nb_snapshot_param_size => nb_snapshot_param_size,
228 delta_snapshot_size =>16,
229 delta_f2_f0_size =>10,
230 delta_f2_f1_size =>10,
219 tech => 0)
231 tech => 0)
220 PORT MAP (
232 PORT MAP (
221 cnv_run => run_cnv,
233 cnv_run => run_cnv,
222 cnv => cnv,
234 cnv => cnv,
223 sck => sck,
235 sck => sck,
224 sdo => sdo,
236 sdo => sdo,
225 cnv_clk => cnv_clk,
237 cnv_clk => cnv_clk,
226 cnv_rstn => cnv_rstn,
238 cnv_rstn => cnv_rstn,
227 clk => clk,
239 clk => clk,
228 rstn => rstn,
240 rstn => rstn,
229 sample_f0_wen => sample_f0_wen,
241 sample_f0_wen => sample_f0_wen,
230 sample_f0_wdata => sample_f0_wdata,
242 sample_f0_wdata => sample_f0_wdata,
231 sample_f1_wen => sample_f1_wen,
243 sample_f1_wen => sample_f1_wen,
232 sample_f1_wdata => sample_f1_wdata,
244 sample_f1_wdata => sample_f1_wdata,
233 sample_f2_wen => sample_f2_wen,
245 sample_f2_wen => sample_f2_wen,
234 sample_f2_wdata => sample_f2_wdata,
246 sample_f2_wdata => sample_f2_wdata,
235 sample_f3_wen => sample_f3_wen,
247 sample_f3_wen => sample_f3_wen,
236 sample_f3_wdata => sample_f3_wdata,
248 sample_f3_wdata => sample_f3_wdata,
237 AHB_Master_In => AHB_Master_In,
249 AHB_Master_In => AHB_Master_In,
238 AHB_Master_Out => AHB_Master_Out,
250 AHB_Master_Out => AHB_Master_Out,
239 coarse_time_0 => coarse_time_0,
251 coarse_time_0 => coarse_time_0,
252 data_shaping_SP0 => data_shaping_SP0,
253 data_shaping_SP1 => data_shaping_SP1,
254 data_shaping_R0 => data_shaping_R0,
255 data_shaping_R1 => data_shaping_R1,
240 delta_snapshot => delta_snapshot,
256 delta_snapshot => delta_snapshot,
241 delta_f2_f1 => delta_f2_f1,
257 delta_f2_f1 => delta_f2_f1,
242 delta_f2_f0 => delta_f2_f0,
258 delta_f2_f0 => delta_f2_f0,
243 enable_f0 => enable_f0,
259 enable_f0 => enable_f0,
244 enable_f1 => enable_f1,
260 enable_f1 => enable_f1,
245 enable_f2 => enable_f2,
261 enable_f2 => enable_f2,
246 enable_f3 => enable_f3,
262 enable_f3 => enable_f3,
247 burst_f0 => burst_f0,
263 burst_f0 => burst_f0,
248 burst_f1 => burst_f1,
264 burst_f1 => burst_f1,
249 burst_f2 => burst_f2,
265 burst_f2 => burst_f2,
250 nb_burst_available => nb_burst_available,
266 nb_burst_available => nb_burst_available,
251 nb_snapshot_param => nb_snapshot_param,
267 nb_snapshot_param => nb_snapshot_param,
252 status_full => status_full,
268 status_full => status_full,
253 status_full_ack => status_full_ack,
269 status_full_ack => status_full_ack,
254 status_full_err => status_full_err,
270 status_full_err => status_full_err,
255 status_new_err => status_new_err,
271 status_new_err => status_new_err,
256 addr_data_f0 => addr_data_f0,
272 addr_data_f0 => addr_data_f0,
257 addr_data_f1 => addr_data_f1,
273 addr_data_f1 => addr_data_f1,
258 addr_data_f2 => addr_data_f2,
274 addr_data_f2 => addr_data_f2,
259 addr_data_f3 => addr_data_f3);
275 addr_data_f3 => addr_data_f3);
260
276
261 PROCESS (clk, rstn)
277 PROCESS (clk, rstn)
262 BEGIN -- PROCESS
278 BEGIN -- PROCESS
263 IF rstn = '0' THEN -- asynchronous reset (active low)
279 IF rstn = '0' THEN -- asynchronous reset (active low)
264 enable_f0 <= '0';
280 enable_f0 <= '0';
265 enable_f1 <= '0';
281 enable_f1 <= '0';
266 enable_f2 <= '0';
282 enable_f2 <= '0';
267 enable_f3 <= '0';
283 enable_f3 <= '0';
268 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
284 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
269 enable_f0 <= '1'; --TODO test
285 enable_f0 <= '1'; --TODO test
270 enable_f1 <= '1';
286 enable_f1 <= '1';
271 enable_f2 <= '1';
287 enable_f2 <= '1';
272 enable_f3 <= '1';
288 enable_f3 <= '1';
273 END IF;
289 END IF;
274 END PROCESS;
290 END PROCESS;
275
291
276 burst_f0 <= '0'; --TODO test
292 burst_f0 <= '0'; --TODO test
277 burst_f1 <= '0'; --TODO test
293 burst_f1 <= '0'; --TODO test
278 burst_f2 <= '0';
294 burst_f2 <= '0';
279
295
296 data_shaping_SP0 <= '0';
297 data_shaping_SP1 <= '0';
298 data_shaping_R0 <= '1';
299 data_shaping_R1 <= '1';
280
300
281 delta_snapshot <= "0000000000000001";
301 delta_snapshot <= "0000000000000001";
282 --nb_snapshot_param <= "00000001110"; -- 14+1 = 15
302 --nb_snapshot_param <= "00000001110"; -- 14+1 = 15
283 --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2
303 --delta_f2_f0 <= "1010011001";--665 = 14/2*96 -14/2
284 --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4
304 --delta_f2_f1 <= "0000100110";-- 38 = 14/2*6 - 14/4
285
305
286 -- A redefinir car ca ne tombe pas correctement ... ???
306 -- A redefinir car ca ne tombe pas correctement ... ???
287 nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34
307 nb_burst_available <= "00000110010"; -- 3*16 + 2 = 34
288 nb_snapshot_param <= "00000001111"; -- x+1 = 16
308 nb_snapshot_param <= "00000001111"; -- x+1 = 16
289 delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2
309 delta_f2_f0 <= "1011001000";--712 = x/2*96 -x/2
290 delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4
310 delta_f2_f1 <= "0000101001";-- 41 = x/2*6 - x/4
291
311
292 addr_data_f0 <= "00000000000000000000000000000000";
312 addr_data_f0 <= "00000000000000000000000000000000";
293 addr_data_f1 <= "00010000000000000000000000000000";
313 addr_data_f1 <= "00010000000000000000000000000000";
294 addr_data_f2 <= "00100000000000000000000000000000";
314 addr_data_f2 <= "00100000000000000000000000000000";
295 addr_data_f3 <= "00110000000000000000000000000000";
315 addr_data_f3 <= "00110000000000000000000000000000";
296
316
297 PROCESS (clk, rstn)
317 PROCESS (clk, rstn)
298 BEGIN -- PROCESS
318 BEGIN -- PROCESS
299 IF rstn = '0' THEN -- asynchronous reset (active low)
319 IF rstn = '0' THEN -- asynchronous reset (active low)
300 status_full_ack <= (OTHERS => '0');
320 status_full_ack <= (OTHERS => '0');
301 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
321 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
302 status_full_ack <= status_full;
322 status_full_ack <= status_full;
303 END IF;
323 END IF;
304 END PROCESS;
324 END PROCESS;
305
325
306
326
307 coarse_time_0_t <= not coarse_time_0_t after 50 ms;
327 coarse_time_0_t <= not coarse_time_0_t after 50 ms;
308
328
309 PROCESS (clk, rstn)
329 PROCESS (clk, rstn)
310 BEGIN -- PROCESS
330 BEGIN -- PROCESS
311 IF rstn = '0' THEN -- asynchronous reset (active low)
331 IF rstn = '0' THEN -- asynchronous reset (active low)
312 coarse_time_0_t2 <= '0';
332 coarse_time_0_t2 <= '0';
313 coarse_time_0 <= '0';
333 coarse_time_0 <= '0';
314 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
334 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
315 coarse_time_0_t2 <= coarse_time_0_t;
335 coarse_time_0_t2 <= coarse_time_0_t;
316 coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2);
336 coarse_time_0 <= coarse_time_0_t AND (NOT coarse_time_0_t2);
317 END IF;
337 END IF;
318 END PROCESS;
338 END PROCESS;
319
339
320
340
321 AHB_Master_In.HGRANT(2) <= '1';
341 AHB_Master_In.HGRANT(2) <= '1';
322 AHB_Master_In.HREADY <= '1';
342 AHB_Master_In.HREADY <= '1';
323
343
324
344
325 AHB_Master_In.HRESP <= HRESP_OKAY;
345 AHB_Master_In.HRESP <= HRESP_OKAY;
326
346
327
347
328 END tb;
348 END tb;
Show file before | Show file after | Hide comments
@@ -1,411 +1,498
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3
4
4 LIBRARY lpp;
5 LIBRARY lpp;
5 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10
11
11 LIBRARY techmap;
12 LIBRARY techmap;
12 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
13
14
14 LIBRARY grlib;
15 LIBRARY grlib;
15 USE grlib.amba.ALL;
16 USE grlib.amba.ALL;
16 USE grlib.stdlib.ALL;
17 USE grlib.stdlib.ALL;
17 USE grlib.devices.ALL;
18 USE grlib.devices.ALL;
18 USE GRLIB.DMA2AHB_Package.ALL;
19 USE GRLIB.DMA2AHB_Package.ALL;
19
20
20 ENTITY Top_Data_Acquisition IS
21 ENTITY Top_Data_Acquisition IS
21 GENERIC(
22 GENERIC(
22 hindex : INTEGER := 2;
23 hindex : INTEGER := 2;
23 nb_burst_available_size : INTEGER := 11;
24 nb_burst_available_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
25 nb_snapshot_param_size : INTEGER := 11;
25 delta_snapshot_size : INTEGER := 16;
26 delta_snapshot_size : INTEGER := 16;
26 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f1_size : INTEGER := 10;
28 delta_f2_f1_size : INTEGER := 10;
28 tech : INTEGER := 0
29 tech : INTEGER := 0
29 );
30 );
30 PORT (
31 PORT (
31 -- ADS7886
32 -- ADS7886
32 cnv_run : IN STD_LOGIC;
33 cnv_run : IN STD_LOGIC;
33 cnv : OUT STD_LOGIC;
34 cnv : OUT STD_LOGIC;
34 sck : OUT STD_LOGIC;
35 sck : OUT STD_LOGIC;
35 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
36 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
36 --
37 --
37 cnv_clk : IN STD_LOGIC;
38 cnv_clk : IN STD_LOGIC;
38 cnv_rstn : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
39 --
40 --
40 clk : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42 rstn : IN STD_LOGIC;
42 --
43 --
43 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
44 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
44 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
45 --
46 --
46 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
47 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
47 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
48 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
48 --
49 --
49 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
50 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
50 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
51 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
51 --
52 --
52 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
53 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
53 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
54 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
54
55
55 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
59
59 coarse_time_0 : IN STD_LOGIC;
60 coarse_time_0 : IN STD_LOGIC;
60
61
61 --config
62 --config
63 data_shaping_SP0 : IN STD_LOGIC;
64 data_shaping_SP1 : IN STD_LOGIC;
65 data_shaping_R0 : IN STD_LOGIC;
66 data_shaping_R1 : IN STD_LOGIC;
67
62 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
68 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
63 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
69 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
64 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
70 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
65
71
66 enable_f0 : IN STD_LOGIC;
72 enable_f0 : IN STD_LOGIC;
67 enable_f1 : IN STD_LOGIC;
73 enable_f1 : IN STD_LOGIC;
68 enable_f2 : IN STD_LOGIC;
74 enable_f2 : IN STD_LOGIC;
69 enable_f3 : IN STD_LOGIC;
75 enable_f3 : IN STD_LOGIC;
70
76
71 burst_f0 : IN STD_LOGIC;
77 burst_f0 : IN STD_LOGIC;
72 burst_f1 : IN STD_LOGIC;
78 burst_f1 : IN STD_LOGIC;
73 burst_f2 : IN STD_LOGIC;
79 burst_f2 : IN STD_LOGIC;
74
80
75 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
81 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
76 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
82 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
77 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
84 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
86 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
81
87
82 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
91 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
86 );
92 );
87 END Top_Data_Acquisition;
93 END Top_Data_Acquisition;
88
94
89 ARCHITECTURE tb OF Top_Data_Acquisition IS
95 ARCHITECTURE tb OF Top_Data_Acquisition IS
90
96
91 COMPONENT Downsampling
97 COMPONENT Downsampling
92 GENERIC (
98 GENERIC (
93 ChanelCount : INTEGER;
99 ChanelCount : INTEGER;
94 SampleSize : INTEGER;
100 SampleSize : INTEGER;
95 DivideParam : INTEGER);
101 DivideParam : INTEGER);
96 PORT (
102 PORT (
97 clk : IN STD_LOGIC;
103 clk : IN STD_LOGIC;
98 rstn : IN STD_LOGIC;
104 rstn : IN STD_LOGIC;
99 sample_in_val : IN STD_LOGIC;
105 sample_in_val : IN STD_LOGIC;
100 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
106 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
101 sample_out_val : OUT STD_LOGIC;
107 sample_out_val : OUT STD_LOGIC;
102 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
108 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
103 END COMPONENT;
109 END COMPONENT;
104
110
105 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
106 CONSTANT ChanelCount : INTEGER := 8;
112 CONSTANT ChanelCount : INTEGER := 8;
107 CONSTANT ncycle_cnv_high : INTEGER := 79;
113 CONSTANT ncycle_cnv_high : INTEGER := 79;
108 CONSTANT ncycle_cnv : INTEGER := 500;
114 CONSTANT ncycle_cnv : INTEGER := 500;
109
115
110 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
111 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
117 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
112 SIGNAL sample_val : STD_LOGIC;
118 SIGNAL sample_val : STD_LOGIC;
113 SIGNAL sample_val_delay : STD_LOGIC;
119 SIGNAL sample_val_delay : STD_LOGIC;
114 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
115 CONSTANT Coef_SZ : INTEGER := 9;
121 CONSTANT Coef_SZ : INTEGER := 9;
116 CONSTANT CoefCntPerCel : INTEGER := 6;
122 CONSTANT CoefCntPerCel : INTEGER := 6;
117 CONSTANT CoefPerCel : INTEGER := 5;
123 CONSTANT CoefPerCel : INTEGER := 5;
118 CONSTANT Cels_count : INTEGER := 5;
124 CONSTANT Cels_count : INTEGER := 5;
119
125
120 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
126 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
121 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
127 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
122 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
128 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
123 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
129 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
124 --
130 --
125 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
131 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
126 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
132 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
127 SIGNAL sample_filter_v2_out_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
133 -----------------------------------------------------------------------------
134 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
135 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
137 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
138 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
139 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
140 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
141 -----------------------------------------------------------------------------
142 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
143 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
128 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
129 SIGNAL sample_f0_val : STD_LOGIC;
145 SIGNAL sample_f0_val : STD_LOGIC;
130 SIGNAL sample_f0 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
146 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
147 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
131 --
148 --
132 SIGNAL sample_f1_val : STD_LOGIC;
149 SIGNAL sample_f1_val : STD_LOGIC;
133 SIGNAL sample_f1 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
150 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
151 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
134 --
152 --
135 SIGNAL sample_f2_val : STD_LOGIC;
153 SIGNAL sample_f2_val : STD_LOGIC;
136 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
154 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
137 --
155 --
138 SIGNAL sample_f3_val : STD_LOGIC;
156 SIGNAL sample_f3_val : STD_LOGIC;
139 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
157 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
140
158
141 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
142 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
160 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
143 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
161 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
144 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
162 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
145 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
163 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
146 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
147
165
148 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
166 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
149 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
150 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
151 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
169 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
152 BEGIN
170 BEGIN
153
171
154 -- component instantiation
172 -- component instantiation
155 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
156 DIGITAL_acquisition : AD7688_drvr
174 DIGITAL_acquisition : AD7688_drvr
157 GENERIC MAP (
175 GENERIC MAP (
158 ChanelCount => ChanelCount,
176 ChanelCount => ChanelCount,
159 ncycle_cnv_high => ncycle_cnv_high,
177 ncycle_cnv_high => ncycle_cnv_high,
160 ncycle_cnv => ncycle_cnv)
178 ncycle_cnv => ncycle_cnv)
161 PORT MAP (
179 PORT MAP (
162 cnv_clk => cnv_clk, --
180 cnv_clk => cnv_clk, --
163 cnv_rstn => cnv_rstn, --
181 cnv_rstn => cnv_rstn, --
164 cnv_run => cnv_run, --
182 cnv_run => cnv_run, --
165 cnv => cnv, --
183 cnv => cnv, --
166 clk => clk, --
184 clk => clk, --
167 rstn => rstn, --
185 rstn => rstn, --
168 sck => sck, --
186 sck => sck, --
169 sdo => sdo(ChanelCount-1 DOWNTO 0), --
187 sdo => sdo(ChanelCount-1 DOWNTO 0), --
170 sample => sample,
188 sample => sample,
171 sample_val => sample_val);
189 sample_val => sample_val);
172
190
173 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
174
192
175 PROCESS (clk, rstn)
193 PROCESS (clk, rstn)
176 BEGIN -- PROCESS
194 BEGIN -- PROCESS
177 IF rstn = '0' THEN -- asynchronous reset (active low)
195 IF rstn = '0' THEN -- asynchronous reset (active low)
178 sample_val_delay <= '0';
196 sample_val_delay <= '0';
179 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
197 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
180 sample_val_delay <= sample_val;
198 sample_val_delay <= sample_val;
181 END IF;
199 END IF;
182 END PROCESS;
200 END PROCESS;
183
201
184 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
185 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
203 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
186 SampleLoop : FOR j IN 0 TO 15 GENERATE
204 SampleLoop : FOR j IN 0 TO 15 GENERATE
187 sample_filter_in(i, j) <= sample(i)(j);
205 sample_filter_in(i, j) <= sample(i)(j);
188 END GENERATE;
206 END GENERATE;
189
207
190 sample_filter_in(i, 16) <= sample(i)(15);
208 sample_filter_in(i, 16) <= sample(i)(15);
191 sample_filter_in(i, 17) <= sample(i)(15);
209 sample_filter_in(i, 17) <= sample(i)(15);
192 END GENERATE;
210 END GENERATE;
193
211
194 coefs_v2 <= CoefsInitValCst_v2;
212 coefs_v2 <= CoefsInitValCst_v2;
195
213
196 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
214 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
197 GENERIC MAP (
215 GENERIC MAP (
198 tech => 0,
216 tech => 0,
199 Mem_use => use_RAM,
217 Mem_use => use_CEL, -- use_RAM
200 Sample_SZ => 18,
218 Sample_SZ => 18,
201 Coef_SZ => Coef_SZ,
219 Coef_SZ => Coef_SZ,
202 Coef_Nb => 25,
220 Coef_Nb => 25,
203 Coef_sel_SZ => 5,
221 Coef_sel_SZ => 5,
204 Cels_count => Cels_count,
222 Cels_count => Cels_count,
205 ChanelsCount => ChanelCount)
223 ChanelsCount => ChanelCount)
206 PORT MAP (
224 PORT MAP (
207 rstn => rstn,
225 rstn => rstn,
208 clk => clk,
226 clk => clk,
209 virg_pos => 7,
227 virg_pos => 7,
210 coefs => coefs_v2,
228 coefs => coefs_v2,
211 sample_in_val => sample_val_delay,
229 sample_in_val => sample_val_delay,
212 sample_in => sample_filter_in,
230 sample_in => sample_filter_in,
213 sample_out_val => sample_filter_v2_out_val,
231 sample_out_val => sample_filter_v2_out_val,
214 sample_out => sample_filter_v2_out);
232 sample_out => sample_filter_v2_out);
215
233
216 --sample_filter_v2_out_val <= sample_val_delay;
234 -----------------------------------------------------------------------------
235 -- DATA_SHAPING
236 -----------------------------------------------------------------------------
237 all_data_shaping_in_loop: FOR I IN 17 DOWNTO 0 GENERATE
238 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0,I);
239 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1,I);
240 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2,I);
241 END GENERATE all_data_shaping_in_loop;
242
243 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
244 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
245
246 PROCESS (clk, rstn)
247 BEGIN -- PROCESS
248 IF rstn = '0' THEN -- asynchronous reset (active low)
249 sample_data_shaping_out_val <= '0';
250 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
251 sample_data_shaping_out_val <= sample_filter_v2_out_val;
252 END IF;
253 END PROCESS;
217
254
218 ChanelLoopOut : FOR i IN 0 TO 5 GENERATE
255 SampleLoop_data_shaping: FOR j IN 0 TO 17 GENERATE
256 PROCESS (clk, rstn)
257 BEGIN
258 IF rstn = '0' THEN
259 sample_data_shaping_out(0,j) <= '0';
260 sample_data_shaping_out(1,j) <= '0';
261 sample_data_shaping_out(2,j) <= '0';
262 sample_data_shaping_out(3,j) <= '0';
263 sample_data_shaping_out(4,j) <= '0';
264 sample_data_shaping_out(5,j) <= '0';
265 sample_data_shaping_out(6,j) <= '0';
266 sample_data_shaping_out(7,j) <= '0';
267 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
268 sample_data_shaping_out(0,j) <= sample_filter_v2_out(0,j);
269 IF data_shaping_SP0 = '1' THEN
270 sample_data_shaping_out(1,j) <= sample_data_shaping_f1_f0_s(j);
271 ELSE
272 sample_data_shaping_out(1,j) <= sample_filter_v2_out(1,j);
273 END IF;
274 IF data_shaping_SP1 = '1' THEN
275 sample_data_shaping_out(2,j) <= sample_data_shaping_f2_f1_s(j);
276 ELSE
277 sample_data_shaping_out(2,j) <= sample_filter_v2_out(2,j);
278 END IF;
279 sample_data_shaping_out(4,j) <= sample_filter_v2_out(4,j);
280 sample_data_shaping_out(5,j) <= sample_filter_v2_out(5,j);
281 sample_data_shaping_out(6,j) <= sample_filter_v2_out(6,j);
282 sample_data_shaping_out(7,j) <= sample_filter_v2_out(7,j);
283 END IF;
284 END PROCESS;
285 END GENERATE;
286
287 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
288 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
219 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
289 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
220 sample_filter_v2_out_s(i, j) <= sample_filter_v2_out(i, j);
290 sample_filter_v2_out_s(i,j) <= sample_data_shaping_out(i,j);
221 --sample_filter_v2_out_s(i, j) <= sample_filter_in(i, j);
222 END GENERATE;
291 END GENERATE;
223 END GENERATE;
292 END GENERATE;
224 -----------------------------------------------------------------------------
293 -----------------------------------------------------------------------------
225 -- F0 -- @24.576 kHz
294 -- F0 -- @24.576 kHz
226 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
227 Downsampling_f0 : Downsampling
296 Downsampling_f0 : Downsampling
228 GENERIC MAP (
297 GENERIC MAP (
229 ChanelCount => 6,
298 ChanelCount => 8,
230 SampleSize => 16,
299 SampleSize => 16,
231 DivideParam => 4)
300 DivideParam => 4)
232 PORT MAP (
301 PORT MAP (
233 clk => clk,
302 clk => clk,
234 rstn => rstn,
303 rstn => rstn,
235 sample_in_val => sample_filter_v2_out_val,
304 sample_in_val => sample_filter_v2_out_val_s,
236 sample_in => sample_filter_v2_out_s,
305 sample_in => sample_filter_v2_out_s,
237 sample_out_val => sample_f0_val,
306 sample_out_val => sample_f0_val,
238 sample_out => sample_f0);
307 sample_out => sample_f0);
239
308
240 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
309 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
241 sample_f0_wdata_s(I) <= sample_f0(0, I);
310 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
242 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I);
311 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
243 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I);
312 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
244 sample_f0_wdata_s(16*3+I) <= sample_f0(3, I);
313 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
245 sample_f0_wdata_s(16*4+I) <= sample_f0(4, I);
314 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
246 sample_f0_wdata_s(16*5+I) <= sample_f0(5, I);
315 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
247 END GENERATE all_bit_sample_f0;
316 END GENERATE all_bit_sample_f0;
248
317
249 sample_f0_wen <= NOT(sample_f0_val) &
318 sample_f0_wen <= NOT(sample_f0_val) &
250 NOT(sample_f0_val) &
319 NOT(sample_f0_val) &
251 NOT(sample_f0_val) &
320 NOT(sample_f0_val) &
252 NOT(sample_f0_val) &
321 NOT(sample_f0_val) &
253 NOT(sample_f0_val) &
322 NOT(sample_f0_val) &
254 NOT(sample_f0_val);
323 NOT(sample_f0_val);
255
324
256 -----------------------------------------------------------------------------
325 -----------------------------------------------------------------------------
257 -- F1 -- @4096 Hz
326 -- F1 -- @4096 Hz
258 -----------------------------------------------------------------------------
327 -----------------------------------------------------------------------------
259 Downsampling_f1 : Downsampling
328 Downsampling_f1 : Downsampling
260 GENERIC MAP (
329 GENERIC MAP (
261 ChanelCount => 6,
330 ChanelCount => 8,
262 SampleSize => 16,
331 SampleSize => 16,
263 DivideParam => 6)
332 DivideParam => 6)
264 PORT MAP (
333 PORT MAP (
265 clk => clk,
334 clk => clk,
266 rstn => rstn,
335 rstn => rstn,
267 sample_in_val => sample_f0_val ,
336 sample_in_val => sample_f0_val ,
268 sample_in => sample_f0,
337 sample_in => sample_f0,
269 sample_out_val => sample_f1_val,
338 sample_out_val => sample_f1_val,
270 sample_out => sample_f1);
339 sample_out => sample_f1);
271
340
272 sample_f1_wen <= NOT(sample_f1_val) &
341 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
273 NOT(sample_f1_val) &
342 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
274 NOT(sample_f1_val) &
343 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
275 NOT(sample_f1_val) &
344 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
276 NOT(sample_f1_val) &
345 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
277 NOT(sample_f1_val);
346 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
347 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
348 END GENERATE all_bit_sample_f1;
278
349
279 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
350 sample_f1_wen <= NOT(sample_f1_val) &
280 sample_f1_wdata_s(I) <= sample_f1(0, I);
351 NOT(sample_f1_val) &
281 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I);
352 NOT(sample_f1_val) &
282 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I);
353 NOT(sample_f1_val) &
283 sample_f1_wdata_s(16*3+I) <= sample_f1(3, I);
354 NOT(sample_f1_val) &
284 sample_f1_wdata_s(16*4+I) <= sample_f1(4, I);
355 NOT(sample_f1_val);
285 sample_f1_wdata_s(16*5+I) <= sample_f1(5, I);
286 END GENERATE all_bit_sample_f1;
287
356
288 -----------------------------------------------------------------------------
357 -----------------------------------------------------------------------------
289 -- F2 -- @256 Hz
358 -- F2 -- @256 Hz
290 -----------------------------------------------------------------------------
359 -----------------------------------------------------------------------------
360 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
361 sample_f0_s(0, I) <= sample_f0(0, I); -- V
362 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
363 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
364 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
365 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
366 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
367 END GENERATE all_bit_sample_f0_s;
368
291 Downsampling_f2 : Downsampling
369 Downsampling_f2 : Downsampling
292 GENERIC MAP (
370 GENERIC MAP (
293 ChanelCount => 6,
371 ChanelCount => 6,
294 SampleSize => 16,
372 SampleSize => 16,
295 DivideParam => 96)
373 DivideParam => 96)
296 PORT MAP (
374 PORT MAP (
297 clk => clk,
375 clk => clk,
298 rstn => rstn,
376 rstn => rstn,
299 sample_in_val => sample_f0_val ,
377 sample_in_val => sample_f0_val ,
300 sample_in => sample_f0,
378 sample_in => sample_f0_s,
301 sample_out_val => sample_f2_val,
379 sample_out_val => sample_f2_val,
302 sample_out => sample_f2);
380 sample_out => sample_f2);
303
381
304 sample_f2_wen <= NOT(sample_f2_val) &
382 sample_f2_wen <= NOT(sample_f2_val) &
305 NOT(sample_f2_val) &
383 NOT(sample_f2_val) &
306 NOT(sample_f2_val) &
384 NOT(sample_f2_val) &
307 NOT(sample_f2_val) &
385 NOT(sample_f2_val) &
308 NOT(sample_f2_val) &
386 NOT(sample_f2_val) &
309 NOT(sample_f2_val);
387 NOT(sample_f2_val);
310
388
311 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
389 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
312 sample_f2_wdata_s(I) <= sample_f2(0, I);
390 sample_f2_wdata_s(I) <= sample_f2(0, I);
313 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
391 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
314 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
392 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
315 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
393 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
316 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
394 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
317 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
395 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
318 END GENERATE all_bit_sample_f2;
396 END GENERATE all_bit_sample_f2;
319
397
320 -----------------------------------------------------------------------------
398 -----------------------------------------------------------------------------
321 -- F3 -- @16 Hz
399 -- F3 -- @16 Hz
322 -----------------------------------------------------------------------------
400 -----------------------------------------------------------------------------
401 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
402 sample_f1_s(0, I) <= sample_f1(0, I); -- V
403 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
404 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
405 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
406 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
407 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
408 END GENERATE all_bit_sample_f1_s;
409
323 Downsampling_f3 : Downsampling
410 Downsampling_f3 : Downsampling
324 GENERIC MAP (
411 GENERIC MAP (
325 ChanelCount => 6,
412 ChanelCount => 6,
326 SampleSize => 16,
413 SampleSize => 16,
327 DivideParam => 256)
414 DivideParam => 256)
328 PORT MAP (
415 PORT MAP (
329 clk => clk,
416 clk => clk,
330 rstn => rstn,
417 rstn => rstn,
331 sample_in_val => sample_f1_val ,
418 sample_in_val => sample_f1_val ,
332 sample_in => sample_f1,
419 sample_in => sample_f1_s,
333 sample_out_val => sample_f3_val,
420 sample_out_val => sample_f3_val,
334 sample_out => sample_f3);
421 sample_out => sample_f3);
335
422
336 sample_f3_wen <= (NOT sample_f3_val) &
423 sample_f3_wen <= (NOT sample_f3_val) &
337 (NOT sample_f3_val) &
424 (NOT sample_f3_val) &
338 (NOT sample_f3_val) &
425 (NOT sample_f3_val) &
339 (NOT sample_f3_val) &
426 (NOT sample_f3_val) &
340 (NOT sample_f3_val) &
427 (NOT sample_f3_val) &
341 (NOT sample_f3_val);
428 (NOT sample_f3_val);
342
429
343 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
430 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
344 sample_f3_wdata_s(I) <= sample_f3(0, I);
431 sample_f3_wdata_s(I) <= sample_f3(0, I);
345 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
432 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
346 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
433 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
347 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
434 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
348 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
435 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
349 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
436 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
350 END GENERATE all_bit_sample_f3;
437 END GENERATE all_bit_sample_f3;
351
438
352 lpp_waveform_1 : lpp_waveform
439 lpp_waveform_1 : lpp_waveform
353 GENERIC MAP (
440 GENERIC MAP (
354 hindex => hindex,
441 hindex => hindex,
355 tech => tech,
442 tech => tech,
356 data_size => 160,
443 data_size => 160,
357 nb_burst_available_size => nb_burst_available_size,
444 nb_burst_available_size => nb_burst_available_size,
358 nb_snapshot_param_size => nb_snapshot_param_size,
445 nb_snapshot_param_size => nb_snapshot_param_size,
359 delta_snapshot_size => delta_snapshot_size,
446 delta_snapshot_size => delta_snapshot_size,
360 delta_f2_f0_size => delta_f2_f0_size,
447 delta_f2_f0_size => delta_f2_f0_size,
361 delta_f2_f1_size => delta_f2_f1_size)
448 delta_f2_f1_size => delta_f2_f1_size)
362 PORT MAP (
449 PORT MAP (
363 clk => clk,
450 clk => clk,
364 rstn => rstn,
451 rstn => rstn,
365
452
366 AHB_Master_In => AHB_Master_In,
453 AHB_Master_In => AHB_Master_In,
367 AHB_Master_Out => AHB_Master_Out,
454 AHB_Master_Out => AHB_Master_Out,
368
455
369 coarse_time_0 => coarse_time_0, -- IN
456 coarse_time_0 => coarse_time_0, -- IN
370 delta_snapshot => delta_snapshot, -- IN
457 delta_snapshot => delta_snapshot, -- IN
371 delta_f2_f1 => delta_f2_f1, -- IN
458 delta_f2_f1 => delta_f2_f1, -- IN
372 delta_f2_f0 => delta_f2_f0, -- IN
459 delta_f2_f0 => delta_f2_f0, -- IN
373 enable_f0 => enable_f0, -- IN
460 enable_f0 => enable_f0, -- IN
374 enable_f1 => enable_f1, -- IN
461 enable_f1 => enable_f1, -- IN
375 enable_f2 => enable_f2, -- IN
462 enable_f2 => enable_f2, -- IN
376 enable_f3 => enable_f3, -- IN
463 enable_f3 => enable_f3, -- IN
377 burst_f0 => burst_f0, -- IN
464 burst_f0 => burst_f0, -- IN
378 burst_f1 => burst_f1, -- IN
465 burst_f1 => burst_f1, -- IN
379 burst_f2 => burst_f2, -- IN
466 burst_f2 => burst_f2, -- IN
380 nb_burst_available => nb_burst_available,
467 nb_burst_available => nb_burst_available,
381 nb_snapshot_param => nb_snapshot_param,
468 nb_snapshot_param => nb_snapshot_param,
382 status_full => status_full,
469 status_full => status_full,
383 status_full_ack => status_full_ack, -- IN
470 status_full_ack => status_full_ack, -- IN
384 status_full_err => status_full_err,
471 status_full_err => status_full_err,
385 status_new_err => status_new_err,
472 status_new_err => status_new_err,
386
473
387 addr_data_f0 => addr_data_f0, -- IN
474 addr_data_f0 => addr_data_f0, -- IN
388 addr_data_f1 => addr_data_f1, -- IN
475 addr_data_f1 => addr_data_f1, -- IN
389 addr_data_f2 => addr_data_f2, -- IN
476 addr_data_f2 => addr_data_f2, -- IN
390 addr_data_f3 => addr_data_f3, -- IN
477 addr_data_f3 => addr_data_f3, -- IN
391
478
392 data_f0_in => data_f0_in_valid,
479 data_f0_in => data_f0_in_valid,
393 data_f1_in => data_f1_in_valid,
480 data_f1_in => data_f1_in_valid,
394 data_f2_in => data_f2_in_valid,
481 data_f2_in => data_f2_in_valid,
395 data_f3_in => data_f3_in_valid,
482 data_f3_in => data_f3_in_valid,
396 data_f0_in_valid => sample_f0_val,
483 data_f0_in_valid => sample_f0_val,
397 data_f1_in_valid => sample_f1_val,
484 data_f1_in_valid => sample_f1_val,
398 data_f2_in_valid => sample_f2_val,
485 data_f2_in_valid => sample_f2_val,
399 data_f3_in_valid => sample_f3_val);
486 data_f3_in_valid => sample_f3_val);
400
487
401 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
488 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
402 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
489 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
403 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
490 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
404 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
491 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
405
492
406 sample_f0_wdata <= sample_f0_wdata_s;
493 sample_f0_wdata <= sample_f0_wdata_s;
407 sample_f1_wdata <= sample_f1_wdata_s;
494 sample_f1_wdata <= sample_f1_wdata_s;
408 sample_f2_wdata <= sample_f2_wdata_s;
495 sample_f2_wdata <= sample_f2_wdata_s;
409 sample_f3_wdata <= sample_f3_wdata_s;
496 sample_f3_wdata <= sample_f3_wdata_s;
410
497
411 END tb;
498 END tb;
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2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
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66 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd
69 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_1word.vhd
67 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd
70 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_send_16word.vhd
68 #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd
71 #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_send_Nword.vhd
69 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd
72 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_selectaddress.vhd
70 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd
73 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_dma_genvalid.vhd
71
74
72 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
75 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
73
76
74 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
77 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
75
78
76 vsim work.TB_Data_Acquisition
79 vsim work.TB_Data_Acquisition
77
80
78 log -r *
81 log -r *
79 do wave_waveform_picker.do
82 do wave_waveform_picker.do
80 run 5 ms
83 run 5 ms
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@@ -1,75 +1,71
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27
28
29
25
30 ENTITY Adder IS
26 ENTITY Adder IS
31 GENERIC(
27 GENERIC(
32 Input_SZ_A : INTEGER := 16;
28 Input_SZ_A : INTEGER := 16;
33 Input_SZ_B : INTEGER := 16
29 Input_SZ_B : INTEGER := 16
34
30
35 );
31 );
36 PORT(
32 PORT(
37 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
38 reset : IN STD_LOGIC;
34 reset : IN STD_LOGIC;
39 clr : IN STD_LOGIC;
35 clr : IN STD_LOGIC;
40 load : IN STD_LOGIC;
36 load : IN STD_LOGIC;
41 add : IN STD_LOGIC;
37 add : IN STD_LOGIC;
42 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
38 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
43 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
39 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
44 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
40 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
45 );
41 );
46 END ENTITY;
42 END ENTITY;
47
43
48
44
49
45
50
46
51 ARCHITECTURE ar_Adder OF Adder IS
47 ARCHITECTURE ar_Adder OF Adder IS
52
48
53 SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
49 SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
54 SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
50 SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
55
51
56 BEGIN
52 BEGIN
57
53
58 RES <= REG;
54 RES <= REG;
59 RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
55 RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
60
56
61 PROCESS(clk, reset)
57 PROCESS(clk, reset)
62 BEGIN
58 BEGIN
63 IF reset = '0' THEN
59 IF reset = '0' THEN
64 REG <= (OTHERS => '0');
60 REG <= (OTHERS => '0');
65 ELSIF clk'EVENT AND clk = '1' then
61 ELSIF clk'EVENT AND clk = '1' then
66 IF clr = '1' THEN
62 IF clr = '1' THEN
67 REG <= (OTHERS => '0');
63 REG <= (OTHERS => '0');
68 ELSIF add = '1' THEN
64 ELSIF add = '1' THEN
69 REG <= RESADD;
65 REG <= RESADD;
70 ELSIF load = '1' THEN
66 ELSIF load = '1' THEN
71 REG <= OP2;
67 REG <= OP2;
72 END IF;
68 END IF;
73 END IF;
69 END IF;
74 END PROCESS;
70 END PROCESS;
75 END ar_Adder;
71 END ar_Adder;
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@@ -1,74 +1,71
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
25
29 --IDLE =00 MAC =01 MULT =10 ADD =11
26 --IDLE =00 MAC =01 MULT =10 ADD =11
30
27
31
28
32 entity MAC_CONTROLER is
29 entity MAC_CONTROLER is
33 port(
30 port(
34 ctrl : in std_logic_vector(1 downto 0);
31 ctrl : in std_logic_vector(1 downto 0);
35 MULT : out std_logic;
32 MULT : out std_logic;
36 ADD : out std_logic;
33 ADD : out std_logic;
37 LOAD_ADDER : out std_logic;
34 LOAD_ADDER : out std_logic;
38 MACMUX_sel : out std_logic;
35 MACMUX_sel : out std_logic;
39 MACMUX2_sel : out std_logic
36 MACMUX2_sel : out std_logic
40
37
41 );
38 );
42 end MAC_CONTROLER;
39 end MAC_CONTROLER;
43
40
44
41
45
42
46
43
47
44
48 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
45 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
49
46
50 begin
47 begin
51
48
52
49
53
50
54 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
55 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
56 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
53 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
57 -- to permit to compute a
54 -- to permit to compute a
58 -- MULT follow by a MAC
55 -- MULT follow by a MAC
59 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
56 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
60 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
57 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
61 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
58 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
62
59
63
60
64 end ar_MAC_CONTROLER;
61 end ar_MAC_CONTROLER;
65
62
66
63
67
64
68
65
69
66
70
67
71
68
72
69
73
70
74
71
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@@ -1,57 +1,53
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
29
25
30 entity MAC_MUX is
26 entity MAC_MUX is
31 generic(
27 generic(
32 Input_SZ_A : integer := 16;
28 Input_SZ_A : integer := 16;
33 Input_SZ_B : integer := 16
29 Input_SZ_B : integer := 16
34
30
35 );
31 );
36 port(
32 port(
37 sel : in std_logic;
33 sel : in std_logic;
38 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
34 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
39 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
35 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
40 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
36 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
41 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
37 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
42 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
38 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
43 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
39 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
44 );
40 );
45 end entity;
41 end entity;
46
42
47
43
48
44
49
45
50 architecture ar_MAC_MUX of MAC_MUX is
46 architecture ar_MAC_MUX of MAC_MUX is
51
47
52 begin
48 begin
53
49
54 OUTA <= INA1 when sel = '0' else INA2;
50 OUTA <= INA1 when sel = '0' else INA2;
55 OUTB <= INB1 when sel = '0' else INB2;
51 OUTB <= INB1 when sel = '0' else INB2;
56
52
57 end ar_MAC_MUX;
53 end ar_MAC_MUX;
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@@ -1,49 +1,46
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
25
29
26
30 entity MAC_MUX2 is
27 entity MAC_MUX2 is
31 generic(Input_SZ : integer := 16);
28 generic(Input_SZ : integer := 16);
32 port(
29 port(
33 sel : in std_logic;
30 sel : in std_logic;
34 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
31 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
35 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
32 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
36 RES : out std_logic_vector(Input_SZ-1 downto 0)
33 RES : out std_logic_vector(Input_SZ-1 downto 0)
37 );
34 );
38 end entity;
35 end entity;
39
36
40
37
41
38
42
39
43 architecture ar_MAC_MUX2 of MAC_MUX2 is
40 architecture ar_MAC_MUX2 of MAC_MUX2 is
44
41
45 begin
42 begin
46
43
47 RES <= RES1 when sel = '0' else RES2;
44 RES <= RES1 when sel = '0' else RES2;
48
45
49 end ar_MAC_MUX2;
46 end ar_MAC_MUX2;
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@@ -1,62 +1,58
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
29
25
30 entity MAC_REG is
26 entity MAC_REG is
31 generic(size : integer := 16);
27 generic(size : integer := 16);
32 port(
28 port(
33 reset : in std_logic;
29 reset : in std_logic;
34 clk : in std_logic;
30 clk : in std_logic;
35 D : in std_logic_vector(size-1 downto 0);
31 D : in std_logic_vector(size-1 downto 0);
36 Q : out std_logic_vector(size-1 downto 0)
32 Q : out std_logic_vector(size-1 downto 0)
37 );
33 );
38 end entity;
34 end entity;
39
35
40
36
41
37
42 architecture ar_MAC_REG of MAC_REG is
38 architecture ar_MAC_REG of MAC_REG is
43 begin
39 begin
44 process(clk,reset)
40 process(clk,reset)
45 begin
41 begin
46 if reset = '0' then
42 if reset = '0' then
47 Q <= (others => '0');
43 Q <= (others => '0');
48 elsif clk'event and clk ='1' then
44 elsif clk'event and clk ='1' then
49 Q <= D;
45 Q <= D;
50 end if;
46 end if;
51 end process;
47 end process;
52 end ar_MAC_REG;
48 end ar_MAC_REG;
53
49
54
50
55
51
56
52
57
53
58
54
59
55
60
56
61
57
62
58
Show file before | Show file after | Hide comments
@@ -1,80 +1,75
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 library lpp;
27 use lpp.general_purpose.all;
28
29
30
31 entity Multiplier is
26 entity Multiplier is
32 generic(
27 generic(
33 Input_SZ_A : integer := 16;
28 Input_SZ_A : integer := 16;
34 Input_SZ_B : integer := 16
29 Input_SZ_B : integer := 16
35
30
36 );
31 );
37 port(
32 port(
38 clk : in std_logic;
33 clk : in std_logic;
39 reset : in std_logic;
34 reset : in std_logic;
40 mult : in std_logic;
35 mult : in std_logic;
41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
36 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
37 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
43 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
38 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
44 );
39 );
45 end Multiplier;
40 end Multiplier;
46
41
47
42
48
43
49
44
50
45
51 architecture ar_Multiplier of Multiplier is
46 architecture ar_Multiplier of Multiplier is
52
47
53 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
48 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
54 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
55
50
56
51
57 begin
52 begin
58
53
59 RES <= REG;
54 RES <= REG;
60 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
55 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
61 process(clk,reset)
56 process(clk,reset)
62 begin
57 begin
63 if reset = '0' then
58 if reset = '0' then
64 REG <= (others => '0');
59 REG <= (others => '0');
65 elsif clk'event and clk ='1' then
60 elsif clk'event and clk ='1' then
66 if mult = '1' then
61 if mult = '1' then
67 REG <= RESMULT;
62 REG <= RESMULT;
68 end if;
63 end if;
69 end if;
64 end if;
70 end process;
65 end process;
71
66
72 end ar_Multiplier;
67 end ar_Multiplier;
73
68
74
69
75
70
76
71
77
72
78
73
79
74
80
75
Show file before | Show file after | Hide comments
@@ -1,217 +1,216
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
25 use lpp.general_purpose.all;
27
26
28 --! Driver de l'ALU
27 --! Driver de l'ALU
29
28
30 entity ALU_Driver is
29 entity ALU_Driver is
31 generic(
30 generic(
32 Input_SZ_1 : integer := 16;
31 Input_SZ_1 : integer := 16;
33 Input_SZ_2 : integer := 16);
32 Input_SZ_2 : integer := 16);
34 port(
33 port(
35 clk : in std_logic; --! Horloge du composant
34 clk : in std_logic; --! Horloge du composant
36 reset : in std_logic; --! Reset general du composant
35 reset : in std_logic; --! Reset general du composant
37 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
38 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
39 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Take : in std_logic; --! Flag, op�rande r�cup�r�
40 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Received : in std_logic; --! Flag, R�sultat bien ressu
41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
42 Valid : out std_logic; --! Flag, R�sultat disponible
41 Valid : out std_logic; --! Flag, R�sultat disponible
43 Read : out std_logic; --! Flag, op�rande disponible
42 Read : out std_logic; --! Flag, op�rande disponible
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
43 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
44 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
45 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
46 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
48 );
47 );
49 end ALU_Driver;
48 end ALU_Driver;
50
49
51 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
50 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
52
51
53 architecture ar_ALU_Driver of ALU_Driver is
52 architecture ar_ALU_Driver of ALU_Driver is
54
53
55 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
54 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
55 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
57 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
56 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
58 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
57 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
59
58
60 signal go_st : std_logic;
59 signal go_st : std_logic;
61 signal Take_reg : std_logic;
60 signal Take_reg : std_logic;
62 signal Received_reg : std_logic;
61 signal Received_reg : std_logic;
63
62
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
63 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
65 signal ect : etat;
64 signal ect : etat;
66 signal st : etat;
65 signal st : etat;
67
66
68 begin
67 begin
69 process(clk,reset)
68 process(clk,reset)
70 begin
69 begin
71
70
72 if(reset='0')then
71 if(reset='0')then
73 ect <= eX;
72 ect <= eX;
74 st <= e0;
73 st <= e0;
75 go_st <= '0';
74 go_st <= '0';
76 CTRL <= ctrl_CLRMAC;
75 CTRL <= ctrl_CLRMAC;
77 COMP <= "00"; -- pas de complement
76 COMP <= "00"; -- pas de complement
78 Read <= '0';
77 Read <= '0';
79 Valid <= '0';
78 Valid <= '0';
80 Take_reg <= '0';
79 Take_reg <= '0';
81 Received_reg <= '0';
80 Received_reg <= '0';
82
81
83 elsif(clk'event and clk='1')then
82 elsif(clk'event and clk='1')then
84 Take_reg <= Take;
83 Take_reg <= Take;
85 Received_reg <= Received;
84 Received_reg <= Received;
86
85
87 case ect is
86 case ect is
88 when eX =>
87 when eX =>
89 go_st <= '0';
88 go_st <= '0';
90 Read <= '1';
89 Read <= '1';
91 CTRL <= ctrl_CLRMAC;
90 CTRL <= ctrl_CLRMAC;
92 ect <= e0;
91 ect <= e0;
93
92
94 when e0 =>
93 when e0 =>
95 OP1re <= IN1;
94 OP1re <= IN1;
96 if(Conjugate='1')then --
95 if(Conjugate='1')then --
97 OP2re <= IN1; --
96 OP2re <= IN1; --
98 else --
97 else --
99 OP2re <= IN2; -- modif 23/06/11
98 OP2re <= IN2; -- modif 23/06/11
100 end if; --
99 end if; --
101 if(Take_reg='0' and Take='1')then
100 if(Take_reg='0' and Take='1')then
102 read <= '0';
101 read <= '0';
103 ect <= e1;
102 ect <= e1;
104 end if;
103 end if;
105
104
106 when e1 =>
105 when e1 =>
107 OP1 <= OP1re;
106 OP1 <= OP1re;
108 OP2 <= OP2re;
107 OP2 <= OP2re;
109 CTRL <= ctrl_MAC;
108 CTRL <= ctrl_MAC;
110 Read <= '1';
109 Read <= '1';
111 ect <= eY;
110 ect <= eY;
112
111
113 when eY =>
112 when eY =>
114 OP1im <= IN1;
113 OP1im <= IN1;
115 if(Conjugate='1')then --
114 if(Conjugate='1')then --
116 OP2im <= IN1; --
115 OP2im <= IN1; --
117 else --
116 else --
118 OP2im <= IN2; -- modif 23/06/11
117 OP2im <= IN2; -- modif 23/06/11
119 end if; --
118 end if; --
120 CTRL <= ctrl_IDLE;
119 CTRL <= ctrl_IDLE;
121 if(Take_reg='1' and Take='0')then
120 if(Take_reg='1' and Take='0')then
122 Read <= '0';
121 Read <= '0';
123 ect <= e2;
122 ect <= e2;
124 end if;
123 end if;
125
124
126 when e2 =>
125 when e2 =>
127 OP1 <= OP1im;
126 OP1 <= OP1im;
128 OP2 <= OP2im;
127 OP2 <= OP2im;
129 CTRL <= ctrl_MAC;
128 CTRL <= ctrl_MAC;
130 ect <= eZ;
129 ect <= eZ;
131
130
132 when eZ =>
131 when eZ =>
133 CTRL <= ctrl_IDLE;
132 CTRL <= ctrl_IDLE;
134 go_st <= '1';
133 go_st <= '1';
135 if(Received_reg='0' and Received='1')then
134 if(Received_reg='0' and Received='1')then
136 if(Conjugate='1')then
135 if(Conjugate='1')then
137 ect <= eX;
136 ect <= eX;
138 else
137 else
139 ect <= e3;
138 ect <= e3;
140 end if;
139 end if;
141 end if;
140 end if;
142
141
143 when e3 =>
142 when e3 =>
144 CTRL <= ctrl_CLRMAC;
143 CTRL <= ctrl_CLRMAC;
145 go_st <= '0';
144 go_st <= '0';
146 ect <= e4;
145 ect <= e4;
147
146
148 when e4 =>
147 when e4 =>
149 OP1 <= OP1im;
148 OP1 <= OP1im;
150 OP2 <= OP2re;
149 OP2 <= OP2re;
151 CTRL <= ctrl_MAC;
150 CTRL <= ctrl_MAC;
152 ect <= e5;
151 ect <= e5;
153
152
154 when e5 =>
153 when e5 =>
155 OP1 <= OP1re;
154 OP1 <= OP1re;
156 OP2 <= OP2im;
155 OP2 <= OP2im;
157 COMP <= "10";
156 COMP <= "10";
158 ect <= eW;
157 ect <= eW;
159
158
160 when eW =>
159 when eW =>
161 CTRL <= ctrl_IDLE;
160 CTRL <= ctrl_IDLE;
162 COMP <= "00";
161 COMP <= "00";
163 go_st <= '1';
162 go_st <= '1';
164 if(Received_reg='1' and Received='0')then
163 if(Received_reg='1' and Received='0')then
165 ect <= eX;
164 ect <= eX;
166 end if;
165 end if;
167 end case;
166 end case;
168 ---------------------------------------------------------------------------------
167 ---------------------------------------------------------------------------------
169 case st is
168 case st is
170 when e0 =>
169 when e0 =>
171 if(go_st='1')then
170 if(go_st='1')then
172 st <= e1;
171 st <= e1;
173 end if;
172 end if;
174
173
175 when e1 =>
174 when e1 =>
176 Valid <= '1';
175 Valid <= '1';
177 st <= e2;
176 st <= e2;
178
177
179 when e2 =>
178 when e2 =>
180 if(Received_reg='0' and Received='1')then
179 if(Received_reg='0' and Received='1')then
181 Valid <= '0';
180 Valid <= '0';
182 if(Conjugate='1')then
181 if(Conjugate='1')then
183 st <= eY;
182 st <= eY;
184 else
183 else
185 st <= eX;
184 st <= eX;
186 end if;
185 end if;
187 end if;
186 end if;
188
187
189 when eX =>
188 when eX =>
190 st <= e3;
189 st <= e3;
191
190
192 when e3 =>
191 when e3 =>
193 if(go_st='1')then
192 if(go_st='1')then
194 st <= e4;
193 st <= e4;
195 end if;
194 end if;
196
195
197 when e4 =>
196 when e4 =>
198 Valid <= '1';
197 Valid <= '1';
199 st <= e5;
198 st <= e5;
200
199
201 when e5 =>
200 when e5 =>
202 if(Received_reg='1' and Received='0')then
201 if(Received_reg='1' and Received='0')then
203 Valid <= '0';
202 Valid <= '0';
204 st <= eY;
203 st <= eY;
205 end if;
204 end if;
206
205
207 when eY =>
206 when eY =>
208 st <= e0;
207 st <= e0;
209
208
210 when others =>
209 when others =>
211 null;
210 null;
212 end case;
211 end case;
213
212
214 end if;
213 end if;
215 end process;
214 end process;
216
215
217 end ar_ALU_Driver; No newline at end of file
216 end ar_ALU_Driver;
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@@ -1,76 +1,84
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 --library lpp;
26 use lpp.lpp_matrix.all;
26 --use lpp.lpp_matrix.all;
27
27
28 entity MatriceSpectrale is
28 entity MatriceSpectrale is
29 generic(
29 generic(
30 Input_SZ : integer := 16;
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
31 Result_SZ : integer := 32);
32 port(
32 port(
33 clkm : in std_logic;
33 clkm : in std_logic;
34 rstn : in std_logic;
34 rstn : in std_logic;
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
37 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 Data_IN : in std_logic_vector(79 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 ACQ : in std_logic;
40 ACQ : in std_logic;
40 FlagError : out std_logic;
41 FlagError : out std_logic;
41 Pong : out std_logic;
42 Pong : out std_logic;
43 Statu : out std_logic_vector(3 downto 0);
42 Write : out std_logic_vector(1 downto 0);
44 Write : out std_logic_vector(1 downto 0);
43 Read : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0);
44 Data_OUT : out std_logic_vector(63 downto 0)
46 ReUse : out std_logic_vector(4 downto 0);
47 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
45 );
48 );
46 end entity;
49 end entity;
47
50
48
51
49 architecture ar_MatriceSpectrale of MatriceSpectrale is
52 architecture ar_MatriceSpectrale of MatriceSpectrale is
50
53
51 signal Matrix_Write : std_logic;
54 signal Matrix_Write : std_logic;
52 signal Matrix_Read : std_logic_vector(1 downto 0);
55 signal Matrix_Read : std_logic_vector(1 downto 0);
53 signal Matrix_Result : std_logic_vector(31 downto 0);
56 signal Matrix_Result : std_logic_vector(31 downto 0);
54
57
55 signal TopSM_Start : std_logic;
58 signal TopSM_Start : std_logic;
56 signal TopSM_Statu : std_logic_vector(3 downto 0);
59 signal TopSM_Statu : std_logic_vector(3 downto 0);
57 signal TopSM_Data1 : std_logic_vector(15 downto 0);
60 signal TopSM_Data1 : std_logic_vector(15 downto 0);
58 signal TopSM_Data2 : std_logic_vector(15 downto 0);
61 signal TopSM_Data2 : std_logic_vector(15 downto 0);
59
62
60 begin
63 begin
61
64
62 TopSM : TopSpecMatrix
65 CTRL0 : entity work.ReUse_CTRLR
66 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
67
68
69 TopSM : entity work.TopSpecMatrix
63 generic map (Input_SZ)
70 generic map (Input_SZ)
64 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
71 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
65
72
66 SM : SpectralMatrix
73 SM : entity work.SpectralMatrix
67 generic map (Input_SZ,Result_SZ)
74 generic map (Input_SZ,Result_SZ)
68 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
75 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
69
76
70 DISP : Dispatch
77 DISP : entity work.Dispatch
71 generic map(Result_SZ)
78 generic map(Result_SZ)
72 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
79 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
73
80
81 Statu <= TopSM_Statu;
74
82
75 end architecture;
83 end architecture;
76
84
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@@ -1,253 +1,266
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic;
44 clk : in std_logic;
45 rst : in std_logic;
45 rst : in std_logic;
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
51 FullFIFO : in std_logic;
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
56 );
57 end component;
57 end component;
58
58
59 component MatriceSpectrale is
59 component MatriceSpectrale is
60 generic(
60 generic(
61 Input_SZ : integer := 16;
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
62 Result_SZ : integer := 32);
63 port(
63 port(
64 clkm : in std_logic;
64 clkm : in std_logic;
65 rstn : in std_logic;
65 rstn : in std_logic;
66
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
68 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 Data_IN : in std_logic_vector(79 downto 0);
70 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
70 ACQ : in std_logic;
71 ACQ : in std_logic;
71 FlagError : out std_logic;
72 FlagError : out std_logic;
72 Pong : out std_logic;
73 Pong : out std_logic;
74 Statu : out std_logic_vector(3 downto 0);
73 Write : out std_logic_vector(1 downto 0);
75 Write : out std_logic_vector(1 downto 0);
74 Read : out std_logic_vector(4 downto 0);
76 Read : out std_logic_vector(4 downto 0);
75 Data_OUT : out std_logic_vector(63 downto 0)
77 ReUse : out std_logic_vector(4 downto 0);
78 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
76 );
79 );
77 end component;
80 end component;
78
81
79
82
80 component TopSpecMatrix is
83 component TopSpecMatrix is
81 generic(
84 generic(
82 Input_SZ : integer := 16);
85 Input_SZ : integer := 16);
83 port(
86 port(
84 clk : in std_logic;
87 clk : in std_logic;
85 rstn : in std_logic;
88 rstn : in std_logic;
86 Write : in std_logic;
89 Write : in std_logic;
87 ReadIn : in std_logic_vector(1 downto 0);
90 ReadIn : in std_logic_vector(1 downto 0);
88 Full : in std_logic_vector(4 downto 0);
91 Full : in std_logic_vector(4 downto 0);
89 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
92 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
90 Start : out std_logic;
93 Start : out std_logic;
91 ReadOut : out std_logic_vector(4 downto 0);
94 ReadOut : out std_logic_vector(4 downto 0);
92 Statu : out std_logic_vector(3 downto 0);
95 Statu : out std_logic_vector(3 downto 0);
93 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
96 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
94 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
97 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
95 );
98 );
96 end component;
99 end component;
97
100
98
101
99 component Top_MatrixSpec is
102 component Top_MatrixSpec is
100 generic(
103 generic(
101 Input_SZ : integer := 16;
104 Input_SZ : integer := 16;
102 Result_SZ : integer := 32);
105 Result_SZ : integer := 32);
103 port(
106 port(
104 clk : in std_logic;
107 clk : in std_logic;
105 reset : in std_logic;
108 reset : in std_logic;
106 Statu : in std_logic_vector(3 downto 0);
109 Statu : in std_logic_vector(3 downto 0);
107 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
110 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
108 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
111 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
109 Full : in std_logic_vector(1 downto 0);
112 Full : in std_logic_vector(1 downto 0);
110 Empty : in std_logic_vector(1 downto 0);
113 Empty : in std_logic_vector(1 downto 0);
111 ReadFIFO : out std_logic_vector(1 downto 0);
114 ReadFIFO : out std_logic_vector(1 downto 0);
112 FullFIFO : in std_logic;
115 FullFIFO : in std_logic;
113 WriteFIFO : out std_logic;
116 WriteFIFO : out std_logic;
114 Result : out std_logic_vector(Result_SZ-1 downto 0)
117 Result : out std_logic_vector(Result_SZ-1 downto 0)
115 );
118 );
116 end component;
119 end component;
117
120
118 component SpectralMatrix is
121 component SpectralMatrix is
119 generic(
122 generic(
120 Input_SZ : integer := 16;
123 Input_SZ : integer := 16;
121 Result_SZ : integer := 32);
124 Result_SZ : integer := 32);
122 port(
125 port(
123 clk : in std_logic;
126 clk : in std_logic;
124 reset : in std_logic;
127 reset : in std_logic;
125 Start : in std_logic;
128 Start : in std_logic;
126 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
129 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
127 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
130 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
128 Statu : in std_logic_vector(3 downto 0);
131 Statu : in std_logic_vector(3 downto 0);
129 -- FullFIFO : in std_logic;
132 -- FullFIFO : in std_logic;
130 ReadFIFO : out std_logic_vector(1 downto 0);
133 ReadFIFO : out std_logic_vector(1 downto 0);
131 WriteFIFO : out std_logic;
134 WriteFIFO : out std_logic;
132 Result : out std_logic_vector(Result_SZ-1 downto 0)
135 Result : out std_logic_vector(Result_SZ-1 downto 0)
133 );
136 );
134 end component;
137 end component;
135
138
136
139
137 component Matrix is
140 component Matrix is
138 generic(
141 generic(
139 Input_SZ : integer := 16);
142 Input_SZ : integer := 16);
140 port(
143 port(
141 clk : in std_logic;
144 clk : in std_logic;
142 raz : in std_logic;
145 raz : in std_logic;
143 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
146 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
144 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
147 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
145 Take : in std_logic;
148 Take : in std_logic;
146 Received : in std_logic;
149 Received : in std_logic;
147 Conjugate : in std_logic;
150 Conjugate : in std_logic;
148 Valid : out std_logic;
151 Valid : out std_logic;
149 Read : out std_logic;
152 Read : out std_logic;
150 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
153 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
151 );
154 );
152 end component;
155 end component;
153
156
154 component GetResult is
157 component GetResult is
155 generic(
158 generic(
156 Result_SZ : integer := 32);
159 Result_SZ : integer := 32);
157 port(
160 port(
158 clk : in std_logic;
161 clk : in std_logic;
159 raz : in std_logic;
162 raz : in std_logic;
160 Valid : in std_logic;
163 Valid : in std_logic;
161 Conjugate : in std_logic;
164 Conjugate : in std_logic;
162 Res : in std_logic_vector(Result_SZ-1 downto 0);
165 Res : in std_logic_vector(Result_SZ-1 downto 0);
163 -- Full : in std_logic;
166 -- Full : in std_logic;
164 WriteFIFO : out std_logic;
167 WriteFIFO : out std_logic;
165 Received : out std_logic;
168 Received : out std_logic;
166 Result : out std_logic_vector(Result_SZ-1 downto 0)
169 Result : out std_logic_vector(Result_SZ-1 downto 0)
167 );
170 );
168 end component;
171 end component;
169
172
170
173
171 component TopMatrix_PDR is
174 component TopMatrix_PDR is
172 generic(
175 generic(
173 Input_SZ : integer := 16;
176 Input_SZ : integer := 16;
174 Result_SZ : integer := 32);
177 Result_SZ : integer := 32);
175 port(
178 port(
176 clk : in std_logic;
179 clk : in std_logic;
177 reset : in std_logic;
180 reset : in std_logic;
178 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
181 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
179 FULLin : in std_logic_vector(4 downto 0);
182 FULLin : in std_logic_vector(4 downto 0);
180 READin : in std_logic_vector(1 downto 0);
183 READin : in std_logic_vector(1 downto 0);
181 WRITEin : in std_logic;
184 WRITEin : in std_logic;
182 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
185 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
183 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
186 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
184 Start : out std_logic;
187 Start : out std_logic;
185 Read : out std_logic_vector(4 downto 0);
188 Read : out std_logic_vector(4 downto 0);
186 Statu : out std_logic_vector(3 downto 0)
189 Statu : out std_logic_vector(3 downto 0)
187 );
190 );
188 end component;
191 end component;
189
192
190
193
191 component Dispatch is
194 component Dispatch is
192 generic(
195 generic(
193 Data_SZ : integer := 32);
196 Data_SZ : integer := 32);
194 port(
197 port(
195 clk : in std_logic;
198 clk : in std_logic;
196 reset : in std_logic;
199 reset : in std_logic;
197 Acq : in std_logic;
200 Acq : in std_logic;
198 Data : in std_logic_vector(Data_SZ-1 downto 0);
201 Data : in std_logic_vector(Data_SZ-1 downto 0);
199 Write : in std_logic;
202 Write : in std_logic;
200 Full : in std_logic_vector(1 downto 0);
203 Full : in std_logic_vector(1 downto 0);
201 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
204 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
202 FifoWrite : out std_logic_vector(1 downto 0);
205 FifoWrite : out std_logic_vector(1 downto 0);
203 Pong : out std_logic;
206 Pong : out std_logic;
204 Error : out std_logic
207 Error : out std_logic
205 );
208 );
206 end component;
209 end component;
207
210
208
211
209 component DriveInputs is
212 component DriveInputs is
210 port(
213 port(
211 clk : in std_logic;
214 clk : in std_logic;
212 raz : in std_logic;
215 raz : in std_logic;
213 Read : in std_logic;
216 Read : in std_logic;
214 Conjugate : in std_logic;
217 Conjugate : in std_logic;
215 Take : out std_logic;
218 Take : out std_logic;
216 ReadFIFO : out std_logic_vector(1 downto 0)
219 ReadFIFO : out std_logic_vector(1 downto 0)
217 );
220 );
218 end component;
221 end component;
219
222
220 component Starter is
223 component Starter is
221 port(
224 port(
222 clk : in std_logic;
225 clk : in std_logic;
223 raz : in std_logic;
226 raz : in std_logic;
224 Full : in std_logic_vector(1 downto 0);
227 Full : in std_logic_vector(1 downto 0);
225 Empty : in std_logic_vector(1 downto 0);
228 Empty : in std_logic_vector(1 downto 0);
226 Statu : in std_logic_vector(3 downto 0);
229 Statu : in std_logic_vector(3 downto 0);
227 Write : in std_logic;
230 Write : in std_logic;
228 Start : out std_logic
231 Start : out std_logic
229 );
232 );
230 end component;
233 end component;
231
234
232 component ALU_Driver is
235 component ALU_Driver is
233 generic(
236 generic(
234 Input_SZ_1 : integer := 16;
237 Input_SZ_1 : integer := 16;
235 Input_SZ_2 : integer := 16);
238 Input_SZ_2 : integer := 16);
236 port(
239 port(
237 clk : in std_logic;
240 clk : in std_logic;
238 reset : in std_logic;
241 reset : in std_logic;
239 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
242 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
240 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
243 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
241 Take : in std_logic;
244 Take : in std_logic;
242 Received : in std_logic;
245 Received : in std_logic;
243 Conjugate : in std_logic;
246 Conjugate : in std_logic;
244 Valid : out std_logic;
247 Valid : out std_logic;
245 Read : out std_logic;
248 Read : out std_logic;
246 CTRL : out std_logic_vector(2 downto 0);
249 CTRL : out std_logic_vector(2 downto 0);
247 COMP : out std_logic_vector(1 downto 0);
250 COMP : out std_logic_vector(1 downto 0);
248 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
251 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
249 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
252 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
250 );
253 );
251 end component;
254 end component;
252
255
256 component ReUse_CTRLR is
257 port(
258 clk : in std_logic;
259 reset : in std_logic;
260 SetReUse : in std_logic_vector(4 downto 0);
261 Statu : in std_logic_vector(3 downto 0);
262 ReUse : out std_logic_vector(4 downto 0)
263 );
264 end component;
265
253 end; No newline at end of file
266 end;
Show file before | Show file after | Hide comments
@@ -1,303 +1,303
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
10 USE techmap.gencomp.ALL;
11
11
12 ENTITY lpp_top_acq IS
12 ENTITY lpp_top_acq IS
13 GENERIC(
13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0
15 );
15 );
16 PORT (
16 PORT (
17 -- ADS7886
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC; -- 25 MHz
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 --
31 --
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
40 );
40 );
41 END lpp_top_acq;
41 END lpp_top_acq;
42
42
43 ARCHITECTURE tb OF lpp_top_acq IS
43 ARCHITECTURE tb OF lpp_top_acq IS
44
44
45 COMPONENT Downsampling
45 COMPONENT Downsampling
46 GENERIC (
46 GENERIC (
47 ChanelCount : INTEGER;
47 ChanelCount : INTEGER;
48 SampleSize : INTEGER;
48 SampleSize : INTEGER;
49 DivideParam : INTEGER);
49 DivideParam : INTEGER);
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_out_val : OUT STD_LOGIC;
55 sample_out_val : OUT STD_LOGIC;
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 END COMPONENT;
57 END COMPONENT;
58
58
59 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
60 CONSTANT ChanelCount : INTEGER := 8;
60 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv : INTEGER := 500;
62 CONSTANT ncycle_cnv : INTEGER := 500;
63
63
64 -----------------------------------------------------------------------------
64 -----------------------------------------------------------------------------
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample_val : STD_LOGIC;
66 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 CONSTANT Coef_SZ : INTEGER := 9;
69 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefPerCel : INTEGER := 5;
71 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
73
73
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 --
76 --
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
79 --
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 --
86 --
87 SIGNAL sample_f0_val : STD_LOGIC;
87 SIGNAL sample_f0_val : STD_LOGIC;
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 SIGNAL sample_f1_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
92 --
93 SIGNAL sample_f2_val : STD_LOGIC;
93 SIGNAL sample_f2_val : STD_LOGIC;
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 --
95 --
96 SIGNAL sample_f3_val : STD_LOGIC;
96 SIGNAL sample_f3_val : STD_LOGIC;
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98
98
99 BEGIN
99 BEGIN
100
100
101 -- component instantiation
101 -- component instantiation
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 DIGITAL_acquisition : AD7688_drvr
103 DIGITAL_acquisition : AD7688_drvr
104 GENERIC MAP (
104 GENERIC MAP (
105 ChanelCount => ChanelCount,
105 ChanelCount => ChanelCount,
106 ncycle_cnv_high => ncycle_cnv_high,
106 ncycle_cnv_high => ncycle_cnv_high,
107 ncycle_cnv => ncycle_cnv)
107 ncycle_cnv => ncycle_cnv)
108 PORT MAP (
108 PORT MAP (
109 cnv_clk => cnv_clk, --
109 cnv_clk => cnv_clk, --
110 cnv_rstn => cnv_rstn, --
110 cnv_rstn => cnv_rstn, --
111 cnv_run => cnv_run, --
111 cnv_run => cnv_run, --
112 cnv => cnv, --
112 cnv => cnv, --
113 clk => clk, --
113 clk => clk, --
114 rstn => rstn, --
114 rstn => rstn, --
115 sck => sck, --
115 sck => sck, --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
117 sample => sample,
117 sample => sample,
118 sample_val => sample_val);
118 sample_val => sample_val);
119
119
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121
121
122 PROCESS (clk, rstn)
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 sample_val_delay <= '0';
125 sample_val_delay <= '0';
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 sample_val_delay <= sample_val;
127 sample_val_delay <= sample_val;
128 END IF;
128 END IF;
129 END PROCESS;
129 END PROCESS;
130
130
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
134 sample_filter_in(i, j) <= sample(i)(j);
134 sample_filter_in(i, j) <= sample(i)(j);
135 END GENERATE;
135 END GENERATE;
136
136
137 sample_filter_in(i, 16) <= sample(i)(15);
137 sample_filter_in(i, 16) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
139 END GENERATE;
139 END GENERATE;
140
140
141 coefs_v2 <= CoefsInitValCst_v2;
141 coefs_v2 <= CoefsInitValCst_v2;
142
142
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 GENERIC MAP (
144 GENERIC MAP (
145 tech => 0,
145 tech => 0,
146 Mem_use => use_CEL,
146 Mem_use => use_RAM,
147 Sample_SZ => 18,
147 Sample_SZ => 18,
148 Coef_SZ => Coef_SZ,
148 Coef_SZ => Coef_SZ,
149 Coef_Nb => 25, -- TODO
149 Coef_Nb => 25, -- TODO
150 Coef_sel_SZ => 5, -- TODO
150 Coef_sel_SZ => 5, -- TODO
151 Cels_count => Cels_count,
151 Cels_count => Cels_count,
152 ChanelsCount => ChanelCount)
152 ChanelsCount => ChanelCount)
153 PORT MAP (
153 PORT MAP (
154 rstn => rstn,
154 rstn => rstn,
155 clk => clk,
155 clk => clk,
156 virg_pos => 7,
156 virg_pos => 7,
157 coefs => coefs_v2,
157 coefs => coefs_v2,
158 sample_in_val => sample_val_delay,
158 sample_in_val => sample_val_delay,
159 sample_in => sample_filter_in,
159 sample_in => sample_filter_in,
160 sample_out_val => sample_filter_v2_out_val,
160 sample_out_val => sample_filter_v2_out_val,
161 sample_out => sample_filter_v2_out);
161 sample_out => sample_filter_v2_out);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 PROCESS (clk, rstn)
164 PROCESS (clk, rstn)
165 BEGIN -- PROCESS
165 BEGIN -- PROCESS
166 IF rstn = '0' THEN -- asynchronous reset (active low)
166 IF rstn = '0' THEN -- asynchronous reset (active low)
167 sample_filter_v2_out_r_val <= '0';
167 sample_filter_v2_out_r_val <= '0';
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
170 sample_filter_v2_out_r(I, J) <= '0';
170 sample_filter_v2_out_r(I, J) <= '0';
171 END LOOP rst_all_bits;
171 END LOOP rst_all_bits;
172 END LOOP rst_all_chanel;
172 END LOOP rst_all_chanel;
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
175 IF sample_filter_v2_out_val = '1' THEN
175 IF sample_filter_v2_out_val = '1' THEN
176 sample_filter_v2_out_r <= sample_filter_v2_out;
176 sample_filter_v2_out_r <= sample_filter_v2_out;
177 END IF;
177 END IF;
178 END IF;
178 END IF;
179 END PROCESS;
179 END PROCESS;
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- F0 -- @24.576 kHz
182 -- F0 -- @24.576 kHz
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184 Downsampling_f0 : Downsampling
184 Downsampling_f0 : Downsampling
185 GENERIC MAP (
185 GENERIC MAP (
186 ChanelCount => ChanelCount,
186 ChanelCount => ChanelCount,
187 SampleSize => 18,
187 SampleSize => 18,
188 DivideParam => 4)
188 DivideParam => 4)
189 PORT MAP (
189 PORT MAP (
190 clk => clk,
190 clk => clk,
191 rstn => rstn,
191 rstn => rstn,
192 sample_in_val => sample_filter_v2_out_val ,
192 sample_in_val => sample_filter_v2_out_val ,
193 sample_in => sample_filter_v2_out,
193 sample_in => sample_filter_v2_out,
194 sample_out_val => sample_f0_val,
194 sample_out_val => sample_f0_val,
195 sample_out => sample_f0);
195 sample_out => sample_f0);
196
196
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
198 sample_f0_wdata(I) <= sample_f0(0, I);
198 sample_f0_wdata(I) <= sample_f0(0, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
203 END GENERATE all_bit_sample_f0;
203 END GENERATE all_bit_sample_f0;
204
204
205 sample_f0_wen <= NOT(sample_f0_val) &
205 sample_f0_wen <= NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
209 NOT(sample_f0_val);
209 NOT(sample_f0_val);
210
210
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 -- F1 -- @4096 Hz
212 -- F1 -- @4096 Hz
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214 Downsampling_f1 : Downsampling
214 Downsampling_f1 : Downsampling
215 GENERIC MAP (
215 GENERIC MAP (
216 ChanelCount => ChanelCount,
216 ChanelCount => ChanelCount,
217 SampleSize => 18,
217 SampleSize => 18,
218 DivideParam => 6)
218 DivideParam => 6)
219 PORT MAP (
219 PORT MAP (
220 clk => clk,
220 clk => clk,
221 rstn => rstn,
221 rstn => rstn,
222 sample_in_val => sample_f0_val ,
222 sample_in_val => sample_f0_val ,
223 sample_in => sample_f0,
223 sample_in => sample_f0,
224 sample_out_val => sample_f1_val,
224 sample_out_val => sample_f1_val,
225 sample_out => sample_f1);
225 sample_out => sample_f1);
226
226
227 sample_f1_wen <= NOT(sample_f1_val) &
227 sample_f1_wen <= NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
231 NOT(sample_f1_val);
231 NOT(sample_f1_val);
232
232
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
234 sample_f1_wdata(I) <= sample_f1(0, I);
234 sample_f1_wdata(I) <= sample_f1(0, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
239 END GENERATE all_bit_sample_f1;
239 END GENERATE all_bit_sample_f1;
240
240
241 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
242 -- F2 -- @16 Hz
242 -- F2 -- @16 Hz
243 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
244 Downsampling_f2 : Downsampling
244 Downsampling_f2 : Downsampling
245 GENERIC MAP (
245 GENERIC MAP (
246 ChanelCount => ChanelCount,
246 ChanelCount => ChanelCount,
247 SampleSize => 18,
247 SampleSize => 18,
248 DivideParam => 96)
248 DivideParam => 96)
249 PORT MAP (
249 PORT MAP (
250 clk => clk,
250 clk => clk,
251 rstn => rstn,
251 rstn => rstn,
252 sample_in_val => sample_f1_val ,
252 sample_in_val => sample_f1_val ,
253 sample_in => sample_f1,
253 sample_in => sample_f1,
254 sample_out_val => sample_f2_val,
254 sample_out_val => sample_f2_val,
255 sample_out => sample_f2);
255 sample_out => sample_f2);
256
256
257 sample_f2_wen <= NOT(sample_f2_val) &
257 sample_f2_wen <= NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
261 NOT(sample_f2_val);
261 NOT(sample_f2_val);
262
262
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
264 sample_f2_wdata(I) <= sample_f2(0, I);
264 sample_f2_wdata(I) <= sample_f2(0, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
269 END GENERATE all_bit_sample_f2;
269 END GENERATE all_bit_sample_f2;
270
270
271 -----------------------------------------------------------------------------
271 -----------------------------------------------------------------------------
272 -- F3 -- @256 Hz
272 -- F3 -- @256 Hz
273 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
274 Downsampling_f3 : Downsampling
274 Downsampling_f3 : Downsampling
275 GENERIC MAP (
275 GENERIC MAP (
276 ChanelCount => ChanelCount,
276 ChanelCount => ChanelCount,
277 SampleSize => 18,
277 SampleSize => 18,
278 DivideParam => 256)
278 DivideParam => 256)
279 PORT MAP (
279 PORT MAP (
280 clk => clk,
280 clk => clk,
281 rstn => rstn,
281 rstn => rstn,
282 sample_in_val => sample_f0_val ,
282 sample_in_val => sample_f0_val ,
283 sample_in => sample_f0,
283 sample_in => sample_f0,
284 sample_out_val => sample_f3_val,
284 sample_out_val => sample_f3_val,
285 sample_out => sample_f3);
285 sample_out => sample_f3);
286
286
287 sample_f3_wen <= (NOT sample_f3_val) &
287 sample_f3_wen <= (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
291 (NOT sample_f3_val);
291 (NOT sample_f3_val);
292
292
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
294 sample_f3_wdata(I) <= sample_f3(0, I);
294 sample_f3_wdata(I) <= sample_f3(0, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
299 END GENERATE all_bit_sample_f3;
299 END GENERATE all_bit_sample_f3;
300
300
301
301
302
302
303 END tb;
303 END tb;
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@@ -1,212 +1,408
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_top_apbreg IS
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_burst_available_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
41 delta_snapshot_size : INTEGER := 16;
42 delta_f2_f0_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
44
39 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
40 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
41 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
42 pirq : INTEGER := 0);
48 pirq : INTEGER := 0);
43 PORT (
49 PORT (
44 -- AMBA AHB system signals
50 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
51 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
47
53
48 -- AMBA APB Slave Interface
54 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
55 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
56 apbo : OUT apb_slv_out_type;
51
57
58 ---------------------------------------------------------------------------
59 -- Spectral Matrix Reg
52 -- IN
60 -- IN
53 ready_matrix_f0_0 : IN STD_LOGIC;
61 ready_matrix_f0_0 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
62 ready_matrix_f0_1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
63 ready_matrix_f1 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
64 ready_matrix_f2 : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
65 error_anticipating_empty_fifo : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
66 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60
68
61 -- OUT
69 -- OUT
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
70 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
71 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
74 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
75 status_error_bad_component_error : OUT STD_LOGIC;
68
76
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
85 -- WaveForm picker Reg
86 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90
91 -- OUT
92 data_shaping_BW : OUT STD_LOGIC;
93 data_shaping_SP0 : OUT STD_LOGIC;
94 data_shaping_SP1 : OUT STD_LOGIC;
95 data_shaping_R0 : OUT STD_LOGIC;
96 data_shaping_R1 : OUT STD_LOGIC;
97
98 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
99 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
100 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
101 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
102 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
103
104 enable_f0 : OUT STD_LOGIC;
105 enable_f1 : OUT STD_LOGIC;
106 enable_f2 : OUT STD_LOGIC;
107 enable_f3 : OUT STD_LOGIC;
108
109 burst_f0 : OUT STD_LOGIC;
110 burst_f1 : OUT STD_LOGIC;
111 burst_f2 : OUT STD_LOGIC;
112
113 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
117
118 ---------------------------------------------------------------------------
75 );
119 );
76
120
77 END lpp_top_apbreg;
121 END lpp_top_apbreg;
78
122
79 ARCHITECTURE beh OF lpp_top_apbreg IS
123 ARCHITECTURE beh OF lpp_top_apbreg IS
80
124
81 CONSTANT REVISION : INTEGER := 1;
125 CONSTANT REVISION : INTEGER := 1;
82
126
83 CONSTANT pconfig : apb_config_type := (
127 CONSTANT pconfig : apb_config_type := (
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 1 => apb_iobar(paddr, pmask));
129 1 => apb_iobar(paddr, pmask));
86
130
87 TYPE lpp_dma_regs IS RECORD
131 TYPE lpp_SpectralMatrix_regs IS RECORD
88 config_active_interruption_onNewMatrix : STD_LOGIC;
132 config_active_interruption_onNewMatrix : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
133 config_active_interruption_onError : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
134 status_ready_matrix_f0_0 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
135 status_ready_matrix_f0_1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
136 status_ready_matrix_f1 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
137 status_ready_matrix_f2 : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
138 status_error_anticipating_empty_fifo : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
139 status_error_bad_component_error : STD_LOGIC;
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 END RECORD;
144 END RECORD;
145 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
101
146
102 SIGNAL reg : lpp_dma_regs;
147 TYPE lpp_WaveformPicker_regs IS RECORD
148 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 data_shaping_BW : STD_LOGIC;
152 data_shaping_SP0 : STD_LOGIC;
153 data_shaping_SP1 : STD_LOGIC;
154 data_shaping_R0 : STD_LOGIC;
155 data_shaping_R1 : STD_LOGIC;
156 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
157 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
158 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
159 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
160 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
161 enable_f0 : STD_LOGIC;
162 enable_f1 : STD_LOGIC;
163 enable_f2 : STD_LOGIC;
164 enable_f3 : STD_LOGIC;
165 burst_f0 : STD_LOGIC;
166 burst_f1 : STD_LOGIC;
167 burst_f2 : STD_LOGIC;
168 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 END RECORD;
173 SIGNAL reg_wp : lpp_WaveformPicker_regs;
103
174
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105
176
106 BEGIN -- beh
177 BEGIN -- beh
107
178
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
179 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
180 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
181 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
182 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
183 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
184 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
185
186 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
187 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
188 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
189 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
190 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
191 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
192
114
193
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
194
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
195
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
196 data_shaping_BW <= reg_wp.data_shaping_BW;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
197 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
198 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
199 data_shaping_R0 <= reg_wp.data_shaping_R0;
200 data_shaping_R1 <= reg_wp.data_shaping_R1;
201
202 delta_snapshot <= reg_wp.delta_snapshot;
203 delta_f2_f1 <= reg_wp.delta_f2_f1;
204 delta_f2_f0 <= reg_wp.delta_f2_f0;
205 nb_burst_available <= reg_wp.nb_burst_available;
206 nb_snapshot_param <= reg_wp.nb_snapshot_param;
207
208 enable_f0 <= reg_wp.enable_f0;
209 enable_f1 <= reg_wp.enable_f1;
210 enable_f2 <= reg_wp.enable_f2;
211 enable_f3 <= reg_wp.enable_f3;
212
213 burst_f0 <= reg_wp.burst_f0;
214 burst_f1 <= reg_wp.burst_f1;
215 burst_f2 <= reg_wp.burst_f2;
216
217 addr_data_f0 <= reg_wp.addr_data_f0;
218 addr_data_f1 <= reg_wp.addr_data_f1;
219 addr_data_f2 <= reg_wp.addr_data_f2;
220 addr_data_f3 <= reg_wp.addr_data_f3;
121
221
122 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
222 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
223 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 BEGIN -- PROCESS lpp_dma_top
224 BEGIN -- PROCESS lpp_dma_top
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
225 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 reg.config_active_interruption_onNewMatrix <= '0';
226 reg_sp.config_active_interruption_onNewMatrix <= '0';
127 reg.config_active_interruption_onError <= '0';
227 reg_sp.config_active_interruption_onError <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
228 reg_sp.status_ready_matrix_f0_0 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
229 reg_sp.status_ready_matrix_f0_1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
230 reg_sp.status_ready_matrix_f1 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
231 reg_sp.status_ready_matrix_f2 <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
232 reg_sp.status_error_anticipating_empty_fifo <= '0';
133 reg.status_error_bad_component_error <= '0';
233 reg_sp.status_error_bad_component_error <= '0';
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
234 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
235 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
236 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
237 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
238 prdata <= (OTHERS => '0');
139
239
140 apbo.pirq <= (OTHERS => '0');
240 apbo.pirq <= (OTHERS => '0');
241
242 status_full_ack <= (OTHERS => '0');
243
244 reg_wp.data_shaping_BW <= '0';
245 reg_wp.data_shaping_SP0 <= '0';
246 reg_wp.data_shaping_SP1 <= '0';
247 reg_wp.data_shaping_R0 <= '0';
248 reg_wp.data_shaping_R1 <= '0';
249 reg_wp.enable_f0 <= '0';
250 reg_wp.enable_f1 <= '0';
251 reg_wp.enable_f2 <= '0';
252 reg_wp.enable_f3 <= '0';
253 reg_wp.burst_f0 <= '0';
254 reg_wp.burst_f1 <= '0';
255 reg_wp.burst_f2 <= '0';
256 reg_wp.addr_data_f0 <= (OTHERS => '0');
257 reg_wp.addr_data_f1 <= (OTHERS => '0');
258 reg_wp.addr_data_f2 <= (OTHERS => '0');
259 reg_wp.addr_data_f3 <= (OTHERS => '0');
260 reg_wp.status_full <= (OTHERS => '0');
261 reg_wp.status_full_err <= (OTHERS => '0');
262 reg_wp.status_new_err <= (OTHERS => '0');
263 reg_wp.delta_snapshot <= (OTHERS => '0');
264 reg_wp.delta_f2_f1 <= (OTHERS => '0');
265 reg_wp.delta_f2_f0 <= (OTHERS => '0');
266 reg_wp.nb_burst_available <= (OTHERS => '0');
267 reg_wp.nb_snapshot_param <= (OTHERS => '0');
141
268
142 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
269 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
270 status_full_ack <= (OTHERS => '0');
143
271
144 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
272 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
145 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
273 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
146 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
274 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
147 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
275 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
148
276
149 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
150 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
279
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
151
283
152 paddr := "000000";
284 paddr := "000000";
153 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
154 prdata <= (OTHERS => '0');
286 prdata <= (OTHERS => '0');
155 IF apbi.psel(pindex) = '1' THEN
287 IF apbi.psel(pindex) = '1' THEN
156 -- APB DMA READ --
288 -- APB DMA READ --
157 CASE paddr(7 DOWNTO 2) IS
289 CASE paddr(7 DOWNTO 2) IS
158 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
290 --
159 prdata(1) <= reg.config_active_interruption_onError;
291 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
160 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
292 prdata(1) <= reg_sp.config_active_interruption_onError;
161 prdata(1) <= reg.status_ready_matrix_f0_1;
293 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
162 prdata(2) <= reg.status_ready_matrix_f1;
294 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
163 prdata(3) <= reg.status_ready_matrix_f2;
295 prdata(2) <= reg_sp.status_ready_matrix_f1;
164 prdata(4) <= reg.status_error_anticipating_empty_fifo;
296 prdata(3) <= reg_sp.status_ready_matrix_f2;
165 prdata(5) <= reg.status_error_bad_component_error;
297 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
166 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
298 prdata(5) <= reg_sp.status_error_bad_component_error;
167 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
299 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
168 WHEN "000100" => prdata <= reg.addr_matrix_f1;
300 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
169 WHEN "000101" => prdata <= reg.addr_matrix_f2;
301 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
170 WHEN "000110" => prdata <= debug_reg;
302 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
303 WHEN "000110" => prdata <= debug_reg;
304 --
305 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
306 prdata(1) <= reg_wp.data_shaping_SP0;
307 prdata(2) <= reg_wp.data_shaping_SP1;
308 prdata(3) <= reg_wp.data_shaping_R0;
309 prdata(4) <= reg_wp.data_shaping_R1;
310 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
311 prdata(1) <= reg_wp.enable_f1;
312 prdata(2) <= reg_wp.enable_f2;
313 prdata(3) <= reg_wp.enable_f3;
314 prdata(4) <= reg_wp.burst_f0;
315 prdata(5) <= reg_wp.burst_f1;
316 prdata(6) <= reg_wp.burst_f2;
317 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
318 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
319 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
320 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
321 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
322 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
323 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
324 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
325 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
326 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
327 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
328 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
329 --
171 WHEN OTHERS => NULL;
330 WHEN OTHERS => NULL;
172 END CASE;
331 END CASE;
173 IF (apbi.pwrite AND apbi.penable) = '1' THEN
332 IF (apbi.pwrite AND apbi.penable) = '1' THEN
174 -- APB DMA WRITE --
333 -- APB DMA WRITE --
175 CASE paddr(7 DOWNTO 2) IS
334 CASE paddr(7 DOWNTO 2) IS
176 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
335 --
177 reg.config_active_interruption_onError <= apbi.pwdata(1);
336 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
178 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
337 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
179 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
338 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
180 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
339 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
181 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
340 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
182 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
341 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
183 reg.status_error_bad_component_error <= apbi.pwdata(5);
342 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
184 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
343 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
185 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
344 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
186 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
345 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
187 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
346 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
347 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
348 --
349 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
350 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
351 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
352 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
353 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
354 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
355 reg_wp.enable_f1 <= apbi.pwdata(1);
356 reg_wp.enable_f2 <= apbi.pwdata(2);
357 reg_wp.enable_f3 <= apbi.pwdata(3);
358 reg_wp.burst_f0 <= apbi.pwdata(4);
359 reg_wp.burst_f1 <= apbi.pwdata(5);
360 reg_wp.burst_f2 <= apbi.pwdata(6);
361 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
362 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
363 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
364 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
365 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
366 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
367 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
368 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
369 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
370 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
371 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
372 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
373 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
374 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
375 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
376 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
377 --
188 WHEN OTHERS => NULL;
378 WHEN OTHERS => NULL;
189 END CASE;
379 END CASE;
190 END IF;
380 END IF;
191 END IF;
381 END IF;
192
382
193 apbo.pirq(pirq) <= ( reg.config_active_interruption_onNewMatrix AND ( ready_matrix_f0_0 OR
383 apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
194 ready_matrix_f0_1 OR
384 ready_matrix_f0_1 OR
195 ready_matrix_f1 OR
385 ready_matrix_f1 OR
196 ready_matrix_f2)
386 ready_matrix_f2)
197 )
387 )
198 OR
388 OR
199 ( reg.config_active_interruption_onError AND ( error_anticipating_empty_fifo OR
389 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
200 error_bad_component_error)
390 error_bad_component_error)
201 );
391 )
392 OR
393 (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
394 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
395 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
396 status_full(3) OR status_full_err(3) OR status_new_err(3)
397 );
202
398
203
399
204 END IF;
400 END IF;
205 END PROCESS lpp_top_apbreg;
401 END PROCESS lpp_top_apbreg;
206
402
207 apbo.pindex <= pindex;
403 apbo.pindex <= pindex;
208 apbo.pconfig <= pconfig;
404 apbo.pconfig <= pconfig;
209 apbo.prdata <= prdata;
405 apbo.prdata <= prdata;
210
406
211
407
212 END beh;
408 END beh;
Show file before | Show file after | Hide comments
@@ -1,80 +1,198
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_top_lfr_pkg IS
15 PACKAGE lpp_top_lfr_pkg IS
16
16
17 COMPONENT lpp_top_acq
17 COMPONENT lpp_top_acq
18 GENERIC(
18 GENERIC(
19 tech : INTEGER := 0
19 tech : INTEGER := 0
20 );
20 );
21 PORT (
21 PORT (
22 -- ADS7886
22 -- ADS7886
23 cnv_run : IN STD_LOGIC;
23 cnv_run : IN STD_LOGIC;
24 cnv : OUT STD_LOGIC;
24 cnv : OUT STD_LOGIC;
25 sck : OUT STD_LOGIC;
25 sck : OUT STD_LOGIC;
26 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
26 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
27 --
27 --
28 cnv_clk : IN STD_LOGIC; -- 49 MHz
28 cnv_clk : IN STD_LOGIC; -- 49 MHz
29 cnv_rstn : IN STD_LOGIC;
29 cnv_rstn : IN STD_LOGIC;
30 --
30 --
31 clk : IN STD_LOGIC; -- 25 MHz
31 clk : IN STD_LOGIC; -- 25 MHz
32 rstn : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 --
33 --
34 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 --
36 --
37 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 --
39 --
40 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
41 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 --
42 --
43 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
44 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 );
45 );
46 END COMPONENT;
46 END COMPONENT;
47
47
48 COMPONENT lpp_top_apbreg
48 COMPONENT lpp_top_apbreg
49 GENERIC (
49 GENERIC (
50 pindex : INTEGER;
50 nb_burst_available_size : INTEGER;
51 paddr : INTEGER;
51 nb_snapshot_param_size : INTEGER;
52 pmask : INTEGER;
52 delta_snapshot_size : INTEGER;
53 pirq : INTEGER);
53 delta_f2_f0_size : INTEGER;
54 delta_f2_f1_size : INTEGER;
55 pindex : INTEGER;
56 paddr : INTEGER;
57 pmask : INTEGER;
58 pirq : INTEGER);
54 PORT (
59 PORT (
55 HCLK : IN STD_ULOGIC;
60 HCLK : IN STD_ULOGIC;
56 HRESETn : IN STD_ULOGIC;
61 HRESETn : IN STD_ULOGIC;
57 apbi : IN apb_slv_in_type;
62 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
63 apbo : OUT apb_slv_out_type;
59 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_0 : IN STD_LOGIC;
60 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f0_1 : IN STD_LOGIC;
61 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
62 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
63 error_anticipating_empty_fifo : IN STD_LOGIC;
68 error_anticipating_empty_fifo : IN STD_LOGIC;
64 error_bad_component_error : IN STD_LOGIC;
69 error_bad_component_error : IN STD_LOGIC;
65 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 status_ready_matrix_f0_0 : OUT STD_LOGIC;
71 status_ready_matrix_f0_0 : OUT STD_LOGIC;
67 status_ready_matrix_f0_1 : OUT STD_LOGIC;
72 status_ready_matrix_f0_1 : OUT STD_LOGIC;
68 status_ready_matrix_f1 : OUT STD_LOGIC;
73 status_ready_matrix_f1 : OUT STD_LOGIC;
69 status_ready_matrix_f2 : OUT STD_LOGIC;
74 status_ready_matrix_f2 : OUT STD_LOGIC;
70 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
75 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
71 status_error_bad_component_error : OUT STD_LOGIC;
76 status_error_bad_component_error : OUT STD_LOGIC;
72 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
73 config_active_interruption_onError : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
74 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
84 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 data_shaping_BW : OUT STD_LOGIC;
88 data_shaping_SP0 : OUT STD_LOGIC;
89 data_shaping_SP1 : OUT STD_LOGIC;
90 data_shaping_R0 : OUT STD_LOGIC;
91 data_shaping_R1 : OUT STD_LOGIC;
92 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
93 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
94 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
95 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
96 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
97 enable_f0 : OUT STD_LOGIC;
98 enable_f1 : OUT STD_LOGIC;
99 enable_f2 : OUT STD_LOGIC;
100 enable_f3 : OUT STD_LOGIC;
101 burst_f0 : OUT STD_LOGIC;
102 burst_f1 : OUT STD_LOGIC;
103 burst_f2 : OUT STD_LOGIC;
104 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
108 END COMPONENT;
109
110 COMPONENT lpp_top_lfr_wf_picker
111 GENERIC (
112 hindex : INTEGER;
113 pindex : INTEGER;
114 paddr : INTEGER;
115 pmask : INTEGER;
116 pirq : INTEGER;
117 tech : INTEGER;
118 nb_burst_available_size : INTEGER;
119 nb_snapshot_param_size : INTEGER;
120 delta_snapshot_size : INTEGER;
121 delta_f2_f0_size : INTEGER;
122 delta_f2_f1_size : INTEGER);
123 PORT (
124 cnv_run : IN STD_LOGIC;
125 cnv : OUT STD_LOGIC;
126 sck : OUT STD_LOGIC;
127 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
128 cnv_clk : IN STD_LOGIC;
129 cnv_rstn : IN STD_LOGIC;
130 HCLK : IN STD_ULOGIC;
131 HRESETn : IN STD_ULOGIC;
132 apbi : IN apb_slv_in_type;
133 apbo : OUT apb_slv_out_type;
134 AHB_Master_In : IN AHB_Mst_In_Type;
135 AHB_Master_Out : OUT AHB_Mst_Out_Type;
136 coarse_time_0 : IN STD_LOGIC;
137 data_shaping_BW : OUT STD_LOGIC);
78 END COMPONENT;
138 END COMPONENT;
79
139
80 END lpp_top_lfr_pkg; No newline at end of file
140
141 COMPONENT lpp_top_lfr_wf_picker_ip
142 GENERIC (
143 hindex : INTEGER;
144 nb_burst_available_size : INTEGER;
145 nb_snapshot_param_size : INTEGER;
146 delta_snapshot_size : INTEGER;
147 delta_f2_f0_size : INTEGER;
148 delta_f2_f1_size : INTEGER;
149 tech : INTEGER);
150 PORT (
151 cnv_run : IN STD_LOGIC;
152 cnv : OUT STD_LOGIC;
153 sck : OUT STD_LOGIC;
154 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
155 cnv_clk : IN STD_LOGIC;
156 cnv_rstn : IN STD_LOGIC;
157 clk : IN STD_LOGIC;
158 rstn : IN STD_LOGIC;
159 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
160 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
161 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
162 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
163 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
164 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
165 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
166 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
167 AHB_Master_In : IN AHB_Mst_In_Type;
168 AHB_Master_Out : OUT AHB_Mst_Out_Type;
169 coarse_time_0 : IN STD_LOGIC;
170 data_shaping_SP0 : IN STD_LOGIC;
171 data_shaping_SP1 : IN STD_LOGIC;
172 data_shaping_R0 : IN STD_LOGIC;
173 data_shaping_R1 : IN STD_LOGIC;
174 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
175 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
176 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
177 enable_f0 : IN STD_LOGIC;
178 enable_f1 : IN STD_LOGIC;
179 enable_f2 : IN STD_LOGIC;
180 enable_f3 : IN STD_LOGIC;
181 burst_f0 : IN STD_LOGIC;
182 burst_f1 : IN STD_LOGIC;
183 burst_f2 : IN STD_LOGIC;
184 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
185 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
186 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
188 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
189 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
190 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
193 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
194 END COMPONENT;
195
196
197
198 END lpp_top_lfr_pkg;
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@@ -1,129 +1,132
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -------------------------------------------------------------------------------
25 -------------------------------------------------------------------------------
26
26
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30
30
31
31
32 ENTITY lpp_waveform_dma_selectaddress IS
32 ENTITY lpp_waveform_dma_selectaddress IS
33 GENERIC (
33 GENERIC (
34 nb_burst_available_size : INTEGER := 11
34 nb_burst_available_size : INTEGER := 11
35 );
35 );
36 PORT (
36 PORT (
37 HCLK : IN STD_ULOGIC;
37 HCLK : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
39
39
40 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
40 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41
42 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
43 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
44
45 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46
41
47 status_full : OUT STD_LOGIC;
42 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
48 status_full_ack : IN STD_LOGIC;
43 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 status_full_err : OUT STD_LOGIC
44
45 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46
47 status_full : OUT STD_LOGIC;
48 status_full_ack : IN STD_LOGIC;
49 status_full_err : OUT STD_LOGIC
50 );
50 );
51 END;
51 END;
52
52
53 ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS
53 ARCHITECTURE Behavioral OF lpp_waveform_dma_selectaddress IS
54 TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED);
54 TYPE state_fsm_select_data IS (IDLE, ADD, FULL, ERR, UPDATED);
55 SIGNAL state : state_fsm_select_data;
55 SIGNAL state : state_fsm_select_data;
56
56
57 SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0);
58 SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
58 SIGNAL nb_send : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
59 SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
59 SIGNAL nb_send_next : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
60
60
61 SIGNAL update_s : STD_LOGIC;
61 SIGNAL update_s : STD_LOGIC;
62 SIGNAL update_r : STD_LOGIC_VECTOR(1 DOWNTO 0);
62 BEGIN
63 BEGIN
63
64
64 update_s <= update(0) OR update(1);
65 update_s <= update(0) OR update(1);
65
66
66 addr_data <= address;
67 addr_data <= address;
67 nb_send_next <= std_logic_vector(unsigned(nb_send) + 1);
68 nb_send_next <= STD_LOGIC_VECTOR(UNSIGNED(nb_send) + 1);
68
69
69 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
70 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
70 BEGIN
71 BEGIN
71 IF HRESETn = '0' THEN
72 IF HRESETn = '0' THEN
72 state <= IDLE;
73 state <= IDLE;
73 address <= (OTHERS => '0');
74 address <= (OTHERS => '0');
74 nb_send <= (OTHERS => '0');
75 nb_send <= (OTHERS => '0');
75 status_full <= '0';
76 status_full <= '0';
76 status_full_err <= '0';
77 status_full_err <= '0';
78 update_r <= "00";
77 ELSIF HCLK'EVENT AND HCLK = '1' THEN
79 ELSIF HCLK'EVENT AND HCLK = '1' THEN
80 update_r <= update;
78 CASE state IS
81 CASE state IS
79 WHEN IDLE =>
82 WHEN IDLE =>
80 IF update_s = '1' THEN
83 IF update_s = '1' THEN
81 state <= ADD;
84 state <= ADD;
82 END IF;
85 END IF;
83
86
84 WHEN ADD =>
87 WHEN ADD =>
85 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
88 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
86 state <= IDLE;
89 state <= IDLE;
87 IF update = "10" THEN
90 IF update_r = "10" THEN
88 address <= std_logic_vector(unsigned(address) + 16);
91 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
89 nb_send <= nb_send_next;
92 nb_send <= nb_send_next;
90 ELSIF update = "01" THEN
93 ELSIF update_r = "01" THEN
91 address <= std_logic_vector(unsigned(address) + 1);
94 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
92 END IF;
95 END IF;
93 ELSE
96 ELSE
94 state <= FULL;
97 state <= FULL;
95 nb_send <= (OTHERS => '0');
98 nb_send <= (OTHERS => '0');
96 status_full <= '1';
99 status_full <= '1';
97 END IF;
100 END IF;
98
101
99 WHEN FULL =>
102 WHEN FULL =>
100 status_full <= '0';
103 status_full <= '0';
101 IF status_full_ack = '1' THEN
104 IF status_full_ack = '1' THEN
102 IF update_s = '1' THEN
105 IF update_s = '1' THEN
103 status_full_err <= '1';
106 status_full_err <= '1';
104 END IF;
107 END IF;
105 state <= UPDATED;
108 state <= UPDATED;
106 ELSE
109 ELSE
107 IF update_s = '1' THEN
110 IF update_s = '1' THEN
108 status_full_err <= '1';
111 status_full_err <= '1';
109 state <= ERR;
112 state <= ERR;
110 END IF;
113 END IF;
111 END IF;
114 END IF;
112
115
113 WHEN ERR =>
116 WHEN ERR =>
114 status_full_err <= '0';
117 status_full_err <= '0';
115 IF status_full_ack = '1' THEN
118 IF status_full_ack = '1' THEN
116 state <= UPDATED;
119 state <= UPDATED;
117 END IF;
120 END IF;
118
121
119 WHEN UPDATED =>
122 WHEN UPDATED =>
120 status_full_err <= '0';
123 status_full_err <= '0';
121 state <= IDLE;
124 state <= IDLE;
122 address <= addr_data_reg;
125 address <= addr_data_reg;
123
126
124 WHEN OTHERS => NULL;
127 WHEN OTHERS => NULL;
125 END CASE;
128 END CASE;
126 END IF;
129 END IF;
127 END PROCESS FSM_SELECT_ADDRESS;
130 END PROCESS FSM_SELECT_ADDRESS;
128
131
129 END Behavioral;
132 END Behavioral;
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