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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity ReUse_CTRLR is
27 port(
28 clk : in std_logic;
29 reset : in std_logic;
30
31 SetReUse : in std_logic_vector(4 downto 0);
32 Statu : in std_logic_vector(3 downto 0);
33
34 ReUse : out std_logic_vector(4 downto 0)
35 );
36 end entity;
37
38
39 architecture ar_ReUse_CTRLR of ReUse_CTRLR is
40
41 signal ResetReUse : std_logic_vector(4 downto 0);
42 signal MatrixParam : integer;
43 signal MatrixParam_Reg : integer;
44
45 begin
46
47
48
49 process (clk,reset)
50 -- variable MatrixParam : integer;
51 begin
52 -- MatrixParam := to_integer(unsigned(Statu));
53
54 if(reset='0')then
55 ResetReUse <= (others => '1');
56 MatrixParam_Reg <= 0;
57
58
59 elsif(clk' event and clk='1')then
60 MatrixParam_Reg <= MatrixParam;
61
62 if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11
63 ResetReUse(0) <= '0';
64 elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12
65 ResetReUse(1) <= '0';
66 elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13
67 ResetReUse(2) <= '0';
68 elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14
69 ResetReUse(3) <= '0';
70 elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15
71 ResetReUse(4) <= '0';
72 end if;
73
74 end if;
75 end process;
76
77 MatrixParam <= to_integer(unsigned(Statu));
78 ReUse <= SetReUse and ResetReUse;
79
80 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27
28
29
25
30 ENTITY Adder IS
26 ENTITY Adder IS
31 GENERIC(
27 GENERIC(
32 Input_SZ_A : INTEGER := 16;
28 Input_SZ_A : INTEGER := 16;
33 Input_SZ_B : INTEGER := 16
29 Input_SZ_B : INTEGER := 16
34
30
35 );
31 );
36 PORT(
32 PORT(
37 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
38 reset : IN STD_LOGIC;
34 reset : IN STD_LOGIC;
39 clr : IN STD_LOGIC;
35 clr : IN STD_LOGIC;
40 load : IN STD_LOGIC;
36 load : IN STD_LOGIC;
41 add : IN STD_LOGIC;
37 add : IN STD_LOGIC;
42 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
38 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
43 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
39 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
44 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
40 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
45 );
41 );
46 END ENTITY;
42 END ENTITY;
47
43
48
44
49
45
50
46
51 ARCHITECTURE ar_Adder OF Adder IS
47 ARCHITECTURE ar_Adder OF Adder IS
52
48
53 SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
49 SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
54 SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
50 SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
55
51
56 BEGIN
52 BEGIN
57
53
58 RES <= REG;
54 RES <= REG;
59 RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
55 RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
60
56
61 PROCESS(clk, reset)
57 PROCESS(clk, reset)
62 BEGIN
58 BEGIN
63 IF reset = '0' THEN
59 IF reset = '0' THEN
64 REG <= (OTHERS => '0');
60 REG <= (OTHERS => '0');
65 ELSIF clk'EVENT AND clk = '1' then
61 ELSIF clk'EVENT AND clk = '1' then
66 IF clr = '1' THEN
62 IF clr = '1' THEN
67 REG <= (OTHERS => '0');
63 REG <= (OTHERS => '0');
68 ELSIF add = '1' THEN
64 ELSIF add = '1' THEN
69 REG <= RESADD;
65 REG <= RESADD;
70 ELSIF load = '1' THEN
66 ELSIF load = '1' THEN
71 REG <= OP2;
67 REG <= OP2;
72 END IF;
68 END IF;
73 END IF;
69 END IF;
74 END PROCESS;
70 END PROCESS;
75 END ar_Adder;
71 END ar_Adder;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
25
29 --IDLE =00 MAC =01 MULT =10 ADD =11
26 --IDLE =00 MAC =01 MULT =10 ADD =11
30
27
31
28
32 entity MAC_CONTROLER is
29 entity MAC_CONTROLER is
33 port(
30 port(
34 ctrl : in std_logic_vector(1 downto 0);
31 ctrl : in std_logic_vector(1 downto 0);
35 MULT : out std_logic;
32 MULT : out std_logic;
36 ADD : out std_logic;
33 ADD : out std_logic;
37 LOAD_ADDER : out std_logic;
34 LOAD_ADDER : out std_logic;
38 MACMUX_sel : out std_logic;
35 MACMUX_sel : out std_logic;
39 MACMUX2_sel : out std_logic
36 MACMUX2_sel : out std_logic
40
37
41 );
38 );
42 end MAC_CONTROLER;
39 end MAC_CONTROLER;
43
40
44
41
45
42
46
43
47
44
48 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
45 architecture ar_MAC_CONTROLER of MAC_CONTROLER is
49
46
50 begin
47 begin
51
48
52
49
53
50
54 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
55 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
56 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
53 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
57 -- to permit to compute a
54 -- to permit to compute a
58 -- MULT follow by a MAC
55 -- MULT follow by a MAC
59 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
56 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
60 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
57 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
61 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
58 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
62
59
63
60
64 end ar_MAC_CONTROLER;
61 end ar_MAC_CONTROLER;
65
62
66
63
67
64
68
65
69
66
70
67
71
68
72
69
73
70
74
71
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
29
25
30 entity MAC_MUX is
26 entity MAC_MUX is
31 generic(
27 generic(
32 Input_SZ_A : integer := 16;
28 Input_SZ_A : integer := 16;
33 Input_SZ_B : integer := 16
29 Input_SZ_B : integer := 16
34
30
35 );
31 );
36 port(
32 port(
37 sel : in std_logic;
33 sel : in std_logic;
38 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
34 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
39 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
35 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
40 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
36 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
41 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
37 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
42 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
38 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
43 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
39 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
44 );
40 );
45 end entity;
41 end entity;
46
42
47
43
48
44
49
45
50 architecture ar_MAC_MUX of MAC_MUX is
46 architecture ar_MAC_MUX of MAC_MUX is
51
47
52 begin
48 begin
53
49
54 OUTA <= INA1 when sel = '0' else INA2;
50 OUTA <= INA1 when sel = '0' else INA2;
55 OUTB <= INB1 when sel = '0' else INB2;
51 OUTB <= INB1 when sel = '0' else INB2;
56
52
57 end ar_MAC_MUX;
53 end ar_MAC_MUX;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
25
29
26
30 entity MAC_MUX2 is
27 entity MAC_MUX2 is
31 generic(Input_SZ : integer := 16);
28 generic(Input_SZ : integer := 16);
32 port(
29 port(
33 sel : in std_logic;
30 sel : in std_logic;
34 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
31 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
35 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
32 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
36 RES : out std_logic_vector(Input_SZ-1 downto 0)
33 RES : out std_logic_vector(Input_SZ-1 downto 0)
37 );
34 );
38 end entity;
35 end entity;
39
36
40
37
41
38
42
39
43 architecture ar_MAC_MUX2 of MAC_MUX2 is
40 architecture ar_MAC_MUX2 of MAC_MUX2 is
44
41
45 begin
42 begin
46
43
47 RES <= RES1 when sel = '0' else RES2;
44 RES <= RES1 when sel = '0' else RES2;
48
45
49 end ar_MAC_MUX2;
46 end ar_MAC_MUX2;
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@@ -1,62 +1,58
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
29
25
30 entity MAC_REG is
26 entity MAC_REG is
31 generic(size : integer := 16);
27 generic(size : integer := 16);
32 port(
28 port(
33 reset : in std_logic;
29 reset : in std_logic;
34 clk : in std_logic;
30 clk : in std_logic;
35 D : in std_logic_vector(size-1 downto 0);
31 D : in std_logic_vector(size-1 downto 0);
36 Q : out std_logic_vector(size-1 downto 0)
32 Q : out std_logic_vector(size-1 downto 0)
37 );
33 );
38 end entity;
34 end entity;
39
35
40
36
41
37
42 architecture ar_MAC_REG of MAC_REG is
38 architecture ar_MAC_REG of MAC_REG is
43 begin
39 begin
44 process(clk,reset)
40 process(clk,reset)
45 begin
41 begin
46 if reset = '0' then
42 if reset = '0' then
47 Q <= (others => '0');
43 Q <= (others => '0');
48 elsif clk'event and clk ='1' then
44 elsif clk'event and clk ='1' then
49 Q <= D;
45 Q <= D;
50 end if;
46 end if;
51 end process;
47 end process;
52 end ar_MAC_REG;
48 end ar_MAC_REG;
53
49
54
50
55
51
56
52
57
53
58
54
59
55
60
56
61
57
62
58
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@@ -1,80 +1,75
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 library lpp;
27 use lpp.general_purpose.all;
28
29
30
31 entity Multiplier is
26 entity Multiplier is
32 generic(
27 generic(
33 Input_SZ_A : integer := 16;
28 Input_SZ_A : integer := 16;
34 Input_SZ_B : integer := 16
29 Input_SZ_B : integer := 16
35
30
36 );
31 );
37 port(
32 port(
38 clk : in std_logic;
33 clk : in std_logic;
39 reset : in std_logic;
34 reset : in std_logic;
40 mult : in std_logic;
35 mult : in std_logic;
41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
36 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
37 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
43 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
38 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
44 );
39 );
45 end Multiplier;
40 end Multiplier;
46
41
47
42
48
43
49
44
50
45
51 architecture ar_Multiplier of Multiplier is
46 architecture ar_Multiplier of Multiplier is
52
47
53 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
48 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
54 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
55
50
56
51
57 begin
52 begin
58
53
59 RES <= REG;
54 RES <= REG;
60 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
55 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2));
61 process(clk,reset)
56 process(clk,reset)
62 begin
57 begin
63 if reset = '0' then
58 if reset = '0' then
64 REG <= (others => '0');
59 REG <= (others => '0');
65 elsif clk'event and clk ='1' then
60 elsif clk'event and clk ='1' then
66 if mult = '1' then
61 if mult = '1' then
67 REG <= RESMULT;
62 REG <= RESMULT;
68 end if;
63 end if;
69 end if;
64 end if;
70 end process;
65 end process;
71
66
72 end ar_Multiplier;
67 end ar_Multiplier;
73
68
74
69
75
70
76
71
77
72
78
73
79
74
80
75
Show file before | Show file after | Hide comments
@@ -1,217 +1,216
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
25 use lpp.general_purpose.all;
27
26
28 --! Driver de l'ALU
27 --! Driver de l'ALU
29
28
30 entity ALU_Driver is
29 entity ALU_Driver is
31 generic(
30 generic(
32 Input_SZ_1 : integer := 16;
31 Input_SZ_1 : integer := 16;
33 Input_SZ_2 : integer := 16);
32 Input_SZ_2 : integer := 16);
34 port(
33 port(
35 clk : in std_logic; --! Horloge du composant
34 clk : in std_logic; --! Horloge du composant
36 reset : in std_logic; --! Reset general du composant
35 reset : in std_logic; --! Reset general du composant
37 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
38 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
39 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Take : in std_logic; --! Flag, op�rande r�cup�r�
40 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Received : in std_logic; --! Flag, R�sultat bien ressu
41 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
42 Valid : out std_logic; --! Flag, R�sultat disponible
41 Valid : out std_logic; --! Flag, R�sultat disponible
43 Read : out std_logic; --! Flag, op�rande disponible
42 Read : out std_logic; --! Flag, op�rande disponible
44 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
43 CTRL : out std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
45 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
44 COMP : out std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes
46 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
45 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
47 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
46 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
48 );
47 );
49 end ALU_Driver;
48 end ALU_Driver;
50
49
51 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
50 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
52
51
53 architecture ar_ALU_Driver of ALU_Driver is
52 architecture ar_ALU_Driver of ALU_Driver is
54
53
55 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
54 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
55 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
57 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
56 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
58 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
57 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
59
58
60 signal go_st : std_logic;
59 signal go_st : std_logic;
61 signal Take_reg : std_logic;
60 signal Take_reg : std_logic;
62 signal Received_reg : std_logic;
61 signal Received_reg : std_logic;
63
62
64 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
63 type etat is (eX,e0,e1,e2,e3,e4,e5,eY,eZ,eW);
65 signal ect : etat;
64 signal ect : etat;
66 signal st : etat;
65 signal st : etat;
67
66
68 begin
67 begin
69 process(clk,reset)
68 process(clk,reset)
70 begin
69 begin
71
70
72 if(reset='0')then
71 if(reset='0')then
73 ect <= eX;
72 ect <= eX;
74 st <= e0;
73 st <= e0;
75 go_st <= '0';
74 go_st <= '0';
76 CTRL <= ctrl_CLRMAC;
75 CTRL <= ctrl_CLRMAC;
77 COMP <= "00"; -- pas de complement
76 COMP <= "00"; -- pas de complement
78 Read <= '0';
77 Read <= '0';
79 Valid <= '0';
78 Valid <= '0';
80 Take_reg <= '0';
79 Take_reg <= '0';
81 Received_reg <= '0';
80 Received_reg <= '0';
82
81
83 elsif(clk'event and clk='1')then
82 elsif(clk'event and clk='1')then
84 Take_reg <= Take;
83 Take_reg <= Take;
85 Received_reg <= Received;
84 Received_reg <= Received;
86
85
87 case ect is
86 case ect is
88 when eX =>
87 when eX =>
89 go_st <= '0';
88 go_st <= '0';
90 Read <= '1';
89 Read <= '1';
91 CTRL <= ctrl_CLRMAC;
90 CTRL <= ctrl_CLRMAC;
92 ect <= e0;
91 ect <= e0;
93
92
94 when e0 =>
93 when e0 =>
95 OP1re <= IN1;
94 OP1re <= IN1;
96 if(Conjugate='1')then --
95 if(Conjugate='1')then --
97 OP2re <= IN1; --
96 OP2re <= IN1; --
98 else --
97 else --
99 OP2re <= IN2; -- modif 23/06/11
98 OP2re <= IN2; -- modif 23/06/11
100 end if; --
99 end if; --
101 if(Take_reg='0' and Take='1')then
100 if(Take_reg='0' and Take='1')then
102 read <= '0';
101 read <= '0';
103 ect <= e1;
102 ect <= e1;
104 end if;
103 end if;
105
104
106 when e1 =>
105 when e1 =>
107 OP1 <= OP1re;
106 OP1 <= OP1re;
108 OP2 <= OP2re;
107 OP2 <= OP2re;
109 CTRL <= ctrl_MAC;
108 CTRL <= ctrl_MAC;
110 Read <= '1';
109 Read <= '1';
111 ect <= eY;
110 ect <= eY;
112
111
113 when eY =>
112 when eY =>
114 OP1im <= IN1;
113 OP1im <= IN1;
115 if(Conjugate='1')then --
114 if(Conjugate='1')then --
116 OP2im <= IN1; --
115 OP2im <= IN1; --
117 else --
116 else --
118 OP2im <= IN2; -- modif 23/06/11
117 OP2im <= IN2; -- modif 23/06/11
119 end if; --
118 end if; --
120 CTRL <= ctrl_IDLE;
119 CTRL <= ctrl_IDLE;
121 if(Take_reg='1' and Take='0')then
120 if(Take_reg='1' and Take='0')then
122 Read <= '0';
121 Read <= '0';
123 ect <= e2;
122 ect <= e2;
124 end if;
123 end if;
125
124
126 when e2 =>
125 when e2 =>
127 OP1 <= OP1im;
126 OP1 <= OP1im;
128 OP2 <= OP2im;
127 OP2 <= OP2im;
129 CTRL <= ctrl_MAC;
128 CTRL <= ctrl_MAC;
130 ect <= eZ;
129 ect <= eZ;
131
130
132 when eZ =>
131 when eZ =>
133 CTRL <= ctrl_IDLE;
132 CTRL <= ctrl_IDLE;
134 go_st <= '1';
133 go_st <= '1';
135 if(Received_reg='0' and Received='1')then
134 if(Received_reg='0' and Received='1')then
136 if(Conjugate='1')then
135 if(Conjugate='1')then
137 ect <= eX;
136 ect <= eX;
138 else
137 else
139 ect <= e3;
138 ect <= e3;
140 end if;
139 end if;
141 end if;
140 end if;
142
141
143 when e3 =>
142 when e3 =>
144 CTRL <= ctrl_CLRMAC;
143 CTRL <= ctrl_CLRMAC;
145 go_st <= '0';
144 go_st <= '0';
146 ect <= e4;
145 ect <= e4;
147
146
148 when e4 =>
147 when e4 =>
149 OP1 <= OP1im;
148 OP1 <= OP1im;
150 OP2 <= OP2re;
149 OP2 <= OP2re;
151 CTRL <= ctrl_MAC;
150 CTRL <= ctrl_MAC;
152 ect <= e5;
151 ect <= e5;
153
152
154 when e5 =>
153 when e5 =>
155 OP1 <= OP1re;
154 OP1 <= OP1re;
156 OP2 <= OP2im;
155 OP2 <= OP2im;
157 COMP <= "10";
156 COMP <= "10";
158 ect <= eW;
157 ect <= eW;
159
158
160 when eW =>
159 when eW =>
161 CTRL <= ctrl_IDLE;
160 CTRL <= ctrl_IDLE;
162 COMP <= "00";
161 COMP <= "00";
163 go_st <= '1';
162 go_st <= '1';
164 if(Received_reg='1' and Received='0')then
163 if(Received_reg='1' and Received='0')then
165 ect <= eX;
164 ect <= eX;
166 end if;
165 end if;
167 end case;
166 end case;
168 ---------------------------------------------------------------------------------
167 ---------------------------------------------------------------------------------
169 case st is
168 case st is
170 when e0 =>
169 when e0 =>
171 if(go_st='1')then
170 if(go_st='1')then
172 st <= e1;
171 st <= e1;
173 end if;
172 end if;
174
173
175 when e1 =>
174 when e1 =>
176 Valid <= '1';
175 Valid <= '1';
177 st <= e2;
176 st <= e2;
178
177
179 when e2 =>
178 when e2 =>
180 if(Received_reg='0' and Received='1')then
179 if(Received_reg='0' and Received='1')then
181 Valid <= '0';
180 Valid <= '0';
182 if(Conjugate='1')then
181 if(Conjugate='1')then
183 st <= eY;
182 st <= eY;
184 else
183 else
185 st <= eX;
184 st <= eX;
186 end if;
185 end if;
187 end if;
186 end if;
188
187
189 when eX =>
188 when eX =>
190 st <= e3;
189 st <= e3;
191
190
192 when e3 =>
191 when e3 =>
193 if(go_st='1')then
192 if(go_st='1')then
194 st <= e4;
193 st <= e4;
195 end if;
194 end if;
196
195
197 when e4 =>
196 when e4 =>
198 Valid <= '1';
197 Valid <= '1';
199 st <= e5;
198 st <= e5;
200
199
201 when e5 =>
200 when e5 =>
202 if(Received_reg='1' and Received='0')then
201 if(Received_reg='1' and Received='0')then
203 Valid <= '0';
202 Valid <= '0';
204 st <= eY;
203 st <= eY;
205 end if;
204 end if;
206
205
207 when eY =>
206 when eY =>
208 st <= e0;
207 st <= e0;
209
208
210 when others =>
209 when others =>
211 null;
210 null;
212 end case;
211 end case;
213
212
214 end if;
213 end if;
215 end process;
214 end process;
216
215
217 end ar_ALU_Driver; No newline at end of file
216 end ar_ALU_Driver;
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@@ -1,76 +1,84
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 --library lpp;
26 use lpp.lpp_matrix.all;
26 --use lpp.lpp_matrix.all;
27
27
28 entity MatriceSpectrale is
28 entity MatriceSpectrale is
29 generic(
29 generic(
30 Input_SZ : integer := 16;
30 Input_SZ : integer := 16;
31 Result_SZ : integer := 32);
31 Result_SZ : integer := 32);
32 port(
32 port(
33 clkm : in std_logic;
33 clkm : in std_logic;
34 rstn : in std_logic;
34 rstn : in std_logic;
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
37 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 FifoOUT_Full : in std_logic_vector(1 downto 0);
38 Data_IN : in std_logic_vector(79 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 ACQ : in std_logic;
40 ACQ : in std_logic;
40 FlagError : out std_logic;
41 FlagError : out std_logic;
41 Pong : out std_logic;
42 Pong : out std_logic;
43 Statu : out std_logic_vector(3 downto 0);
42 Write : out std_logic_vector(1 downto 0);
44 Write : out std_logic_vector(1 downto 0);
43 Read : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0);
44 Data_OUT : out std_logic_vector(63 downto 0)
46 ReUse : out std_logic_vector(4 downto 0);
47 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
45 );
48 );
46 end entity;
49 end entity;
47
50
48
51
49 architecture ar_MatriceSpectrale of MatriceSpectrale is
52 architecture ar_MatriceSpectrale of MatriceSpectrale is
50
53
51 signal Matrix_Write : std_logic;
54 signal Matrix_Write : std_logic;
52 signal Matrix_Read : std_logic_vector(1 downto 0);
55 signal Matrix_Read : std_logic_vector(1 downto 0);
53 signal Matrix_Result : std_logic_vector(31 downto 0);
56 signal Matrix_Result : std_logic_vector(31 downto 0);
54
57
55 signal TopSM_Start : std_logic;
58 signal TopSM_Start : std_logic;
56 signal TopSM_Statu : std_logic_vector(3 downto 0);
59 signal TopSM_Statu : std_logic_vector(3 downto 0);
57 signal TopSM_Data1 : std_logic_vector(15 downto 0);
60 signal TopSM_Data1 : std_logic_vector(15 downto 0);
58 signal TopSM_Data2 : std_logic_vector(15 downto 0);
61 signal TopSM_Data2 : std_logic_vector(15 downto 0);
59
62
60 begin
63 begin
61
64
62 TopSM : TopSpecMatrix
65 CTRL0 : entity work.ReUse_CTRLR
66 port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
67
68
69 TopSM : entity work.TopSpecMatrix
63 generic map (Input_SZ)
70 generic map (Input_SZ)
64 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
71 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
65
72
66 SM : SpectralMatrix
73 SM : entity work.SpectralMatrix
67 generic map (Input_SZ,Result_SZ)
74 generic map (Input_SZ,Result_SZ)
68 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
75 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
69
76
70 DISP : Dispatch
77 DISP : entity work.Dispatch
71 generic map(Result_SZ)
78 generic map(Result_SZ)
72 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
79 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
73
80
81 Statu <= TopSM_Statu;
74
82
75 end architecture;
83 end architecture;
76
84
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@@ -1,253 +1,266
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic;
44 clk : in std_logic;
45 rst : in std_logic;
45 rst : in std_logic;
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
51 FullFIFO : in std_logic;
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
56 );
57 end component;
57 end component;
58
58
59 component MatriceSpectrale is
59 component MatriceSpectrale is
60 generic(
60 generic(
61 Input_SZ : integer := 16;
61 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
62 Result_SZ : integer := 32);
63 port(
63 port(
64 clkm : in std_logic;
64 clkm : in std_logic;
65 rstn : in std_logic;
65 rstn : in std_logic;
66
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
68 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 FifoOUT_Full : in std_logic_vector(1 downto 0);
69 Data_IN : in std_logic_vector(79 downto 0);
70 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
70 ACQ : in std_logic;
71 ACQ : in std_logic;
71 FlagError : out std_logic;
72 FlagError : out std_logic;
72 Pong : out std_logic;
73 Pong : out std_logic;
74 Statu : out std_logic_vector(3 downto 0);
73 Write : out std_logic_vector(1 downto 0);
75 Write : out std_logic_vector(1 downto 0);
74 Read : out std_logic_vector(4 downto 0);
76 Read : out std_logic_vector(4 downto 0);
75 Data_OUT : out std_logic_vector(63 downto 0)
77 ReUse : out std_logic_vector(4 downto 0);
78 Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0)
76 );
79 );
77 end component;
80 end component;
78
81
79
82
80 component TopSpecMatrix is
83 component TopSpecMatrix is
81 generic(
84 generic(
82 Input_SZ : integer := 16);
85 Input_SZ : integer := 16);
83 port(
86 port(
84 clk : in std_logic;
87 clk : in std_logic;
85 rstn : in std_logic;
88 rstn : in std_logic;
86 Write : in std_logic;
89 Write : in std_logic;
87 ReadIn : in std_logic_vector(1 downto 0);
90 ReadIn : in std_logic_vector(1 downto 0);
88 Full : in std_logic_vector(4 downto 0);
91 Full : in std_logic_vector(4 downto 0);
89 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
92 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
90 Start : out std_logic;
93 Start : out std_logic;
91 ReadOut : out std_logic_vector(4 downto 0);
94 ReadOut : out std_logic_vector(4 downto 0);
92 Statu : out std_logic_vector(3 downto 0);
95 Statu : out std_logic_vector(3 downto 0);
93 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
96 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
94 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
97 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
95 );
98 );
96 end component;
99 end component;
97
100
98
101
99 component Top_MatrixSpec is
102 component Top_MatrixSpec is
100 generic(
103 generic(
101 Input_SZ : integer := 16;
104 Input_SZ : integer := 16;
102 Result_SZ : integer := 32);
105 Result_SZ : integer := 32);
103 port(
106 port(
104 clk : in std_logic;
107 clk : in std_logic;
105 reset : in std_logic;
108 reset : in std_logic;
106 Statu : in std_logic_vector(3 downto 0);
109 Statu : in std_logic_vector(3 downto 0);
107 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
110 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
108 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
111 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
109 Full : in std_logic_vector(1 downto 0);
112 Full : in std_logic_vector(1 downto 0);
110 Empty : in std_logic_vector(1 downto 0);
113 Empty : in std_logic_vector(1 downto 0);
111 ReadFIFO : out std_logic_vector(1 downto 0);
114 ReadFIFO : out std_logic_vector(1 downto 0);
112 FullFIFO : in std_logic;
115 FullFIFO : in std_logic;
113 WriteFIFO : out std_logic;
116 WriteFIFO : out std_logic;
114 Result : out std_logic_vector(Result_SZ-1 downto 0)
117 Result : out std_logic_vector(Result_SZ-1 downto 0)
115 );
118 );
116 end component;
119 end component;
117
120
118 component SpectralMatrix is
121 component SpectralMatrix is
119 generic(
122 generic(
120 Input_SZ : integer := 16;
123 Input_SZ : integer := 16;
121 Result_SZ : integer := 32);
124 Result_SZ : integer := 32);
122 port(
125 port(
123 clk : in std_logic;
126 clk : in std_logic;
124 reset : in std_logic;
127 reset : in std_logic;
125 Start : in std_logic;
128 Start : in std_logic;
126 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
129 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
127 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
130 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
128 Statu : in std_logic_vector(3 downto 0);
131 Statu : in std_logic_vector(3 downto 0);
129 -- FullFIFO : in std_logic;
132 -- FullFIFO : in std_logic;
130 ReadFIFO : out std_logic_vector(1 downto 0);
133 ReadFIFO : out std_logic_vector(1 downto 0);
131 WriteFIFO : out std_logic;
134 WriteFIFO : out std_logic;
132 Result : out std_logic_vector(Result_SZ-1 downto 0)
135 Result : out std_logic_vector(Result_SZ-1 downto 0)
133 );
136 );
134 end component;
137 end component;
135
138
136
139
137 component Matrix is
140 component Matrix is
138 generic(
141 generic(
139 Input_SZ : integer := 16);
142 Input_SZ : integer := 16);
140 port(
143 port(
141 clk : in std_logic;
144 clk : in std_logic;
142 raz : in std_logic;
145 raz : in std_logic;
143 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
146 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
144 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
147 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
145 Take : in std_logic;
148 Take : in std_logic;
146 Received : in std_logic;
149 Received : in std_logic;
147 Conjugate : in std_logic;
150 Conjugate : in std_logic;
148 Valid : out std_logic;
151 Valid : out std_logic;
149 Read : out std_logic;
152 Read : out std_logic;
150 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
153 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
151 );
154 );
152 end component;
155 end component;
153
156
154 component GetResult is
157 component GetResult is
155 generic(
158 generic(
156 Result_SZ : integer := 32);
159 Result_SZ : integer := 32);
157 port(
160 port(
158 clk : in std_logic;
161 clk : in std_logic;
159 raz : in std_logic;
162 raz : in std_logic;
160 Valid : in std_logic;
163 Valid : in std_logic;
161 Conjugate : in std_logic;
164 Conjugate : in std_logic;
162 Res : in std_logic_vector(Result_SZ-1 downto 0);
165 Res : in std_logic_vector(Result_SZ-1 downto 0);
163 -- Full : in std_logic;
166 -- Full : in std_logic;
164 WriteFIFO : out std_logic;
167 WriteFIFO : out std_logic;
165 Received : out std_logic;
168 Received : out std_logic;
166 Result : out std_logic_vector(Result_SZ-1 downto 0)
169 Result : out std_logic_vector(Result_SZ-1 downto 0)
167 );
170 );
168 end component;
171 end component;
169
172
170
173
171 component TopMatrix_PDR is
174 component TopMatrix_PDR is
172 generic(
175 generic(
173 Input_SZ : integer := 16;
176 Input_SZ : integer := 16;
174 Result_SZ : integer := 32);
177 Result_SZ : integer := 32);
175 port(
178 port(
176 clk : in std_logic;
179 clk : in std_logic;
177 reset : in std_logic;
180 reset : in std_logic;
178 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
181 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
179 FULLin : in std_logic_vector(4 downto 0);
182 FULLin : in std_logic_vector(4 downto 0);
180 READin : in std_logic_vector(1 downto 0);
183 READin : in std_logic_vector(1 downto 0);
181 WRITEin : in std_logic;
184 WRITEin : in std_logic;
182 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
185 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
183 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
186 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
184 Start : out std_logic;
187 Start : out std_logic;
185 Read : out std_logic_vector(4 downto 0);
188 Read : out std_logic_vector(4 downto 0);
186 Statu : out std_logic_vector(3 downto 0)
189 Statu : out std_logic_vector(3 downto 0)
187 );
190 );
188 end component;
191 end component;
189
192
190
193
191 component Dispatch is
194 component Dispatch is
192 generic(
195 generic(
193 Data_SZ : integer := 32);
196 Data_SZ : integer := 32);
194 port(
197 port(
195 clk : in std_logic;
198 clk : in std_logic;
196 reset : in std_logic;
199 reset : in std_logic;
197 Acq : in std_logic;
200 Acq : in std_logic;
198 Data : in std_logic_vector(Data_SZ-1 downto 0);
201 Data : in std_logic_vector(Data_SZ-1 downto 0);
199 Write : in std_logic;
202 Write : in std_logic;
200 Full : in std_logic_vector(1 downto 0);
203 Full : in std_logic_vector(1 downto 0);
201 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
204 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
202 FifoWrite : out std_logic_vector(1 downto 0);
205 FifoWrite : out std_logic_vector(1 downto 0);
203 Pong : out std_logic;
206 Pong : out std_logic;
204 Error : out std_logic
207 Error : out std_logic
205 );
208 );
206 end component;
209 end component;
207
210
208
211
209 component DriveInputs is
212 component DriveInputs is
210 port(
213 port(
211 clk : in std_logic;
214 clk : in std_logic;
212 raz : in std_logic;
215 raz : in std_logic;
213 Read : in std_logic;
216 Read : in std_logic;
214 Conjugate : in std_logic;
217 Conjugate : in std_logic;
215 Take : out std_logic;
218 Take : out std_logic;
216 ReadFIFO : out std_logic_vector(1 downto 0)
219 ReadFIFO : out std_logic_vector(1 downto 0)
217 );
220 );
218 end component;
221 end component;
219
222
220 component Starter is
223 component Starter is
221 port(
224 port(
222 clk : in std_logic;
225 clk : in std_logic;
223 raz : in std_logic;
226 raz : in std_logic;
224 Full : in std_logic_vector(1 downto 0);
227 Full : in std_logic_vector(1 downto 0);
225 Empty : in std_logic_vector(1 downto 0);
228 Empty : in std_logic_vector(1 downto 0);
226 Statu : in std_logic_vector(3 downto 0);
229 Statu : in std_logic_vector(3 downto 0);
227 Write : in std_logic;
230 Write : in std_logic;
228 Start : out std_logic
231 Start : out std_logic
229 );
232 );
230 end component;
233 end component;
231
234
232 component ALU_Driver is
235 component ALU_Driver is
233 generic(
236 generic(
234 Input_SZ_1 : integer := 16;
237 Input_SZ_1 : integer := 16;
235 Input_SZ_2 : integer := 16);
238 Input_SZ_2 : integer := 16);
236 port(
239 port(
237 clk : in std_logic;
240 clk : in std_logic;
238 reset : in std_logic;
241 reset : in std_logic;
239 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
242 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
240 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
243 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
241 Take : in std_logic;
244 Take : in std_logic;
242 Received : in std_logic;
245 Received : in std_logic;
243 Conjugate : in std_logic;
246 Conjugate : in std_logic;
244 Valid : out std_logic;
247 Valid : out std_logic;
245 Read : out std_logic;
248 Read : out std_logic;
246 CTRL : out std_logic_vector(2 downto 0);
249 CTRL : out std_logic_vector(2 downto 0);
247 COMP : out std_logic_vector(1 downto 0);
250 COMP : out std_logic_vector(1 downto 0);
248 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
251 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
249 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
252 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
250 );
253 );
251 end component;
254 end component;
252
255
256 component ReUse_CTRLR is
257 port(
258 clk : in std_logic;
259 reset : in std_logic;
260 SetReUse : in std_logic_vector(4 downto 0);
261 Statu : in std_logic_vector(3 downto 0);
262 ReUse : out std_logic_vector(4 downto 0)
263 );
264 end component;
265
253 end; No newline at end of file
266 end;
Show file before | Show file after | Hide comments
@@ -1,303 +1,303
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
10 USE techmap.gencomp.ALL;
11
11
12 ENTITY lpp_top_acq IS
12 ENTITY lpp_top_acq IS
13 GENERIC(
13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0
15 );
15 );
16 PORT (
16 PORT (
17 -- ADS7886
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC; -- 25 MHz
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 --
31 --
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
40 );
40 );
41 END lpp_top_acq;
41 END lpp_top_acq;
42
42
43 ARCHITECTURE tb OF lpp_top_acq IS
43 ARCHITECTURE tb OF lpp_top_acq IS
44
44
45 COMPONENT Downsampling
45 COMPONENT Downsampling
46 GENERIC (
46 GENERIC (
47 ChanelCount : INTEGER;
47 ChanelCount : INTEGER;
48 SampleSize : INTEGER;
48 SampleSize : INTEGER;
49 DivideParam : INTEGER);
49 DivideParam : INTEGER);
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_out_val : OUT STD_LOGIC;
55 sample_out_val : OUT STD_LOGIC;
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 END COMPONENT;
57 END COMPONENT;
58
58
59 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
60 CONSTANT ChanelCount : INTEGER := 8;
60 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv : INTEGER := 500;
62 CONSTANT ncycle_cnv : INTEGER := 500;
63
63
64 -----------------------------------------------------------------------------
64 -----------------------------------------------------------------------------
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample_val : STD_LOGIC;
66 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 CONSTANT Coef_SZ : INTEGER := 9;
69 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefPerCel : INTEGER := 5;
71 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
73
73
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 --
76 --
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
79 --
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 --
86 --
87 SIGNAL sample_f0_val : STD_LOGIC;
87 SIGNAL sample_f0_val : STD_LOGIC;
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 SIGNAL sample_f1_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
92 --
93 SIGNAL sample_f2_val : STD_LOGIC;
93 SIGNAL sample_f2_val : STD_LOGIC;
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 --
95 --
96 SIGNAL sample_f3_val : STD_LOGIC;
96 SIGNAL sample_f3_val : STD_LOGIC;
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98
98
99 BEGIN
99 BEGIN
100
100
101 -- component instantiation
101 -- component instantiation
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 DIGITAL_acquisition : AD7688_drvr
103 DIGITAL_acquisition : AD7688_drvr
104 GENERIC MAP (
104 GENERIC MAP (
105 ChanelCount => ChanelCount,
105 ChanelCount => ChanelCount,
106 ncycle_cnv_high => ncycle_cnv_high,
106 ncycle_cnv_high => ncycle_cnv_high,
107 ncycle_cnv => ncycle_cnv)
107 ncycle_cnv => ncycle_cnv)
108 PORT MAP (
108 PORT MAP (
109 cnv_clk => cnv_clk, --
109 cnv_clk => cnv_clk, --
110 cnv_rstn => cnv_rstn, --
110 cnv_rstn => cnv_rstn, --
111 cnv_run => cnv_run, --
111 cnv_run => cnv_run, --
112 cnv => cnv, --
112 cnv => cnv, --
113 clk => clk, --
113 clk => clk, --
114 rstn => rstn, --
114 rstn => rstn, --
115 sck => sck, --
115 sck => sck, --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
117 sample => sample,
117 sample => sample,
118 sample_val => sample_val);
118 sample_val => sample_val);
119
119
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121
121
122 PROCESS (clk, rstn)
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 sample_val_delay <= '0';
125 sample_val_delay <= '0';
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 sample_val_delay <= sample_val;
127 sample_val_delay <= sample_val;
128 END IF;
128 END IF;
129 END PROCESS;
129 END PROCESS;
130
130
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
134 sample_filter_in(i, j) <= sample(i)(j);
134 sample_filter_in(i, j) <= sample(i)(j);
135 END GENERATE;
135 END GENERATE;
136
136
137 sample_filter_in(i, 16) <= sample(i)(15);
137 sample_filter_in(i, 16) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
139 END GENERATE;
139 END GENERATE;
140
140
141 coefs_v2 <= CoefsInitValCst_v2;
141 coefs_v2 <= CoefsInitValCst_v2;
142
142
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 GENERIC MAP (
144 GENERIC MAP (
145 tech => 0,
145 tech => 0,
146 Mem_use => use_CEL,
146 Mem_use => use_RAM,
147 Sample_SZ => 18,
147 Sample_SZ => 18,
148 Coef_SZ => Coef_SZ,
148 Coef_SZ => Coef_SZ,
149 Coef_Nb => 25, -- TODO
149 Coef_Nb => 25, -- TODO
150 Coef_sel_SZ => 5, -- TODO
150 Coef_sel_SZ => 5, -- TODO
151 Cels_count => Cels_count,
151 Cels_count => Cels_count,
152 ChanelsCount => ChanelCount)
152 ChanelsCount => ChanelCount)
153 PORT MAP (
153 PORT MAP (
154 rstn => rstn,
154 rstn => rstn,
155 clk => clk,
155 clk => clk,
156 virg_pos => 7,
156 virg_pos => 7,
157 coefs => coefs_v2,
157 coefs => coefs_v2,
158 sample_in_val => sample_val_delay,
158 sample_in_val => sample_val_delay,
159 sample_in => sample_filter_in,
159 sample_in => sample_filter_in,
160 sample_out_val => sample_filter_v2_out_val,
160 sample_out_val => sample_filter_v2_out_val,
161 sample_out => sample_filter_v2_out);
161 sample_out => sample_filter_v2_out);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 PROCESS (clk, rstn)
164 PROCESS (clk, rstn)
165 BEGIN -- PROCESS
165 BEGIN -- PROCESS
166 IF rstn = '0' THEN -- asynchronous reset (active low)
166 IF rstn = '0' THEN -- asynchronous reset (active low)
167 sample_filter_v2_out_r_val <= '0';
167 sample_filter_v2_out_r_val <= '0';
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
170 sample_filter_v2_out_r(I, J) <= '0';
170 sample_filter_v2_out_r(I, J) <= '0';
171 END LOOP rst_all_bits;
171 END LOOP rst_all_bits;
172 END LOOP rst_all_chanel;
172 END LOOP rst_all_chanel;
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
175 IF sample_filter_v2_out_val = '1' THEN
175 IF sample_filter_v2_out_val = '1' THEN
176 sample_filter_v2_out_r <= sample_filter_v2_out;
176 sample_filter_v2_out_r <= sample_filter_v2_out;
177 END IF;
177 END IF;
178 END IF;
178 END IF;
179 END PROCESS;
179 END PROCESS;
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- F0 -- @24.576 kHz
182 -- F0 -- @24.576 kHz
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184 Downsampling_f0 : Downsampling
184 Downsampling_f0 : Downsampling
185 GENERIC MAP (
185 GENERIC MAP (
186 ChanelCount => ChanelCount,
186 ChanelCount => ChanelCount,
187 SampleSize => 18,
187 SampleSize => 18,
188 DivideParam => 4)
188 DivideParam => 4)
189 PORT MAP (
189 PORT MAP (
190 clk => clk,
190 clk => clk,
191 rstn => rstn,
191 rstn => rstn,
192 sample_in_val => sample_filter_v2_out_val ,
192 sample_in_val => sample_filter_v2_out_val ,
193 sample_in => sample_filter_v2_out,
193 sample_in => sample_filter_v2_out,
194 sample_out_val => sample_f0_val,
194 sample_out_val => sample_f0_val,
195 sample_out => sample_f0);
195 sample_out => sample_f0);
196
196
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
198 sample_f0_wdata(I) <= sample_f0(0, I);
198 sample_f0_wdata(I) <= sample_f0(0, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
203 END GENERATE all_bit_sample_f0;
203 END GENERATE all_bit_sample_f0;
204
204
205 sample_f0_wen <= NOT(sample_f0_val) &
205 sample_f0_wen <= NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
209 NOT(sample_f0_val);
209 NOT(sample_f0_val);
210
210
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 -- F1 -- @4096 Hz
212 -- F1 -- @4096 Hz
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214 Downsampling_f1 : Downsampling
214 Downsampling_f1 : Downsampling
215 GENERIC MAP (
215 GENERIC MAP (
216 ChanelCount => ChanelCount,
216 ChanelCount => ChanelCount,
217 SampleSize => 18,
217 SampleSize => 18,
218 DivideParam => 6)
218 DivideParam => 6)
219 PORT MAP (
219 PORT MAP (
220 clk => clk,
220 clk => clk,
221 rstn => rstn,
221 rstn => rstn,
222 sample_in_val => sample_f0_val ,
222 sample_in_val => sample_f0_val ,
223 sample_in => sample_f0,
223 sample_in => sample_f0,
224 sample_out_val => sample_f1_val,
224 sample_out_val => sample_f1_val,
225 sample_out => sample_f1);
225 sample_out => sample_f1);
226
226
227 sample_f1_wen <= NOT(sample_f1_val) &
227 sample_f1_wen <= NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
231 NOT(sample_f1_val);
231 NOT(sample_f1_val);
232
232
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
234 sample_f1_wdata(I) <= sample_f1(0, I);
234 sample_f1_wdata(I) <= sample_f1(0, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
239 END GENERATE all_bit_sample_f1;
239 END GENERATE all_bit_sample_f1;
240
240
241 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
242 -- F2 -- @16 Hz
242 -- F2 -- @16 Hz
243 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
244 Downsampling_f2 : Downsampling
244 Downsampling_f2 : Downsampling
245 GENERIC MAP (
245 GENERIC MAP (
246 ChanelCount => ChanelCount,
246 ChanelCount => ChanelCount,
247 SampleSize => 18,
247 SampleSize => 18,
248 DivideParam => 256)
248 DivideParam => 256)
249 PORT MAP (
249 PORT MAP (
250 clk => clk,
250 clk => clk,
251 rstn => rstn,
251 rstn => rstn,
252 sample_in_val => sample_f1_val ,
252 sample_in_val => sample_f1_val ,
253 sample_in => sample_f1,
253 sample_in => sample_f1,
254 sample_out_val => sample_f2_val,
254 sample_out_val => sample_f2_val,
255 sample_out => sample_f2);
255 sample_out => sample_f2);
256
256
257 sample_f2_wen <= NOT(sample_f2_val) &
257 sample_f2_wen <= NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
261 NOT(sample_f2_val);
261 NOT(sample_f2_val);
262
262
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
264 sample_f2_wdata(I) <= sample_f2(0, I);
264 sample_f2_wdata(I) <= sample_f2(0, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
269 END GENERATE all_bit_sample_f2;
269 END GENERATE all_bit_sample_f2;
270
270
271 -----------------------------------------------------------------------------
271 -----------------------------------------------------------------------------
272 -- F3 -- @256 Hz
272 -- F3 -- @256 Hz
273 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
274 Downsampling_f3 : Downsampling
274 Downsampling_f3 : Downsampling
275 GENERIC MAP (
275 GENERIC MAP (
276 ChanelCount => ChanelCount,
276 ChanelCount => ChanelCount,
277 SampleSize => 18,
277 SampleSize => 18,
278 DivideParam => 96)
278 DivideParam => 96)
279 PORT MAP (
279 PORT MAP (
280 clk => clk,
280 clk => clk,
281 rstn => rstn,
281 rstn => rstn,
282 sample_in_val => sample_f0_val ,
282 sample_in_val => sample_f0_val ,
283 sample_in => sample_f0,
283 sample_in => sample_f0,
284 sample_out_val => sample_f3_val,
284 sample_out_val => sample_f3_val,
285 sample_out => sample_f3);
285 sample_out => sample_f3);
286
286
287 sample_f3_wen <= (NOT sample_f3_val) &
287 sample_f3_wen <= (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
291 (NOT sample_f3_val);
291 (NOT sample_f3_val);
292
292
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
294 sample_f3_wdata(I) <= sample_f3(0, I);
294 sample_f3_wdata(I) <= sample_f3(0, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
299 END GENERATE all_bit_sample_f3;
299 END GENERATE all_bit_sample_f3;
300
300
301
301
302
302
303 END tb;
303 END tb;
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