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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.numeric_std.ALL;
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USE IEEE.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.general_purpose.ALL;
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ENTITY Adder IS
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GENERIC(
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Input_SZ_A : INTEGER := 16;
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Input_SZ_B : INTEGER := 16
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);
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PORT(
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clk : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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clr : IN STD_LOGIC;
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load : IN STD_LOGIC;
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add : IN STD_LOGIC;
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OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
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RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
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);
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END ENTITY;
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ARCHITECTURE ar_Adder OF Adder IS
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SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
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BEGIN
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RES <= REG;
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RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
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PROCESS(clk, reset)
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BEGIN
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IF reset = '0' THEN
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REG <= (OTHERS => '0');
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ELSIF clk'EVENT AND clk = '1' then
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IF clr = '1' THEN
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REG <= (OTHERS => '0');
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ELSIF add = '1' THEN
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REG <= RESADD;
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ELSIF load = '1' THEN
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REG <= OP2;
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END IF;
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END IF;
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END PROCESS;
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END ar_Adder;
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