##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Remove "Sync Stage" between Filter and DownSampler into waveformPicker
pellion -
r205:6eb3be2045fd JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,280 +1,278
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_top_lfr_pkg IS
15 PACKAGE lpp_top_lfr_pkg IS
16
16
17 COMPONENT lpp_top_acq
17 COMPONENT lpp_top_acq
18 GENERIC(
18 GENERIC(
19 tech : INTEGER := 0;
19 tech : INTEGER := 0;
20 Mem_use : integer := use_RAM
20 Mem_use : integer := use_RAM
21 );
21 );
22 PORT (
22 PORT (
23 -- ADS7886
23 -- ADS7886
24 cnv_run : IN STD_LOGIC;
24 cnv_run : IN STD_LOGIC;
25 cnv : OUT STD_LOGIC;
25 cnv : OUT STD_LOGIC;
26 sck : OUT STD_LOGIC;
26 sck : OUT STD_LOGIC;
27 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
27 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
28 --
28 --
29 cnv_clk : IN STD_LOGIC; -- 49 MHz
29 cnv_clk : IN STD_LOGIC; -- 49 MHz
30 cnv_rstn : IN STD_LOGIC;
30 cnv_rstn : IN STD_LOGIC;
31 --
31 --
32 clk : IN STD_LOGIC; -- 25 MHz
32 clk : IN STD_LOGIC; -- 25 MHz
33 rstn : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 --
34 --
35 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 --
40 --
41 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 --
43 --
44 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
46 );
46 );
47 END COMPONENT;
47 END COMPONENT;
48
48
49 COMPONENT lpp_top_apbreg
49 COMPONENT lpp_top_apbreg
50 GENERIC (
50 GENERIC (
51 nb_burst_available_size : INTEGER;
51 nb_burst_available_size : INTEGER;
52 nb_snapshot_param_size : INTEGER;
52 nb_snapshot_param_size : INTEGER;
53 delta_snapshot_size : INTEGER;
53 delta_snapshot_size : INTEGER;
54 delta_f2_f0_size : INTEGER;
54 delta_f2_f0_size : INTEGER;
55 delta_f2_f1_size : INTEGER;
55 delta_f2_f1_size : INTEGER;
56 pindex : INTEGER;
56 pindex : INTEGER;
57 paddr : INTEGER;
57 paddr : INTEGER;
58 pmask : INTEGER;
58 pmask : INTEGER;
59 pirq : INTEGER);
59 pirq : INTEGER);
60 PORT (
60 PORT (
61 HCLK : IN STD_ULOGIC;
61 HCLK : IN STD_ULOGIC;
62 HRESETn : IN STD_ULOGIC;
62 HRESETn : IN STD_ULOGIC;
63 apbi : IN apb_slv_in_type;
63 apbi : IN apb_slv_in_type;
64 apbo : OUT apb_slv_out_type;
64 apbo : OUT apb_slv_out_type;
65 ready_matrix_f0_0 : IN STD_LOGIC;
65 ready_matrix_f0_0 : IN STD_LOGIC;
66 ready_matrix_f0_1 : IN STD_LOGIC;
66 ready_matrix_f0_1 : IN STD_LOGIC;
67 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f2 : IN STD_LOGIC;
68 ready_matrix_f2 : IN STD_LOGIC;
69 error_anticipating_empty_fifo : IN STD_LOGIC;
69 error_anticipating_empty_fifo : IN STD_LOGIC;
70 error_bad_component_error : IN STD_LOGIC;
70 error_bad_component_error : IN STD_LOGIC;
71 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
84 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 data_shaping_BW : OUT STD_LOGIC;
88 data_shaping_BW : OUT STD_LOGIC;
89 data_shaping_SP0 : OUT STD_LOGIC;
89 data_shaping_SP0 : OUT STD_LOGIC;
90 data_shaping_SP1 : OUT STD_LOGIC;
90 data_shaping_SP1 : OUT STD_LOGIC;
91 data_shaping_R0 : OUT STD_LOGIC;
91 data_shaping_R0 : OUT STD_LOGIC;
92 data_shaping_R1 : OUT STD_LOGIC;
92 data_shaping_R1 : OUT STD_LOGIC;
93 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
93 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
94 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
94 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
95 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
95 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
96 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
96 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
97 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
97 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
98 enable_f0 : OUT STD_LOGIC;
98 enable_f0 : OUT STD_LOGIC;
99 enable_f1 : OUT STD_LOGIC;
99 enable_f1 : OUT STD_LOGIC;
100 enable_f2 : OUT STD_LOGIC;
100 enable_f2 : OUT STD_LOGIC;
101 enable_f3 : OUT STD_LOGIC;
101 enable_f3 : OUT STD_LOGIC;
102 burst_f0 : OUT STD_LOGIC;
102 burst_f0 : OUT STD_LOGIC;
103 burst_f1 : OUT STD_LOGIC;
103 burst_f1 : OUT STD_LOGIC;
104 burst_f2 : OUT STD_LOGIC;
104 burst_f2 : OUT STD_LOGIC;
105 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
108 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
109 END COMPONENT;
109 END COMPONENT;
110
110
111 COMPONENT lpp_top_lfr_wf_picker
111 COMPONENT lpp_top_lfr_wf_picker
112 GENERIC (
112 GENERIC (
113 hindex : INTEGER;
113 hindex : INTEGER;
114 pindex : INTEGER;
114 pindex : INTEGER;
115 paddr : INTEGER;
115 paddr : INTEGER;
116 pmask : INTEGER;
116 pmask : INTEGER;
117 pirq : INTEGER;
117 pirq : INTEGER;
118 tech : INTEGER;
118 tech : INTEGER;
119 nb_burst_available_size : INTEGER;
119 nb_burst_available_size : INTEGER;
120 nb_snapshot_param_size : INTEGER;
120 nb_snapshot_param_size : INTEGER;
121 delta_snapshot_size : INTEGER;
121 delta_snapshot_size : INTEGER;
122 delta_f2_f0_size : INTEGER;
122 delta_f2_f0_size : INTEGER;
123 delta_f2_f1_size : INTEGER;
123 delta_f2_f1_size : INTEGER;
124 ENABLE_FILTER : STD_LOGIC);
124 ENABLE_FILTER : STD_LOGIC);
125 PORT (
125 PORT (
126 cnv_run : IN STD_LOGIC;
126 cnv_run : IN STD_LOGIC;
127 cnv : OUT STD_LOGIC;
127 cnv : OUT STD_LOGIC;
128 sck : OUT STD_LOGIC;
128 sck : OUT STD_LOGIC;
129 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
129 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
130 cnv_clk : IN STD_LOGIC;
130 cnv_clk : IN STD_LOGIC;
131 cnv_rstn : IN STD_LOGIC;
131 cnv_rstn : IN STD_LOGIC;
132 HCLK : IN STD_ULOGIC;
132 HCLK : IN STD_ULOGIC;
133 HRESETn : IN STD_ULOGIC;
133 HRESETn : IN STD_ULOGIC;
134 apbi : IN apb_slv_in_type;
134 apbi : IN apb_slv_in_type;
135 apbo : OUT apb_slv_out_type;
135 apbo : OUT apb_slv_out_type;
136 AHB_Master_In : IN AHB_Mst_In_Type;
136 AHB_Master_In : IN AHB_Mst_In_Type;
137 AHB_Master_Out : OUT AHB_Mst_Out_Type;
137 AHB_Master_Out : OUT AHB_Mst_Out_Type;
138 coarse_time_0 : IN STD_LOGIC;
138 coarse_time_0 : IN STD_LOGIC;
139 data_shaping_BW : OUT STD_LOGIC);
139 data_shaping_BW : OUT STD_LOGIC);
140 END COMPONENT;
140 END COMPONENT;
141
141
142
142
143 COMPONENT lpp_top_lfr_wf_picker_ip
143 COMPONENT lpp_top_lfr_wf_picker_ip
144 GENERIC (
144 GENERIC (
145 hindex : INTEGER;
145 hindex : INTEGER;
146 nb_burst_available_size : INTEGER;
146 nb_burst_available_size : INTEGER;
147 nb_snapshot_param_size : INTEGER;
147 nb_snapshot_param_size : INTEGER;
148 delta_snapshot_size : INTEGER;
148 delta_snapshot_size : INTEGER;
149 delta_f2_f0_size : INTEGER;
149 delta_f2_f0_size : INTEGER;
150 delta_f2_f1_size : INTEGER;
150 delta_f2_f1_size : INTEGER;
151 tech : INTEGER;
151 tech : INTEGER;
152 Mem_use : INTEGER);
152 Mem_use : INTEGER);
153 PORT (
153 PORT (
154 sample : IN Samples(7 DOWNTO 0);
154 sample : IN Samples(7 DOWNTO 0);
155 sample_val : IN STD_LOGIC;
155 sample_val : IN STD_LOGIC;
156 cnv_clk : IN STD_LOGIC;
157 cnv_rstn : IN STD_LOGIC;
158 clk : IN STD_LOGIC;
156 clk : IN STD_LOGIC;
159 rstn : IN STD_LOGIC;
157 rstn : IN STD_LOGIC;
160 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
158 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
161 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
159 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
162 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
160 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
163 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
161 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
164 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
162 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
165 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
163 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
166 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
164 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
167 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
165 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 AHB_Master_In : IN AHB_Mst_In_Type;
166 AHB_Master_In : IN AHB_Mst_In_Type;
169 AHB_Master_Out : OUT AHB_Mst_Out_Type;
167 AHB_Master_Out : OUT AHB_Mst_Out_Type;
170 coarse_time_0 : IN STD_LOGIC;
168 coarse_time_0 : IN STD_LOGIC;
171 data_shaping_SP0 : IN STD_LOGIC;
169 data_shaping_SP0 : IN STD_LOGIC;
172 data_shaping_SP1 : IN STD_LOGIC;
170 data_shaping_SP1 : IN STD_LOGIC;
173 data_shaping_R0 : IN STD_LOGIC;
171 data_shaping_R0 : IN STD_LOGIC;
174 data_shaping_R1 : IN STD_LOGIC;
172 data_shaping_R1 : IN STD_LOGIC;
175 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
173 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
176 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
174 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
177 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
175 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
178 enable_f0 : IN STD_LOGIC;
176 enable_f0 : IN STD_LOGIC;
179 enable_f1 : IN STD_LOGIC;
177 enable_f1 : IN STD_LOGIC;
180 enable_f2 : IN STD_LOGIC;
178 enable_f2 : IN STD_LOGIC;
181 enable_f3 : IN STD_LOGIC;
179 enable_f3 : IN STD_LOGIC;
182 burst_f0 : IN STD_LOGIC;
180 burst_f0 : IN STD_LOGIC;
183 burst_f1 : IN STD_LOGIC;
181 burst_f1 : IN STD_LOGIC;
184 burst_f2 : IN STD_LOGIC;
182 burst_f2 : IN STD_LOGIC;
185 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
183 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
186 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
184 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
187 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
188 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
189 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
187 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
190 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
188 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
191 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
189 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
193 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
194 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
192 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
195 END COMPONENT;
193 END COMPONENT;
196
194
197 COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
195 COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
198 GENERIC (
196 GENERIC (
199 hindex : INTEGER;
197 hindex : INTEGER;
200 nb_burst_available_size : INTEGER;
198 nb_burst_available_size : INTEGER;
201 nb_snapshot_param_size : INTEGER;
199 nb_snapshot_param_size : INTEGER;
202 delta_snapshot_size : INTEGER;
200 delta_snapshot_size : INTEGER;
203 delta_f2_f0_size : INTEGER;
201 delta_f2_f0_size : INTEGER;
204 delta_f2_f1_size : INTEGER;
202 delta_f2_f1_size : INTEGER;
205 tech : INTEGER);
203 tech : INTEGER);
206 PORT (
204 PORT (
207 sample : IN Samples(7 DOWNTO 0);
205 sample : IN Samples(7 DOWNTO 0);
208 sample_val : IN STD_LOGIC;
206 sample_val : IN STD_LOGIC;
209 cnv_clk : IN STD_LOGIC;
207 cnv_clk : IN STD_LOGIC;
210 cnv_rstn : IN STD_LOGIC;
208 cnv_rstn : IN STD_LOGIC;
211 clk : IN STD_LOGIC;
209 clk : IN STD_LOGIC;
212 rstn : IN STD_LOGIC;
210 rstn : IN STD_LOGIC;
213 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
211 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
214 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
212 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
215 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
213 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
216 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
214 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
217 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
215 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
218 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
216 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
219 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
217 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
220 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
218 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
221 AHB_Master_In : IN AHB_Mst_In_Type;
219 AHB_Master_In : IN AHB_Mst_In_Type;
222 AHB_Master_Out : OUT AHB_Mst_Out_Type;
220 AHB_Master_Out : OUT AHB_Mst_Out_Type;
223 coarse_time_0 : IN STD_LOGIC;
221 coarse_time_0 : IN STD_LOGIC;
224 data_shaping_SP0 : IN STD_LOGIC;
222 data_shaping_SP0 : IN STD_LOGIC;
225 data_shaping_SP1 : IN STD_LOGIC;
223 data_shaping_SP1 : IN STD_LOGIC;
226 data_shaping_R0 : IN STD_LOGIC;
224 data_shaping_R0 : IN STD_LOGIC;
227 data_shaping_R1 : IN STD_LOGIC;
225 data_shaping_R1 : IN STD_LOGIC;
228 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
226 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
229 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
227 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
230 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
228 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
231 enable_f0 : IN STD_LOGIC;
229 enable_f0 : IN STD_LOGIC;
232 enable_f1 : IN STD_LOGIC;
230 enable_f1 : IN STD_LOGIC;
233 enable_f2 : IN STD_LOGIC;
231 enable_f2 : IN STD_LOGIC;
234 enable_f3 : IN STD_LOGIC;
232 enable_f3 : IN STD_LOGIC;
235 burst_f0 : IN STD_LOGIC;
233 burst_f0 : IN STD_LOGIC;
236 burst_f1 : IN STD_LOGIC;
234 burst_f1 : IN STD_LOGIC;
237 burst_f2 : IN STD_LOGIC;
235 burst_f2 : IN STD_LOGIC;
238 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
236 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
239 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
237 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
240 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
238 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
239 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
242 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
240 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
243 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
244 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
242 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
246 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
247 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
245 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
248 END COMPONENT;
246 END COMPONENT;
249
247
250 COMPONENT top_wf_picker
248 COMPONENT top_wf_picker
251 GENERIC (
249 GENERIC (
252 hindex : INTEGER;
250 hindex : INTEGER;
253 pindex : INTEGER;
251 pindex : INTEGER;
254 paddr : INTEGER;
252 paddr : INTEGER;
255 pmask : INTEGER;
253 pmask : INTEGER;
256 pirq : INTEGER;
254 pirq : INTEGER;
257 tech : INTEGER;
255 tech : INTEGER;
258 nb_burst_available_size : INTEGER;
256 nb_burst_available_size : INTEGER;
259 nb_snapshot_param_size : INTEGER;
257 nb_snapshot_param_size : INTEGER;
260 delta_snapshot_size : INTEGER;
258 delta_snapshot_size : INTEGER;
261 delta_f2_f0_size : INTEGER;
259 delta_f2_f0_size : INTEGER;
262 delta_f2_f1_size : INTEGER;
260 delta_f2_f1_size : INTEGER;
263 ENABLE_FILTER : STD_LOGIC);
261 ENABLE_FILTER : STD_LOGIC);
264 PORT (
262 PORT (
265 cnv_clk : IN STD_LOGIC;
263 cnv_clk : IN STD_LOGIC;
266 cnv_rstn : IN STD_LOGIC;
264 cnv_rstn : IN STD_LOGIC;
267 sample_B : IN Samples14v(2 DOWNTO 0);
265 sample_B : IN Samples14v(2 DOWNTO 0);
268 sample_E : IN Samples14v(4 DOWNTO 0);
266 sample_E : IN Samples14v(4 DOWNTO 0);
269 sample_val : IN STD_LOGIC;
267 sample_val : IN STD_LOGIC;
270 HCLK : IN STD_ULOGIC;
268 HCLK : IN STD_ULOGIC;
271 HRESETn : IN STD_ULOGIC;
269 HRESETn : IN STD_ULOGIC;
272 apbi : IN apb_slv_in_type;
270 apbi : IN apb_slv_in_type;
273 apbo : OUT apb_slv_out_type;
271 apbo : OUT apb_slv_out_type;
274 AHB_Master_In : IN AHB_Mst_In_Type;
272 AHB_Master_In : IN AHB_Mst_In_Type;
275 AHB_Master_Out : OUT AHB_Mst_Out_Type;
273 AHB_Master_Out : OUT AHB_Mst_Out_Type;
276 coarse_time_0 : IN STD_LOGIC;
274 coarse_time_0 : IN STD_LOGIC;
277 data_shaping_BW : OUT STD_LOGIC);
275 data_shaping_BW : OUT STD_LOGIC);
278 END COMPONENT;
276 END COMPONENT;
279
277
280 END lpp_top_lfr_pkg;
278 END lpp_top_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,342 +1,342
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
12
13 LIBRARY techmap;
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
14 USE techmap.gencomp.ALL;
15
15
16 LIBRARY grlib;
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
21
22 ENTITY lpp_top_lfr_wf_picker IS
22 ENTITY lpp_top_lfr_wf_picker IS
23 GENERIC (
23 GENERIC (
24 hindex : INTEGER := 2;
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 15;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 15;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 15;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
35 ENABLE_FILTER : STD_LOGIC := '1'
35 ENABLE_FILTER : STD_LOGIC := '1'
36 );
36 );
37 PORT (
37 PORT (
38 -- ADS7886
38 -- ADS7886
39 cnv_run : IN STD_LOGIC;
39 cnv_run : IN STD_LOGIC;
40 cnv : OUT STD_LOGIC;
40 cnv : OUT STD_LOGIC;
41 sck : OUT STD_LOGIC;
41 sck : OUT STD_LOGIC;
42 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
42 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
43 --
43 --
44 cnv_clk : IN STD_LOGIC;
44 cnv_clk : IN STD_LOGIC;
45 cnv_rstn : IN STD_LOGIC;
45 cnv_rstn : IN STD_LOGIC;
46
46
47 -- AMBA AHB system signals
47 -- AMBA AHB system signals
48 HCLK : IN STD_ULOGIC;
48 HCLK : IN STD_ULOGIC;
49 HRESETn : IN STD_ULOGIC;
49 HRESETn : IN STD_ULOGIC;
50
50
51 -- AMBA APB Slave Interface
51 -- AMBA APB Slave Interface
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 --
59 --
60 coarse_time_0 : IN STD_LOGIC;
60 coarse_time_0 : IN STD_LOGIC;
61
61
62 --
62 --
63 data_shaping_BW : OUT STD_LOGIC
63 data_shaping_BW : OUT STD_LOGIC
64 );
64 );
65 END lpp_top_lfr_wf_picker;
65 END lpp_top_lfr_wf_picker;
66
66
67 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
67 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
68
68
69 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
69 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
70 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
70 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
71 SIGNAL ready_matrix_f1 : STD_LOGIC;
71 SIGNAL ready_matrix_f1 : STD_LOGIC;
72 SIGNAL ready_matrix_f2 : STD_LOGIC;
72 SIGNAL ready_matrix_f2 : STD_LOGIC;
73 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
73 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
74 SIGNAL error_bad_component_error : STD_LOGIC;
74 SIGNAL error_bad_component_error : STD_LOGIC;
75 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
76 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
79 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
79 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
80 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
80 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
81 SIGNAL status_error_bad_component_error : STD_LOGIC;
81 SIGNAL status_error_bad_component_error : STD_LOGIC;
82 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
82 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
83 SIGNAL config_active_interruption_onError : STD_LOGIC;
83 SIGNAL config_active_interruption_onError : STD_LOGIC;
84 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
88
88
89 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
93 SIGNAL data_shaping_SP0 : STD_LOGIC;
93 SIGNAL data_shaping_SP0 : STD_LOGIC;
94 SIGNAL data_shaping_SP1 : STD_LOGIC;
94 SIGNAL data_shaping_SP1 : STD_LOGIC;
95 SIGNAL data_shaping_R0 : STD_LOGIC;
95 SIGNAL data_shaping_R0 : STD_LOGIC;
96 SIGNAL data_shaping_R1 : STD_LOGIC;
96 SIGNAL data_shaping_R1 : STD_LOGIC;
97 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
97 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
99 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
99 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
100 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
100 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
101 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
101 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
102 SIGNAL enable_f0 : STD_LOGIC;
102 SIGNAL enable_f0 : STD_LOGIC;
103 SIGNAL enable_f1 : STD_LOGIC;
103 SIGNAL enable_f1 : STD_LOGIC;
104 SIGNAL enable_f2 : STD_LOGIC;
104 SIGNAL enable_f2 : STD_LOGIC;
105 SIGNAL enable_f3 : STD_LOGIC;
105 SIGNAL enable_f3 : STD_LOGIC;
106 SIGNAL burst_f0 : STD_LOGIC;
106 SIGNAL burst_f0 : STD_LOGIC;
107 SIGNAL burst_f1 : STD_LOGIC;
107 SIGNAL burst_f1 : STD_LOGIC;
108 SIGNAL burst_f2 : STD_LOGIC;
108 SIGNAL burst_f2 : STD_LOGIC;
109 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113
113
114 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
114 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
120 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
121 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
121 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
122
122
123 CONSTANT ChanelCount : INTEGER := 8;
123 CONSTANT ChanelCount : INTEGER := 8;
124 CONSTANT ncycle_cnv_high : INTEGER := 40;
124 CONSTANT ncycle_cnv_high : INTEGER := 40;
125 CONSTANT ncycle_cnv : INTEGER := 250;
125 CONSTANT ncycle_cnv : INTEGER := 250;
126 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
127 SIGNAL sample_val : STD_LOGIC;
127 SIGNAL sample_val : STD_LOGIC;
128
128
129 BEGIN
129 BEGIN
130
130
131 ready_matrix_f0_0 <= '0';
131 ready_matrix_f0_0 <= '0';
132 ready_matrix_f0_1 <= '0';
132 ready_matrix_f0_1 <= '0';
133 ready_matrix_f1 <= '0';
133 ready_matrix_f1 <= '0';
134 ready_matrix_f2 <= '0';
134 ready_matrix_f2 <= '0';
135 error_anticipating_empty_fifo <= '0';
135 error_anticipating_empty_fifo <= '0';
136 error_bad_component_error <= '0';
136 error_bad_component_error <= '0';
137 debug_reg <= (OTHERS => '0');
137 debug_reg <= (OTHERS => '0');
138
138
139 lpp_top_apbreg_1 : lpp_top_apbreg
139 lpp_top_apbreg_1 : lpp_top_apbreg
140 GENERIC MAP (
140 GENERIC MAP (
141 nb_burst_available_size => nb_burst_available_size,
141 nb_burst_available_size => nb_burst_available_size,
142 nb_snapshot_param_size => nb_snapshot_param_size,
142 nb_snapshot_param_size => nb_snapshot_param_size,
143 delta_snapshot_size => delta_snapshot_size,
143 delta_snapshot_size => delta_snapshot_size,
144 delta_f2_f0_size => delta_f2_f0_size,
144 delta_f2_f0_size => delta_f2_f0_size,
145 delta_f2_f1_size => delta_f2_f1_size,
145 delta_f2_f1_size => delta_f2_f1_size,
146 pindex => pindex,
146 pindex => pindex,
147 paddr => paddr,
147 paddr => paddr,
148 pmask => pmask,
148 pmask => pmask,
149 pirq => pirq)
149 pirq => pirq)
150 PORT MAP (
150 PORT MAP (
151 HCLK => HCLK,
151 HCLK => HCLK,
152 HRESETn => HRESETn,
152 HRESETn => HRESETn,
153 apbi => apbi,
153 apbi => apbi,
154 apbo => apbo,
154 apbo => apbo,
155
155
156 ready_matrix_f0_0 => ready_matrix_f0_0,
156 ready_matrix_f0_0 => ready_matrix_f0_0,
157 ready_matrix_f0_1 => ready_matrix_f0_1,
157 ready_matrix_f0_1 => ready_matrix_f0_1,
158 ready_matrix_f1 => ready_matrix_f1,
158 ready_matrix_f1 => ready_matrix_f1,
159 ready_matrix_f2 => ready_matrix_f2,
159 ready_matrix_f2 => ready_matrix_f2,
160 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
160 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
161 error_bad_component_error => error_bad_component_error,
161 error_bad_component_error => error_bad_component_error,
162 debug_reg => debug_reg,
162 debug_reg => debug_reg,
163 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
163 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
164 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
164 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
165 status_ready_matrix_f1 => status_ready_matrix_f1,
165 status_ready_matrix_f1 => status_ready_matrix_f1,
166 status_ready_matrix_f2 => status_ready_matrix_f2,
166 status_ready_matrix_f2 => status_ready_matrix_f2,
167 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
167 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
168 status_error_bad_component_error => status_error_bad_component_error,
168 status_error_bad_component_error => status_error_bad_component_error,
169 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
169 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
170 config_active_interruption_onError => config_active_interruption_onError,
170 config_active_interruption_onError => config_active_interruption_onError,
171 addr_matrix_f0_0 => addr_matrix_f0_0,
171 addr_matrix_f0_0 => addr_matrix_f0_0,
172 addr_matrix_f0_1 => addr_matrix_f0_1,
172 addr_matrix_f0_1 => addr_matrix_f0_1,
173 addr_matrix_f1 => addr_matrix_f1,
173 addr_matrix_f1 => addr_matrix_f1,
174 addr_matrix_f2 => addr_matrix_f2,
174 addr_matrix_f2 => addr_matrix_f2,
175
175
176 status_full => status_full,
176 status_full => status_full,
177 status_full_ack => status_full_ack,
177 status_full_ack => status_full_ack,
178 status_full_err => status_full_err,
178 status_full_err => status_full_err,
179 status_new_err => status_new_err,
179 status_new_err => status_new_err,
180 data_shaping_BW => data_shaping_BW,
180 data_shaping_BW => data_shaping_BW,
181 data_shaping_SP0 => data_shaping_SP0,
181 data_shaping_SP0 => data_shaping_SP0,
182 data_shaping_SP1 => data_shaping_SP1,
182 data_shaping_SP1 => data_shaping_SP1,
183 data_shaping_R0 => data_shaping_R0,
183 data_shaping_R0 => data_shaping_R0,
184 data_shaping_R1 => data_shaping_R1,
184 data_shaping_R1 => data_shaping_R1,
185 delta_snapshot => delta_snapshot,
185 delta_snapshot => delta_snapshot,
186 delta_f2_f1 => delta_f2_f1,
186 delta_f2_f1 => delta_f2_f1,
187 delta_f2_f0 => delta_f2_f0,
187 delta_f2_f0 => delta_f2_f0,
188 nb_burst_available => nb_burst_available,
188 nb_burst_available => nb_burst_available,
189 nb_snapshot_param => nb_snapshot_param,
189 nb_snapshot_param => nb_snapshot_param,
190 enable_f0 => enable_f0,
190 enable_f0 => enable_f0,
191 enable_f1 => enable_f1,
191 enable_f1 => enable_f1,
192 enable_f2 => enable_f2,
192 enable_f2 => enable_f2,
193 enable_f3 => enable_f3,
193 enable_f3 => enable_f3,
194 burst_f0 => burst_f0,
194 burst_f0 => burst_f0,
195 burst_f1 => burst_f1,
195 burst_f1 => burst_f1,
196 burst_f2 => burst_f2,
196 burst_f2 => burst_f2,
197 addr_data_f0 => addr_data_f0,
197 addr_data_f0 => addr_data_f0,
198 addr_data_f1 => addr_data_f1,
198 addr_data_f1 => addr_data_f1,
199 addr_data_f2 => addr_data_f2,
199 addr_data_f2 => addr_data_f2,
200 addr_data_f3 => addr_data_f3);
200 addr_data_f3 => addr_data_f3);
201
201
202
202
203
203
204
204
205 DIGITAL_acquisition : AD7688_drvr_sync
205 DIGITAL_acquisition : AD7688_drvr_sync
206 GENERIC MAP (
206 GENERIC MAP (
207 ChanelCount => ChanelCount,
207 ChanelCount => ChanelCount,
208 ncycle_cnv_high => ncycle_cnv_high,
208 ncycle_cnv_high => ncycle_cnv_high,
209 ncycle_cnv => ncycle_cnv)
209 ncycle_cnv => ncycle_cnv)
210 PORT MAP (
210 PORT MAP (
211 cnv_clk => cnv_clk, --
211 cnv_clk => cnv_clk, --
212 cnv_rstn => cnv_rstn, --
212 cnv_rstn => cnv_rstn, --
213 cnv_run => cnv_run, --
213 cnv_run => cnv_run, --
214 cnv => cnv, --
214 cnv => cnv, --
215 sck => sck, --
215 sck => sck, --
216 sdo => sdo(ChanelCount-1 DOWNTO 0), --
216 sdo => sdo(ChanelCount-1 DOWNTO 0), --
217 sample => sample,
217 sample => sample,
218 sample_val => sample_val);
218 sample_val => sample_val);
219
219
220
220
221 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
221 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
222
222
223 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
223 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
224 GENERIC MAP (
224 GENERIC MAP (
225 hindex => hindex,
225 hindex => hindex,
226 nb_burst_available_size => nb_burst_available_size,
226 nb_burst_available_size => nb_burst_available_size,
227 nb_snapshot_param_size => nb_snapshot_param_size,
227 nb_snapshot_param_size => nb_snapshot_param_size,
228 delta_snapshot_size => delta_snapshot_size,
228 delta_snapshot_size => delta_snapshot_size,
229 delta_f2_f0_size => delta_f2_f0_size,
229 delta_f2_f0_size => delta_f2_f0_size,
230 delta_f2_f1_size => delta_f2_f1_size,
230 delta_f2_f1_size => delta_f2_f1_size,
231 tech => tech,
231 tech => tech,
232 Mem_use => lpp.iir_filter.use_RAM
232 Mem_use => lpp.iir_filter.use_RAM
233 )
233 )
234 PORT MAP (
234 PORT MAP (
235 sample => sample,
235 sample => sample,
236 sample_val => sample_val,
236 sample_val => sample_val,
237
237
238 cnv_clk => cnv_clk,
238 -- cnv_clk => cnv_clk,
239 cnv_rstn => cnv_rstn,
239 -- cnv_rstn => cnv_rstn,
240
240
241 clk => HCLK,
241 clk => HCLK,
242 rstn => HRESETn,
242 rstn => HRESETn,
243
243
244 sample_f0_wen => sample_f0_wen,
244 sample_f0_wen => sample_f0_wen,
245 sample_f0_wdata => sample_f0_wdata,
245 sample_f0_wdata => sample_f0_wdata,
246 sample_f1_wen => sample_f1_wen,
246 sample_f1_wen => sample_f1_wen,
247 sample_f1_wdata => sample_f1_wdata,
247 sample_f1_wdata => sample_f1_wdata,
248 sample_f2_wen => sample_f2_wen,
248 sample_f2_wen => sample_f2_wen,
249 sample_f2_wdata => sample_f2_wdata,
249 sample_f2_wdata => sample_f2_wdata,
250 sample_f3_wen => sample_f3_wen,
250 sample_f3_wen => sample_f3_wen,
251 sample_f3_wdata => sample_f3_wdata,
251 sample_f3_wdata => sample_f3_wdata,
252 AHB_Master_In => AHB_Master_In,
252 AHB_Master_In => AHB_Master_In,
253 AHB_Master_Out => AHB_Master_Out,
253 AHB_Master_Out => AHB_Master_Out,
254 coarse_time_0 => coarse_time_0,
254 coarse_time_0 => coarse_time_0,
255 data_shaping_SP0 => data_shaping_SP0,
255 data_shaping_SP0 => data_shaping_SP0,
256 data_shaping_SP1 => data_shaping_SP1,
256 data_shaping_SP1 => data_shaping_SP1,
257 data_shaping_R0 => data_shaping_R0,
257 data_shaping_R0 => data_shaping_R0,
258 data_shaping_R1 => data_shaping_R1,
258 data_shaping_R1 => data_shaping_R1,
259 delta_snapshot => delta_snapshot,
259 delta_snapshot => delta_snapshot,
260 delta_f2_f1 => delta_f2_f1,
260 delta_f2_f1 => delta_f2_f1,
261 delta_f2_f0 => delta_f2_f0,
261 delta_f2_f0 => delta_f2_f0,
262 enable_f0 => enable_f0,
262 enable_f0 => enable_f0,
263 enable_f1 => enable_f1,
263 enable_f1 => enable_f1,
264 enable_f2 => enable_f2,
264 enable_f2 => enable_f2,
265 enable_f3 => enable_f3,
265 enable_f3 => enable_f3,
266 burst_f0 => burst_f0,
266 burst_f0 => burst_f0,
267 burst_f1 => burst_f1,
267 burst_f1 => burst_f1,
268 burst_f2 => burst_f2,
268 burst_f2 => burst_f2,
269 nb_burst_available => nb_burst_available,
269 nb_burst_available => nb_burst_available,
270 nb_snapshot_param => nb_snapshot_param,
270 nb_snapshot_param => nb_snapshot_param,
271 status_full => status_full,
271 status_full => status_full,
272 status_full_ack => status_full_ack,
272 status_full_ack => status_full_ack,
273 status_full_err => status_full_err,
273 status_full_err => status_full_err,
274 status_new_err => status_new_err,
274 status_new_err => status_new_err,
275 addr_data_f0 => addr_data_f0,
275 addr_data_f0 => addr_data_f0,
276 addr_data_f1 => addr_data_f1,
276 addr_data_f1 => addr_data_f1,
277 addr_data_f2 => addr_data_f2,
277 addr_data_f2 => addr_data_f2,
278 addr_data_f3 => addr_data_f3);
278 addr_data_f3 => addr_data_f3);
279
279
280 END GENERATE wf_picker_with_filter;
280 END GENERATE wf_picker_with_filter;
281
281
282
282
283 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
283 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
284
284
285 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
285 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
286 GENERIC MAP (
286 GENERIC MAP (
287 hindex => hindex,
287 hindex => hindex,
288 nb_burst_available_size => nb_burst_available_size,
288 nb_burst_available_size => nb_burst_available_size,
289 nb_snapshot_param_size => nb_snapshot_param_size,
289 nb_snapshot_param_size => nb_snapshot_param_size,
290 delta_snapshot_size => delta_snapshot_size,
290 delta_snapshot_size => delta_snapshot_size,
291 delta_f2_f0_size => delta_f2_f0_size,
291 delta_f2_f0_size => delta_f2_f0_size,
292 delta_f2_f1_size => delta_f2_f1_size,
292 delta_f2_f1_size => delta_f2_f1_size,
293 tech => tech
293 tech => tech
294 )
294 )
295 PORT MAP (
295 PORT MAP (
296 sample => sample,
296 sample => sample,
297 sample_val => sample_val,
297 sample_val => sample_val,
298
298
299 cnv_clk => cnv_clk,
299 cnv_clk => cnv_clk,
300 cnv_rstn => cnv_rstn,
300 cnv_rstn => cnv_rstn,
301
301
302 clk => HCLK,
302 clk => HCLK,
303 rstn => HRESETn,
303 rstn => HRESETn,
304
304
305 sample_f0_wen => sample_f0_wen,
305 sample_f0_wen => sample_f0_wen,
306 sample_f0_wdata => sample_f0_wdata,
306 sample_f0_wdata => sample_f0_wdata,
307 sample_f1_wen => sample_f1_wen,
307 sample_f1_wen => sample_f1_wen,
308 sample_f1_wdata => sample_f1_wdata,
308 sample_f1_wdata => sample_f1_wdata,
309 sample_f2_wen => sample_f2_wen,
309 sample_f2_wen => sample_f2_wen,
310 sample_f2_wdata => sample_f2_wdata,
310 sample_f2_wdata => sample_f2_wdata,
311 sample_f3_wen => sample_f3_wen,
311 sample_f3_wen => sample_f3_wen,
312 sample_f3_wdata => sample_f3_wdata,
312 sample_f3_wdata => sample_f3_wdata,
313 AHB_Master_In => AHB_Master_In,
313 AHB_Master_In => AHB_Master_In,
314 AHB_Master_Out => AHB_Master_Out,
314 AHB_Master_Out => AHB_Master_Out,
315 coarse_time_0 => coarse_time_0,
315 coarse_time_0 => coarse_time_0,
316 data_shaping_SP0 => data_shaping_SP0,
316 data_shaping_SP0 => data_shaping_SP0,
317 data_shaping_SP1 => data_shaping_SP1,
317 data_shaping_SP1 => data_shaping_SP1,
318 data_shaping_R0 => data_shaping_R0,
318 data_shaping_R0 => data_shaping_R0,
319 data_shaping_R1 => data_shaping_R1,
319 data_shaping_R1 => data_shaping_R1,
320 delta_snapshot => delta_snapshot,
320 delta_snapshot => delta_snapshot,
321 delta_f2_f1 => delta_f2_f1,
321 delta_f2_f1 => delta_f2_f1,
322 delta_f2_f0 => delta_f2_f0,
322 delta_f2_f0 => delta_f2_f0,
323 enable_f0 => enable_f0,
323 enable_f0 => enable_f0,
324 enable_f1 => enable_f1,
324 enable_f1 => enable_f1,
325 enable_f2 => enable_f2,
325 enable_f2 => enable_f2,
326 enable_f3 => enable_f3,
326 enable_f3 => enable_f3,
327 burst_f0 => burst_f0,
327 burst_f0 => burst_f0,
328 burst_f1 => burst_f1,
328 burst_f1 => burst_f1,
329 burst_f2 => burst_f2,
329 burst_f2 => burst_f2,
330 nb_burst_available => nb_burst_available,
330 nb_burst_available => nb_burst_available,
331 nb_snapshot_param => nb_snapshot_param,
331 nb_snapshot_param => nb_snapshot_param,
332 status_full => status_full,
332 status_full => status_full,
333 status_full_ack => status_full_ack,
333 status_full_ack => status_full_ack,
334 status_full_err => status_full_err,
334 status_full_err => status_full_err,
335 status_new_err => status_new_err,
335 status_new_err => status_new_err,
336 addr_data_f0 => addr_data_f0,
336 addr_data_f0 => addr_data_f0,
337 addr_data_f1 => addr_data_f1,
337 addr_data_f1 => addr_data_f1,
338 addr_data_f2 => addr_data_f2,
338 addr_data_f2 => addr_data_f2,
339 addr_data_f3 => addr_data_f3);
339 addr_data_f3 => addr_data_f3);
340
340
341 END GENERATE wf_picker_without_filter;
341 END GENERATE wf_picker_without_filter;
342 END tb;
342 END tb;
Show file before | Show file after | Hide comments
@@ -1,587 +1,579
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.general_purpose.SYNC_FF;
11 USE lpp.general_purpose.SYNC_FF;
12
12
13 LIBRARY techmap;
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
14 USE techmap.gencomp.ALL;
15
15
16 LIBRARY grlib;
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
21
22 ENTITY lpp_top_lfr_wf_picker_ip IS
22 ENTITY lpp_top_lfr_wf_picker_ip IS
23 GENERIC(
23 GENERIC(
24 hindex : INTEGER := 2;
24 hindex : INTEGER := 2;
25 nb_burst_available_size : INTEGER := 11;
25 nb_burst_available_size : INTEGER := 11;
26 nb_snapshot_param_size : INTEGER := 11;
26 nb_snapshot_param_size : INTEGER := 11;
27 delta_snapshot_size : INTEGER := 16;
27 delta_snapshot_size : INTEGER := 16;
28 delta_f2_f0_size : INTEGER := 10;
28 delta_f2_f0_size : INTEGER := 10;
29 delta_f2_f1_size : INTEGER := 10;
29 delta_f2_f1_size : INTEGER := 10;
30 tech : INTEGER := 0;
30 tech : INTEGER := 0;
31 Mem_use : INTEGER := use_RAM
31 Mem_use : INTEGER := use_RAM
32 );
32 );
33 PORT (
33 PORT (
34 -- ADS7886
35 -- cnv_run : IN STD_LOGIC;
36 -- cnv : OUT STD_LOGIC;
37 -- sck : OUT STD_LOGIC;
38 -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
39 sample : IN Samples(7 DOWNTO 0);
34 sample : IN Samples(7 DOWNTO 0);
40 sample_val : IN STD_LOGIC;
35 sample_val : IN STD_LOGIC;
41 --
36 --
42 cnv_clk : IN STD_LOGIC;
43 cnv_rstn : IN STD_LOGIC;
44 --
45 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
47 --
39 --
48 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
40 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
49 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
41 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
50 --
42 --
51 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
43 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
52 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
44 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
53 --
45 --
54 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
46 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
55 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
47 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
56 --
48 --
57 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
49 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
58 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
50 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
59
51
60 -- AMBA AHB Master Interface
52 -- AMBA AHB Master Interface
61 AHB_Master_In : IN AHB_Mst_In_Type;
53 AHB_Master_In : IN AHB_Mst_In_Type;
62 AHB_Master_Out : OUT AHB_Mst_Out_Type;
54 AHB_Master_Out : OUT AHB_Mst_Out_Type;
63
55
64 coarse_time_0 : IN STD_LOGIC;
56 coarse_time_0 : IN STD_LOGIC;
65
57
66 --config
58 --config
67 data_shaping_SP0 : IN STD_LOGIC;
59 data_shaping_SP0 : IN STD_LOGIC;
68 data_shaping_SP1 : IN STD_LOGIC;
60 data_shaping_SP1 : IN STD_LOGIC;
69 data_shaping_R0 : IN STD_LOGIC;
61 data_shaping_R0 : IN STD_LOGIC;
70 data_shaping_R1 : IN STD_LOGIC;
62 data_shaping_R1 : IN STD_LOGIC;
71
63
72 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
64 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
73 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
65 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
74 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
66 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
75
67
76 enable_f0 : IN STD_LOGIC;
68 enable_f0 : IN STD_LOGIC;
77 enable_f1 : IN STD_LOGIC;
69 enable_f1 : IN STD_LOGIC;
78 enable_f2 : IN STD_LOGIC;
70 enable_f2 : IN STD_LOGIC;
79 enable_f3 : IN STD_LOGIC;
71 enable_f3 : IN STD_LOGIC;
80
72
81 burst_f0 : IN STD_LOGIC;
73 burst_f0 : IN STD_LOGIC;
82 burst_f1 : IN STD_LOGIC;
74 burst_f1 : IN STD_LOGIC;
83 burst_f2 : IN STD_LOGIC;
75 burst_f2 : IN STD_LOGIC;
84
76
85 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
77 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
86 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
87 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
91
83
92 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
95 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
87 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
96 );
88 );
97 END lpp_top_lfr_wf_picker_ip;
89 END lpp_top_lfr_wf_picker_ip;
98
90
99 ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
91 ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
100
92
101 COMPONENT Downsampling
93 COMPONENT Downsampling
102 GENERIC (
94 GENERIC (
103 ChanelCount : INTEGER;
95 ChanelCount : INTEGER;
104 SampleSize : INTEGER;
96 SampleSize : INTEGER;
105 DivideParam : INTEGER);
97 DivideParam : INTEGER);
106 PORT (
98 PORT (
107 clk : IN STD_LOGIC;
99 clk : IN STD_LOGIC;
108 rstn : IN STD_LOGIC;
100 rstn : IN STD_LOGIC;
109 sample_in_val : IN STD_LOGIC;
101 sample_in_val : IN STD_LOGIC;
110 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
102 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
111 sample_out_val : OUT STD_LOGIC;
103 sample_out_val : OUT STD_LOGIC;
112 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
104 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
113 END COMPONENT;
105 END COMPONENT;
114
106
115 COMPONENT SYNC_FF
107 COMPONENT SYNC_FF
116 GENERIC (
108 GENERIC (
117 NB_FF_OF_SYNC : INTEGER);
109 NB_FF_OF_SYNC : INTEGER);
118 PORT (
110 PORT (
119 clk : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
112 rstn : IN STD_LOGIC;
121 A : IN STD_LOGIC;
113 A : IN STD_LOGIC;
122 A_sync : OUT STD_LOGIC);
114 A_sync : OUT STD_LOGIC);
123 END COMPONENT;
115 END COMPONENT;
124
116
125 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
126 CONSTANT ChanelCount : INTEGER := 8;
118 CONSTANT ChanelCount : INTEGER := 8;
127
119
128 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
129 SIGNAL sample_val_delay : STD_LOGIC;
121 SIGNAL sample_val_delay : STD_LOGIC;
130 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
131 CONSTANT Coef_SZ : INTEGER := 9;
123 CONSTANT Coef_SZ : INTEGER := 9;
132 CONSTANT CoefCntPerCel : INTEGER := 6;
124 CONSTANT CoefCntPerCel : INTEGER := 6;
133 CONSTANT CoefPerCel : INTEGER := 5;
125 CONSTANT CoefPerCel : INTEGER := 5;
134 CONSTANT Cels_count : INTEGER := 5;
126 CONSTANT Cels_count : INTEGER := 5;
135
127
136 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
128 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
137 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
129 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
138 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
130 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
139 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
131 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
140 --
132 --
141 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
133 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
142 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
134 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
143 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
144 SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 --SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
145
137
146 SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
138 --SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
147 SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
139 --SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
148 SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
140 --SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
149 SIGNAL only_one_hot : STD_LOGIC;
141 --SIGNAL only_one_hot : STD_LOGIC;
150 SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
142 --SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
151 SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
143 --SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
152 SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
144 --SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
153 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
154 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
146 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
155 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
147 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
156 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
148 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
157 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
149 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
158 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
150 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
159 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
151 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
160 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
152 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
161 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
162 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
154 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
163 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
155 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
164 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
165 SIGNAL sample_f0_val : STD_LOGIC;
157 SIGNAL sample_f0_val : STD_LOGIC;
166 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
158 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
167 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
159 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
168 --
160 --
169 SIGNAL sample_f1_val : STD_LOGIC;
161 SIGNAL sample_f1_val : STD_LOGIC;
170 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
162 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
171 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
163 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
172 --
164 --
173 SIGNAL sample_f2_val : STD_LOGIC;
165 SIGNAL sample_f2_val : STD_LOGIC;
174 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
166 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
175 --
167 --
176 SIGNAL sample_f3_val : STD_LOGIC;
168 SIGNAL sample_f3_val : STD_LOGIC;
177 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
169 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
178
170
179 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
180 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
172 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
181 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
173 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
182 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
174 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
183 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
175 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
184 -----------------------------------------------------------------------------
176 -----------------------------------------------------------------------------
185
177
186 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
178 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
187 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
179 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
188 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
180 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
189 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
181 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
190 BEGIN
182 BEGIN
191
183
192 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
193 PROCESS (cnv_clk, cnv_rstn)
185 PROCESS (clk, rstn)
194 BEGIN -- PROCESS
186 BEGIN -- PROCESS
195 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
187 IF rstn = '0' THEN -- asynchronous reset (active low)
196 sample_val_delay <= '0';
188 sample_val_delay <= '0';
197 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
189 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 sample_val_delay <= sample_val;
190 sample_val_delay <= sample_val;
199 END IF;
191 END IF;
200 END PROCESS;
192 END PROCESS;
201
193
202 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
203 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
195 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
204 SampleLoop : FOR j IN 0 TO 15 GENERATE
196 SampleLoop : FOR j IN 0 TO 15 GENERATE
205 sample_filter_in(i, j) <= sample(i)(j);
197 sample_filter_in(i, j) <= sample(i)(j);
206 END GENERATE;
198 END GENERATE;
207
199
208 sample_filter_in(i, 16) <= sample(i)(15);
200 sample_filter_in(i, 16) <= sample(i)(15);
209 sample_filter_in(i, 17) <= sample(i)(15);
201 sample_filter_in(i, 17) <= sample(i)(15);
210 END GENERATE;
202 END GENERATE;
211
203
212 coefs_v2 <= CoefsInitValCst_v2;
204 coefs_v2 <= CoefsInitValCst_v2;
213
205
214 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
206 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 GENERIC MAP (
207 GENERIC MAP (
216 tech => 0,
208 tech => 0,
217 Mem_use => Mem_use, -- use_RAM
209 Mem_use => Mem_use, -- use_RAM
218 Sample_SZ => 18,
210 Sample_SZ => 18,
219 Coef_SZ => Coef_SZ,
211 Coef_SZ => Coef_SZ,
220 Coef_Nb => 25,
212 Coef_Nb => 25,
221 Coef_sel_SZ => 5,
213 Coef_sel_SZ => 5,
222 Cels_count => Cels_count,
214 Cels_count => Cels_count,
223 ChanelsCount => ChanelCount)
215 ChanelsCount => ChanelCount)
224 PORT MAP (
216 PORT MAP (
225 rstn => cnv_rstn,
217 rstn => rstn,
226 clk => cnv_clk,
218 clk => clk,
227 virg_pos => 7,
219 virg_pos => 7,
228 coefs => coefs_v2,
220 coefs => coefs_v2,
229 sample_in_val => sample_val_delay,
221 sample_in_val => sample_val_delay,
230 sample_in => sample_filter_in,
222 sample_in => sample_filter_in,
231 sample_out_val => sample_filter_v2_out_val,
223 sample_out_val => sample_filter_v2_out_val,
232 sample_out => sample_filter_v2_out);
224 sample_out => sample_filter_v2_out);
233
225
234
226
235 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
236 -- RESYNC STAGE
228 -- RESYNC STAGE
237 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
238
230
239 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
231 --all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
240 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
232 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
241 PROCESS (cnv_clk, cnv_rstn)
233 -- PROCESS (cnv_clk, cnv_rstn)
242 BEGIN -- PROCESS
234 -- BEGIN -- PROCESS
243 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
235 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
244 sample_filter_v2_out_reg(I, J) <= '0';
236 -- sample_filter_v2_out_reg(I, J) <= '0';
245 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
237 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
246 IF sample_filter_v2_out_val = '1' THEN
238 -- IF sample_filter_v2_out_val = '1' THEN
247 sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
239 -- sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
248 END IF;
240 -- END IF;
249 END IF;
241 -- END IF;
250 END PROCESS;
242 -- END PROCESS;
251 END GENERATE all_data_reg;
243 -- END GENERATE all_data_reg;
252 END GENERATE all_sample_reg;
244 --END GENERATE all_sample_reg;
253
245
254 PROCESS (cnv_clk, cnv_rstn)
246 --PROCESS (cnv_clk, cnv_rstn)
255 BEGIN -- PROCESS
247 --BEGIN -- PROCESS
256 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
248 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
257 sample_filter_v2_out_reg_val <= '0';
249 -- sample_filter_v2_out_reg_val <= '0';
258 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
250 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
259 IF sample_filter_v2_out_val = '1' THEN
251 -- IF sample_filter_v2_out_val = '1' THEN
260 sample_filter_v2_out_reg_val <= '1';
252 -- sample_filter_v2_out_reg_val <= '1';
261 ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
253 -- ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
262 sample_filter_v2_out_reg_val <= '0';
254 -- sample_filter_v2_out_reg_val <= '0';
263 END IF;
255 -- END IF;
264 END IF;
256 -- END IF;
265 END PROCESS;
257 --END PROCESS;
266
258
267 SYNC_FF_1 : SYNC_FF
259 --SYNC_FF_1 : SYNC_FF
268 GENERIC MAP (
260 -- GENERIC MAP (
269 NB_FF_OF_SYNC => 2)
261 -- NB_FF_OF_SYNC => 2)
270 PORT MAP (
262 -- PORT MAP (
271 clk => clk,
263 -- clk => clk,
272 rstn => rstn,
264 -- rstn => rstn,
273 A => sample_filter_v2_out_reg_val,
265 -- A => sample_filter_v2_out_reg_val,
274 A_sync => sample_filter_v2_out_reg_val_s);
266 -- A_sync => sample_filter_v2_out_reg_val_s);
275
267
276 SYNC_FF_2 : SYNC_FF
268 --SYNC_FF_2 : SYNC_FF
277 GENERIC MAP (
269 -- GENERIC MAP (
278 NB_FF_OF_SYNC => 2)
270 -- NB_FF_OF_SYNC => 2)
279 PORT MAP (
271 -- PORT MAP (
280 clk => cnv_clk,
272 -- clk => cnv_clk,
281 rstn => cnv_rstn,
273 -- rstn => cnv_rstn,
282 A => sample_filter_v2_out_reg_val_s,
274 -- A => sample_filter_v2_out_reg_val_s,
283 A_sync => sample_filter_v2_out_reg_val_s2);
275 -- A_sync => sample_filter_v2_out_reg_val_s2);
284
276
285
277
286 PROCESS (clk, rstn)
278 --PROCESS (clk, rstn)
287 BEGIN -- PROCESS
279 --BEGIN -- PROCESS
288 IF rstn = '0' THEN -- asynchronous reset (active low)
280 -- IF rstn = '0' THEN -- asynchronous reset (active low)
289 sample_filter_v2_out_sync_val_t <= '0';
281 -- sample_filter_v2_out_sync_val_t <= '0';
290 sample_filter_v2_out_sync_val <= '0';
282 -- sample_filter_v2_out_sync_val <= '0';
291 only_one_hot <= '0';
283 -- only_one_hot <= '0';
292 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
284 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
293 sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
285 -- sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
294 only_one_hot <= sample_filter_v2_out_reg_val_s;
286 -- only_one_hot <= sample_filter_v2_out_reg_val_s;
295 sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
287 -- sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
296 END IF;
288 -- END IF;
297 END PROCESS;
289 --END PROCESS;
298
290
299
291
300 all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
292 --all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
301 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
293 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
302 PROCESS (clk, cnv_rstn)
294 -- PROCESS (clk, cnv_rstn)
303 BEGIN -- PROCESS
295 -- BEGIN -- PROCESS
304 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
296 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
305 sample_filter_v2_out_sync(I,J) <= '0';
297 -- sample_filter_v2_out_sync(I,J) <= '0';
306 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
298 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
307 IF sample_filter_v2_out_sync_val_t = '1' THEN
299 -- IF sample_filter_v2_out_sync_val_t = '1' THEN
308 sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
300 -- sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
309 END IF;
301 -- END IF;
310 END IF;
302 -- END IF;
311 END PROCESS;
303 -- END PROCESS;
312 END GENERATE all_data_reg;
304 -- END GENERATE all_data_reg;
313 END GENERATE all_sample_reg2;
305 --END GENERATE all_sample_reg2;
314
306
315
307
316 -----------------------------------------------------------------------------
308 -----------------------------------------------------------------------------
317 -- DATA_SHAPING
309 -- DATA_SHAPING
318 -----------------------------------------------------------------------------
310 -----------------------------------------------------------------------------
319 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
311 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
320 sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
312 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
321 sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
313 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
322 sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
314 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
323 END GENERATE all_data_shaping_in_loop;
315 END GENERATE all_data_shaping_in_loop;
324
316
325 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
317 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
326 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
318 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
327
319
328 PROCESS (clk, rstn)
320 PROCESS (clk, rstn)
329 BEGIN -- PROCESS
321 BEGIN -- PROCESS
330 IF rstn = '0' THEN -- asynchronous reset (active low)
322 IF rstn = '0' THEN -- asynchronous reset (active low)
331 sample_data_shaping_out_val <= '0';
323 sample_data_shaping_out_val <= '0';
332 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
324 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
333 sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
325 sample_data_shaping_out_val <= sample_filter_v2_out_val;
334 END IF;
326 END IF;
335 END PROCESS;
327 END PROCESS;
336
328
337 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
329 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
338 PROCESS (clk, rstn)
330 PROCESS (clk, rstn)
339 BEGIN
331 BEGIN
340 IF rstn = '0' THEN
332 IF rstn = '0' THEN
341 sample_data_shaping_out(0, j) <= '0';
333 sample_data_shaping_out(0, j) <= '0';
342 sample_data_shaping_out(1, j) <= '0';
334 sample_data_shaping_out(1, j) <= '0';
343 sample_data_shaping_out(2, j) <= '0';
335 sample_data_shaping_out(2, j) <= '0';
344 sample_data_shaping_out(3, j) <= '0';
336 sample_data_shaping_out(3, j) <= '0';
345 sample_data_shaping_out(4, j) <= '0';
337 sample_data_shaping_out(4, j) <= '0';
346 sample_data_shaping_out(5, j) <= '0';
338 sample_data_shaping_out(5, j) <= '0';
347 sample_data_shaping_out(6, j) <= '0';
339 sample_data_shaping_out(6, j) <= '0';
348 sample_data_shaping_out(7, j) <= '0';
340 sample_data_shaping_out(7, j) <= '0';
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
341 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
342 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
351 IF data_shaping_SP0 = '1' THEN
343 IF data_shaping_SP0 = '1' THEN
352 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
344 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
353 ELSE
345 ELSE
354 sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
346 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
355 END IF;
347 END IF;
356 IF data_shaping_SP1 = '1' THEN
348 IF data_shaping_SP1 = '1' THEN
357 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
349 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
358 ELSE
350 ELSE
359 sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
351 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
360 END IF;
352 END IF;
361 sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
353 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
362 sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
354 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
363 sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
355 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
364 sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
356 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
365 sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
357 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
366 END IF;
358 END IF;
367 END PROCESS;
359 END PROCESS;
368 END GENERATE;
360 END GENERATE;
369
361
370 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
362 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
371 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
363 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
372 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
364 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
373 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
365 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
374 END GENERATE;
366 END GENERATE;
375 END GENERATE;
367 END GENERATE;
376 -----------------------------------------------------------------------------
368 -----------------------------------------------------------------------------
377 -- F0 -- @24.576 kHz
369 -- F0 -- @24.576 kHz
378 -----------------------------------------------------------------------------
370 -----------------------------------------------------------------------------
379 Downsampling_f0 : Downsampling
371 Downsampling_f0 : Downsampling
380 GENERIC MAP (
372 GENERIC MAP (
381 ChanelCount => 8,
373 ChanelCount => 8,
382 SampleSize => 16,
374 SampleSize => 16,
383 DivideParam => 4)
375 DivideParam => 4)
384 PORT MAP (
376 PORT MAP (
385 clk => clk,
377 clk => clk,
386 rstn => rstn,
378 rstn => rstn,
387 sample_in_val => sample_filter_v2_out_val_s,
379 sample_in_val => sample_filter_v2_out_val_s,
388 sample_in => sample_filter_v2_out_s,
380 sample_in => sample_filter_v2_out_s,
389 sample_out_val => sample_f0_val,
381 sample_out_val => sample_f0_val,
390 sample_out => sample_f0);
382 sample_out => sample_f0);
391
383
392 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
384 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
393 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
385 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
394 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
386 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
395 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
387 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
396 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
388 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
397 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
389 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
398 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
390 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
399 END GENERATE all_bit_sample_f0;
391 END GENERATE all_bit_sample_f0;
400
392
401 sample_f0_wen <= NOT(sample_f0_val) &
393 sample_f0_wen <= NOT(sample_f0_val) &
402 NOT(sample_f0_val) &
394 NOT(sample_f0_val) &
403 NOT(sample_f0_val) &
395 NOT(sample_f0_val) &
404 NOT(sample_f0_val) &
396 NOT(sample_f0_val) &
405 NOT(sample_f0_val) &
397 NOT(sample_f0_val) &
406 NOT(sample_f0_val);
398 NOT(sample_f0_val);
407
399
408 -----------------------------------------------------------------------------
400 -----------------------------------------------------------------------------
409 -- F1 -- @4096 Hz
401 -- F1 -- @4096 Hz
410 -----------------------------------------------------------------------------
402 -----------------------------------------------------------------------------
411 Downsampling_f1 : Downsampling
403 Downsampling_f1 : Downsampling
412 GENERIC MAP (
404 GENERIC MAP (
413 ChanelCount => 8,
405 ChanelCount => 8,
414 SampleSize => 16,
406 SampleSize => 16,
415 DivideParam => 6)
407 DivideParam => 6)
416 PORT MAP (
408 PORT MAP (
417 clk => clk,
409 clk => clk,
418 rstn => rstn,
410 rstn => rstn,
419 sample_in_val => sample_f0_val ,
411 sample_in_val => sample_f0_val ,
420 sample_in => sample_f0,
412 sample_in => sample_f0,
421 sample_out_val => sample_f1_val,
413 sample_out_val => sample_f1_val,
422 sample_out => sample_f1);
414 sample_out => sample_f1);
423
415
424 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
416 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
425 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
417 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
426 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
418 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
427 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
419 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
428 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
420 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
429 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
421 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
430 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
422 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
431 END GENERATE all_bit_sample_f1;
423 END GENERATE all_bit_sample_f1;
432
424
433 sample_f1_wen <= NOT(sample_f1_val) &
425 sample_f1_wen <= NOT(sample_f1_val) &
434 NOT(sample_f1_val) &
426 NOT(sample_f1_val) &
435 NOT(sample_f1_val) &
427 NOT(sample_f1_val) &
436 NOT(sample_f1_val) &
428 NOT(sample_f1_val) &
437 NOT(sample_f1_val) &
429 NOT(sample_f1_val) &
438 NOT(sample_f1_val);
430 NOT(sample_f1_val);
439
431
440 -----------------------------------------------------------------------------
432 -----------------------------------------------------------------------------
441 -- F2 -- @256 Hz
433 -- F2 -- @256 Hz
442 -----------------------------------------------------------------------------
434 -----------------------------------------------------------------------------
443 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
435 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
444 sample_f0_s(0, I) <= sample_f0(0, I); -- V
436 sample_f0_s(0, I) <= sample_f0(0, I); -- V
445 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
437 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
446 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
438 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
447 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
439 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
448 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
440 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
449 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
441 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
450 END GENERATE all_bit_sample_f0_s;
442 END GENERATE all_bit_sample_f0_s;
451
443
452 Downsampling_f2 : Downsampling
444 Downsampling_f2 : Downsampling
453 GENERIC MAP (
445 GENERIC MAP (
454 ChanelCount => 6,
446 ChanelCount => 6,
455 SampleSize => 16,
447 SampleSize => 16,
456 DivideParam => 96)
448 DivideParam => 96)
457 PORT MAP (
449 PORT MAP (
458 clk => clk,
450 clk => clk,
459 rstn => rstn,
451 rstn => rstn,
460 sample_in_val => sample_f0_val ,
452 sample_in_val => sample_f0_val ,
461 sample_in => sample_f0_s,
453 sample_in => sample_f0_s,
462 sample_out_val => sample_f2_val,
454 sample_out_val => sample_f2_val,
463 sample_out => sample_f2);
455 sample_out => sample_f2);
464
456
465 sample_f2_wen <= NOT(sample_f2_val) &
457 sample_f2_wen <= NOT(sample_f2_val) &
466 NOT(sample_f2_val) &
458 NOT(sample_f2_val) &
467 NOT(sample_f2_val) &
459 NOT(sample_f2_val) &
468 NOT(sample_f2_val) &
460 NOT(sample_f2_val) &
469 NOT(sample_f2_val) &
461 NOT(sample_f2_val) &
470 NOT(sample_f2_val);
462 NOT(sample_f2_val);
471
463
472 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
464 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
473 sample_f2_wdata_s(I) <= sample_f2(0, I);
465 sample_f2_wdata_s(I) <= sample_f2(0, I);
474 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
466 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
475 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
467 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
476 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
468 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
477 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
469 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
478 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
470 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
479 END GENERATE all_bit_sample_f2;
471 END GENERATE all_bit_sample_f2;
480
472
481 -----------------------------------------------------------------------------
473 -----------------------------------------------------------------------------
482 -- F3 -- @16 Hz
474 -- F3 -- @16 Hz
483 -----------------------------------------------------------------------------
475 -----------------------------------------------------------------------------
484 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
476 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
485 sample_f1_s(0, I) <= sample_f1(0, I); -- V
477 sample_f1_s(0, I) <= sample_f1(0, I); -- V
486 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
478 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
487 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
479 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
488 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
480 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
489 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
481 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
490 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
482 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
491 END GENERATE all_bit_sample_f1_s;
483 END GENERATE all_bit_sample_f1_s;
492
484
493 Downsampling_f3 : Downsampling
485 Downsampling_f3 : Downsampling
494 GENERIC MAP (
486 GENERIC MAP (
495 ChanelCount => 6,
487 ChanelCount => 6,
496 SampleSize => 16,
488 SampleSize => 16,
497 DivideParam => 256)
489 DivideParam => 256)
498 PORT MAP (
490 PORT MAP (
499 clk => clk,
491 clk => clk,
500 rstn => rstn,
492 rstn => rstn,
501 sample_in_val => sample_f1_val ,
493 sample_in_val => sample_f1_val ,
502 sample_in => sample_f1_s,
494 sample_in => sample_f1_s,
503 sample_out_val => sample_f3_val,
495 sample_out_val => sample_f3_val,
504 sample_out => sample_f3);
496 sample_out => sample_f3);
505
497
506 sample_f3_wen <= (NOT sample_f3_val) &
498 sample_f3_wen <= (NOT sample_f3_val) &
507 (NOT sample_f3_val) &
499 (NOT sample_f3_val) &
508 (NOT sample_f3_val) &
500 (NOT sample_f3_val) &
509 (NOT sample_f3_val) &
501 (NOT sample_f3_val) &
510 (NOT sample_f3_val) &
502 (NOT sample_f3_val) &
511 (NOT sample_f3_val);
503 (NOT sample_f3_val);
512
504
513 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
505 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
514 sample_f3_wdata_s(I) <= sample_f3(0, I);
506 sample_f3_wdata_s(I) <= sample_f3(0, I);
515 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
507 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
516 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
508 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
517 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
509 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
518 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
510 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
519 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
511 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
520 END GENERATE all_bit_sample_f3;
512 END GENERATE all_bit_sample_f3;
521
513
522 lpp_waveform_1 : lpp_waveform
514 lpp_waveform_1 : lpp_waveform
523 GENERIC MAP (
515 GENERIC MAP (
524 hindex => hindex,
516 hindex => hindex,
525 tech => tech,
517 tech => tech,
526 data_size => 160,
518 data_size => 160,
527 nb_burst_available_size => nb_burst_available_size,
519 nb_burst_available_size => nb_burst_available_size,
528 nb_snapshot_param_size => nb_snapshot_param_size,
520 nb_snapshot_param_size => nb_snapshot_param_size,
529 delta_snapshot_size => delta_snapshot_size,
521 delta_snapshot_size => delta_snapshot_size,
530 delta_f2_f0_size => delta_f2_f0_size,
522 delta_f2_f0_size => delta_f2_f0_size,
531 delta_f2_f1_size => delta_f2_f1_size)
523 delta_f2_f1_size => delta_f2_f1_size)
532 PORT MAP (
524 PORT MAP (
533 clk => clk,
525 clk => clk,
534 rstn => rstn,
526 rstn => rstn,
535
527
536 AHB_Master_In => AHB_Master_In,
528 AHB_Master_In => AHB_Master_In,
537 AHB_Master_Out => AHB_Master_Out,
529 AHB_Master_Out => AHB_Master_Out,
538
530
539 coarse_time_0 => coarse_time_0, -- IN
531 coarse_time_0 => coarse_time_0, -- IN
540 delta_snapshot => delta_snapshot, -- IN
532 delta_snapshot => delta_snapshot, -- IN
541 delta_f2_f1 => delta_f2_f1, -- IN
533 delta_f2_f1 => delta_f2_f1, -- IN
542 delta_f2_f0 => delta_f2_f0, -- IN
534 delta_f2_f0 => delta_f2_f0, -- IN
543 enable_f0 => enable_f0, -- IN
535 enable_f0 => enable_f0, -- IN
544 enable_f1 => enable_f1, -- IN
536 enable_f1 => enable_f1, -- IN
545 enable_f2 => enable_f2, -- IN
537 enable_f2 => enable_f2, -- IN
546 enable_f3 => enable_f3, -- IN
538 enable_f3 => enable_f3, -- IN
547 burst_f0 => burst_f0, -- IN
539 burst_f0 => burst_f0, -- IN
548 burst_f1 => burst_f1, -- IN
540 burst_f1 => burst_f1, -- IN
549 burst_f2 => burst_f2, -- IN
541 burst_f2 => burst_f2, -- IN
550 nb_burst_available => nb_burst_available,
542 nb_burst_available => nb_burst_available,
551 nb_snapshot_param => nb_snapshot_param,
543 nb_snapshot_param => nb_snapshot_param,
552 status_full => status_full,
544 status_full => status_full,
553 status_full_ack => status_full_ack, -- IN
545 status_full_ack => status_full_ack, -- IN
554 status_full_err => status_full_err,
546 status_full_err => status_full_err,
555 status_new_err => status_new_err,
547 status_new_err => status_new_err,
556
548
557 addr_data_f0 => addr_data_f0, -- IN
549 addr_data_f0 => addr_data_f0, -- IN
558 addr_data_f1 => addr_data_f1, -- IN
550 addr_data_f1 => addr_data_f1, -- IN
559 addr_data_f2 => addr_data_f2, -- IN
551 addr_data_f2 => addr_data_f2, -- IN
560 addr_data_f3 => addr_data_f3, -- IN
552 addr_data_f3 => addr_data_f3, -- IN
561
553
562 data_f0_in => data_f0_in_valid,
554 data_f0_in => data_f0_in_valid,
563 data_f1_in => data_f1_in_valid,
555 data_f1_in => data_f1_in_valid,
564 data_f2_in => data_f2_in_valid,
556 data_f2_in => data_f2_in_valid,
565 data_f3_in => data_f3_in_valid,
557 data_f3_in => data_f3_in_valid,
566
558
567 data_f0_in_valid => sample_f0_val,
559 data_f0_in_valid => sample_f0_val,
568 data_f1_in_valid => sample_f1_val,
560 data_f1_in_valid => sample_f1_val,
569 data_f2_in_valid => sample_f2_val,
561 data_f2_in_valid => sample_f2_val,
570 data_f3_in_valid => sample_f3_val);
562 data_f3_in_valid => sample_f3_val);
571
563
572 data_f0_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
564 data_f0_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
573 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
565 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
574 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
566 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
575 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
567 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
576
568
577 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
569 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
578 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
570 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
579 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
571 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
580 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
572 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
581
573
582 sample_f0_wdata <= sample_f0_wdata_s;
574 sample_f0_wdata <= sample_f0_wdata_s;
583 sample_f1_wdata <= sample_f1_wdata_s;
575 sample_f1_wdata <= sample_f1_wdata_s;
584 sample_f2_wdata <= sample_f2_wdata_s;
576 sample_f2_wdata <= sample_f2_wdata_s;
585 sample_f3_wdata <= sample_f3_wdata_s;
577 sample_f3_wdata <= sample_f3_wdata_s;
586
578
587 END tb;
579 END tb;
Show file before | Show file after | Hide comments
@@ -1,349 +1,349
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
12
13 LIBRARY techmap;
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
14 USE techmap.gencomp.ALL;
15
15
16 LIBRARY grlib;
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
21
22 ENTITY top_wf_picker IS
22 ENTITY top_wf_picker IS
23 GENERIC (
23 GENERIC (
24 hindex : INTEGER := 2;
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 15;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 15;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 15;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
35 ENABLE_FILTER : STD_LOGIC := '1'
35 ENABLE_FILTER : STD_LOGIC := '1'
36 );
36 );
37 PORT (
37 PORT (
38 cnv_clk : IN STD_LOGIC;
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
40 --
41 sample_B : IN Samples14v(2 DOWNTO 0);
41 sample_B : IN Samples14v(2 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
43 sample_val : IN STD_LOGIC;
43 sample_val : IN STD_LOGIC;
44
44
45 -- AMBA AHB system signals
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
48
49 -- AMBA APB Slave Interface
49 -- AMBA APB Slave Interface
50 apbi : IN apb_slv_in_type;
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
51 apbo : OUT apb_slv_out_type;
52
52
53 -- AMBA AHB Master Interface
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
56
57 --
57 --
58 coarse_time_0 : IN STD_LOGIC;
58 coarse_time_0 : IN STD_LOGIC;
59
59
60 --
60 --
61 data_shaping_BW : OUT STD_LOGIC
61 data_shaping_BW : OUT STD_LOGIC
62 );
62 );
63 END top_wf_picker;
63 END top_wf_picker;
64
64
65 ARCHITECTURE tb OF top_wf_picker IS
65 ARCHITECTURE tb OF top_wf_picker IS
66
66
67 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
67 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f1 : STD_LOGIC;
69 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f2 : STD_LOGIC;
70 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
71 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_bad_component_error : STD_LOGIC;
72 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
74 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
78 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_bad_component_error : STD_LOGIC;
79 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
80 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onError : STD_LOGIC;
81 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
82 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL data_shaping_SP0 : STD_LOGIC;
91 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP1 : STD_LOGIC;
92 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_R0 : STD_LOGIC;
93 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R1 : STD_LOGIC;
94 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
95 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
96 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
98 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
99 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL enable_f0 : STD_LOGIC;
100 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f1 : STD_LOGIC;
101 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f2 : STD_LOGIC;
102 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f3 : STD_LOGIC;
103 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL burst_f0 : STD_LOGIC;
104 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f1 : STD_LOGIC;
105 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f2 : STD_LOGIC;
106 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111
111
112 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
112 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
113 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
114 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
116 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
120
121 CONSTANT ChanelCount : INTEGER := 8;
121 CONSTANT ChanelCount : INTEGER := 8;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
123 CONSTANT ncycle_cnv : INTEGER := 250;
123 CONSTANT ncycle_cnv : INTEGER := 250;
124
124
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
127
127
128 BEGIN
128 BEGIN
129
129
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
132
132
133
133
134 ready_matrix_f0_0 <= '0';
134 ready_matrix_f0_0 <= '0';
135 ready_matrix_f0_1 <= '0';
135 ready_matrix_f0_1 <= '0';
136 ready_matrix_f1 <= '0';
136 ready_matrix_f1 <= '0';
137 ready_matrix_f2 <= '0';
137 ready_matrix_f2 <= '0';
138 error_anticipating_empty_fifo <= '0';
138 error_anticipating_empty_fifo <= '0';
139 error_bad_component_error <= '0';
139 error_bad_component_error <= '0';
140 debug_reg <= (OTHERS => '0');
140 debug_reg <= (OTHERS => '0');
141
141
142 lpp_top_apbreg_1 : lpp_top_apbreg
142 lpp_top_apbreg_1 : lpp_top_apbreg
143 GENERIC MAP (
143 GENERIC MAP (
144 nb_burst_available_size => nb_burst_available_size,
144 nb_burst_available_size => nb_burst_available_size,
145 nb_snapshot_param_size => nb_snapshot_param_size,
145 nb_snapshot_param_size => nb_snapshot_param_size,
146 delta_snapshot_size => delta_snapshot_size,
146 delta_snapshot_size => delta_snapshot_size,
147 delta_f2_f0_size => delta_f2_f0_size,
147 delta_f2_f0_size => delta_f2_f0_size,
148 delta_f2_f1_size => delta_f2_f1_size,
148 delta_f2_f1_size => delta_f2_f1_size,
149 pindex => pindex,
149 pindex => pindex,
150 paddr => paddr,
150 paddr => paddr,
151 pmask => pmask,
151 pmask => pmask,
152 pirq => pirq)
152 pirq => pirq)
153 PORT MAP (
153 PORT MAP (
154 HCLK => HCLK,
154 HCLK => HCLK,
155 HRESETn => HRESETn,
155 HRESETn => HRESETn,
156 apbi => apbi,
156 apbi => apbi,
157 apbo => apbo,
157 apbo => apbo,
158
158
159 ready_matrix_f0_0 => ready_matrix_f0_0,
159 ready_matrix_f0_0 => ready_matrix_f0_0,
160 ready_matrix_f0_1 => ready_matrix_f0_1,
160 ready_matrix_f0_1 => ready_matrix_f0_1,
161 ready_matrix_f1 => ready_matrix_f1,
161 ready_matrix_f1 => ready_matrix_f1,
162 ready_matrix_f2 => ready_matrix_f2,
162 ready_matrix_f2 => ready_matrix_f2,
163 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
163 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
164 error_bad_component_error => error_bad_component_error,
164 error_bad_component_error => error_bad_component_error,
165 debug_reg => debug_reg,
165 debug_reg => debug_reg,
166 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
166 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
167 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
167 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
168 status_ready_matrix_f1 => status_ready_matrix_f1,
168 status_ready_matrix_f1 => status_ready_matrix_f1,
169 status_ready_matrix_f2 => status_ready_matrix_f2,
169 status_ready_matrix_f2 => status_ready_matrix_f2,
170 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
170 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
171 status_error_bad_component_error => status_error_bad_component_error,
171 status_error_bad_component_error => status_error_bad_component_error,
172 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
172 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
173 config_active_interruption_onError => config_active_interruption_onError,
173 config_active_interruption_onError => config_active_interruption_onError,
174 addr_matrix_f0_0 => addr_matrix_f0_0,
174 addr_matrix_f0_0 => addr_matrix_f0_0,
175 addr_matrix_f0_1 => addr_matrix_f0_1,
175 addr_matrix_f0_1 => addr_matrix_f0_1,
176 addr_matrix_f1 => addr_matrix_f1,
176 addr_matrix_f1 => addr_matrix_f1,
177 addr_matrix_f2 => addr_matrix_f2,
177 addr_matrix_f2 => addr_matrix_f2,
178
178
179 status_full => status_full,
179 status_full => status_full,
180 status_full_ack => status_full_ack,
180 status_full_ack => status_full_ack,
181 status_full_err => status_full_err,
181 status_full_err => status_full_err,
182 status_new_err => status_new_err,
182 status_new_err => status_new_err,
183 data_shaping_BW => data_shaping_BW,
183 data_shaping_BW => data_shaping_BW,
184 data_shaping_SP0 => data_shaping_SP0,
184 data_shaping_SP0 => data_shaping_SP0,
185 data_shaping_SP1 => data_shaping_SP1,
185 data_shaping_SP1 => data_shaping_SP1,
186 data_shaping_R0 => data_shaping_R0,
186 data_shaping_R0 => data_shaping_R0,
187 data_shaping_R1 => data_shaping_R1,
187 data_shaping_R1 => data_shaping_R1,
188 delta_snapshot => delta_snapshot,
188 delta_snapshot => delta_snapshot,
189 delta_f2_f1 => delta_f2_f1,
189 delta_f2_f1 => delta_f2_f1,
190 delta_f2_f0 => delta_f2_f0,
190 delta_f2_f0 => delta_f2_f0,
191 nb_burst_available => nb_burst_available,
191 nb_burst_available => nb_burst_available,
192 nb_snapshot_param => nb_snapshot_param,
192 nb_snapshot_param => nb_snapshot_param,
193 enable_f0 => enable_f0,
193 enable_f0 => enable_f0,
194 enable_f1 => enable_f1,
194 enable_f1 => enable_f1,
195 enable_f2 => enable_f2,
195 enable_f2 => enable_f2,
196 enable_f3 => enable_f3,
196 enable_f3 => enable_f3,
197 burst_f0 => burst_f0,
197 burst_f0 => burst_f0,
198 burst_f1 => burst_f1,
198 burst_f1 => burst_f1,
199 burst_f2 => burst_f2,
199 burst_f2 => burst_f2,
200 addr_data_f0 => addr_data_f0,
200 addr_data_f0 => addr_data_f0,
201 addr_data_f1 => addr_data_f1,
201 addr_data_f1 => addr_data_f1,
202 addr_data_f2 => addr_data_f2,
202 addr_data_f2 => addr_data_f2,
203 addr_data_f3 => addr_data_f3);
203 addr_data_f3 => addr_data_f3);
204
204
205
205
206
206
207
207
208 --DIGITAL_acquisition : AD7688_drvr_sync
208 --DIGITAL_acquisition : AD7688_drvr_sync
209 -- GENERIC MAP (
209 -- GENERIC MAP (
210 -- ChanelCount => ChanelCount,
210 -- ChanelCount => ChanelCount,
211 -- ncycle_cnv_high => ncycle_cnv_high,
211 -- ncycle_cnv_high => ncycle_cnv_high,
212 -- ncycle_cnv => ncycle_cnv)
212 -- ncycle_cnv => ncycle_cnv)
213 -- PORT MAP (
213 -- PORT MAP (
214 -- cnv_clk => cnv_clk, --
214 -- cnv_clk => cnv_clk, --
215 -- cnv_rstn => cnv_rstn, --
215 -- cnv_rstn => cnv_rstn, --
216 -- cnv_run => cnv_run, --
216 -- cnv_run => cnv_run, --
217 -- cnv => cnv, --
217 -- cnv => cnv, --
218 -- sck => sck, --
218 -- sck => sck, --
219 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
219 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
220 -- sample => sample,
220 -- sample => sample,
221 -- sample_val => sample_val);
221 -- sample_val => sample_val);
222
222
223 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
223 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
224 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
224 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
225 END GENERATE all_channel;
225 END GENERATE all_channel;
226
226
227
227
228 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
228 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
229
229
230 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
230 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
231 GENERIC MAP (
231 GENERIC MAP (
232 hindex => hindex,
232 hindex => hindex,
233 nb_burst_available_size => nb_burst_available_size,
233 nb_burst_available_size => nb_burst_available_size,
234 nb_snapshot_param_size => nb_snapshot_param_size,
234 nb_snapshot_param_size => nb_snapshot_param_size,
235 delta_snapshot_size => delta_snapshot_size,
235 delta_snapshot_size => delta_snapshot_size,
236 delta_f2_f0_size => delta_f2_f0_size,
236 delta_f2_f0_size => delta_f2_f0_size,
237 delta_f2_f1_size => delta_f2_f1_size,
237 delta_f2_f1_size => delta_f2_f1_size,
238 tech => tech,
238 tech => tech,
239 Mem_use => use_RAM
239 Mem_use => use_RAM
240 )
240 )
241 PORT MAP (
241 PORT MAP (
242 sample => sample_s,
242 sample => sample_s,
243 sample_val => sample_val,
243 sample_val => sample_val,
244
244
245 cnv_clk => HCLK,--cnv_clk,
245 -- cnv_clk => HCLK,--cnv_clk,
246 cnv_rstn => HRESETn,--cnv_rstn,
246 -- cnv_rstn => HRESETn,--cnv_rstn,
247
247
248 clk => HCLK,
248 clk => HCLK,
249 rstn => HRESETn,
249 rstn => HRESETn,
250
250
251 sample_f0_wen => sample_f0_wen,
251 sample_f0_wen => sample_f0_wen,
252 sample_f0_wdata => sample_f0_wdata,
252 sample_f0_wdata => sample_f0_wdata,
253 sample_f1_wen => sample_f1_wen,
253 sample_f1_wen => sample_f1_wen,
254 sample_f1_wdata => sample_f1_wdata,
254 sample_f1_wdata => sample_f1_wdata,
255 sample_f2_wen => sample_f2_wen,
255 sample_f2_wen => sample_f2_wen,
256 sample_f2_wdata => sample_f2_wdata,
256 sample_f2_wdata => sample_f2_wdata,
257 sample_f3_wen => sample_f3_wen,
257 sample_f3_wen => sample_f3_wen,
258 sample_f3_wdata => sample_f3_wdata,
258 sample_f3_wdata => sample_f3_wdata,
259 AHB_Master_In => AHB_Master_In,
259 AHB_Master_In => AHB_Master_In,
260 AHB_Master_Out => AHB_Master_Out,
260 AHB_Master_Out => AHB_Master_Out,
261 coarse_time_0 => coarse_time_0,
261 coarse_time_0 => coarse_time_0,
262 data_shaping_SP0 => data_shaping_SP0,
262 data_shaping_SP0 => data_shaping_SP0,
263 data_shaping_SP1 => data_shaping_SP1,
263 data_shaping_SP1 => data_shaping_SP1,
264 data_shaping_R0 => data_shaping_R0,
264 data_shaping_R0 => data_shaping_R0,
265 data_shaping_R1 => data_shaping_R1,
265 data_shaping_R1 => data_shaping_R1,
266 delta_snapshot => delta_snapshot,
266 delta_snapshot => delta_snapshot,
267 delta_f2_f1 => delta_f2_f1,
267 delta_f2_f1 => delta_f2_f1,
268 delta_f2_f0 => delta_f2_f0,
268 delta_f2_f0 => delta_f2_f0,
269 enable_f0 => enable_f0,
269 enable_f0 => enable_f0,
270 enable_f1 => enable_f1,
270 enable_f1 => enable_f1,
271 enable_f2 => enable_f2,
271 enable_f2 => enable_f2,
272 enable_f3 => enable_f3,
272 enable_f3 => enable_f3,
273 burst_f0 => burst_f0,
273 burst_f0 => burst_f0,
274 burst_f1 => burst_f1,
274 burst_f1 => burst_f1,
275 burst_f2 => burst_f2,
275 burst_f2 => burst_f2,
276 nb_burst_available => nb_burst_available,
276 nb_burst_available => nb_burst_available,
277 nb_snapshot_param => nb_snapshot_param,
277 nb_snapshot_param => nb_snapshot_param,
278 status_full => status_full,
278 status_full => status_full,
279 status_full_ack => status_full_ack,
279 status_full_ack => status_full_ack,
280 status_full_err => status_full_err,
280 status_full_err => status_full_err,
281 status_new_err => status_new_err,
281 status_new_err => status_new_err,
282 addr_data_f0 => addr_data_f0,
282 addr_data_f0 => addr_data_f0,
283 addr_data_f1 => addr_data_f1,
283 addr_data_f1 => addr_data_f1,
284 addr_data_f2 => addr_data_f2,
284 addr_data_f2 => addr_data_f2,
285 addr_data_f3 => addr_data_f3);
285 addr_data_f3 => addr_data_f3);
286
286
287 END GENERATE wf_picker_with_filter;
287 END GENERATE wf_picker_with_filter;
288
288
289
289
290 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
290 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
291
291
292 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
292 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
293 GENERIC MAP (
293 GENERIC MAP (
294 hindex => hindex,
294 hindex => hindex,
295 nb_burst_available_size => nb_burst_available_size,
295 nb_burst_available_size => nb_burst_available_size,
296 nb_snapshot_param_size => nb_snapshot_param_size,
296 nb_snapshot_param_size => nb_snapshot_param_size,
297 delta_snapshot_size => delta_snapshot_size,
297 delta_snapshot_size => delta_snapshot_size,
298 delta_f2_f0_size => delta_f2_f0_size,
298 delta_f2_f0_size => delta_f2_f0_size,
299 delta_f2_f1_size => delta_f2_f1_size,
299 delta_f2_f1_size => delta_f2_f1_size,
300 tech => tech
300 tech => tech
301 )
301 )
302 PORT MAP (
302 PORT MAP (
303 sample => sample_s,
303 sample => sample_s,
304 sample_val => sample_val,
304 sample_val => sample_val,
305
305
306 cnv_clk => cnv_clk,
306 cnv_clk => cnv_clk,
307 cnv_rstn => cnv_rstn,
307 cnv_rstn => cnv_rstn,
308
308
309 clk => HCLK,
309 clk => HCLK,
310 rstn => HRESETn,
310 rstn => HRESETn,
311
311
312 sample_f0_wen => sample_f0_wen,
312 sample_f0_wen => sample_f0_wen,
313 sample_f0_wdata => sample_f0_wdata,
313 sample_f0_wdata => sample_f0_wdata,
314 sample_f1_wen => sample_f1_wen,
314 sample_f1_wen => sample_f1_wen,
315 sample_f1_wdata => sample_f1_wdata,
315 sample_f1_wdata => sample_f1_wdata,
316 sample_f2_wen => sample_f2_wen,
316 sample_f2_wen => sample_f2_wen,
317 sample_f2_wdata => sample_f2_wdata,
317 sample_f2_wdata => sample_f2_wdata,
318 sample_f3_wen => sample_f3_wen,
318 sample_f3_wen => sample_f3_wen,
319 sample_f3_wdata => sample_f3_wdata,
319 sample_f3_wdata => sample_f3_wdata,
320 AHB_Master_In => AHB_Master_In,
320 AHB_Master_In => AHB_Master_In,
321 AHB_Master_Out => AHB_Master_Out,
321 AHB_Master_Out => AHB_Master_Out,
322 coarse_time_0 => coarse_time_0,
322 coarse_time_0 => coarse_time_0,
323 data_shaping_SP0 => data_shaping_SP0,
323 data_shaping_SP0 => data_shaping_SP0,
324 data_shaping_SP1 => data_shaping_SP1,
324 data_shaping_SP1 => data_shaping_SP1,
325 data_shaping_R0 => data_shaping_R0,
325 data_shaping_R0 => data_shaping_R0,
326 data_shaping_R1 => data_shaping_R1,
326 data_shaping_R1 => data_shaping_R1,
327 delta_snapshot => delta_snapshot,
327 delta_snapshot => delta_snapshot,
328 delta_f2_f1 => delta_f2_f1,
328 delta_f2_f1 => delta_f2_f1,
329 delta_f2_f0 => delta_f2_f0,
329 delta_f2_f0 => delta_f2_f0,
330 enable_f0 => enable_f0,
330 enable_f0 => enable_f0,
331 enable_f1 => enable_f1,
331 enable_f1 => enable_f1,
332 enable_f2 => enable_f2,
332 enable_f2 => enable_f2,
333 enable_f3 => enable_f3,
333 enable_f3 => enable_f3,
334 burst_f0 => burst_f0,
334 burst_f0 => burst_f0,
335 burst_f1 => burst_f1,
335 burst_f1 => burst_f1,
336 burst_f2 => burst_f2,
336 burst_f2 => burst_f2,
337 nb_burst_available => nb_burst_available,
337 nb_burst_available => nb_burst_available,
338 nb_snapshot_param => nb_snapshot_param,
338 nb_snapshot_param => nb_snapshot_param,
339 status_full => status_full,
339 status_full => status_full,
340 status_full_ack => status_full_ack,
340 status_full_ack => status_full_ack,
341 status_full_err => status_full_err,
341 status_full_err => status_full_err,
342 status_new_err => status_new_err,
342 status_new_err => status_new_err,
343 addr_data_f0 => addr_data_f0,
343 addr_data_f0 => addr_data_f0,
344 addr_data_f1 => addr_data_f1,
344 addr_data_f1 => addr_data_f1,
345 addr_data_f2 => addr_data_f2,
345 addr_data_f2 => addr_data_f2,
346 addr_data_f3 => addr_data_f3);
346 addr_data_f3 => addr_data_f3);
347
347
348 END GENERATE wf_picker_without_filter;
348 END GENERATE wf_picker_without_filter;
349 END tb;
349 END tb; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,277 +1,276
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY grlib;
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
7 USE grlib.stdlib.ALL;
8 USE grlib.devices.ALL;
8 USE grlib.devices.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
9 USE GRLIB.DMA2AHB_Package.ALL;
10
10
11 LIBRARY lpp;
11 LIBRARY lpp;
12 USE lpp.lpp_waveform_pkg.ALL;
12 USE lpp.lpp_waveform_pkg.ALL;
13
13
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 ENTITY lpp_waveform IS
17 ENTITY lpp_waveform IS
18
18
19 GENERIC (
19 GENERIC (
20 hindex : INTEGER := 2;
20 hindex : INTEGER := 2;
21 tech : INTEGER := inferred;
21 tech : INTEGER := inferred;
22 data_size : INTEGER := 160;
22 data_size : INTEGER := 160;
23 nb_burst_available_size : INTEGER := 11;
23 nb_burst_available_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
25 delta_snapshot_size : INTEGER := 16;
25 delta_snapshot_size : INTEGER := 16;
26 delta_f2_f0_size : INTEGER := 10;
26 delta_f2_f0_size : INTEGER := 10;
27 delta_f2_f1_size : INTEGER := 10);
27 delta_f2_f1_size : INTEGER := 10);
28
28
29 PORT (
29 PORT (
30 clk : IN STD_LOGIC;
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32
32
33 -- AMBA AHB Master Interface
33 -- AMBA AHB Master Interface
34 AHB_Master_In : IN AHB_Mst_In_Type;
34 AHB_Master_In : IN AHB_Mst_In_Type;
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
36
36
37 coarse_time_0 : IN STD_LOGIC;
37 coarse_time_0 : IN STD_LOGIC;
38
38
39 --config
39 --config
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
43
43
44 enable_f0 : IN STD_LOGIC;
44 enable_f0 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
47 enable_f3 : IN STD_LOGIC;
48
48
49 burst_f0 : IN STD_LOGIC;
49 burst_f0 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
50 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
52
52
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63
63
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
68
68
69 data_f0_in_valid : IN STD_LOGIC;
69 data_f0_in_valid : IN STD_LOGIC;
70 data_f1_in_valid : IN STD_LOGIC;
70 data_f1_in_valid : IN STD_LOGIC;
71 data_f2_in_valid : IN STD_LOGIC;
71 data_f2_in_valid : IN STD_LOGIC;
72 data_f3_in_valid : IN STD_LOGIC
72 data_f3_in_valid : IN STD_LOGIC
73 );
73 );
74
74
75 END lpp_waveform;
75 END lpp_waveform;
76
76
77 ARCHITECTURE beh OF lpp_waveform IS
77 ARCHITECTURE beh OF lpp_waveform IS
78 SIGNAL start_snapshot_f0 : STD_LOGIC;
78 SIGNAL start_snapshot_f0 : STD_LOGIC;
79 SIGNAL start_snapshot_f1 : STD_LOGIC;
79 SIGNAL start_snapshot_f1 : STD_LOGIC;
80 SIGNAL start_snapshot_f2 : STD_LOGIC;
80 SIGNAL start_snapshot_f2 : STD_LOGIC;
81
81
82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86
86
87 SIGNAL data_f0_out_valid : STD_LOGIC;
87 SIGNAL data_f0_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
92
92
93 --
93 --
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --
102 --
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
106
106
107 BEGIN -- beh
107 BEGIN -- beh
108
108
109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
110 GENERIC MAP (
110 GENERIC MAP (
111 delta_snapshot_size => delta_snapshot_size,
111 delta_snapshot_size => delta_snapshot_size,
112 delta_f2_f0_size => delta_f2_f0_size,
112 delta_f2_f0_size => delta_f2_f0_size,
113 delta_f2_f1_size => delta_f2_f1_size)
113 delta_f2_f1_size => delta_f2_f1_size)
114 PORT MAP (
114 PORT MAP (
115 clk => clk,
115 clk => clk,
116 rstn => rstn,
116 rstn => rstn,
117 delta_snapshot => delta_snapshot,
117 delta_snapshot => delta_snapshot,
118 delta_f2_f1 => delta_f2_f1,
118 delta_f2_f1 => delta_f2_f1,
119 delta_f2_f0 => delta_f2_f0,
119 delta_f2_f0 => delta_f2_f0,
120 coarse_time_0 => coarse_time_0,
120 coarse_time_0 => coarse_time_0,
121 data_f0_in_valid => data_f0_in_valid,
121 data_f0_in_valid => data_f0_in_valid,
122 data_f2_in_valid => data_f2_in_valid,
122 data_f2_in_valid => data_f2_in_valid,
123 start_snapshot_f0 => start_snapshot_f0,
123 start_snapshot_f0 => start_snapshot_f0,
124 start_snapshot_f1 => start_snapshot_f1,
124 start_snapshot_f1 => start_snapshot_f1,
125 start_snapshot_f2 => start_snapshot_f2);
125 start_snapshot_f2 => start_snapshot_f2);
126
126
127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
128 GENERIC MAP (
128 GENERIC MAP (
129 data_size => data_size,
129 data_size => data_size,
130 nb_snapshot_param_size => nb_snapshot_param_size)
130 nb_snapshot_param_size => nb_snapshot_param_size)
131 PORT MAP (
131 PORT MAP (
132 clk => clk,
132 clk => clk,
133 rstn => rstn,
133 rstn => rstn,
134 enable => enable_f0,
134 enable => enable_f0,
135 burst_enable => burst_f0,
135 burst_enable => burst_f0,
136 nb_snapshot_param => nb_snapshot_param,
136 nb_snapshot_param => nb_snapshot_param,
137 start_snapshot => start_snapshot_f0,
137 start_snapshot => start_snapshot_f0,
138 data_in => data_f0_in,
138 data_in => data_f0_in,
139 data_in_valid => data_f0_in_valid,
139 data_in_valid => data_f0_in_valid,
140 data_out => data_f0_out,
140 data_out => data_f0_out,
141 data_out_valid => data_f0_out_valid);
141 data_out_valid => data_f0_out_valid);
142
142
143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
144
144
145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
146 GENERIC MAP (
146 GENERIC MAP (
147 data_size => data_size,
147 data_size => data_size,
148 nb_snapshot_param_size => nb_snapshot_param_size+1)
148 nb_snapshot_param_size => nb_snapshot_param_size+1)
149 PORT MAP (
149 PORT MAP (
150 clk => clk,
150 clk => clk,
151 rstn => rstn,
151 rstn => rstn,
152 enable => enable_f1,
152 enable => enable_f1,
153 burst_enable => burst_f1,
153 burst_enable => burst_f1,
154 nb_snapshot_param => nb_snapshot_param_more_one,
154 nb_snapshot_param => nb_snapshot_param_more_one,
155 start_snapshot => start_snapshot_f1,
155 start_snapshot => start_snapshot_f1,
156 data_in => data_f1_in,
156 data_in => data_f1_in,
157 data_in_valid => data_f1_in_valid,
157 data_in_valid => data_f1_in_valid,
158 data_out => data_f1_out,
158 data_out => data_f1_out,
159 data_out_valid => data_f1_out_valid);
159 data_out_valid => data_f1_out_valid);
160
160
161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
162 GENERIC MAP (
162 GENERIC MAP (
163 data_size => data_size,
163 data_size => data_size,
164 nb_snapshot_param_size => nb_snapshot_param_size+1)
164 nb_snapshot_param_size => nb_snapshot_param_size+1)
165 PORT MAP (
165 PORT MAP (
166 clk => clk,
166 clk => clk,
167 rstn => rstn,
167 rstn => rstn,
168 enable => enable_f2,
168 enable => enable_f2,
169 burst_enable => burst_f2,
169 burst_enable => burst_f2,
170 nb_snapshot_param => nb_snapshot_param_more_one,
170 nb_snapshot_param => nb_snapshot_param_more_one,
171 start_snapshot => start_snapshot_f2,
171 start_snapshot => start_snapshot_f2,
172 data_in => data_f2_in,
172 data_in => data_f2_in,
173 data_in_valid => data_f2_in_valid,
173 data_in_valid => data_f2_in_valid,
174 data_out => data_f2_out,
174 data_out => data_f2_out,
175 data_out_valid => data_f2_out_valid);
175 data_out_valid => data_f2_out_valid);
176
176
177 lpp_waveform_burst_f3: lpp_waveform_burst
177 lpp_waveform_burst_f3: lpp_waveform_burst
178 GENERIC MAP (
178 GENERIC MAP (
179 data_size => data_size)
179 data_size => data_size)
180 PORT MAP (
180 PORT MAP (
181 clk => clk,
181 clk => clk,
182 rstn => rstn,
182 rstn => rstn,
183 enable => enable_f3,
183 enable => enable_f3,
184 data_in => data_f3_in,
184 data_in => data_f3_in,
185 data_in_valid => data_f3_in_valid,
185 data_in_valid => data_f3_in_valid,
186 data_out => data_f3_out,
186 data_out => data_f3_out,
187 data_out_valid => data_f3_out_valid);
187 data_out_valid => data_f3_out_valid);
188
188
189
189
190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
191
191
192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
194 PORT MAP (
194 PORT MAP (
195 HCLK => clk,
195 HCLK => clk,
196 HRESETn => rstn,
196 HRESETn => rstn,
197 valid_in => valid_in(I),
197 valid_in => valid_in(I),
198 ack_in => valid_ack(I),
198 ack_in => valid_ack(I),
199 valid_out => valid_out(I),
199 valid_out => valid_out(I),
200 error => status_new_err(I));
200 error => status_new_err(I));
201 END GENERATE all_input_valid;
201 END GENERATE all_input_valid;
202
202
203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
204 GENERIC MAP (tech => tech)
204 GENERIC MAP (tech => tech)
205 PORT MAP (
205 PORT MAP (
206 clk => clk,
206 clk => clk,
207 rstn => rstn,
207 rstn => rstn,
208 data_f0_valid => valid_out(0),
208 data_f0_valid => valid_out(0),
209 data_f1_valid => valid_out(1),
209 data_f1_valid => valid_out(1),
210 data_f2_valid => valid_out(2),
210 data_f2_valid => valid_out(2),
211 data_f3_valid => valid_out(3),
211 data_f3_valid => valid_out(3),
212
212
213 data_valid_ack => valid_ack,
213 data_valid_ack => valid_ack,
214
214
215 data_f0 => data_f0_out,
215 data_f0 => data_f0_out,
216 data_f1 => data_f1_out,
216 data_f1 => data_f1_out,
217 data_f2 => data_f2_out,
217 data_f2 => data_f2_out,
218 data_f3 => data_f3_out,
218 data_f3 => data_f3_out,
219
219
220 ready => ready_arb,
220 ready => ready_arb,
221 time_wen => time_wen,
221 time_wen => time_wen,
222 data_wen => data_wen,
222 data_wen => data_wen,
223 data => wdata);
223 data => wdata);
224
224
225 ready_arb <= NOT ready;
225 ready_arb <= NOT ready;
226
226
227 lpp_waveform_fifo_1: lpp_waveform_fifo
227 lpp_waveform_fifo_1: lpp_waveform_fifo
228 GENERIC MAP (tech => tech)
228 GENERIC MAP (tech => tech)
229 PORT MAP (
229 PORT MAP (
230 clk => clk,
230 clk => clk,
231 rstn => rstn,
231 rstn => rstn,
232 ready => ready,
232 ready => ready,
233 time_ren => time_ren, -- todo
233 time_ren => time_ren, -- todo
234 data_ren => data_ren, -- todo
234 data_ren => data_ren, -- todo
235 rdata => rdata, -- todo
235 rdata => rdata, -- todo
236
236
237 time_wen => time_wen,
237 time_wen => time_wen,
238 data_wen => data_wen,
238 data_wen => data_wen,
239 wdata => wdata);
239 wdata => wdata);
240
240
241 --time_ren <= (OTHERS => '1');
241 --time_ren <= (OTHERS => '1');
242 --data_ren <= (OTHERS => '1');
242 --data_ren <= (OTHERS => '1');
243
243
244 pp_waveform_dma_1: lpp_waveform_dma
244 pp_waveform_dma_1: lpp_waveform_dma
245 GENERIC MAP (
245 GENERIC MAP (
246 data_size => data_size,
246 data_size => data_size,
247 tech => tech,
247 tech => tech,
248 hindex => hindex,
248 hindex => hindex,
249 nb_burst_available_size => nb_burst_available_size)
249 nb_burst_available_size => nb_burst_available_size)
250 PORT MAP (
250 PORT MAP (
251 HCLK => clk,
251 HCLK => clk,
252 HRESETn => rstn,
252 HRESETn => rstn,
253 AHB_Master_In => AHB_Master_In,
253 AHB_Master_In => AHB_Master_In,
254 AHB_Master_Out => AHB_Master_Out,
254 AHB_Master_Out => AHB_Master_Out,
255 data_ready => ready,
255 data_ready => ready,
256 data => rdata,
256 data => rdata,
257 data_data_ren => data_ren,
257 data_data_ren => data_ren,
258 data_time_ren => time_ren,
258 data_time_ren => time_ren,
259 --data_f0_in => data_f0_out,
259 --data_f0_in => data_f0_out,
260 --data_f1_in => data_f1_out,
260 --data_f1_in => data_f1_out,
261 --data_f2_in => data_f2_out,
261 --data_f2_in => data_f2_out,
262 --data_f3_in => data_f3_out,
262 --data_f3_in => data_f3_out,
263 --data_f0_in_valid => data_f0_out_valid,
263 --data_f0_in_valid => data_f0_out_valid,
264 --data_f1_in_valid => data_f1_out_valid,
264 --data_f1_in_valid => data_f1_out_valid,
265 --data_f2_in_valid => data_f2_out_valid,
265 --data_f2_in_valid => data_f2_out_valid,
266 --data_f3_in_valid => data_f3_out_valid,
266 --data_f3_in_valid => data_f3_out_valid,
267 nb_burst_available => nb_burst_available,
267 nb_burst_available => nb_burst_available,
268 status_full => status_full,
268 status_full => status_full,
269 status_full_ack => status_full_ack,
269 status_full_ack => status_full_ack,
270 status_full_err => status_full_err,
270 status_full_err => status_full_err,
271 -- status_new_err => status_new_err,
272 addr_data_f0 => addr_data_f0,
271 addr_data_f0 => addr_data_f0,
273 addr_data_f1 => addr_data_f1,
272 addr_data_f1 => addr_data_f1,
274 addr_data_f2 => addr_data_f2,
273 addr_data_f2 => addr_data_f2,
275 addr_data_f3 => addr_data_f3);
274 addr_data_f3 => addr_data_f3);
276
275
277 END beh;
276 END beh;
General Comments 0
You need to be logged in to leave comments. Login now