diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
@@ -153,8 +153,6 @@ PACKAGE lpp_top_lfr_pkg IS
     PORT (
     sample               : IN Samples(7 DOWNTO 0);
     sample_val           : IN STD_LOGIC;
-      cnv_clk            : IN  STD_LOGIC;
-      cnv_rstn           : IN  STD_LOGIC;
       clk                : IN  STD_LOGIC;
       rstn               : IN  STD_LOGIC;
       sample_f0_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd
@@ -235,8 +235,8 @@ BEGIN
         sample     => sample,
         sample_val => sample_val,
 
-        cnv_clk  => cnv_clk,
-        cnv_rstn => cnv_rstn,
+--        cnv_clk  => cnv_clk,
+--        cnv_rstn => cnv_rstn,
 
         clk  => HCLK,
         rstn => HRESETn,
diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd
@@ -31,17 +31,9 @@ ENTITY lpp_top_lfr_wf_picker_ip IS
     Mem_use                 : INTEGER := use_RAM
     );
   PORT (
-    -- ADS7886
---    cnv_run         : IN  STD_LOGIC;
---    cnv             : OUT STD_LOGIC;
---    sck             : OUT STD_LOGIC;
---    sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
     sample           : IN Samples(7 DOWNTO 0);
     sample_val       : IN STD_LOGIC;
     --
-    cnv_clk         : IN  STD_LOGIC;
-    cnv_rstn        : IN  STD_LOGIC;
-    --
     clk             : IN  STD_LOGIC;
     rstn            : IN  STD_LOGIC;
     --
@@ -141,15 +133,15 @@ ARCHITECTURE tb OF lpp_top_lfr_wf_picker
   SIGNAL sample_filter_v2_out_val : STD_LOGIC;
   SIGNAL sample_filter_v2_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
   -----------------------------------------------------------------------------
-  SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
+  --SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
 
-  SIGNAL sample_filter_v2_out_reg_val    : STD_LOGIC;
-  SIGNAL sample_filter_v2_out_reg_val_s  : STD_LOGIC;
-  SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
-  SIGNAL only_one_hot                    : STD_LOGIC;
-  SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
-  SIGNAL sample_filter_v2_out_sync_val   : STD_LOGIC;
-  SIGNAL sample_filter_v2_out_sync       : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
+  --SIGNAL sample_filter_v2_out_reg_val    : STD_LOGIC;
+  --SIGNAL sample_filter_v2_out_reg_val_s  : STD_LOGIC;
+  --SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
+  --SIGNAL only_one_hot                    : STD_LOGIC;
+  --SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
+  --SIGNAL sample_filter_v2_out_sync_val   : STD_LOGIC;
+  --SIGNAL sample_filter_v2_out_sync       : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
   -----------------------------------------------------------------------------
   SIGNAL sample_data_shaping_out_val     : STD_LOGIC;
   SIGNAL sample_data_shaping_out         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -190,11 +182,11 @@ ARCHITECTURE tb OF lpp_top_lfr_wf_picker
 BEGIN
   
   -----------------------------------------------------------------------------
-  PROCESS (cnv_clk, cnv_rstn)
+  PROCESS (clk, rstn)
   BEGIN  -- PROCESS
-    IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+    IF rstn = '0' THEN              -- asynchronous reset (active low)
       sample_val_delay <= '0';
-    ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
       sample_val_delay <= sample_val;
     END IF;
   END PROCESS;
@@ -222,8 +214,8 @@ BEGIN
       Cels_count   => Cels_count,
       ChanelsCount => ChanelCount)
     PORT MAP (
-      rstn           => cnv_rstn,
-      clk            => cnv_clk,
+      rstn           => rstn,
+      clk            => clk,
       virg_pos       => 7,
       coefs          => coefs_v2,
       sample_in_val  => sample_val_delay,
@@ -236,90 +228,90 @@ BEGIN
   -- RESYNC STAGE
   -----------------------------------------------------------------------------
 
-  all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
-    all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
-      PROCESS (cnv_clk, cnv_rstn)
-      BEGIN  -- PROCESS
-        IF cnv_rstn = '0' THEN          -- asynchronous reset (active low)
-          sample_filter_v2_out_reg(I, J) <= '0';
-        ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
-          IF sample_filter_v2_out_val = '1' THEN
-            sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
-          END IF;
-        END IF;
-      END PROCESS;
-    END GENERATE all_data_reg;
-  END GENERATE all_sample_reg;
+  --all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
+  --  all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
+  --    PROCESS (cnv_clk, cnv_rstn)
+  --    BEGIN  -- PROCESS
+  --      IF cnv_rstn = '0' THEN          -- asynchronous reset (active low)
+  --        sample_filter_v2_out_reg(I, J) <= '0';
+  --      ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+  --        IF sample_filter_v2_out_val = '1' THEN
+  --          sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
+  --        END IF;
+  --      END IF;
+  --    END PROCESS;
+  --  END GENERATE all_data_reg;
+  --END GENERATE all_sample_reg;
 
-  PROCESS (cnv_clk, cnv_rstn)
-  BEGIN  -- PROCESS
-    IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
-      sample_filter_v2_out_reg_val <= '0';
-    ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
-      IF sample_filter_v2_out_val = '1' THEN
-        sample_filter_v2_out_reg_val <= '1';
-      ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
-        sample_filter_v2_out_reg_val <= '0';
-      END IF;
-    END IF;
-  END PROCESS;
+  --PROCESS (cnv_clk, cnv_rstn)
+  --BEGIN  -- PROCESS
+  --  IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+  --    sample_filter_v2_out_reg_val <= '0';
+  --  ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+  --    IF sample_filter_v2_out_val = '1' THEN
+  --      sample_filter_v2_out_reg_val <= '1';
+  --    ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
+  --      sample_filter_v2_out_reg_val <= '0';
+  --    END IF;
+  --  END IF;
+  --END PROCESS;
 
-  SYNC_FF_1 : SYNC_FF
-    GENERIC MAP (
-      NB_FF_OF_SYNC => 2)
-    PORT MAP (
-      clk    => clk,
-      rstn   => rstn,
-      A      => sample_filter_v2_out_reg_val,
-      A_sync => sample_filter_v2_out_reg_val_s);
+  --SYNC_FF_1 : SYNC_FF
+  --  GENERIC MAP (
+  --    NB_FF_OF_SYNC => 2)
+  --  PORT MAP (
+  --    clk    => clk,
+  --    rstn   => rstn,
+  --    A      => sample_filter_v2_out_reg_val,
+  --    A_sync => sample_filter_v2_out_reg_val_s);
 
-  SYNC_FF_2 : SYNC_FF
-    GENERIC MAP (
-      NB_FF_OF_SYNC => 2)
-    PORT MAP (
-      clk    => cnv_clk,
-      rstn   => cnv_rstn,
-      A      => sample_filter_v2_out_reg_val_s,
-      A_sync => sample_filter_v2_out_reg_val_s2);
+  --SYNC_FF_2 : SYNC_FF
+  --  GENERIC MAP (
+  --    NB_FF_OF_SYNC => 2)
+  --  PORT MAP (
+  --    clk    => cnv_clk,
+  --    rstn   => cnv_rstn,
+  --    A      => sample_filter_v2_out_reg_val_s,
+  --    A_sync => sample_filter_v2_out_reg_val_s2);
 
 
-  PROCESS (clk, rstn)
-  BEGIN  -- PROCESS
-    IF rstn = '0' THEN                  -- asynchronous reset (active low)
-      sample_filter_v2_out_sync_val_t <= '0';
-      sample_filter_v2_out_sync_val   <= '0';
-      only_one_hot                    <= '0';
-    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-      sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
-      only_one_hot                    <= sample_filter_v2_out_reg_val_s;
-      sample_filter_v2_out_sync_val   <= sample_filter_v2_out_sync_val_t;
-    END IF;
-  END PROCESS;
+  --PROCESS (clk, rstn)
+  --BEGIN  -- PROCESS
+  --  IF rstn = '0' THEN                  -- asynchronous reset (active low)
+  --    sample_filter_v2_out_sync_val_t <= '0';
+  --    sample_filter_v2_out_sync_val   <= '0';
+  --    only_one_hot                    <= '0';
+  --  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+  --    sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
+  --    only_one_hot                    <= sample_filter_v2_out_reg_val_s;
+  --    sample_filter_v2_out_sync_val   <= sample_filter_v2_out_sync_val_t;
+  --  END IF;
+  --END PROCESS;
 
 
-  all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
-    all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
-      PROCESS (clk, cnv_rstn)
-      BEGIN  -- PROCESS
-        IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
-          sample_filter_v2_out_sync(I,J) <= '0';
-        ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-          IF sample_filter_v2_out_sync_val_t = '1' THEN
-            sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
-          END IF;
-        END IF;
-      END PROCESS;
-    END GENERATE all_data_reg;
-  END GENERATE all_sample_reg2;
+  --all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
+  --  all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
+  --    PROCESS (clk, cnv_rstn)
+  --    BEGIN  -- PROCESS
+  --      IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+  --        sample_filter_v2_out_sync(I,J) <= '0';
+  --      ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+  --        IF sample_filter_v2_out_sync_val_t = '1' THEN
+  --          sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
+  --        END IF;
+  --      END IF;
+  --    END PROCESS;
+  --  END GENERATE all_data_reg;
+  --END GENERATE all_sample_reg2;
 
 
   -----------------------------------------------------------------------------
   -- DATA_SHAPING
   ----------------------------------------------------------------------------- 
   all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
-    sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
-    sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
-    sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
+    sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
+    sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
+    sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
   END GENERATE all_data_shaping_in_loop;
 
   sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
@@ -330,7 +322,7 @@ BEGIN
     IF rstn = '0' THEN                  -- asynchronous reset (active low)
       sample_data_shaping_out_val <= '0';
     ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-      sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
+      sample_data_shaping_out_val <= sample_filter_v2_out_val;
     END IF;
   END PROCESS;
 
@@ -347,22 +339,22 @@ BEGIN
         sample_data_shaping_out(6, j) <= '0';
         sample_data_shaping_out(7, j) <= '0';
       ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-        sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
+        sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
         IF data_shaping_SP0 = '1' THEN
           sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
         ELSE
-          sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
+          sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
         END IF;
         IF data_shaping_SP1 = '1' THEN
           sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
         ELSE
-          sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
+          sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
         END IF;
-        sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
-        sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
-        sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
-        sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
-        sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
+        sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
+        sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
+        sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
+        sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
+        sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
       END IF;
     END PROCESS;
   END GENERATE;
diff --git a/lib/lpp/lpp_top_lfr/top_wf_picker.vhd b/lib/lpp/lpp_top_lfr/top_wf_picker.vhd
--- a/lib/lpp/lpp_top_lfr/top_wf_picker.vhd
+++ b/lib/lpp/lpp_top_lfr/top_wf_picker.vhd
@@ -1,349 +1,349 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-LIBRARY lpp;
-USE lpp.lpp_ad_conv.ALL;
-USE lpp.iir_filter.ALL;
-USE lpp.FILTERcfg.ALL;
-USE lpp.lpp_memory.ALL;
-USE lpp.lpp_waveform_pkg.ALL;
-USE lpp.lpp_top_lfr_pkg.ALL;
-
-LIBRARY techmap;
-USE techmap.gencomp.ALL;
-
-LIBRARY grlib;
-USE grlib.amba.ALL;
-USE grlib.stdlib.ALL;
-USE grlib.devices.ALL;
-USE GRLIB.DMA2AHB_Package.ALL;
-
-ENTITY top_wf_picker IS
-  GENERIC (
-    hindex                  : INTEGER   := 2;
-    pindex                  : INTEGER   := 15;
-    paddr                   : INTEGER   := 15;
-    pmask                   : INTEGER   := 16#fff#;
-    pirq                    : INTEGER   := 15;
-    tech                    : INTEGER   := 0;
-    nb_burst_available_size : INTEGER   := 11;
-    nb_snapshot_param_size  : INTEGER   := 11;
-    delta_snapshot_size     : INTEGER   := 16;
-    delta_f2_f0_size        : INTEGER   := 10;
-    delta_f2_f1_size        : INTEGER   := 10;
-    ENABLE_FILTER           : STD_LOGIC := '1'
-    );
-  PORT (
-    cnv_clk  : IN  STD_LOGIC;
-    cnv_rstn : IN  STD_LOGIC;
-    --
-    sample_B   : IN Samples14v(2 DOWNTO 0);
-    sample_E   : IN Samples14v(4 DOWNTO 0);
-    sample_val : IN STD_LOGIC;
-
-    -- AMBA AHB system signals
-    HCLK    : IN STD_ULOGIC;
-    HRESETn : IN STD_ULOGIC;
-
-    -- AMBA APB Slave Interface
-    apbi : IN  apb_slv_in_type;
-    apbo : OUT apb_slv_out_type;
-
-    -- AMBA AHB Master Interface
-    AHB_Master_In  : IN  AHB_Mst_In_Type;
-    AHB_Master_Out : OUT AHB_Mst_Out_Type;
-
-    --
-    coarse_time_0 : IN STD_LOGIC;
-
-    -- 
-    data_shaping_BW : OUT STD_LOGIC
-    );
-END top_wf_picker;
-
-ARCHITECTURE tb OF top_wf_picker IS
-  
-  SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
-  SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
-  SIGNAL ready_matrix_f1                        : STD_LOGIC;
-  SIGNAL ready_matrix_f2                        : STD_LOGIC;
-  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
-  SIGNAL error_bad_component_error              : STD_LOGIC;
-  SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
-  SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
-  SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
-  SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
-  SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
-  SIGNAL status_error_bad_component_error       : STD_LOGIC;
-  SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
-  SIGNAL config_active_interruption_onError     : STD_LOGIC;
-  SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-  SIGNAL status_full        : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL status_full_ack    : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL status_full_err    : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL status_new_err     : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL data_shaping_SP0   : STD_LOGIC;
-  SIGNAL data_shaping_SP1   : STD_LOGIC;
-  SIGNAL data_shaping_R0    : STD_LOGIC;
-  SIGNAL data_shaping_R1    : STD_LOGIC;
-  SIGNAL delta_snapshot     : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
-  SIGNAL delta_f2_f1        : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
-  SIGNAL delta_f2_f0        : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
-  SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
-  SIGNAL nb_snapshot_param  : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
-  SIGNAL enable_f0          : STD_LOGIC;
-  SIGNAL enable_f1          : STD_LOGIC;
-  SIGNAL enable_f2          : STD_LOGIC;
-  SIGNAL enable_f3          : STD_LOGIC;
-  SIGNAL burst_f0           : STD_LOGIC;
-  SIGNAL burst_f1           : STD_LOGIC;
-  SIGNAL burst_f2           : STD_LOGIC;
-  SIGNAL addr_data_f0       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_data_f1       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_data_f2       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_data_f3       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-  SIGNAL sample_f0_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
-  SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f1_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
-  SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f2_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
-  SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f3_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
-  SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-
-  CONSTANT ChanelCount     : INTEGER := 8;
-  CONSTANT ncycle_cnv_high : INTEGER := 40;
-  CONSTANT ncycle_cnv      : INTEGER := 250;
-  
-  SIGNAL  sample_s          : Samples(ChanelCount-1 DOWNTO 0);
-  SIGNAL  sample            :  Samples14v(7 DOWNTO 0);
-  
-BEGIN
-
-  sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
-  sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-  
-  
-  ready_matrix_f0_0             <= '0';
-  ready_matrix_f0_1             <= '0';
-  ready_matrix_f1               <= '0';
-  ready_matrix_f2               <= '0';
-  error_anticipating_empty_fifo <= '0';
-  error_bad_component_error     <= '0';
-  debug_reg                     <= (OTHERS => '0');
-
-  lpp_top_apbreg_1 : lpp_top_apbreg
-    GENERIC MAP (
-      nb_burst_available_size => nb_burst_available_size,
-      nb_snapshot_param_size  => nb_snapshot_param_size,
-      delta_snapshot_size     => delta_snapshot_size,
-      delta_f2_f0_size        => delta_f2_f0_size,
-      delta_f2_f1_size        => delta_f2_f1_size,
-      pindex                  => pindex,
-      paddr                   => paddr,
-      pmask                   => pmask,
-      pirq                    => pirq)
-    PORT MAP (
-      HCLK    => HCLK,
-      HRESETn => HRESETn,
-      apbi    => apbi,
-      apbo    => apbo,
-
-      ready_matrix_f0_0                      => ready_matrix_f0_0,
-      ready_matrix_f0_1                      => ready_matrix_f0_1,
-      ready_matrix_f1                        => ready_matrix_f1,
-      ready_matrix_f2                        => ready_matrix_f2,
-      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
-      error_bad_component_error              => error_bad_component_error,
-      debug_reg                              => debug_reg,
-      status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
-      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
-      status_ready_matrix_f1                 => status_ready_matrix_f1,
-      status_ready_matrix_f2                 => status_ready_matrix_f2,
-      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
-      status_error_bad_component_error       => status_error_bad_component_error,
-      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
-      config_active_interruption_onError     => config_active_interruption_onError,
-      addr_matrix_f0_0                       => addr_matrix_f0_0,
-      addr_matrix_f0_1                       => addr_matrix_f0_1,
-      addr_matrix_f1                         => addr_matrix_f1,
-      addr_matrix_f2                         => addr_matrix_f2,
-
-      status_full        => status_full,
-      status_full_ack    => status_full_ack,
-      status_full_err    => status_full_err,
-      status_new_err     => status_new_err,
-      data_shaping_BW    => data_shaping_BW,
-      data_shaping_SP0   => data_shaping_SP0,
-      data_shaping_SP1   => data_shaping_SP1,
-      data_shaping_R0    => data_shaping_R0,
-      data_shaping_R1    => data_shaping_R1,
-      delta_snapshot     => delta_snapshot,
-      delta_f2_f1        => delta_f2_f1,
-      delta_f2_f0        => delta_f2_f0,
-      nb_burst_available => nb_burst_available,
-      nb_snapshot_param  => nb_snapshot_param,
-      enable_f0          => enable_f0,
-      enable_f1          => enable_f1,
-      enable_f2          => enable_f2,
-      enable_f3          => enable_f3,
-      burst_f0           => burst_f0,
-      burst_f1           => burst_f1,
-      burst_f2           => burst_f2,
-      addr_data_f0       => addr_data_f0,
-      addr_data_f1       => addr_data_f1,
-      addr_data_f2       => addr_data_f2,
-      addr_data_f3       => addr_data_f3);
-
-
-
-  
-  --DIGITAL_acquisition : AD7688_drvr_sync
-  --  GENERIC MAP (
-  --    ChanelCount     => ChanelCount,
-  --    ncycle_cnv_high => ncycle_cnv_high,
-  --    ncycle_cnv      => ncycle_cnv)
-  --  PORT MAP (
-  --    cnv_clk    => cnv_clk,                      -- 
-  --    cnv_rstn   => cnv_rstn,                     -- 
-  --    cnv_run    => cnv_run,                      --
-  --    cnv        => cnv,                          -- 
-  --    sck        => sck,                          -- 
-  --    sdo        => sdo(ChanelCount-1 DOWNTO 0),  -- 
-  --    sample     => sample,
-  --    sample_val => sample_val);
-
-  all_channel: FOR i IN 7 DOWNTO 0 GENERATE
-    sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
-  END GENERATE all_channel;
-
-  
-  wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
-    
-    lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
-      GENERIC MAP (
-        hindex                  => hindex,
-        nb_burst_available_size => nb_burst_available_size,
-        nb_snapshot_param_size  => nb_snapshot_param_size,
-        delta_snapshot_size     => delta_snapshot_size,
-        delta_f2_f0_size        => delta_f2_f0_size,
-        delta_f2_f1_size        => delta_f2_f1_size,
-        tech                    => tech,
-        Mem_use                 => use_RAM
-        )
-      PORT MAP (
-        sample     => sample_s,
-        sample_val => sample_val,
-
-        cnv_clk  => HCLK,--cnv_clk,
-        cnv_rstn => HRESETn,--cnv_rstn,
-
-        clk  => HCLK,
-        rstn => HRESETn,
-
-        sample_f0_wen      => sample_f0_wen,
-        sample_f0_wdata    => sample_f0_wdata,
-        sample_f1_wen      => sample_f1_wen,
-        sample_f1_wdata    => sample_f1_wdata,
-        sample_f2_wen      => sample_f2_wen,
-        sample_f2_wdata    => sample_f2_wdata,
-        sample_f3_wen      => sample_f3_wen,
-        sample_f3_wdata    => sample_f3_wdata,
-        AHB_Master_In      => AHB_Master_In,
-        AHB_Master_Out     => AHB_Master_Out,
-        coarse_time_0      => coarse_time_0,
-        data_shaping_SP0   => data_shaping_SP0,
-        data_shaping_SP1   => data_shaping_SP1,
-        data_shaping_R0    => data_shaping_R0,
-        data_shaping_R1    => data_shaping_R1,
-        delta_snapshot     => delta_snapshot,
-        delta_f2_f1        => delta_f2_f1,
-        delta_f2_f0        => delta_f2_f0,
-        enable_f0          => enable_f0,
-        enable_f1          => enable_f1,
-        enable_f2          => enable_f2,
-        enable_f3          => enable_f3,
-        burst_f0           => burst_f0,
-        burst_f1           => burst_f1,
-        burst_f2           => burst_f2,
-        nb_burst_available => nb_burst_available,
-        nb_snapshot_param  => nb_snapshot_param,
-        status_full        => status_full,
-        status_full_ack    => status_full_ack,
-        status_full_err    => status_full_err,
-        status_new_err     => status_new_err,
-        addr_data_f0       => addr_data_f0,
-        addr_data_f1       => addr_data_f1,
-        addr_data_f2       => addr_data_f2,
-        addr_data_f3       => addr_data_f3);
-
-  END GENERATE wf_picker_with_filter;
-
-  
-  wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
-    
-    lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
-      GENERIC MAP (
-        hindex                  => hindex,
-        nb_burst_available_size => nb_burst_available_size,
-        nb_snapshot_param_size  => nb_snapshot_param_size,
-        delta_snapshot_size     => delta_snapshot_size,
-        delta_f2_f0_size        => delta_f2_f0_size,
-        delta_f2_f1_size        => delta_f2_f1_size,
-        tech                    => tech
-        )
-      PORT MAP (
-        sample     => sample_s,
-        sample_val => sample_val,
-
-        cnv_clk  => cnv_clk,
-        cnv_rstn => cnv_rstn,
-
-        clk  => HCLK,
-        rstn => HRESETn,
-
-        sample_f0_wen      => sample_f0_wen,
-        sample_f0_wdata    => sample_f0_wdata,
-        sample_f1_wen      => sample_f1_wen,
-        sample_f1_wdata    => sample_f1_wdata,
-        sample_f2_wen      => sample_f2_wen,
-        sample_f2_wdata    => sample_f2_wdata,
-        sample_f3_wen      => sample_f3_wen,
-        sample_f3_wdata    => sample_f3_wdata,
-        AHB_Master_In      => AHB_Master_In,
-        AHB_Master_Out     => AHB_Master_Out,
-        coarse_time_0      => coarse_time_0,
-        data_shaping_SP0   => data_shaping_SP0,
-        data_shaping_SP1   => data_shaping_SP1,
-        data_shaping_R0    => data_shaping_R0,
-        data_shaping_R1    => data_shaping_R1,
-        delta_snapshot     => delta_snapshot,
-        delta_f2_f1        => delta_f2_f1,
-        delta_f2_f0        => delta_f2_f0,
-        enable_f0          => enable_f0,
-        enable_f1          => enable_f1,
-        enable_f2          => enable_f2,
-        enable_f3          => enable_f3,
-        burst_f0           => burst_f0,
-        burst_f1           => burst_f1,
-        burst_f2           => burst_f2,
-        nb_burst_available => nb_burst_available,
-        nb_snapshot_param  => nb_snapshot_param,
-        status_full        => status_full,
-        status_full_ack    => status_full_ack,
-        status_full_err    => status_full_err,
-        status_new_err     => status_new_err,
-        addr_data_f0       => addr_data_f0,
-        addr_data_f1       => addr_data_f1,
-        addr_data_f2       => addr_data_f2,
-        addr_data_f3       => addr_data_f3);
-
-  END GENERATE wf_picker_without_filter;
-END tb;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lpp;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.iir_filter.ALL;
+USE lpp.FILTERcfg.ALL;
+USE lpp.lpp_memory.ALL;
+USE lpp.lpp_waveform_pkg.ALL;
+USE lpp.lpp_top_lfr_pkg.ALL;
+
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
+
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE grlib.stdlib.ALL;
+USE grlib.devices.ALL;
+USE GRLIB.DMA2AHB_Package.ALL;
+
+ENTITY top_wf_picker IS
+  GENERIC (
+    hindex                  : INTEGER   := 2;
+    pindex                  : INTEGER   := 15;
+    paddr                   : INTEGER   := 15;
+    pmask                   : INTEGER   := 16#fff#;
+    pirq                    : INTEGER   := 15;
+    tech                    : INTEGER   := 0;
+    nb_burst_available_size : INTEGER   := 11;
+    nb_snapshot_param_size  : INTEGER   := 11;
+    delta_snapshot_size     : INTEGER   := 16;
+    delta_f2_f0_size        : INTEGER   := 10;
+    delta_f2_f1_size        : INTEGER   := 10;
+    ENABLE_FILTER           : STD_LOGIC := '1'
+    );
+  PORT (
+    cnv_clk  : IN  STD_LOGIC;
+    cnv_rstn : IN  STD_LOGIC;
+    --
+    sample_B   : IN Samples14v(2 DOWNTO 0);
+    sample_E   : IN Samples14v(4 DOWNTO 0);
+    sample_val : IN STD_LOGIC;
+
+    -- AMBA AHB system signals
+    HCLK    : IN STD_ULOGIC;
+    HRESETn : IN STD_ULOGIC;
+
+    -- AMBA APB Slave Interface
+    apbi : IN  apb_slv_in_type;
+    apbo : OUT apb_slv_out_type;
+
+    -- AMBA AHB Master Interface
+    AHB_Master_In  : IN  AHB_Mst_In_Type;
+    AHB_Master_Out : OUT AHB_Mst_Out_Type;
+
+    --
+    coarse_time_0 : IN STD_LOGIC;
+
+    -- 
+    data_shaping_BW : OUT STD_LOGIC
+    );
+END top_wf_picker;
+
+ARCHITECTURE tb OF top_wf_picker IS
+  
+  SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
+  SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
+  SIGNAL ready_matrix_f1                        : STD_LOGIC;
+  SIGNAL ready_matrix_f2                        : STD_LOGIC;
+  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
+  SIGNAL error_bad_component_error              : STD_LOGIC;
+  SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
+  SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
+  SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
+  SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
+  SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
+  SIGNAL status_error_bad_component_error       : STD_LOGIC;
+  SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
+  SIGNAL config_active_interruption_onError     : STD_LOGIC;
+  SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  SIGNAL status_full        : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL status_full_ack    : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL status_full_err    : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL status_new_err     : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL data_shaping_SP0   : STD_LOGIC;
+  SIGNAL data_shaping_SP1   : STD_LOGIC;
+  SIGNAL data_shaping_R0    : STD_LOGIC;
+  SIGNAL data_shaping_R1    : STD_LOGIC;
+  SIGNAL delta_snapshot     : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
+  SIGNAL delta_f2_f1        : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
+  SIGNAL delta_f2_f0        : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
+  SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
+  SIGNAL nb_snapshot_param  : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
+  SIGNAL enable_f0          : STD_LOGIC;
+  SIGNAL enable_f1          : STD_LOGIC;
+  SIGNAL enable_f2          : STD_LOGIC;
+  SIGNAL enable_f3          : STD_LOGIC;
+  SIGNAL burst_f0           : STD_LOGIC;
+  SIGNAL burst_f1           : STD_LOGIC;
+  SIGNAL burst_f2           : STD_LOGIC;
+  SIGNAL addr_data_f0       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_data_f1       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_data_f2       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_data_f3       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  SIGNAL sample_f0_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+  SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f1_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+  SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f2_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+  SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f3_wen   : STD_LOGIC_VECTOR(5 DOWNTO 0);
+  SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+
+  CONSTANT ChanelCount     : INTEGER := 8;
+  CONSTANT ncycle_cnv_high : INTEGER := 40;
+  CONSTANT ncycle_cnv      : INTEGER := 250;
+  
+  SIGNAL  sample_s          : Samples(ChanelCount-1 DOWNTO 0);
+  SIGNAL  sample            :  Samples14v(7 DOWNTO 0);
+  
+BEGIN
+
+  sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+  sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+  
+  
+  ready_matrix_f0_0             <= '0';
+  ready_matrix_f0_1             <= '0';
+  ready_matrix_f1               <= '0';
+  ready_matrix_f2               <= '0';
+  error_anticipating_empty_fifo <= '0';
+  error_bad_component_error     <= '0';
+  debug_reg                     <= (OTHERS => '0');
+
+  lpp_top_apbreg_1 : lpp_top_apbreg
+    GENERIC MAP (
+      nb_burst_available_size => nb_burst_available_size,
+      nb_snapshot_param_size  => nb_snapshot_param_size,
+      delta_snapshot_size     => delta_snapshot_size,
+      delta_f2_f0_size        => delta_f2_f0_size,
+      delta_f2_f1_size        => delta_f2_f1_size,
+      pindex                  => pindex,
+      paddr                   => paddr,
+      pmask                   => pmask,
+      pirq                    => pirq)
+    PORT MAP (
+      HCLK    => HCLK,
+      HRESETn => HRESETn,
+      apbi    => apbi,
+      apbo    => apbo,
+
+      ready_matrix_f0_0                      => ready_matrix_f0_0,
+      ready_matrix_f0_1                      => ready_matrix_f0_1,
+      ready_matrix_f1                        => ready_matrix_f1,
+      ready_matrix_f2                        => ready_matrix_f2,
+      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
+      error_bad_component_error              => error_bad_component_error,
+      debug_reg                              => debug_reg,
+      status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
+      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
+      status_ready_matrix_f1                 => status_ready_matrix_f1,
+      status_ready_matrix_f2                 => status_ready_matrix_f2,
+      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
+      status_error_bad_component_error       => status_error_bad_component_error,
+      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
+      config_active_interruption_onError     => config_active_interruption_onError,
+      addr_matrix_f0_0                       => addr_matrix_f0_0,
+      addr_matrix_f0_1                       => addr_matrix_f0_1,
+      addr_matrix_f1                         => addr_matrix_f1,
+      addr_matrix_f2                         => addr_matrix_f2,
+
+      status_full        => status_full,
+      status_full_ack    => status_full_ack,
+      status_full_err    => status_full_err,
+      status_new_err     => status_new_err,
+      data_shaping_BW    => data_shaping_BW,
+      data_shaping_SP0   => data_shaping_SP0,
+      data_shaping_SP1   => data_shaping_SP1,
+      data_shaping_R0    => data_shaping_R0,
+      data_shaping_R1    => data_shaping_R1,
+      delta_snapshot     => delta_snapshot,
+      delta_f2_f1        => delta_f2_f1,
+      delta_f2_f0        => delta_f2_f0,
+      nb_burst_available => nb_burst_available,
+      nb_snapshot_param  => nb_snapshot_param,
+      enable_f0          => enable_f0,
+      enable_f1          => enable_f1,
+      enable_f2          => enable_f2,
+      enable_f3          => enable_f3,
+      burst_f0           => burst_f0,
+      burst_f1           => burst_f1,
+      burst_f2           => burst_f2,
+      addr_data_f0       => addr_data_f0,
+      addr_data_f1       => addr_data_f1,
+      addr_data_f2       => addr_data_f2,
+      addr_data_f3       => addr_data_f3);
+
+
+
+  
+  --DIGITAL_acquisition : AD7688_drvr_sync
+  --  GENERIC MAP (
+  --    ChanelCount     => ChanelCount,
+  --    ncycle_cnv_high => ncycle_cnv_high,
+  --    ncycle_cnv      => ncycle_cnv)
+  --  PORT MAP (
+  --    cnv_clk    => cnv_clk,                      -- 
+  --    cnv_rstn   => cnv_rstn,                     -- 
+  --    cnv_run    => cnv_run,                      --
+  --    cnv        => cnv,                          -- 
+  --    sck        => sck,                          -- 
+  --    sdo        => sdo(ChanelCount-1 DOWNTO 0),  -- 
+  --    sample     => sample,
+  --    sample_val => sample_val);
+
+  all_channel: FOR i IN 7 DOWNTO 0 GENERATE
+    sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
+  END GENERATE all_channel;
+
+  
+  wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
+    
+    lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
+      GENERIC MAP (
+        hindex                  => hindex,
+        nb_burst_available_size => nb_burst_available_size,
+        nb_snapshot_param_size  => nb_snapshot_param_size,
+        delta_snapshot_size     => delta_snapshot_size,
+        delta_f2_f0_size        => delta_f2_f0_size,
+        delta_f2_f1_size        => delta_f2_f1_size,
+        tech                    => tech,
+        Mem_use                 => use_RAM
+        )
+      PORT MAP (
+        sample     => sample_s,
+        sample_val => sample_val,
+
+       -- cnv_clk  => HCLK,--cnv_clk,
+       -- cnv_rstn => HRESETn,--cnv_rstn,
+
+        clk  => HCLK,
+        rstn => HRESETn,
+
+        sample_f0_wen      => sample_f0_wen,
+        sample_f0_wdata    => sample_f0_wdata,
+        sample_f1_wen      => sample_f1_wen,
+        sample_f1_wdata    => sample_f1_wdata,
+        sample_f2_wen      => sample_f2_wen,
+        sample_f2_wdata    => sample_f2_wdata,
+        sample_f3_wen      => sample_f3_wen,
+        sample_f3_wdata    => sample_f3_wdata,
+        AHB_Master_In      => AHB_Master_In,
+        AHB_Master_Out     => AHB_Master_Out,
+        coarse_time_0      => coarse_time_0,
+        data_shaping_SP0   => data_shaping_SP0,
+        data_shaping_SP1   => data_shaping_SP1,
+        data_shaping_R0    => data_shaping_R0,
+        data_shaping_R1    => data_shaping_R1,
+        delta_snapshot     => delta_snapshot,
+        delta_f2_f1        => delta_f2_f1,
+        delta_f2_f0        => delta_f2_f0,
+        enable_f0          => enable_f0,
+        enable_f1          => enable_f1,
+        enable_f2          => enable_f2,
+        enable_f3          => enable_f3,
+        burst_f0           => burst_f0,
+        burst_f1           => burst_f1,
+        burst_f2           => burst_f2,
+        nb_burst_available => nb_burst_available,
+        nb_snapshot_param  => nb_snapshot_param,
+        status_full        => status_full,
+        status_full_ack    => status_full_ack,
+        status_full_err    => status_full_err,
+        status_new_err     => status_new_err,
+        addr_data_f0       => addr_data_f0,
+        addr_data_f1       => addr_data_f1,
+        addr_data_f2       => addr_data_f2,
+        addr_data_f3       => addr_data_f3);
+
+  END GENERATE wf_picker_with_filter;
+
+  
+  wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
+    
+    lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
+      GENERIC MAP (
+        hindex                  => hindex,
+        nb_burst_available_size => nb_burst_available_size,
+        nb_snapshot_param_size  => nb_snapshot_param_size,
+        delta_snapshot_size     => delta_snapshot_size,
+        delta_f2_f0_size        => delta_f2_f0_size,
+        delta_f2_f1_size        => delta_f2_f1_size,
+        tech                    => tech
+        )
+      PORT MAP (
+        sample     => sample_s,
+        sample_val => sample_val,
+
+        cnv_clk  => cnv_clk,
+        cnv_rstn => cnv_rstn,
+
+        clk  => HCLK,
+        rstn => HRESETn,
+
+        sample_f0_wen      => sample_f0_wen,
+        sample_f0_wdata    => sample_f0_wdata,
+        sample_f1_wen      => sample_f1_wen,
+        sample_f1_wdata    => sample_f1_wdata,
+        sample_f2_wen      => sample_f2_wen,
+        sample_f2_wdata    => sample_f2_wdata,
+        sample_f3_wen      => sample_f3_wen,
+        sample_f3_wdata    => sample_f3_wdata,
+        AHB_Master_In      => AHB_Master_In,
+        AHB_Master_Out     => AHB_Master_Out,
+        coarse_time_0      => coarse_time_0,
+        data_shaping_SP0   => data_shaping_SP0,
+        data_shaping_SP1   => data_shaping_SP1,
+        data_shaping_R0    => data_shaping_R0,
+        data_shaping_R1    => data_shaping_R1,
+        delta_snapshot     => delta_snapshot,
+        delta_f2_f1        => delta_f2_f1,
+        delta_f2_f0        => delta_f2_f0,
+        enable_f0          => enable_f0,
+        enable_f1          => enable_f1,
+        enable_f2          => enable_f2,
+        enable_f3          => enable_f3,
+        burst_f0           => burst_f0,
+        burst_f1           => burst_f1,
+        burst_f2           => burst_f2,
+        nb_burst_available => nb_burst_available,
+        nb_snapshot_param  => nb_snapshot_param,
+        status_full        => status_full,
+        status_full_ack    => status_full_ack,
+        status_full_err    => status_full_err,
+        status_new_err     => status_new_err,
+        addr_data_f0       => addr_data_f0,
+        addr_data_f1       => addr_data_f1,
+        addr_data_f2       => addr_data_f2,
+        addr_data_f3       => addr_data_f3);
+
+  END GENERATE wf_picker_without_filter;
+END tb;
\ No newline at end of file
diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd
--- a/lib/lpp/lpp_waveform/lpp_waveform.vhd
+++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd
@@ -268,7 +268,6 @@ BEGIN  -- beh
      status_full       => status_full,
      status_full_ack   => status_full_ack,
      status_full_err   => status_full_err,
---     status_new_err    => status_new_err,
      addr_data_f0      => addr_data_f0,
      addr_data_f1      => addr_data_f1,
      addr_data_f2      => addr_data_f2,