HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r205:6eb3be2045fd

Remove "Sync Stage" between Filter and DownSampler into waveformPicker

pellion -

r205:6eb3be2045fd JC

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r205:6eb3be2045fd

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lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd 0 -2

                  PORT (
                  sample               : IN Samples(7 DOWNTO 0);
                  sample_val           : IN STD_LOGIC;
-                   cnv_clk            : IN  STD_LOGIC;
-                   cnv_rstn           : IN  STD_LOGIC;
                    clk                : IN  STD_LOGIC;
                    rstn               : IN  STD_LOGIC;
                    sample_f0_wen      : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +2 -2

                      sample     => sample,
                      sample_val => sample_val,
-                     cnv_clk  => cnv_clk,
-                     cnv_rstn => cnv_rstn,
+             --        cnv_clk  => cnv_clk,
+             --        cnv_rstn => cnv_rstn,
                      clk  => HCLK,
                      rstn => HRESETn,

lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker_ip.vhd +93 -101

                  Mem_use                 : INTEGER := use_RAM
                  );
                PORT (
-                 -- ADS7886
-             --    cnv_run         : IN  STD_LOGIC;
-             --    cnv             : OUT STD_LOGIC;
-             --    sck             : OUT STD_LOGIC;
-             --    sdo             : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                  sample           : IN Samples(7 DOWNTO 0);
                  sample_val       : IN STD_LOGIC;
                  --
-                 cnv_clk         : IN  STD_LOGIC;
-                 cnv_rstn        : IN  STD_LOGIC;
-                 --
                  clk             : IN  STD_LOGIC;
                  rstn            : IN  STD_LOGIC;
                  --
                SIGNAL sample_filter_v2_out_val : STD_LOGIC;
                SIGNAL sample_filter_v2_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                -----------------------------------------------------------------------------
-               SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
+               --SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
-               SIGNAL sample_filter_v2_out_reg_val    : STD_LOGIC;
-               SIGNAL sample_filter_v2_out_reg_val_s  : STD_LOGIC;
-               SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
-               SIGNAL only_one_hot                    : STD_LOGIC;
-               SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
-               SIGNAL sample_filter_v2_out_sync_val   : STD_LOGIC;
-               SIGNAL sample_filter_v2_out_sync       : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
+               --SIGNAL sample_filter_v2_out_reg_val    : STD_LOGIC;
+               --SIGNAL sample_filter_v2_out_reg_val_s  : STD_LOGIC;
+               --SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
+               --SIGNAL only_one_hot                    : STD_LOGIC;
+               --SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
+               --SIGNAL sample_filter_v2_out_sync_val   : STD_LOGIC;
+               --SIGNAL sample_filter_v2_out_sync       : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
                -----------------------------------------------------------------------------
                SIGNAL sample_data_shaping_out_val     : STD_LOGIC;
                SIGNAL sample_data_shaping_out         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
              BEGIN
                -----------------------------------------------------------------------------
-               PROCESS (cnv_clk, cnv_rstn)
+               PROCESS (clk, rstn)
                BEGIN  -- PROCESS
-                 IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+                 IF rstn = '0' THEN              -- asynchronous reset (active low)
                    sample_val_delay <= '0';
-                 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                    sample_val_delay <= sample_val;
                  END IF;
                END PROCESS;
                    Cels_count   => Cels_count,
                    ChanelsCount => ChanelCount)
                  PORT MAP (
-                   rstn           => cnv_rstn,
-                   clk            => cnv_clk,
+                   rstn           => rstn,
+                   clk            => clk,
                    virg_pos       => 7,
                    coefs          => coefs_v2,
                    sample_in_val  => sample_val_delay,
                -- RESYNC STAGE
                -----------------------------------------------------------------------------
-               all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
-                 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
-                   PROCESS (cnv_clk, cnv_rstn)
-                   BEGIN  -- PROCESS
-                     IF cnv_rstn = '0' THEN          -- asynchronous reset (active low)
-                       sample_filter_v2_out_reg(I, J) <= '0';
-                     ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
-                       IF sample_filter_v2_out_val = '1' THEN
-                         sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
-                       END IF;
-                     END IF;
-                   END PROCESS;
-                 END GENERATE all_data_reg;
-               END GENERATE all_sample_reg;
+               --all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
+               --  all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
+               --    PROCESS (cnv_clk, cnv_rstn)
+               --    BEGIN  -- PROCESS
+               --      IF cnv_rstn = '0' THEN          -- asynchronous reset (active low)
+               --        sample_filter_v2_out_reg(I, J) <= '0';
+               --      ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+               --        IF sample_filter_v2_out_val = '1' THEN
+               --          sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
+               --        END IF;
+               --      END IF;
+               --    END PROCESS;
+               --  END GENERATE all_data_reg;
+               --END GENERATE all_sample_reg;
-               PROCESS (cnv_clk, cnv_rstn)
-               BEGIN  -- PROCESS
-                 IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
-                   sample_filter_v2_out_reg_val <= '0';
-                 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
-                   IF sample_filter_v2_out_val = '1' THEN
-                     sample_filter_v2_out_reg_val <= '1';
-                   ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
-                     sample_filter_v2_out_reg_val <= '0';
-                   END IF;
-                 END IF;
-               END PROCESS;
+               --PROCESS (cnv_clk, cnv_rstn)
+               --BEGIN  -- PROCESS
+               --  IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+               --    sample_filter_v2_out_reg_val <= '0';
+               --  ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+               --    IF sample_filter_v2_out_val = '1' THEN
+               --      sample_filter_v2_out_reg_val <= '1';
+               --    ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
+               --      sample_filter_v2_out_reg_val <= '0';
+               --    END IF;
+               --  END IF;
+               --END PROCESS;
-               SYNC_FF_1 : SYNC_FF
-                 GENERIC MAP (
-                   NB_FF_OF_SYNC => 2)
-                 PORT MAP (
-                   clk    => clk,
-                   rstn   => rstn,
-                   A      => sample_filter_v2_out_reg_val,
-                   A_sync => sample_filter_v2_out_reg_val_s);
+               --SYNC_FF_1 : SYNC_FF
+               --  GENERIC MAP (
+               --    NB_FF_OF_SYNC => 2)
+               --  PORT MAP (
+               --    clk    => clk,
+               --    rstn   => rstn,
+               --    A      => sample_filter_v2_out_reg_val,
+               --    A_sync => sample_filter_v2_out_reg_val_s);
-               SYNC_FF_2 : SYNC_FF
-                 GENERIC MAP (
-                   NB_FF_OF_SYNC => 2)
-                 PORT MAP (
-                   clk    => cnv_clk,
-                   rstn   => cnv_rstn,
-                   A      => sample_filter_v2_out_reg_val_s,
-                   A_sync => sample_filter_v2_out_reg_val_s2);
+               --SYNC_FF_2 : SYNC_FF
+               --  GENERIC MAP (
+               --    NB_FF_OF_SYNC => 2)
+               --  PORT MAP (
+               --    clk    => cnv_clk,
+               --    rstn   => cnv_rstn,
+               --    A      => sample_filter_v2_out_reg_val_s,
+               --    A_sync => sample_filter_v2_out_reg_val_s2);
-               PROCESS (clk, rstn)
-               BEGIN  -- PROCESS
-                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
-                   sample_filter_v2_out_sync_val_t <= '0';
-                   sample_filter_v2_out_sync_val   <= '0';
-                   only_one_hot                    <= '0';
-                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                   sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
-                   only_one_hot                    <= sample_filter_v2_out_reg_val_s;
-                   sample_filter_v2_out_sync_val   <= sample_filter_v2_out_sync_val_t;
-                 END IF;
-               END PROCESS;
+               --PROCESS (clk, rstn)
+               --BEGIN  -- PROCESS
+               --  IF rstn = '0' THEN                  -- asynchronous reset (active low)
+               --    sample_filter_v2_out_sync_val_t <= '0';
+               --    sample_filter_v2_out_sync_val   <= '0';
+               --    only_one_hot                    <= '0';
+               --  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+               --    sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
+               --    only_one_hot                    <= sample_filter_v2_out_reg_val_s;
+               --    sample_filter_v2_out_sync_val   <= sample_filter_v2_out_sync_val_t;
+               --  END IF;
+               --END PROCESS;
-               all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
-                 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
-                   PROCESS (clk, cnv_rstn)
-                   BEGIN  -- PROCESS
-                     IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
-                       sample_filter_v2_out_sync(I,J) <= '0';
-                     ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                       IF sample_filter_v2_out_sync_val_t = '1' THEN
-                         sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
-                       END IF;
-                     END IF;
-                   END PROCESS;
-                 END GENERATE all_data_reg;
-               END GENERATE all_sample_reg2;
+               --all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
+               --  all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
+               --    PROCESS (clk, cnv_rstn)
+               --    BEGIN  -- PROCESS
+               --      IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+               --        sample_filter_v2_out_sync(I,J) <= '0';
+               --      ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+               --        IF sample_filter_v2_out_sync_val_t = '1' THEN
+               --          sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
+               --        END IF;
+               --      END IF;
+               --    END PROCESS;
+               --  END GENERATE all_data_reg;
+               --END GENERATE all_sample_reg2;
                -----------------------------------------------------------------------------
                -- DATA_SHAPING
                -----------------------------------------------------------------------------
                all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
-                 sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
-                 sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
-                 sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
+                 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
+                 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
+                 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
                END GENERATE all_data_shaping_in_loop;
                sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
                  IF rstn = '0' THEN                  -- asynchronous reset (active low)
                    sample_data_shaping_out_val <= '0';
                  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                   sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
+                   sample_data_shaping_out_val <= sample_filter_v2_out_val;
                  END IF;
                END PROCESS;
                      sample_data_shaping_out(6, j) <= '0';
                      sample_data_shaping_out(7, j) <= '0';
                    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                     sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
+                     sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
                      IF data_shaping_SP0 = '1' THEN
                        sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
                      ELSE
-                       sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
+                       sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
                      END IF;
                      IF data_shaping_SP1 = '1' THEN
                        sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
                      ELSE
-                       sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
+                       sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
                      END IF;
-                     sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
-                     sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
-                     sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
-                     sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
-                     sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
+                     sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
+                     sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
+                     sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
+                     sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
+                     sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
                    END IF;
                  END PROCESS;
                END GENERATE;

lib/lpp/lpp_top_lfr/top_wf_picker.vhd +3 -3

                      sample     => sample_s,
                      sample_val => sample_val,
-                     cnv_clk  => HCLK,--cnv_clk,
-                     cnv_rstn => HRESETn,--cnv_rstn,
+                    -- cnv_clk  => HCLK,--cnv_clk,
+                    -- cnv_rstn => HRESETn,--cnv_rstn,
                      clk  => HCLK,
                      rstn => HRESETn,
                      addr_data_f3       => addr_data_f3);
                END GENERATE wf_picker_without_filter;
-             END tb;
+             END tb;
  No newline at end of file

lib/lpp/lpp_waveform/lpp_waveform.vhd 0 -1

                   status_full       => status_full,
                   status_full_ack   => status_full_ack,
                   status_full_err   => status_full_err,
-             --     status_new_err    => status_new_err,
                   addr_data_f0      => addr_data_f0,
                   addr_data_f1      => addr_data_f1,
                   addr_data_f2      => addr_data_f2,

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