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Remove "Sync Stage" between Filter and DownSampler into waveformPicker
pellion -
r205:6eb3be2045fd JC
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@@ -153,8 +153,6 PACKAGE lpp_top_lfr_pkg IS
153 153 PORT (
154 154 sample : IN Samples(7 DOWNTO 0);
155 155 sample_val : IN STD_LOGIC;
156 cnv_clk : IN STD_LOGIC;
157 cnv_rstn : IN STD_LOGIC;
158 156 clk : IN STD_LOGIC;
159 157 rstn : IN STD_LOGIC;
160 158 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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@@ -235,8 +235,8 BEGIN
235 235 sample => sample,
236 236 sample_val => sample_val,
237 237
238 cnv_clk => cnv_clk,
239 cnv_rstn => cnv_rstn,
238 -- cnv_clk => cnv_clk,
239 -- cnv_rstn => cnv_rstn,
240 240
241 241 clk => HCLK,
242 242 rstn => HRESETn,
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@@ -31,17 +31,9 ENTITY lpp_top_lfr_wf_picker_ip IS
31 31 Mem_use : INTEGER := use_RAM
32 32 );
33 33 PORT (
34 -- ADS7886
35 -- cnv_run : IN STD_LOGIC;
36 -- cnv : OUT STD_LOGIC;
37 -- sck : OUT STD_LOGIC;
38 -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
39 34 sample : IN Samples(7 DOWNTO 0);
40 35 sample_val : IN STD_LOGIC;
41 36 --
42 cnv_clk : IN STD_LOGIC;
43 cnv_rstn : IN STD_LOGIC;
44 --
45 37 clk : IN STD_LOGIC;
46 38 rstn : IN STD_LOGIC;
47 39 --
@@ -141,15 +133,15 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
141 133 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
142 134 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
143 135 -----------------------------------------------------------------------------
144 SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 --SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
145 137
146 SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
147 SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
148 SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
149 SIGNAL only_one_hot : STD_LOGIC;
150 SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
151 SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
152 SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
138 --SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
139 --SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
140 --SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
141 --SIGNAL only_one_hot : STD_LOGIC;
142 --SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
143 --SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
144 --SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
153 145 -----------------------------------------------------------------------------
154 146 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
155 147 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -190,11 +182,11 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
190 182 BEGIN
191 183
192 184 -----------------------------------------------------------------------------
193 PROCESS (cnv_clk, cnv_rstn)
185 PROCESS (clk, rstn)
194 186 BEGIN -- PROCESS
195 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
187 IF rstn = '0' THEN -- asynchronous reset (active low)
196 188 sample_val_delay <= '0';
197 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
189 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 190 sample_val_delay <= sample_val;
199 191 END IF;
200 192 END PROCESS;
@@ -222,8 +214,8 BEGIN
222 214 Cels_count => Cels_count,
223 215 ChanelsCount => ChanelCount)
224 216 PORT MAP (
225 rstn => cnv_rstn,
226 clk => cnv_clk,
217 rstn => rstn,
218 clk => clk,
227 219 virg_pos => 7,
228 220 coefs => coefs_v2,
229 221 sample_in_val => sample_val_delay,
@@ -236,90 +228,90 BEGIN
236 228 -- RESYNC STAGE
237 229 -----------------------------------------------------------------------------
238 230
239 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
240 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
241 PROCESS (cnv_clk, cnv_rstn)
242 BEGIN -- PROCESS
243 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
244 sample_filter_v2_out_reg(I, J) <= '0';
245 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
246 IF sample_filter_v2_out_val = '1' THEN
247 sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
248 END IF;
249 END IF;
250 END PROCESS;
251 END GENERATE all_data_reg;
252 END GENERATE all_sample_reg;
231 --all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
232 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
233 -- PROCESS (cnv_clk, cnv_rstn)
234 -- BEGIN -- PROCESS
235 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
236 -- sample_filter_v2_out_reg(I, J) <= '0';
237 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
238 -- IF sample_filter_v2_out_val = '1' THEN
239 -- sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
240 -- END IF;
241 -- END IF;
242 -- END PROCESS;
243 -- END GENERATE all_data_reg;
244 --END GENERATE all_sample_reg;
253 245
254 PROCESS (cnv_clk, cnv_rstn)
255 BEGIN -- PROCESS
256 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
257 sample_filter_v2_out_reg_val <= '0';
258 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
259 IF sample_filter_v2_out_val = '1' THEN
260 sample_filter_v2_out_reg_val <= '1';
261 ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
262 sample_filter_v2_out_reg_val <= '0';
263 END IF;
264 END IF;
265 END PROCESS;
246 --PROCESS (cnv_clk, cnv_rstn)
247 --BEGIN -- PROCESS
248 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
249 -- sample_filter_v2_out_reg_val <= '0';
250 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
251 -- IF sample_filter_v2_out_val = '1' THEN
252 -- sample_filter_v2_out_reg_val <= '1';
253 -- ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
254 -- sample_filter_v2_out_reg_val <= '0';
255 -- END IF;
256 -- END IF;
257 --END PROCESS;
266 258
267 SYNC_FF_1 : SYNC_FF
268 GENERIC MAP (
269 NB_FF_OF_SYNC => 2)
270 PORT MAP (
271 clk => clk,
272 rstn => rstn,
273 A => sample_filter_v2_out_reg_val,
274 A_sync => sample_filter_v2_out_reg_val_s);
259 --SYNC_FF_1 : SYNC_FF
260 -- GENERIC MAP (
261 -- NB_FF_OF_SYNC => 2)
262 -- PORT MAP (
263 -- clk => clk,
264 -- rstn => rstn,
265 -- A => sample_filter_v2_out_reg_val,
266 -- A_sync => sample_filter_v2_out_reg_val_s);
275 267
276 SYNC_FF_2 : SYNC_FF
277 GENERIC MAP (
278 NB_FF_OF_SYNC => 2)
279 PORT MAP (
280 clk => cnv_clk,
281 rstn => cnv_rstn,
282 A => sample_filter_v2_out_reg_val_s,
283 A_sync => sample_filter_v2_out_reg_val_s2);
268 --SYNC_FF_2 : SYNC_FF
269 -- GENERIC MAP (
270 -- NB_FF_OF_SYNC => 2)
271 -- PORT MAP (
272 -- clk => cnv_clk,
273 -- rstn => cnv_rstn,
274 -- A => sample_filter_v2_out_reg_val_s,
275 -- A_sync => sample_filter_v2_out_reg_val_s2);
284 276
285 277
286 PROCESS (clk, rstn)
287 BEGIN -- PROCESS
288 IF rstn = '0' THEN -- asynchronous reset (active low)
289 sample_filter_v2_out_sync_val_t <= '0';
290 sample_filter_v2_out_sync_val <= '0';
291 only_one_hot <= '0';
292 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
293 sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
294 only_one_hot <= sample_filter_v2_out_reg_val_s;
295 sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
296 END IF;
297 END PROCESS;
278 --PROCESS (clk, rstn)
279 --BEGIN -- PROCESS
280 -- IF rstn = '0' THEN -- asynchronous reset (active low)
281 -- sample_filter_v2_out_sync_val_t <= '0';
282 -- sample_filter_v2_out_sync_val <= '0';
283 -- only_one_hot <= '0';
284 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
285 -- sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
286 -- only_one_hot <= sample_filter_v2_out_reg_val_s;
287 -- sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
288 -- END IF;
289 --END PROCESS;
298 290
299 291
300 all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
301 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
302 PROCESS (clk, cnv_rstn)
303 BEGIN -- PROCESS
304 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
305 sample_filter_v2_out_sync(I,J) <= '0';
306 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
307 IF sample_filter_v2_out_sync_val_t = '1' THEN
308 sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
309 END IF;
310 END IF;
311 END PROCESS;
312 END GENERATE all_data_reg;
313 END GENERATE all_sample_reg2;
292 --all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
293 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
294 -- PROCESS (clk, cnv_rstn)
295 -- BEGIN -- PROCESS
296 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
297 -- sample_filter_v2_out_sync(I,J) <= '0';
298 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
299 -- IF sample_filter_v2_out_sync_val_t = '1' THEN
300 -- sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
301 -- END IF;
302 -- END IF;
303 -- END PROCESS;
304 -- END GENERATE all_data_reg;
305 --END GENERATE all_sample_reg2;
314 306
315 307
316 308 -----------------------------------------------------------------------------
317 309 -- DATA_SHAPING
318 310 -----------------------------------------------------------------------------
319 311 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
320 sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
321 sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
322 sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
312 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
313 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
314 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
323 315 END GENERATE all_data_shaping_in_loop;
324 316
325 317 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
@@ -330,7 +322,7 BEGIN
330 322 IF rstn = '0' THEN -- asynchronous reset (active low)
331 323 sample_data_shaping_out_val <= '0';
332 324 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
333 sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
325 sample_data_shaping_out_val <= sample_filter_v2_out_val;
334 326 END IF;
335 327 END PROCESS;
336 328
@@ -347,22 +339,22 BEGIN
347 339 sample_data_shaping_out(6, j) <= '0';
348 340 sample_data_shaping_out(7, j) <= '0';
349 341 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
342 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
351 343 IF data_shaping_SP0 = '1' THEN
352 344 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
353 345 ELSE
354 sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
346 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
355 347 END IF;
356 348 IF data_shaping_SP1 = '1' THEN
357 349 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
358 350 ELSE
359 sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
351 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
360 352 END IF;
361 sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
362 sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
363 sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
364 sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
365 sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
353 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
354 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
355 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
356 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
357 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
366 358 END IF;
367 359 END PROCESS;
368 360 END GENERATE;
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@@ -1,349 +1,349
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
15
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
22 ENTITY top_wf_picker IS
23 GENERIC (
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
35 ENABLE_FILTER : STD_LOGIC := '1'
36 );
37 PORT (
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
41 sample_B : IN Samples14v(2 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
43 sample_val : IN STD_LOGIC;
44
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
49 -- AMBA APB Slave Interface
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
52
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
57 --
58 coarse_time_0 : IN STD_LOGIC;
59
60 --
61 data_shaping_BW : OUT STD_LOGIC
62 );
63 END top_wf_picker;
64
65 ARCHITECTURE tb OF top_wf_picker IS
66
67 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111
112 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
121 CONSTANT ChanelCount : INTEGER := 8;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
123 CONSTANT ncycle_cnv : INTEGER := 250;
124
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
127
128 BEGIN
129
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
132
133
134 ready_matrix_f0_0 <= '0';
135 ready_matrix_f0_1 <= '0';
136 ready_matrix_f1 <= '0';
137 ready_matrix_f2 <= '0';
138 error_anticipating_empty_fifo <= '0';
139 error_bad_component_error <= '0';
140 debug_reg <= (OTHERS => '0');
141
142 lpp_top_apbreg_1 : lpp_top_apbreg
143 GENERIC MAP (
144 nb_burst_available_size => nb_burst_available_size,
145 nb_snapshot_param_size => nb_snapshot_param_size,
146 delta_snapshot_size => delta_snapshot_size,
147 delta_f2_f0_size => delta_f2_f0_size,
148 delta_f2_f1_size => delta_f2_f1_size,
149 pindex => pindex,
150 paddr => paddr,
151 pmask => pmask,
152 pirq => pirq)
153 PORT MAP (
154 HCLK => HCLK,
155 HRESETn => HRESETn,
156 apbi => apbi,
157 apbo => apbo,
158
159 ready_matrix_f0_0 => ready_matrix_f0_0,
160 ready_matrix_f0_1 => ready_matrix_f0_1,
161 ready_matrix_f1 => ready_matrix_f1,
162 ready_matrix_f2 => ready_matrix_f2,
163 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
164 error_bad_component_error => error_bad_component_error,
165 debug_reg => debug_reg,
166 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
167 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
168 status_ready_matrix_f1 => status_ready_matrix_f1,
169 status_ready_matrix_f2 => status_ready_matrix_f2,
170 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
171 status_error_bad_component_error => status_error_bad_component_error,
172 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
173 config_active_interruption_onError => config_active_interruption_onError,
174 addr_matrix_f0_0 => addr_matrix_f0_0,
175 addr_matrix_f0_1 => addr_matrix_f0_1,
176 addr_matrix_f1 => addr_matrix_f1,
177 addr_matrix_f2 => addr_matrix_f2,
178
179 status_full => status_full,
180 status_full_ack => status_full_ack,
181 status_full_err => status_full_err,
182 status_new_err => status_new_err,
183 data_shaping_BW => data_shaping_BW,
184 data_shaping_SP0 => data_shaping_SP0,
185 data_shaping_SP1 => data_shaping_SP1,
186 data_shaping_R0 => data_shaping_R0,
187 data_shaping_R1 => data_shaping_R1,
188 delta_snapshot => delta_snapshot,
189 delta_f2_f1 => delta_f2_f1,
190 delta_f2_f0 => delta_f2_f0,
191 nb_burst_available => nb_burst_available,
192 nb_snapshot_param => nb_snapshot_param,
193 enable_f0 => enable_f0,
194 enable_f1 => enable_f1,
195 enable_f2 => enable_f2,
196 enable_f3 => enable_f3,
197 burst_f0 => burst_f0,
198 burst_f1 => burst_f1,
199 burst_f2 => burst_f2,
200 addr_data_f0 => addr_data_f0,
201 addr_data_f1 => addr_data_f1,
202 addr_data_f2 => addr_data_f2,
203 addr_data_f3 => addr_data_f3);
204
205
206
207
208 --DIGITAL_acquisition : AD7688_drvr_sync
209 -- GENERIC MAP (
210 -- ChanelCount => ChanelCount,
211 -- ncycle_cnv_high => ncycle_cnv_high,
212 -- ncycle_cnv => ncycle_cnv)
213 -- PORT MAP (
214 -- cnv_clk => cnv_clk, --
215 -- cnv_rstn => cnv_rstn, --
216 -- cnv_run => cnv_run, --
217 -- cnv => cnv, --
218 -- sck => sck, --
219 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
220 -- sample => sample,
221 -- sample_val => sample_val);
222
223 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
224 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
225 END GENERATE all_channel;
226
227
228 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
229
230 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
231 GENERIC MAP (
232 hindex => hindex,
233 nb_burst_available_size => nb_burst_available_size,
234 nb_snapshot_param_size => nb_snapshot_param_size,
235 delta_snapshot_size => delta_snapshot_size,
236 delta_f2_f0_size => delta_f2_f0_size,
237 delta_f2_f1_size => delta_f2_f1_size,
238 tech => tech,
239 Mem_use => use_RAM
240 )
241 PORT MAP (
242 sample => sample_s,
243 sample_val => sample_val,
244
245 cnv_clk => HCLK,--cnv_clk,
246 cnv_rstn => HRESETn,--cnv_rstn,
247
248 clk => HCLK,
249 rstn => HRESETn,
250
251 sample_f0_wen => sample_f0_wen,
252 sample_f0_wdata => sample_f0_wdata,
253 sample_f1_wen => sample_f1_wen,
254 sample_f1_wdata => sample_f1_wdata,
255 sample_f2_wen => sample_f2_wen,
256 sample_f2_wdata => sample_f2_wdata,
257 sample_f3_wen => sample_f3_wen,
258 sample_f3_wdata => sample_f3_wdata,
259 AHB_Master_In => AHB_Master_In,
260 AHB_Master_Out => AHB_Master_Out,
261 coarse_time_0 => coarse_time_0,
262 data_shaping_SP0 => data_shaping_SP0,
263 data_shaping_SP1 => data_shaping_SP1,
264 data_shaping_R0 => data_shaping_R0,
265 data_shaping_R1 => data_shaping_R1,
266 delta_snapshot => delta_snapshot,
267 delta_f2_f1 => delta_f2_f1,
268 delta_f2_f0 => delta_f2_f0,
269 enable_f0 => enable_f0,
270 enable_f1 => enable_f1,
271 enable_f2 => enable_f2,
272 enable_f3 => enable_f3,
273 burst_f0 => burst_f0,
274 burst_f1 => burst_f1,
275 burst_f2 => burst_f2,
276 nb_burst_available => nb_burst_available,
277 nb_snapshot_param => nb_snapshot_param,
278 status_full => status_full,
279 status_full_ack => status_full_ack,
280 status_full_err => status_full_err,
281 status_new_err => status_new_err,
282 addr_data_f0 => addr_data_f0,
283 addr_data_f1 => addr_data_f1,
284 addr_data_f2 => addr_data_f2,
285 addr_data_f3 => addr_data_f3);
286
287 END GENERATE wf_picker_with_filter;
288
289
290 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
291
292 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
293 GENERIC MAP (
294 hindex => hindex,
295 nb_burst_available_size => nb_burst_available_size,
296 nb_snapshot_param_size => nb_snapshot_param_size,
297 delta_snapshot_size => delta_snapshot_size,
298 delta_f2_f0_size => delta_f2_f0_size,
299 delta_f2_f1_size => delta_f2_f1_size,
300 tech => tech
301 )
302 PORT MAP (
303 sample => sample_s,
304 sample_val => sample_val,
305
306 cnv_clk => cnv_clk,
307 cnv_rstn => cnv_rstn,
308
309 clk => HCLK,
310 rstn => HRESETn,
311
312 sample_f0_wen => sample_f0_wen,
313 sample_f0_wdata => sample_f0_wdata,
314 sample_f1_wen => sample_f1_wen,
315 sample_f1_wdata => sample_f1_wdata,
316 sample_f2_wen => sample_f2_wen,
317 sample_f2_wdata => sample_f2_wdata,
318 sample_f3_wen => sample_f3_wen,
319 sample_f3_wdata => sample_f3_wdata,
320 AHB_Master_In => AHB_Master_In,
321 AHB_Master_Out => AHB_Master_Out,
322 coarse_time_0 => coarse_time_0,
323 data_shaping_SP0 => data_shaping_SP0,
324 data_shaping_SP1 => data_shaping_SP1,
325 data_shaping_R0 => data_shaping_R0,
326 data_shaping_R1 => data_shaping_R1,
327 delta_snapshot => delta_snapshot,
328 delta_f2_f1 => delta_f2_f1,
329 delta_f2_f0 => delta_f2_f0,
330 enable_f0 => enable_f0,
331 enable_f1 => enable_f1,
332 enable_f2 => enable_f2,
333 enable_f3 => enable_f3,
334 burst_f0 => burst_f0,
335 burst_f1 => burst_f1,
336 burst_f2 => burst_f2,
337 nb_burst_available => nb_burst_available,
338 nb_snapshot_param => nb_snapshot_param,
339 status_full => status_full,
340 status_full_ack => status_full_ack,
341 status_full_err => status_full_err,
342 status_new_err => status_new_err,
343 addr_data_f0 => addr_data_f0,
344 addr_data_f1 => addr_data_f1,
345 addr_data_f2 => addr_data_f2,
346 addr_data_f3 => addr_data_f3);
347
348 END GENERATE wf_picker_without_filter;
349 END tb;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
15
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
22 ENTITY top_wf_picker IS
23 GENERIC (
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
35 ENABLE_FILTER : STD_LOGIC := '1'
36 );
37 PORT (
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
41 sample_B : IN Samples14v(2 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
43 sample_val : IN STD_LOGIC;
44
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
49 -- AMBA APB Slave Interface
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
52
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
57 --
58 coarse_time_0 : IN STD_LOGIC;
59
60 --
61 data_shaping_BW : OUT STD_LOGIC
62 );
63 END top_wf_picker;
64
65 ARCHITECTURE tb OF top_wf_picker IS
66
67 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111
112 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
121 CONSTANT ChanelCount : INTEGER := 8;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
123 CONSTANT ncycle_cnv : INTEGER := 250;
124
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
127
128 BEGIN
129
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
132
133
134 ready_matrix_f0_0 <= '0';
135 ready_matrix_f0_1 <= '0';
136 ready_matrix_f1 <= '0';
137 ready_matrix_f2 <= '0';
138 error_anticipating_empty_fifo <= '0';
139 error_bad_component_error <= '0';
140 debug_reg <= (OTHERS => '0');
141
142 lpp_top_apbreg_1 : lpp_top_apbreg
143 GENERIC MAP (
144 nb_burst_available_size => nb_burst_available_size,
145 nb_snapshot_param_size => nb_snapshot_param_size,
146 delta_snapshot_size => delta_snapshot_size,
147 delta_f2_f0_size => delta_f2_f0_size,
148 delta_f2_f1_size => delta_f2_f1_size,
149 pindex => pindex,
150 paddr => paddr,
151 pmask => pmask,
152 pirq => pirq)
153 PORT MAP (
154 HCLK => HCLK,
155 HRESETn => HRESETn,
156 apbi => apbi,
157 apbo => apbo,
158
159 ready_matrix_f0_0 => ready_matrix_f0_0,
160 ready_matrix_f0_1 => ready_matrix_f0_1,
161 ready_matrix_f1 => ready_matrix_f1,
162 ready_matrix_f2 => ready_matrix_f2,
163 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
164 error_bad_component_error => error_bad_component_error,
165 debug_reg => debug_reg,
166 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
167 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
168 status_ready_matrix_f1 => status_ready_matrix_f1,
169 status_ready_matrix_f2 => status_ready_matrix_f2,
170 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
171 status_error_bad_component_error => status_error_bad_component_error,
172 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
173 config_active_interruption_onError => config_active_interruption_onError,
174 addr_matrix_f0_0 => addr_matrix_f0_0,
175 addr_matrix_f0_1 => addr_matrix_f0_1,
176 addr_matrix_f1 => addr_matrix_f1,
177 addr_matrix_f2 => addr_matrix_f2,
178
179 status_full => status_full,
180 status_full_ack => status_full_ack,
181 status_full_err => status_full_err,
182 status_new_err => status_new_err,
183 data_shaping_BW => data_shaping_BW,
184 data_shaping_SP0 => data_shaping_SP0,
185 data_shaping_SP1 => data_shaping_SP1,
186 data_shaping_R0 => data_shaping_R0,
187 data_shaping_R1 => data_shaping_R1,
188 delta_snapshot => delta_snapshot,
189 delta_f2_f1 => delta_f2_f1,
190 delta_f2_f0 => delta_f2_f0,
191 nb_burst_available => nb_burst_available,
192 nb_snapshot_param => nb_snapshot_param,
193 enable_f0 => enable_f0,
194 enable_f1 => enable_f1,
195 enable_f2 => enable_f2,
196 enable_f3 => enable_f3,
197 burst_f0 => burst_f0,
198 burst_f1 => burst_f1,
199 burst_f2 => burst_f2,
200 addr_data_f0 => addr_data_f0,
201 addr_data_f1 => addr_data_f1,
202 addr_data_f2 => addr_data_f2,
203 addr_data_f3 => addr_data_f3);
204
205
206
207
208 --DIGITAL_acquisition : AD7688_drvr_sync
209 -- GENERIC MAP (
210 -- ChanelCount => ChanelCount,
211 -- ncycle_cnv_high => ncycle_cnv_high,
212 -- ncycle_cnv => ncycle_cnv)
213 -- PORT MAP (
214 -- cnv_clk => cnv_clk, --
215 -- cnv_rstn => cnv_rstn, --
216 -- cnv_run => cnv_run, --
217 -- cnv => cnv, --
218 -- sck => sck, --
219 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
220 -- sample => sample,
221 -- sample_val => sample_val);
222
223 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
224 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
225 END GENERATE all_channel;
226
227
228 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
229
230 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
231 GENERIC MAP (
232 hindex => hindex,
233 nb_burst_available_size => nb_burst_available_size,
234 nb_snapshot_param_size => nb_snapshot_param_size,
235 delta_snapshot_size => delta_snapshot_size,
236 delta_f2_f0_size => delta_f2_f0_size,
237 delta_f2_f1_size => delta_f2_f1_size,
238 tech => tech,
239 Mem_use => use_RAM
240 )
241 PORT MAP (
242 sample => sample_s,
243 sample_val => sample_val,
244
245 -- cnv_clk => HCLK,--cnv_clk,
246 -- cnv_rstn => HRESETn,--cnv_rstn,
247
248 clk => HCLK,
249 rstn => HRESETn,
250
251 sample_f0_wen => sample_f0_wen,
252 sample_f0_wdata => sample_f0_wdata,
253 sample_f1_wen => sample_f1_wen,
254 sample_f1_wdata => sample_f1_wdata,
255 sample_f2_wen => sample_f2_wen,
256 sample_f2_wdata => sample_f2_wdata,
257 sample_f3_wen => sample_f3_wen,
258 sample_f3_wdata => sample_f3_wdata,
259 AHB_Master_In => AHB_Master_In,
260 AHB_Master_Out => AHB_Master_Out,
261 coarse_time_0 => coarse_time_0,
262 data_shaping_SP0 => data_shaping_SP0,
263 data_shaping_SP1 => data_shaping_SP1,
264 data_shaping_R0 => data_shaping_R0,
265 data_shaping_R1 => data_shaping_R1,
266 delta_snapshot => delta_snapshot,
267 delta_f2_f1 => delta_f2_f1,
268 delta_f2_f0 => delta_f2_f0,
269 enable_f0 => enable_f0,
270 enable_f1 => enable_f1,
271 enable_f2 => enable_f2,
272 enable_f3 => enable_f3,
273 burst_f0 => burst_f0,
274 burst_f1 => burst_f1,
275 burst_f2 => burst_f2,
276 nb_burst_available => nb_burst_available,
277 nb_snapshot_param => nb_snapshot_param,
278 status_full => status_full,
279 status_full_ack => status_full_ack,
280 status_full_err => status_full_err,
281 status_new_err => status_new_err,
282 addr_data_f0 => addr_data_f0,
283 addr_data_f1 => addr_data_f1,
284 addr_data_f2 => addr_data_f2,
285 addr_data_f3 => addr_data_f3);
286
287 END GENERATE wf_picker_with_filter;
288
289
290 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
291
292 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
293 GENERIC MAP (
294 hindex => hindex,
295 nb_burst_available_size => nb_burst_available_size,
296 nb_snapshot_param_size => nb_snapshot_param_size,
297 delta_snapshot_size => delta_snapshot_size,
298 delta_f2_f0_size => delta_f2_f0_size,
299 delta_f2_f1_size => delta_f2_f1_size,
300 tech => tech
301 )
302 PORT MAP (
303 sample => sample_s,
304 sample_val => sample_val,
305
306 cnv_clk => cnv_clk,
307 cnv_rstn => cnv_rstn,
308
309 clk => HCLK,
310 rstn => HRESETn,
311
312 sample_f0_wen => sample_f0_wen,
313 sample_f0_wdata => sample_f0_wdata,
314 sample_f1_wen => sample_f1_wen,
315 sample_f1_wdata => sample_f1_wdata,
316 sample_f2_wen => sample_f2_wen,
317 sample_f2_wdata => sample_f2_wdata,
318 sample_f3_wen => sample_f3_wen,
319 sample_f3_wdata => sample_f3_wdata,
320 AHB_Master_In => AHB_Master_In,
321 AHB_Master_Out => AHB_Master_Out,
322 coarse_time_0 => coarse_time_0,
323 data_shaping_SP0 => data_shaping_SP0,
324 data_shaping_SP1 => data_shaping_SP1,
325 data_shaping_R0 => data_shaping_R0,
326 data_shaping_R1 => data_shaping_R1,
327 delta_snapshot => delta_snapshot,
328 delta_f2_f1 => delta_f2_f1,
329 delta_f2_f0 => delta_f2_f0,
330 enable_f0 => enable_f0,
331 enable_f1 => enable_f1,
332 enable_f2 => enable_f2,
333 enable_f3 => enable_f3,
334 burst_f0 => burst_f0,
335 burst_f1 => burst_f1,
336 burst_f2 => burst_f2,
337 nb_burst_available => nb_burst_available,
338 nb_snapshot_param => nb_snapshot_param,
339 status_full => status_full,
340 status_full_ack => status_full_ack,
341 status_full_err => status_full_err,
342 status_new_err => status_new_err,
343 addr_data_f0 => addr_data_f0,
344 addr_data_f1 => addr_data_f1,
345 addr_data_f2 => addr_data_f2,
346 addr_data_f3 => addr_data_f3);
347
348 END GENERATE wf_picker_without_filter;
349 END tb; No newline at end of file
Show file before | Show file after | Hide comments
@@ -268,7 +268,6 BEGIN -- beh
268 268 status_full => status_full,
269 269 status_full_ack => status_full_ack,
270 270 status_full_err => status_full_err,
271 -- status_new_err => status_new_err,
272 271 addr_data_f0 => addr_data_f0,
273 272 addr_data_f1 => addr_data_f1,
274 273 addr_data_f2 => addr_data_f2,
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