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Remove "Sync Stage" between Filter and DownSampler into waveformPicker
pellion -
r205:6eb3be2045fd JC
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1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_top_lfr_pkg IS
16 16
17 17 COMPONENT lpp_top_acq
18 18 GENERIC(
19 19 tech : INTEGER := 0;
20 20 Mem_use : integer := use_RAM
21 21 );
22 22 PORT (
23 23 -- ADS7886
24 24 cnv_run : IN STD_LOGIC;
25 25 cnv : OUT STD_LOGIC;
26 26 sck : OUT STD_LOGIC;
27 27 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
28 28 --
29 29 cnv_clk : IN STD_LOGIC; -- 49 MHz
30 30 cnv_rstn : IN STD_LOGIC;
31 31 --
32 32 clk : IN STD_LOGIC; -- 25 MHz
33 33 rstn : IN STD_LOGIC;
34 34 --
35 35 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40 --
41 41 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 42 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
43 43 --
44 44 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
46 46 );
47 47 END COMPONENT;
48 48
49 49 COMPONENT lpp_top_apbreg
50 50 GENERIC (
51 51 nb_burst_available_size : INTEGER;
52 52 nb_snapshot_param_size : INTEGER;
53 53 delta_snapshot_size : INTEGER;
54 54 delta_f2_f0_size : INTEGER;
55 55 delta_f2_f1_size : INTEGER;
56 56 pindex : INTEGER;
57 57 paddr : INTEGER;
58 58 pmask : INTEGER;
59 59 pirq : INTEGER);
60 60 PORT (
61 61 HCLK : IN STD_ULOGIC;
62 62 HRESETn : IN STD_ULOGIC;
63 63 apbi : IN apb_slv_in_type;
64 64 apbo : OUT apb_slv_out_type;
65 65 ready_matrix_f0_0 : IN STD_LOGIC;
66 66 ready_matrix_f0_1 : IN STD_LOGIC;
67 67 ready_matrix_f1 : IN STD_LOGIC;
68 68 ready_matrix_f2 : IN STD_LOGIC;
69 69 error_anticipating_empty_fifo : IN STD_LOGIC;
70 70 error_bad_component_error : IN STD_LOGIC;
71 71 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 77 status_error_bad_component_error : OUT STD_LOGIC;
78 78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 79 config_active_interruption_onError : OUT STD_LOGIC;
80 80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 85 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 86 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 88 data_shaping_BW : OUT STD_LOGIC;
89 89 data_shaping_SP0 : OUT STD_LOGIC;
90 90 data_shaping_SP1 : OUT STD_LOGIC;
91 91 data_shaping_R0 : OUT STD_LOGIC;
92 92 data_shaping_R1 : OUT STD_LOGIC;
93 93 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
94 94 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
95 95 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
96 96 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
97 97 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
98 98 enable_f0 : OUT STD_LOGIC;
99 99 enable_f1 : OUT STD_LOGIC;
100 100 enable_f2 : OUT STD_LOGIC;
101 101 enable_f3 : OUT STD_LOGIC;
102 102 burst_f0 : OUT STD_LOGIC;
103 103 burst_f1 : OUT STD_LOGIC;
104 104 burst_f2 : OUT STD_LOGIC;
105 105 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
109 109 END COMPONENT;
110 110
111 111 COMPONENT lpp_top_lfr_wf_picker
112 112 GENERIC (
113 113 hindex : INTEGER;
114 114 pindex : INTEGER;
115 115 paddr : INTEGER;
116 116 pmask : INTEGER;
117 117 pirq : INTEGER;
118 118 tech : INTEGER;
119 119 nb_burst_available_size : INTEGER;
120 120 nb_snapshot_param_size : INTEGER;
121 121 delta_snapshot_size : INTEGER;
122 122 delta_f2_f0_size : INTEGER;
123 123 delta_f2_f1_size : INTEGER;
124 124 ENABLE_FILTER : STD_LOGIC);
125 125 PORT (
126 126 cnv_run : IN STD_LOGIC;
127 127 cnv : OUT STD_LOGIC;
128 128 sck : OUT STD_LOGIC;
129 129 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
130 130 cnv_clk : IN STD_LOGIC;
131 131 cnv_rstn : IN STD_LOGIC;
132 132 HCLK : IN STD_ULOGIC;
133 133 HRESETn : IN STD_ULOGIC;
134 134 apbi : IN apb_slv_in_type;
135 135 apbo : OUT apb_slv_out_type;
136 136 AHB_Master_In : IN AHB_Mst_In_Type;
137 137 AHB_Master_Out : OUT AHB_Mst_Out_Type;
138 138 coarse_time_0 : IN STD_LOGIC;
139 139 data_shaping_BW : OUT STD_LOGIC);
140 140 END COMPONENT;
141 141
142 142
143 143 COMPONENT lpp_top_lfr_wf_picker_ip
144 144 GENERIC (
145 145 hindex : INTEGER;
146 146 nb_burst_available_size : INTEGER;
147 147 nb_snapshot_param_size : INTEGER;
148 148 delta_snapshot_size : INTEGER;
149 149 delta_f2_f0_size : INTEGER;
150 150 delta_f2_f1_size : INTEGER;
151 151 tech : INTEGER;
152 152 Mem_use : INTEGER);
153 153 PORT (
154 154 sample : IN Samples(7 DOWNTO 0);
155 155 sample_val : IN STD_LOGIC;
156 cnv_clk : IN STD_LOGIC;
157 cnv_rstn : IN STD_LOGIC;
158 156 clk : IN STD_LOGIC;
159 157 rstn : IN STD_LOGIC;
160 158 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
161 159 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
162 160 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
163 161 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
164 162 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
165 163 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
166 164 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
167 165 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
168 166 AHB_Master_In : IN AHB_Mst_In_Type;
169 167 AHB_Master_Out : OUT AHB_Mst_Out_Type;
170 168 coarse_time_0 : IN STD_LOGIC;
171 169 data_shaping_SP0 : IN STD_LOGIC;
172 170 data_shaping_SP1 : IN STD_LOGIC;
173 171 data_shaping_R0 : IN STD_LOGIC;
174 172 data_shaping_R1 : IN STD_LOGIC;
175 173 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
176 174 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
177 175 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
178 176 enable_f0 : IN STD_LOGIC;
179 177 enable_f1 : IN STD_LOGIC;
180 178 enable_f2 : IN STD_LOGIC;
181 179 enable_f3 : IN STD_LOGIC;
182 180 burst_f0 : IN STD_LOGIC;
183 181 burst_f1 : IN STD_LOGIC;
184 182 burst_f2 : IN STD_LOGIC;
185 183 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
186 184 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
187 185 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
188 186 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
189 187 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
190 188 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
191 189 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
192 190 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
193 191 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
194 192 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
195 193 END COMPONENT;
196 194
197 195 COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter
198 196 GENERIC (
199 197 hindex : INTEGER;
200 198 nb_burst_available_size : INTEGER;
201 199 nb_snapshot_param_size : INTEGER;
202 200 delta_snapshot_size : INTEGER;
203 201 delta_f2_f0_size : INTEGER;
204 202 delta_f2_f1_size : INTEGER;
205 203 tech : INTEGER);
206 204 PORT (
207 205 sample : IN Samples(7 DOWNTO 0);
208 206 sample_val : IN STD_LOGIC;
209 207 cnv_clk : IN STD_LOGIC;
210 208 cnv_rstn : IN STD_LOGIC;
211 209 clk : IN STD_LOGIC;
212 210 rstn : IN STD_LOGIC;
213 211 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
214 212 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
215 213 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
216 214 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
217 215 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
218 216 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
219 217 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
220 218 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
221 219 AHB_Master_In : IN AHB_Mst_In_Type;
222 220 AHB_Master_Out : OUT AHB_Mst_Out_Type;
223 221 coarse_time_0 : IN STD_LOGIC;
224 222 data_shaping_SP0 : IN STD_LOGIC;
225 223 data_shaping_SP1 : IN STD_LOGIC;
226 224 data_shaping_R0 : IN STD_LOGIC;
227 225 data_shaping_R1 : IN STD_LOGIC;
228 226 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
229 227 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
230 228 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
231 229 enable_f0 : IN STD_LOGIC;
232 230 enable_f1 : IN STD_LOGIC;
233 231 enable_f2 : IN STD_LOGIC;
234 232 enable_f3 : IN STD_LOGIC;
235 233 burst_f0 : IN STD_LOGIC;
236 234 burst_f1 : IN STD_LOGIC;
237 235 burst_f2 : IN STD_LOGIC;
238 236 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
239 237 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
240 238 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
241 239 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
242 240 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
243 241 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
244 242 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 243 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
246 244 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
247 245 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
248 246 END COMPONENT;
249 247
250 248 COMPONENT top_wf_picker
251 249 GENERIC (
252 250 hindex : INTEGER;
253 251 pindex : INTEGER;
254 252 paddr : INTEGER;
255 253 pmask : INTEGER;
256 254 pirq : INTEGER;
257 255 tech : INTEGER;
258 256 nb_burst_available_size : INTEGER;
259 257 nb_snapshot_param_size : INTEGER;
260 258 delta_snapshot_size : INTEGER;
261 259 delta_f2_f0_size : INTEGER;
262 260 delta_f2_f1_size : INTEGER;
263 261 ENABLE_FILTER : STD_LOGIC);
264 262 PORT (
265 263 cnv_clk : IN STD_LOGIC;
266 264 cnv_rstn : IN STD_LOGIC;
267 265 sample_B : IN Samples14v(2 DOWNTO 0);
268 266 sample_E : IN Samples14v(4 DOWNTO 0);
269 267 sample_val : IN STD_LOGIC;
270 268 HCLK : IN STD_ULOGIC;
271 269 HRESETn : IN STD_ULOGIC;
272 270 apbi : IN apb_slv_in_type;
273 271 apbo : OUT apb_slv_out_type;
274 272 AHB_Master_In : IN AHB_Mst_In_Type;
275 273 AHB_Master_Out : OUT AHB_Mst_Out_Type;
276 274 coarse_time_0 : IN STD_LOGIC;
277 275 data_shaping_BW : OUT STD_LOGIC);
278 276 END COMPONENT;
279 277
280 278 END lpp_top_lfr_pkg;
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@@ -1,342 +1,342
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_top_lfr_pkg.ALL;
12 12
13 13 LIBRARY techmap;
14 14 USE techmap.gencomp.ALL;
15 15
16 16 LIBRARY grlib;
17 17 USE grlib.amba.ALL;
18 18 USE grlib.stdlib.ALL;
19 19 USE grlib.devices.ALL;
20 20 USE GRLIB.DMA2AHB_Package.ALL;
21 21
22 22 ENTITY lpp_top_lfr_wf_picker IS
23 23 GENERIC (
24 24 hindex : INTEGER := 2;
25 25 pindex : INTEGER := 15;
26 26 paddr : INTEGER := 15;
27 27 pmask : INTEGER := 16#fff#;
28 28 pirq : INTEGER := 15;
29 29 tech : INTEGER := 0;
30 30 nb_burst_available_size : INTEGER := 11;
31 31 nb_snapshot_param_size : INTEGER := 11;
32 32 delta_snapshot_size : INTEGER := 16;
33 33 delta_f2_f0_size : INTEGER := 10;
34 34 delta_f2_f1_size : INTEGER := 10;
35 35 ENABLE_FILTER : STD_LOGIC := '1'
36 36 );
37 37 PORT (
38 38 -- ADS7886
39 39 cnv_run : IN STD_LOGIC;
40 40 cnv : OUT STD_LOGIC;
41 41 sck : OUT STD_LOGIC;
42 42 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
43 43 --
44 44 cnv_clk : IN STD_LOGIC;
45 45 cnv_rstn : IN STD_LOGIC;
46 46
47 47 -- AMBA AHB system signals
48 48 HCLK : IN STD_ULOGIC;
49 49 HRESETn : IN STD_ULOGIC;
50 50
51 51 -- AMBA APB Slave Interface
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 --
60 60 coarse_time_0 : IN STD_LOGIC;
61 61
62 62 --
63 63 data_shaping_BW : OUT STD_LOGIC
64 64 );
65 65 END lpp_top_lfr_wf_picker;
66 66
67 67 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
68 68
69 69 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
70 70 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
71 71 SIGNAL ready_matrix_f1 : STD_LOGIC;
72 72 SIGNAL ready_matrix_f2 : STD_LOGIC;
73 73 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
74 74 SIGNAL error_bad_component_error : STD_LOGIC;
75 75 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
77 77 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
78 78 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
79 79 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
80 80 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
81 81 SIGNAL status_error_bad_component_error : STD_LOGIC;
82 82 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
83 83 SIGNAL config_active_interruption_onError : STD_LOGIC;
84 84 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88
89 89 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 90 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92 92 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
93 93 SIGNAL data_shaping_SP0 : STD_LOGIC;
94 94 SIGNAL data_shaping_SP1 : STD_LOGIC;
95 95 SIGNAL data_shaping_R0 : STD_LOGIC;
96 96 SIGNAL data_shaping_R1 : STD_LOGIC;
97 97 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
98 98 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
99 99 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
100 100 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
101 101 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
102 102 SIGNAL enable_f0 : STD_LOGIC;
103 103 SIGNAL enable_f1 : STD_LOGIC;
104 104 SIGNAL enable_f2 : STD_LOGIC;
105 105 SIGNAL enable_f3 : STD_LOGIC;
106 106 SIGNAL burst_f0 : STD_LOGIC;
107 107 SIGNAL burst_f1 : STD_LOGIC;
108 108 SIGNAL burst_f2 : STD_LOGIC;
109 109 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 111 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 112 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113 113
114 114 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 115 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 117 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 118 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 119 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 120 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
121 121 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
122 122
123 123 CONSTANT ChanelCount : INTEGER := 8;
124 124 CONSTANT ncycle_cnv_high : INTEGER := 40;
125 125 CONSTANT ncycle_cnv : INTEGER := 250;
126 126 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
127 127 SIGNAL sample_val : STD_LOGIC;
128 128
129 129 BEGIN
130 130
131 131 ready_matrix_f0_0 <= '0';
132 132 ready_matrix_f0_1 <= '0';
133 133 ready_matrix_f1 <= '0';
134 134 ready_matrix_f2 <= '0';
135 135 error_anticipating_empty_fifo <= '0';
136 136 error_bad_component_error <= '0';
137 137 debug_reg <= (OTHERS => '0');
138 138
139 139 lpp_top_apbreg_1 : lpp_top_apbreg
140 140 GENERIC MAP (
141 141 nb_burst_available_size => nb_burst_available_size,
142 142 nb_snapshot_param_size => nb_snapshot_param_size,
143 143 delta_snapshot_size => delta_snapshot_size,
144 144 delta_f2_f0_size => delta_f2_f0_size,
145 145 delta_f2_f1_size => delta_f2_f1_size,
146 146 pindex => pindex,
147 147 paddr => paddr,
148 148 pmask => pmask,
149 149 pirq => pirq)
150 150 PORT MAP (
151 151 HCLK => HCLK,
152 152 HRESETn => HRESETn,
153 153 apbi => apbi,
154 154 apbo => apbo,
155 155
156 156 ready_matrix_f0_0 => ready_matrix_f0_0,
157 157 ready_matrix_f0_1 => ready_matrix_f0_1,
158 158 ready_matrix_f1 => ready_matrix_f1,
159 159 ready_matrix_f2 => ready_matrix_f2,
160 160 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
161 161 error_bad_component_error => error_bad_component_error,
162 162 debug_reg => debug_reg,
163 163 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
164 164 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
165 165 status_ready_matrix_f1 => status_ready_matrix_f1,
166 166 status_ready_matrix_f2 => status_ready_matrix_f2,
167 167 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
168 168 status_error_bad_component_error => status_error_bad_component_error,
169 169 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
170 170 config_active_interruption_onError => config_active_interruption_onError,
171 171 addr_matrix_f0_0 => addr_matrix_f0_0,
172 172 addr_matrix_f0_1 => addr_matrix_f0_1,
173 173 addr_matrix_f1 => addr_matrix_f1,
174 174 addr_matrix_f2 => addr_matrix_f2,
175 175
176 176 status_full => status_full,
177 177 status_full_ack => status_full_ack,
178 178 status_full_err => status_full_err,
179 179 status_new_err => status_new_err,
180 180 data_shaping_BW => data_shaping_BW,
181 181 data_shaping_SP0 => data_shaping_SP0,
182 182 data_shaping_SP1 => data_shaping_SP1,
183 183 data_shaping_R0 => data_shaping_R0,
184 184 data_shaping_R1 => data_shaping_R1,
185 185 delta_snapshot => delta_snapshot,
186 186 delta_f2_f1 => delta_f2_f1,
187 187 delta_f2_f0 => delta_f2_f0,
188 188 nb_burst_available => nb_burst_available,
189 189 nb_snapshot_param => nb_snapshot_param,
190 190 enable_f0 => enable_f0,
191 191 enable_f1 => enable_f1,
192 192 enable_f2 => enable_f2,
193 193 enable_f3 => enable_f3,
194 194 burst_f0 => burst_f0,
195 195 burst_f1 => burst_f1,
196 196 burst_f2 => burst_f2,
197 197 addr_data_f0 => addr_data_f0,
198 198 addr_data_f1 => addr_data_f1,
199 199 addr_data_f2 => addr_data_f2,
200 200 addr_data_f3 => addr_data_f3);
201 201
202 202
203 203
204 204
205 205 DIGITAL_acquisition : AD7688_drvr_sync
206 206 GENERIC MAP (
207 207 ChanelCount => ChanelCount,
208 208 ncycle_cnv_high => ncycle_cnv_high,
209 209 ncycle_cnv => ncycle_cnv)
210 210 PORT MAP (
211 211 cnv_clk => cnv_clk, --
212 212 cnv_rstn => cnv_rstn, --
213 213 cnv_run => cnv_run, --
214 214 cnv => cnv, --
215 215 sck => sck, --
216 216 sdo => sdo(ChanelCount-1 DOWNTO 0), --
217 217 sample => sample,
218 218 sample_val => sample_val);
219 219
220 220
221 221 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
222 222
223 223 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
224 224 GENERIC MAP (
225 225 hindex => hindex,
226 226 nb_burst_available_size => nb_burst_available_size,
227 227 nb_snapshot_param_size => nb_snapshot_param_size,
228 228 delta_snapshot_size => delta_snapshot_size,
229 229 delta_f2_f0_size => delta_f2_f0_size,
230 230 delta_f2_f1_size => delta_f2_f1_size,
231 231 tech => tech,
232 232 Mem_use => lpp.iir_filter.use_RAM
233 233 )
234 234 PORT MAP (
235 235 sample => sample,
236 236 sample_val => sample_val,
237 237
238 cnv_clk => cnv_clk,
239 cnv_rstn => cnv_rstn,
238 -- cnv_clk => cnv_clk,
239 -- cnv_rstn => cnv_rstn,
240 240
241 241 clk => HCLK,
242 242 rstn => HRESETn,
243 243
244 244 sample_f0_wen => sample_f0_wen,
245 245 sample_f0_wdata => sample_f0_wdata,
246 246 sample_f1_wen => sample_f1_wen,
247 247 sample_f1_wdata => sample_f1_wdata,
248 248 sample_f2_wen => sample_f2_wen,
249 249 sample_f2_wdata => sample_f2_wdata,
250 250 sample_f3_wen => sample_f3_wen,
251 251 sample_f3_wdata => sample_f3_wdata,
252 252 AHB_Master_In => AHB_Master_In,
253 253 AHB_Master_Out => AHB_Master_Out,
254 254 coarse_time_0 => coarse_time_0,
255 255 data_shaping_SP0 => data_shaping_SP0,
256 256 data_shaping_SP1 => data_shaping_SP1,
257 257 data_shaping_R0 => data_shaping_R0,
258 258 data_shaping_R1 => data_shaping_R1,
259 259 delta_snapshot => delta_snapshot,
260 260 delta_f2_f1 => delta_f2_f1,
261 261 delta_f2_f0 => delta_f2_f0,
262 262 enable_f0 => enable_f0,
263 263 enable_f1 => enable_f1,
264 264 enable_f2 => enable_f2,
265 265 enable_f3 => enable_f3,
266 266 burst_f0 => burst_f0,
267 267 burst_f1 => burst_f1,
268 268 burst_f2 => burst_f2,
269 269 nb_burst_available => nb_burst_available,
270 270 nb_snapshot_param => nb_snapshot_param,
271 271 status_full => status_full,
272 272 status_full_ack => status_full_ack,
273 273 status_full_err => status_full_err,
274 274 status_new_err => status_new_err,
275 275 addr_data_f0 => addr_data_f0,
276 276 addr_data_f1 => addr_data_f1,
277 277 addr_data_f2 => addr_data_f2,
278 278 addr_data_f3 => addr_data_f3);
279 279
280 280 END GENERATE wf_picker_with_filter;
281 281
282 282
283 283 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
284 284
285 285 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
286 286 GENERIC MAP (
287 287 hindex => hindex,
288 288 nb_burst_available_size => nb_burst_available_size,
289 289 nb_snapshot_param_size => nb_snapshot_param_size,
290 290 delta_snapshot_size => delta_snapshot_size,
291 291 delta_f2_f0_size => delta_f2_f0_size,
292 292 delta_f2_f1_size => delta_f2_f1_size,
293 293 tech => tech
294 294 )
295 295 PORT MAP (
296 296 sample => sample,
297 297 sample_val => sample_val,
298 298
299 299 cnv_clk => cnv_clk,
300 300 cnv_rstn => cnv_rstn,
301 301
302 302 clk => HCLK,
303 303 rstn => HRESETn,
304 304
305 305 sample_f0_wen => sample_f0_wen,
306 306 sample_f0_wdata => sample_f0_wdata,
307 307 sample_f1_wen => sample_f1_wen,
308 308 sample_f1_wdata => sample_f1_wdata,
309 309 sample_f2_wen => sample_f2_wen,
310 310 sample_f2_wdata => sample_f2_wdata,
311 311 sample_f3_wen => sample_f3_wen,
312 312 sample_f3_wdata => sample_f3_wdata,
313 313 AHB_Master_In => AHB_Master_In,
314 314 AHB_Master_Out => AHB_Master_Out,
315 315 coarse_time_0 => coarse_time_0,
316 316 data_shaping_SP0 => data_shaping_SP0,
317 317 data_shaping_SP1 => data_shaping_SP1,
318 318 data_shaping_R0 => data_shaping_R0,
319 319 data_shaping_R1 => data_shaping_R1,
320 320 delta_snapshot => delta_snapshot,
321 321 delta_f2_f1 => delta_f2_f1,
322 322 delta_f2_f0 => delta_f2_f0,
323 323 enable_f0 => enable_f0,
324 324 enable_f1 => enable_f1,
325 325 enable_f2 => enable_f2,
326 326 enable_f3 => enable_f3,
327 327 burst_f0 => burst_f0,
328 328 burst_f1 => burst_f1,
329 329 burst_f2 => burst_f2,
330 330 nb_burst_available => nb_burst_available,
331 331 nb_snapshot_param => nb_snapshot_param,
332 332 status_full => status_full,
333 333 status_full_ack => status_full_ack,
334 334 status_full_err => status_full_err,
335 335 status_new_err => status_new_err,
336 336 addr_data_f0 => addr_data_f0,
337 337 addr_data_f1 => addr_data_f1,
338 338 addr_data_f2 => addr_data_f2,
339 339 addr_data_f3 => addr_data_f3);
340 340
341 341 END GENERATE wf_picker_without_filter;
342 342 END tb;
Show file before | Show file after | Hide comments
@@ -1,587 +1,579
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.general_purpose.SYNC_FF;
12 12
13 13 LIBRARY techmap;
14 14 USE techmap.gencomp.ALL;
15 15
16 16 LIBRARY grlib;
17 17 USE grlib.amba.ALL;
18 18 USE grlib.stdlib.ALL;
19 19 USE grlib.devices.ALL;
20 20 USE GRLIB.DMA2AHB_Package.ALL;
21 21
22 22 ENTITY lpp_top_lfr_wf_picker_ip IS
23 23 GENERIC(
24 24 hindex : INTEGER := 2;
25 25 nb_burst_available_size : INTEGER := 11;
26 26 nb_snapshot_param_size : INTEGER := 11;
27 27 delta_snapshot_size : INTEGER := 16;
28 28 delta_f2_f0_size : INTEGER := 10;
29 29 delta_f2_f1_size : INTEGER := 10;
30 30 tech : INTEGER := 0;
31 31 Mem_use : INTEGER := use_RAM
32 32 );
33 33 PORT (
34 -- ADS7886
35 -- cnv_run : IN STD_LOGIC;
36 -- cnv : OUT STD_LOGIC;
37 -- sck : OUT STD_LOGIC;
38 -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
39 34 sample : IN Samples(7 DOWNTO 0);
40 35 sample_val : IN STD_LOGIC;
41 36 --
42 cnv_clk : IN STD_LOGIC;
43 cnv_rstn : IN STD_LOGIC;
44 --
45 37 clk : IN STD_LOGIC;
46 38 rstn : IN STD_LOGIC;
47 39 --
48 40 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
49 41 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
50 42 --
51 43 sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
52 44 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
53 45 --
54 46 sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
55 47 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
56 48 --
57 49 sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
58 50 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
59 51
60 52 -- AMBA AHB Master Interface
61 53 AHB_Master_In : IN AHB_Mst_In_Type;
62 54 AHB_Master_Out : OUT AHB_Mst_Out_Type;
63 55
64 56 coarse_time_0 : IN STD_LOGIC;
65 57
66 58 --config
67 59 data_shaping_SP0 : IN STD_LOGIC;
68 60 data_shaping_SP1 : IN STD_LOGIC;
69 61 data_shaping_R0 : IN STD_LOGIC;
70 62 data_shaping_R1 : IN STD_LOGIC;
71 63
72 64 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
73 65 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
74 66 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
75 67
76 68 enable_f0 : IN STD_LOGIC;
77 69 enable_f1 : IN STD_LOGIC;
78 70 enable_f2 : IN STD_LOGIC;
79 71 enable_f3 : IN STD_LOGIC;
80 72
81 73 burst_f0 : IN STD_LOGIC;
82 74 burst_f1 : IN STD_LOGIC;
83 75 burst_f2 : IN STD_LOGIC;
84 76
85 77 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
86 78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
87 79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
91 83
92 84 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 85 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 86 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
95 87 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
96 88 );
97 89 END lpp_top_lfr_wf_picker_ip;
98 90
99 91 ARCHITECTURE tb OF lpp_top_lfr_wf_picker_ip IS
100 92
101 93 COMPONENT Downsampling
102 94 GENERIC (
103 95 ChanelCount : INTEGER;
104 96 SampleSize : INTEGER;
105 97 DivideParam : INTEGER);
106 98 PORT (
107 99 clk : IN STD_LOGIC;
108 100 rstn : IN STD_LOGIC;
109 101 sample_in_val : IN STD_LOGIC;
110 102 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
111 103 sample_out_val : OUT STD_LOGIC;
112 104 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
113 105 END COMPONENT;
114 106
115 107 COMPONENT SYNC_FF
116 108 GENERIC (
117 109 NB_FF_OF_SYNC : INTEGER);
118 110 PORT (
119 111 clk : IN STD_LOGIC;
120 112 rstn : IN STD_LOGIC;
121 113 A : IN STD_LOGIC;
122 114 A_sync : OUT STD_LOGIC);
123 115 END COMPONENT;
124 116
125 117 -----------------------------------------------------------------------------
126 118 CONSTANT ChanelCount : INTEGER := 8;
127 119
128 120 -----------------------------------------------------------------------------
129 121 SIGNAL sample_val_delay : STD_LOGIC;
130 122 -----------------------------------------------------------------------------
131 123 CONSTANT Coef_SZ : INTEGER := 9;
132 124 CONSTANT CoefCntPerCel : INTEGER := 6;
133 125 CONSTANT CoefPerCel : INTEGER := 5;
134 126 CONSTANT Cels_count : INTEGER := 5;
135 127
136 128 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
137 129 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
138 130 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
139 131 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
140 132 --
141 133 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
142 134 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
143 135 -----------------------------------------------------------------------------
144 SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 --SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
145 137
146 SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
147 SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
148 SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
149 SIGNAL only_one_hot : STD_LOGIC;
150 SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
151 SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
152 SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
138 --SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
139 --SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
140 --SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
141 --SIGNAL only_one_hot : STD_LOGIC;
142 --SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
143 --SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
144 --SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
153 145 -----------------------------------------------------------------------------
154 146 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
155 147 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
156 148 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
157 149 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
158 150 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
159 151 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
160 152 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
161 153 -----------------------------------------------------------------------------
162 154 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
163 155 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
164 156 -----------------------------------------------------------------------------
165 157 SIGNAL sample_f0_val : STD_LOGIC;
166 158 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
167 159 SIGNAL sample_f0_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
168 160 --
169 161 SIGNAL sample_f1_val : STD_LOGIC;
170 162 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
171 163 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
172 164 --
173 165 SIGNAL sample_f2_val : STD_LOGIC;
174 166 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
175 167 --
176 168 SIGNAL sample_f3_val : STD_LOGIC;
177 169 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
178 170
179 171 -----------------------------------------------------------------------------
180 172 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
181 173 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
182 174 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
183 175 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
184 176 -----------------------------------------------------------------------------
185 177
186 178 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
187 179 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
188 180 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
189 181 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
190 182 BEGIN
191 183
192 184 -----------------------------------------------------------------------------
193 PROCESS (cnv_clk, cnv_rstn)
185 PROCESS (clk, rstn)
194 186 BEGIN -- PROCESS
195 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
187 IF rstn = '0' THEN -- asynchronous reset (active low)
196 188 sample_val_delay <= '0';
197 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
189 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 190 sample_val_delay <= sample_val;
199 191 END IF;
200 192 END PROCESS;
201 193
202 194 -----------------------------------------------------------------------------
203 195 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
204 196 SampleLoop : FOR j IN 0 TO 15 GENERATE
205 197 sample_filter_in(i, j) <= sample(i)(j);
206 198 END GENERATE;
207 199
208 200 sample_filter_in(i, 16) <= sample(i)(15);
209 201 sample_filter_in(i, 17) <= sample(i)(15);
210 202 END GENERATE;
211 203
212 204 coefs_v2 <= CoefsInitValCst_v2;
213 205
214 206 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
215 207 GENERIC MAP (
216 208 tech => 0,
217 209 Mem_use => Mem_use, -- use_RAM
218 210 Sample_SZ => 18,
219 211 Coef_SZ => Coef_SZ,
220 212 Coef_Nb => 25,
221 213 Coef_sel_SZ => 5,
222 214 Cels_count => Cels_count,
223 215 ChanelsCount => ChanelCount)
224 216 PORT MAP (
225 rstn => cnv_rstn,
226 clk => cnv_clk,
217 rstn => rstn,
218 clk => clk,
227 219 virg_pos => 7,
228 220 coefs => coefs_v2,
229 221 sample_in_val => sample_val_delay,
230 222 sample_in => sample_filter_in,
231 223 sample_out_val => sample_filter_v2_out_val,
232 224 sample_out => sample_filter_v2_out);
233 225
234 226
235 227 -----------------------------------------------------------------------------
236 228 -- RESYNC STAGE
237 229 -----------------------------------------------------------------------------
238 230
239 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
240 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
241 PROCESS (cnv_clk, cnv_rstn)
242 BEGIN -- PROCESS
243 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
244 sample_filter_v2_out_reg(I, J) <= '0';
245 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
246 IF sample_filter_v2_out_val = '1' THEN
247 sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
248 END IF;
249 END IF;
250 END PROCESS;
251 END GENERATE all_data_reg;
252 END GENERATE all_sample_reg;
231 --all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
232 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
233 -- PROCESS (cnv_clk, cnv_rstn)
234 -- BEGIN -- PROCESS
235 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
236 -- sample_filter_v2_out_reg(I, J) <= '0';
237 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
238 -- IF sample_filter_v2_out_val = '1' THEN
239 -- sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
240 -- END IF;
241 -- END IF;
242 -- END PROCESS;
243 -- END GENERATE all_data_reg;
244 --END GENERATE all_sample_reg;
253 245
254 PROCESS (cnv_clk, cnv_rstn)
255 BEGIN -- PROCESS
256 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
257 sample_filter_v2_out_reg_val <= '0';
258 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
259 IF sample_filter_v2_out_val = '1' THEN
260 sample_filter_v2_out_reg_val <= '1';
261 ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
262 sample_filter_v2_out_reg_val <= '0';
263 END IF;
264 END IF;
265 END PROCESS;
246 --PROCESS (cnv_clk, cnv_rstn)
247 --BEGIN -- PROCESS
248 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
249 -- sample_filter_v2_out_reg_val <= '0';
250 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
251 -- IF sample_filter_v2_out_val = '1' THEN
252 -- sample_filter_v2_out_reg_val <= '1';
253 -- ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
254 -- sample_filter_v2_out_reg_val <= '0';
255 -- END IF;
256 -- END IF;
257 --END PROCESS;
266 258
267 SYNC_FF_1 : SYNC_FF
268 GENERIC MAP (
269 NB_FF_OF_SYNC => 2)
270 PORT MAP (
271 clk => clk,
272 rstn => rstn,
273 A => sample_filter_v2_out_reg_val,
274 A_sync => sample_filter_v2_out_reg_val_s);
259 --SYNC_FF_1 : SYNC_FF
260 -- GENERIC MAP (
261 -- NB_FF_OF_SYNC => 2)
262 -- PORT MAP (
263 -- clk => clk,
264 -- rstn => rstn,
265 -- A => sample_filter_v2_out_reg_val,
266 -- A_sync => sample_filter_v2_out_reg_val_s);
275 267
276 SYNC_FF_2 : SYNC_FF
277 GENERIC MAP (
278 NB_FF_OF_SYNC => 2)
279 PORT MAP (
280 clk => cnv_clk,
281 rstn => cnv_rstn,
282 A => sample_filter_v2_out_reg_val_s,
283 A_sync => sample_filter_v2_out_reg_val_s2);
268 --SYNC_FF_2 : SYNC_FF
269 -- GENERIC MAP (
270 -- NB_FF_OF_SYNC => 2)
271 -- PORT MAP (
272 -- clk => cnv_clk,
273 -- rstn => cnv_rstn,
274 -- A => sample_filter_v2_out_reg_val_s,
275 -- A_sync => sample_filter_v2_out_reg_val_s2);
284 276
285 277
286 PROCESS (clk, rstn)
287 BEGIN -- PROCESS
288 IF rstn = '0' THEN -- asynchronous reset (active low)
289 sample_filter_v2_out_sync_val_t <= '0';
290 sample_filter_v2_out_sync_val <= '0';
291 only_one_hot <= '0';
292 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
293 sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
294 only_one_hot <= sample_filter_v2_out_reg_val_s;
295 sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
296 END IF;
297 END PROCESS;
278 --PROCESS (clk, rstn)
279 --BEGIN -- PROCESS
280 -- IF rstn = '0' THEN -- asynchronous reset (active low)
281 -- sample_filter_v2_out_sync_val_t <= '0';
282 -- sample_filter_v2_out_sync_val <= '0';
283 -- only_one_hot <= '0';
284 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
285 -- sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
286 -- only_one_hot <= sample_filter_v2_out_reg_val_s;
287 -- sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
288 -- END IF;
289 --END PROCESS;
298 290
299 291
300 all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
301 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
302 PROCESS (clk, cnv_rstn)
303 BEGIN -- PROCESS
304 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
305 sample_filter_v2_out_sync(I,J) <= '0';
306 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
307 IF sample_filter_v2_out_sync_val_t = '1' THEN
308 sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
309 END IF;
310 END IF;
311 END PROCESS;
312 END GENERATE all_data_reg;
313 END GENERATE all_sample_reg2;
292 --all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
293 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
294 -- PROCESS (clk, cnv_rstn)
295 -- BEGIN -- PROCESS
296 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
297 -- sample_filter_v2_out_sync(I,J) <= '0';
298 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
299 -- IF sample_filter_v2_out_sync_val_t = '1' THEN
300 -- sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
301 -- END IF;
302 -- END IF;
303 -- END PROCESS;
304 -- END GENERATE all_data_reg;
305 --END GENERATE all_sample_reg2;
314 306
315 307
316 308 -----------------------------------------------------------------------------
317 309 -- DATA_SHAPING
318 310 -----------------------------------------------------------------------------
319 311 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
320 sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
321 sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
322 sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
312 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
313 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
314 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
323 315 END GENERATE all_data_shaping_in_loop;
324 316
325 317 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
326 318 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
327 319
328 320 PROCESS (clk, rstn)
329 321 BEGIN -- PROCESS
330 322 IF rstn = '0' THEN -- asynchronous reset (active low)
331 323 sample_data_shaping_out_val <= '0';
332 324 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
333 sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
325 sample_data_shaping_out_val <= sample_filter_v2_out_val;
334 326 END IF;
335 327 END PROCESS;
336 328
337 329 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
338 330 PROCESS (clk, rstn)
339 331 BEGIN
340 332 IF rstn = '0' THEN
341 333 sample_data_shaping_out(0, j) <= '0';
342 334 sample_data_shaping_out(1, j) <= '0';
343 335 sample_data_shaping_out(2, j) <= '0';
344 336 sample_data_shaping_out(3, j) <= '0';
345 337 sample_data_shaping_out(4, j) <= '0';
346 338 sample_data_shaping_out(5, j) <= '0';
347 339 sample_data_shaping_out(6, j) <= '0';
348 340 sample_data_shaping_out(7, j) <= '0';
349 341 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
342 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
351 343 IF data_shaping_SP0 = '1' THEN
352 344 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
353 345 ELSE
354 sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
346 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
355 347 END IF;
356 348 IF data_shaping_SP1 = '1' THEN
357 349 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
358 350 ELSE
359 sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
351 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
360 352 END IF;
361 sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
362 sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
363 sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
364 sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
365 sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
353 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
354 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
355 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
356 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
357 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
366 358 END IF;
367 359 END PROCESS;
368 360 END GENERATE;
369 361
370 362 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
371 363 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
372 364 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
373 365 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
374 366 END GENERATE;
375 367 END GENERATE;
376 368 -----------------------------------------------------------------------------
377 369 -- F0 -- @24.576 kHz
378 370 -----------------------------------------------------------------------------
379 371 Downsampling_f0 : Downsampling
380 372 GENERIC MAP (
381 373 ChanelCount => 8,
382 374 SampleSize => 16,
383 375 DivideParam => 4)
384 376 PORT MAP (
385 377 clk => clk,
386 378 rstn => rstn,
387 379 sample_in_val => sample_filter_v2_out_val_s,
388 380 sample_in => sample_filter_v2_out_s,
389 381 sample_out_val => sample_f0_val,
390 382 sample_out => sample_f0);
391 383
392 384 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
393 385 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
394 386 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
395 387 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
396 388 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
397 389 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
398 390 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
399 391 END GENERATE all_bit_sample_f0;
400 392
401 393 sample_f0_wen <= NOT(sample_f0_val) &
402 394 NOT(sample_f0_val) &
403 395 NOT(sample_f0_val) &
404 396 NOT(sample_f0_val) &
405 397 NOT(sample_f0_val) &
406 398 NOT(sample_f0_val);
407 399
408 400 -----------------------------------------------------------------------------
409 401 -- F1 -- @4096 Hz
410 402 -----------------------------------------------------------------------------
411 403 Downsampling_f1 : Downsampling
412 404 GENERIC MAP (
413 405 ChanelCount => 8,
414 406 SampleSize => 16,
415 407 DivideParam => 6)
416 408 PORT MAP (
417 409 clk => clk,
418 410 rstn => rstn,
419 411 sample_in_val => sample_f0_val ,
420 412 sample_in => sample_f0,
421 413 sample_out_val => sample_f1_val,
422 414 sample_out => sample_f1);
423 415
424 416 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
425 417 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
426 418 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
427 419 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
428 420 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
429 421 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
430 422 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
431 423 END GENERATE all_bit_sample_f1;
432 424
433 425 sample_f1_wen <= NOT(sample_f1_val) &
434 426 NOT(sample_f1_val) &
435 427 NOT(sample_f1_val) &
436 428 NOT(sample_f1_val) &
437 429 NOT(sample_f1_val) &
438 430 NOT(sample_f1_val);
439 431
440 432 -----------------------------------------------------------------------------
441 433 -- F2 -- @256 Hz
442 434 -----------------------------------------------------------------------------
443 435 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
444 436 sample_f0_s(0, I) <= sample_f0(0, I); -- V
445 437 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
446 438 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
447 439 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
448 440 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
449 441 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
450 442 END GENERATE all_bit_sample_f0_s;
451 443
452 444 Downsampling_f2 : Downsampling
453 445 GENERIC MAP (
454 446 ChanelCount => 6,
455 447 SampleSize => 16,
456 448 DivideParam => 96)
457 449 PORT MAP (
458 450 clk => clk,
459 451 rstn => rstn,
460 452 sample_in_val => sample_f0_val ,
461 453 sample_in => sample_f0_s,
462 454 sample_out_val => sample_f2_val,
463 455 sample_out => sample_f2);
464 456
465 457 sample_f2_wen <= NOT(sample_f2_val) &
466 458 NOT(sample_f2_val) &
467 459 NOT(sample_f2_val) &
468 460 NOT(sample_f2_val) &
469 461 NOT(sample_f2_val) &
470 462 NOT(sample_f2_val);
471 463
472 464 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
473 465 sample_f2_wdata_s(I) <= sample_f2(0, I);
474 466 sample_f2_wdata_s(16*1+I) <= sample_f2(1, I);
475 467 sample_f2_wdata_s(16*2+I) <= sample_f2(2, I);
476 468 sample_f2_wdata_s(16*3+I) <= sample_f2(3, I);
477 469 sample_f2_wdata_s(16*4+I) <= sample_f2(4, I);
478 470 sample_f2_wdata_s(16*5+I) <= sample_f2(5, I);
479 471 END GENERATE all_bit_sample_f2;
480 472
481 473 -----------------------------------------------------------------------------
482 474 -- F3 -- @16 Hz
483 475 -----------------------------------------------------------------------------
484 476 all_bit_sample_f1_s : FOR I IN 15 DOWNTO 0 GENERATE
485 477 sample_f1_s(0, I) <= sample_f1(0, I); -- V
486 478 sample_f1_s(1, I) <= sample_f1(1, I); -- E1
487 479 sample_f1_s(2, I) <= sample_f1(2, I); -- E2
488 480 sample_f1_s(3, I) <= sample_f1(5, I); -- B1
489 481 sample_f1_s(4, I) <= sample_f1(6, I); -- B2
490 482 sample_f1_s(5, I) <= sample_f1(7, I); -- B3
491 483 END GENERATE all_bit_sample_f1_s;
492 484
493 485 Downsampling_f3 : Downsampling
494 486 GENERIC MAP (
495 487 ChanelCount => 6,
496 488 SampleSize => 16,
497 489 DivideParam => 256)
498 490 PORT MAP (
499 491 clk => clk,
500 492 rstn => rstn,
501 493 sample_in_val => sample_f1_val ,
502 494 sample_in => sample_f1_s,
503 495 sample_out_val => sample_f3_val,
504 496 sample_out => sample_f3);
505 497
506 498 sample_f3_wen <= (NOT sample_f3_val) &
507 499 (NOT sample_f3_val) &
508 500 (NOT sample_f3_val) &
509 501 (NOT sample_f3_val) &
510 502 (NOT sample_f3_val) &
511 503 (NOT sample_f3_val);
512 504
513 505 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
514 506 sample_f3_wdata_s(I) <= sample_f3(0, I);
515 507 sample_f3_wdata_s(16*1+I) <= sample_f3(1, I);
516 508 sample_f3_wdata_s(16*2+I) <= sample_f3(2, I);
517 509 sample_f3_wdata_s(16*3+I) <= sample_f3(3, I);
518 510 sample_f3_wdata_s(16*4+I) <= sample_f3(4, I);
519 511 sample_f3_wdata_s(16*5+I) <= sample_f3(5, I);
520 512 END GENERATE all_bit_sample_f3;
521 513
522 514 lpp_waveform_1 : lpp_waveform
523 515 GENERIC MAP (
524 516 hindex => hindex,
525 517 tech => tech,
526 518 data_size => 160,
527 519 nb_burst_available_size => nb_burst_available_size,
528 520 nb_snapshot_param_size => nb_snapshot_param_size,
529 521 delta_snapshot_size => delta_snapshot_size,
530 522 delta_f2_f0_size => delta_f2_f0_size,
531 523 delta_f2_f1_size => delta_f2_f1_size)
532 524 PORT MAP (
533 525 clk => clk,
534 526 rstn => rstn,
535 527
536 528 AHB_Master_In => AHB_Master_In,
537 529 AHB_Master_Out => AHB_Master_Out,
538 530
539 531 coarse_time_0 => coarse_time_0, -- IN
540 532 delta_snapshot => delta_snapshot, -- IN
541 533 delta_f2_f1 => delta_f2_f1, -- IN
542 534 delta_f2_f0 => delta_f2_f0, -- IN
543 535 enable_f0 => enable_f0, -- IN
544 536 enable_f1 => enable_f1, -- IN
545 537 enable_f2 => enable_f2, -- IN
546 538 enable_f3 => enable_f3, -- IN
547 539 burst_f0 => burst_f0, -- IN
548 540 burst_f1 => burst_f1, -- IN
549 541 burst_f2 => burst_f2, -- IN
550 542 nb_burst_available => nb_burst_available,
551 543 nb_snapshot_param => nb_snapshot_param,
552 544 status_full => status_full,
553 545 status_full_ack => status_full_ack, -- IN
554 546 status_full_err => status_full_err,
555 547 status_new_err => status_new_err,
556 548
557 549 addr_data_f0 => addr_data_f0, -- IN
558 550 addr_data_f1 => addr_data_f1, -- IN
559 551 addr_data_f2 => addr_data_f2, -- IN
560 552 addr_data_f3 => addr_data_f3, -- IN
561 553
562 554 data_f0_in => data_f0_in_valid,
563 555 data_f1_in => data_f1_in_valid,
564 556 data_f2_in => data_f2_in_valid,
565 557 data_f3_in => data_f3_in_valid,
566 558
567 559 data_f0_in_valid => sample_f0_val,
568 560 data_f1_in_valid => sample_f1_val,
569 561 data_f2_in_valid => sample_f2_val,
570 562 data_f3_in_valid => sample_f3_val);
571 563
572 564 data_f0_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
573 565 data_f1_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
574 566 data_f2_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
575 567 data_f3_in_valid((4*16)-1 DOWNTO 0) <= (OTHERS => '0');
576 568
577 569 data_f0_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f0_wdata_s;
578 570 data_f1_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f1_wdata_s;
579 571 data_f2_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f2_wdata_s;
580 572 data_f3_in_valid((10*16)-1 DOWNTO (4*16)) <= sample_f3_wdata_s;
581 573
582 574 sample_f0_wdata <= sample_f0_wdata_s;
583 575 sample_f1_wdata <= sample_f1_wdata_s;
584 576 sample_f2_wdata <= sample_f2_wdata_s;
585 577 sample_f3_wdata <= sample_f3_wdata_s;
586 578
587 579 END tb;
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@@ -1,349 +1,349
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
15
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
22 ENTITY top_wf_picker IS
23 GENERIC (
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
35 ENABLE_FILTER : STD_LOGIC := '1'
36 );
37 PORT (
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
41 sample_B : IN Samples14v(2 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
43 sample_val : IN STD_LOGIC;
44
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
49 -- AMBA APB Slave Interface
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
52
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
57 --
58 coarse_time_0 : IN STD_LOGIC;
59
60 --
61 data_shaping_BW : OUT STD_LOGIC
62 );
63 END top_wf_picker;
64
65 ARCHITECTURE tb OF top_wf_picker IS
66
67 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111
112 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
121 CONSTANT ChanelCount : INTEGER := 8;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
123 CONSTANT ncycle_cnv : INTEGER := 250;
124
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
127
128 BEGIN
129
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
132
133
134 ready_matrix_f0_0 <= '0';
135 ready_matrix_f0_1 <= '0';
136 ready_matrix_f1 <= '0';
137 ready_matrix_f2 <= '0';
138 error_anticipating_empty_fifo <= '0';
139 error_bad_component_error <= '0';
140 debug_reg <= (OTHERS => '0');
141
142 lpp_top_apbreg_1 : lpp_top_apbreg
143 GENERIC MAP (
144 nb_burst_available_size => nb_burst_available_size,
145 nb_snapshot_param_size => nb_snapshot_param_size,
146 delta_snapshot_size => delta_snapshot_size,
147 delta_f2_f0_size => delta_f2_f0_size,
148 delta_f2_f1_size => delta_f2_f1_size,
149 pindex => pindex,
150 paddr => paddr,
151 pmask => pmask,
152 pirq => pirq)
153 PORT MAP (
154 HCLK => HCLK,
155 HRESETn => HRESETn,
156 apbi => apbi,
157 apbo => apbo,
158
159 ready_matrix_f0_0 => ready_matrix_f0_0,
160 ready_matrix_f0_1 => ready_matrix_f0_1,
161 ready_matrix_f1 => ready_matrix_f1,
162 ready_matrix_f2 => ready_matrix_f2,
163 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
164 error_bad_component_error => error_bad_component_error,
165 debug_reg => debug_reg,
166 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
167 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
168 status_ready_matrix_f1 => status_ready_matrix_f1,
169 status_ready_matrix_f2 => status_ready_matrix_f2,
170 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
171 status_error_bad_component_error => status_error_bad_component_error,
172 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
173 config_active_interruption_onError => config_active_interruption_onError,
174 addr_matrix_f0_0 => addr_matrix_f0_0,
175 addr_matrix_f0_1 => addr_matrix_f0_1,
176 addr_matrix_f1 => addr_matrix_f1,
177 addr_matrix_f2 => addr_matrix_f2,
178
179 status_full => status_full,
180 status_full_ack => status_full_ack,
181 status_full_err => status_full_err,
182 status_new_err => status_new_err,
183 data_shaping_BW => data_shaping_BW,
184 data_shaping_SP0 => data_shaping_SP0,
185 data_shaping_SP1 => data_shaping_SP1,
186 data_shaping_R0 => data_shaping_R0,
187 data_shaping_R1 => data_shaping_R1,
188 delta_snapshot => delta_snapshot,
189 delta_f2_f1 => delta_f2_f1,
190 delta_f2_f0 => delta_f2_f0,
191 nb_burst_available => nb_burst_available,
192 nb_snapshot_param => nb_snapshot_param,
193 enable_f0 => enable_f0,
194 enable_f1 => enable_f1,
195 enable_f2 => enable_f2,
196 enable_f3 => enable_f3,
197 burst_f0 => burst_f0,
198 burst_f1 => burst_f1,
199 burst_f2 => burst_f2,
200 addr_data_f0 => addr_data_f0,
201 addr_data_f1 => addr_data_f1,
202 addr_data_f2 => addr_data_f2,
203 addr_data_f3 => addr_data_f3);
204
205
206
207
208 --DIGITAL_acquisition : AD7688_drvr_sync
209 -- GENERIC MAP (
210 -- ChanelCount => ChanelCount,
211 -- ncycle_cnv_high => ncycle_cnv_high,
212 -- ncycle_cnv => ncycle_cnv)
213 -- PORT MAP (
214 -- cnv_clk => cnv_clk, --
215 -- cnv_rstn => cnv_rstn, --
216 -- cnv_run => cnv_run, --
217 -- cnv => cnv, --
218 -- sck => sck, --
219 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
220 -- sample => sample,
221 -- sample_val => sample_val);
222
223 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
224 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
225 END GENERATE all_channel;
226
227
228 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
229
230 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
231 GENERIC MAP (
232 hindex => hindex,
233 nb_burst_available_size => nb_burst_available_size,
234 nb_snapshot_param_size => nb_snapshot_param_size,
235 delta_snapshot_size => delta_snapshot_size,
236 delta_f2_f0_size => delta_f2_f0_size,
237 delta_f2_f1_size => delta_f2_f1_size,
238 tech => tech,
239 Mem_use => use_RAM
240 )
241 PORT MAP (
242 sample => sample_s,
243 sample_val => sample_val,
244
245 cnv_clk => HCLK,--cnv_clk,
246 cnv_rstn => HRESETn,--cnv_rstn,
247
248 clk => HCLK,
249 rstn => HRESETn,
250
251 sample_f0_wen => sample_f0_wen,
252 sample_f0_wdata => sample_f0_wdata,
253 sample_f1_wen => sample_f1_wen,
254 sample_f1_wdata => sample_f1_wdata,
255 sample_f2_wen => sample_f2_wen,
256 sample_f2_wdata => sample_f2_wdata,
257 sample_f3_wen => sample_f3_wen,
258 sample_f3_wdata => sample_f3_wdata,
259 AHB_Master_In => AHB_Master_In,
260 AHB_Master_Out => AHB_Master_Out,
261 coarse_time_0 => coarse_time_0,
262 data_shaping_SP0 => data_shaping_SP0,
263 data_shaping_SP1 => data_shaping_SP1,
264 data_shaping_R0 => data_shaping_R0,
265 data_shaping_R1 => data_shaping_R1,
266 delta_snapshot => delta_snapshot,
267 delta_f2_f1 => delta_f2_f1,
268 delta_f2_f0 => delta_f2_f0,
269 enable_f0 => enable_f0,
270 enable_f1 => enable_f1,
271 enable_f2 => enable_f2,
272 enable_f3 => enable_f3,
273 burst_f0 => burst_f0,
274 burst_f1 => burst_f1,
275 burst_f2 => burst_f2,
276 nb_burst_available => nb_burst_available,
277 nb_snapshot_param => nb_snapshot_param,
278 status_full => status_full,
279 status_full_ack => status_full_ack,
280 status_full_err => status_full_err,
281 status_new_err => status_new_err,
282 addr_data_f0 => addr_data_f0,
283 addr_data_f1 => addr_data_f1,
284 addr_data_f2 => addr_data_f2,
285 addr_data_f3 => addr_data_f3);
286
287 END GENERATE wf_picker_with_filter;
288
289
290 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
291
292 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
293 GENERIC MAP (
294 hindex => hindex,
295 nb_burst_available_size => nb_burst_available_size,
296 nb_snapshot_param_size => nb_snapshot_param_size,
297 delta_snapshot_size => delta_snapshot_size,
298 delta_f2_f0_size => delta_f2_f0_size,
299 delta_f2_f1_size => delta_f2_f1_size,
300 tech => tech
301 )
302 PORT MAP (
303 sample => sample_s,
304 sample_val => sample_val,
305
306 cnv_clk => cnv_clk,
307 cnv_rstn => cnv_rstn,
308
309 clk => HCLK,
310 rstn => HRESETn,
311
312 sample_f0_wen => sample_f0_wen,
313 sample_f0_wdata => sample_f0_wdata,
314 sample_f1_wen => sample_f1_wen,
315 sample_f1_wdata => sample_f1_wdata,
316 sample_f2_wen => sample_f2_wen,
317 sample_f2_wdata => sample_f2_wdata,
318 sample_f3_wen => sample_f3_wen,
319 sample_f3_wdata => sample_f3_wdata,
320 AHB_Master_In => AHB_Master_In,
321 AHB_Master_Out => AHB_Master_Out,
322 coarse_time_0 => coarse_time_0,
323 data_shaping_SP0 => data_shaping_SP0,
324 data_shaping_SP1 => data_shaping_SP1,
325 data_shaping_R0 => data_shaping_R0,
326 data_shaping_R1 => data_shaping_R1,
327 delta_snapshot => delta_snapshot,
328 delta_f2_f1 => delta_f2_f1,
329 delta_f2_f0 => delta_f2_f0,
330 enable_f0 => enable_f0,
331 enable_f1 => enable_f1,
332 enable_f2 => enable_f2,
333 enable_f3 => enable_f3,
334 burst_f0 => burst_f0,
335 burst_f1 => burst_f1,
336 burst_f2 => burst_f2,
337 nb_burst_available => nb_burst_available,
338 nb_snapshot_param => nb_snapshot_param,
339 status_full => status_full,
340 status_full_ack => status_full_ack,
341 status_full_err => status_full_err,
342 status_new_err => status_new_err,
343 addr_data_f0 => addr_data_f0,
344 addr_data_f1 => addr_data_f1,
345 addr_data_f2 => addr_data_f2,
346 addr_data_f3 => addr_data_f3);
347
348 END GENERATE wf_picker_without_filter;
349 END tb;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
15
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
22 ENTITY top_wf_picker IS
23 GENERIC (
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10;
35 ENABLE_FILTER : STD_LOGIC := '1'
36 );
37 PORT (
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
41 sample_B : IN Samples14v(2 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
43 sample_val : IN STD_LOGIC;
44
45 -- AMBA AHB system signals
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48
49 -- AMBA APB Slave Interface
50 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
52
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
57 --
58 coarse_time_0 : IN STD_LOGIC;
59
60 --
61 data_shaping_BW : OUT STD_LOGIC
62 );
63 END top_wf_picker;
64
65 ARCHITECTURE tb OF top_wf_picker IS
66
67 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111
112 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120
121 CONSTANT ChanelCount : INTEGER := 8;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
123 CONSTANT ncycle_cnv : INTEGER := 250;
124
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
127
128 BEGIN
129
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
132
133
134 ready_matrix_f0_0 <= '0';
135 ready_matrix_f0_1 <= '0';
136 ready_matrix_f1 <= '0';
137 ready_matrix_f2 <= '0';
138 error_anticipating_empty_fifo <= '0';
139 error_bad_component_error <= '0';
140 debug_reg <= (OTHERS => '0');
141
142 lpp_top_apbreg_1 : lpp_top_apbreg
143 GENERIC MAP (
144 nb_burst_available_size => nb_burst_available_size,
145 nb_snapshot_param_size => nb_snapshot_param_size,
146 delta_snapshot_size => delta_snapshot_size,
147 delta_f2_f0_size => delta_f2_f0_size,
148 delta_f2_f1_size => delta_f2_f1_size,
149 pindex => pindex,
150 paddr => paddr,
151 pmask => pmask,
152 pirq => pirq)
153 PORT MAP (
154 HCLK => HCLK,
155 HRESETn => HRESETn,
156 apbi => apbi,
157 apbo => apbo,
158
159 ready_matrix_f0_0 => ready_matrix_f0_0,
160 ready_matrix_f0_1 => ready_matrix_f0_1,
161 ready_matrix_f1 => ready_matrix_f1,
162 ready_matrix_f2 => ready_matrix_f2,
163 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
164 error_bad_component_error => error_bad_component_error,
165 debug_reg => debug_reg,
166 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
167 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
168 status_ready_matrix_f1 => status_ready_matrix_f1,
169 status_ready_matrix_f2 => status_ready_matrix_f2,
170 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
171 status_error_bad_component_error => status_error_bad_component_error,
172 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
173 config_active_interruption_onError => config_active_interruption_onError,
174 addr_matrix_f0_0 => addr_matrix_f0_0,
175 addr_matrix_f0_1 => addr_matrix_f0_1,
176 addr_matrix_f1 => addr_matrix_f1,
177 addr_matrix_f2 => addr_matrix_f2,
178
179 status_full => status_full,
180 status_full_ack => status_full_ack,
181 status_full_err => status_full_err,
182 status_new_err => status_new_err,
183 data_shaping_BW => data_shaping_BW,
184 data_shaping_SP0 => data_shaping_SP0,
185 data_shaping_SP1 => data_shaping_SP1,
186 data_shaping_R0 => data_shaping_R0,
187 data_shaping_R1 => data_shaping_R1,
188 delta_snapshot => delta_snapshot,
189 delta_f2_f1 => delta_f2_f1,
190 delta_f2_f0 => delta_f2_f0,
191 nb_burst_available => nb_burst_available,
192 nb_snapshot_param => nb_snapshot_param,
193 enable_f0 => enable_f0,
194 enable_f1 => enable_f1,
195 enable_f2 => enable_f2,
196 enable_f3 => enable_f3,
197 burst_f0 => burst_f0,
198 burst_f1 => burst_f1,
199 burst_f2 => burst_f2,
200 addr_data_f0 => addr_data_f0,
201 addr_data_f1 => addr_data_f1,
202 addr_data_f2 => addr_data_f2,
203 addr_data_f3 => addr_data_f3);
204
205
206
207
208 --DIGITAL_acquisition : AD7688_drvr_sync
209 -- GENERIC MAP (
210 -- ChanelCount => ChanelCount,
211 -- ncycle_cnv_high => ncycle_cnv_high,
212 -- ncycle_cnv => ncycle_cnv)
213 -- PORT MAP (
214 -- cnv_clk => cnv_clk, --
215 -- cnv_rstn => cnv_rstn, --
216 -- cnv_run => cnv_run, --
217 -- cnv => cnv, --
218 -- sck => sck, --
219 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
220 -- sample => sample,
221 -- sample_val => sample_val);
222
223 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
224 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
225 END GENERATE all_channel;
226
227
228 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
229
230 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
231 GENERIC MAP (
232 hindex => hindex,
233 nb_burst_available_size => nb_burst_available_size,
234 nb_snapshot_param_size => nb_snapshot_param_size,
235 delta_snapshot_size => delta_snapshot_size,
236 delta_f2_f0_size => delta_f2_f0_size,
237 delta_f2_f1_size => delta_f2_f1_size,
238 tech => tech,
239 Mem_use => use_RAM
240 )
241 PORT MAP (
242 sample => sample_s,
243 sample_val => sample_val,
244
245 -- cnv_clk => HCLK,--cnv_clk,
246 -- cnv_rstn => HRESETn,--cnv_rstn,
247
248 clk => HCLK,
249 rstn => HRESETn,
250
251 sample_f0_wen => sample_f0_wen,
252 sample_f0_wdata => sample_f0_wdata,
253 sample_f1_wen => sample_f1_wen,
254 sample_f1_wdata => sample_f1_wdata,
255 sample_f2_wen => sample_f2_wen,
256 sample_f2_wdata => sample_f2_wdata,
257 sample_f3_wen => sample_f3_wen,
258 sample_f3_wdata => sample_f3_wdata,
259 AHB_Master_In => AHB_Master_In,
260 AHB_Master_Out => AHB_Master_Out,
261 coarse_time_0 => coarse_time_0,
262 data_shaping_SP0 => data_shaping_SP0,
263 data_shaping_SP1 => data_shaping_SP1,
264 data_shaping_R0 => data_shaping_R0,
265 data_shaping_R1 => data_shaping_R1,
266 delta_snapshot => delta_snapshot,
267 delta_f2_f1 => delta_f2_f1,
268 delta_f2_f0 => delta_f2_f0,
269 enable_f0 => enable_f0,
270 enable_f1 => enable_f1,
271 enable_f2 => enable_f2,
272 enable_f3 => enable_f3,
273 burst_f0 => burst_f0,
274 burst_f1 => burst_f1,
275 burst_f2 => burst_f2,
276 nb_burst_available => nb_burst_available,
277 nb_snapshot_param => nb_snapshot_param,
278 status_full => status_full,
279 status_full_ack => status_full_ack,
280 status_full_err => status_full_err,
281 status_new_err => status_new_err,
282 addr_data_f0 => addr_data_f0,
283 addr_data_f1 => addr_data_f1,
284 addr_data_f2 => addr_data_f2,
285 addr_data_f3 => addr_data_f3);
286
287 END GENERATE wf_picker_with_filter;
288
289
290 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
291
292 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
293 GENERIC MAP (
294 hindex => hindex,
295 nb_burst_available_size => nb_burst_available_size,
296 nb_snapshot_param_size => nb_snapshot_param_size,
297 delta_snapshot_size => delta_snapshot_size,
298 delta_f2_f0_size => delta_f2_f0_size,
299 delta_f2_f1_size => delta_f2_f1_size,
300 tech => tech
301 )
302 PORT MAP (
303 sample => sample_s,
304 sample_val => sample_val,
305
306 cnv_clk => cnv_clk,
307 cnv_rstn => cnv_rstn,
308
309 clk => HCLK,
310 rstn => HRESETn,
311
312 sample_f0_wen => sample_f0_wen,
313 sample_f0_wdata => sample_f0_wdata,
314 sample_f1_wen => sample_f1_wen,
315 sample_f1_wdata => sample_f1_wdata,
316 sample_f2_wen => sample_f2_wen,
317 sample_f2_wdata => sample_f2_wdata,
318 sample_f3_wen => sample_f3_wen,
319 sample_f3_wdata => sample_f3_wdata,
320 AHB_Master_In => AHB_Master_In,
321 AHB_Master_Out => AHB_Master_Out,
322 coarse_time_0 => coarse_time_0,
323 data_shaping_SP0 => data_shaping_SP0,
324 data_shaping_SP1 => data_shaping_SP1,
325 data_shaping_R0 => data_shaping_R0,
326 data_shaping_R1 => data_shaping_R1,
327 delta_snapshot => delta_snapshot,
328 delta_f2_f1 => delta_f2_f1,
329 delta_f2_f0 => delta_f2_f0,
330 enable_f0 => enable_f0,
331 enable_f1 => enable_f1,
332 enable_f2 => enable_f2,
333 enable_f3 => enable_f3,
334 burst_f0 => burst_f0,
335 burst_f1 => burst_f1,
336 burst_f2 => burst_f2,
337 nb_burst_available => nb_burst_available,
338 nb_snapshot_param => nb_snapshot_param,
339 status_full => status_full,
340 status_full_ack => status_full_ack,
341 status_full_err => status_full_err,
342 status_new_err => status_new_err,
343 addr_data_f0 => addr_data_f0,
344 addr_data_f1 => addr_data_f1,
345 addr_data_f2 => addr_data_f2,
346 addr_data_f3 => addr_data_f3);
347
348 END GENERATE wf_picker_without_filter;
349 END tb; No newline at end of file
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@@ -1,277 +1,276
1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY grlib;
6 6 USE grlib.amba.ALL;
7 7 USE grlib.stdlib.ALL;
8 8 USE grlib.devices.ALL;
9 9 USE GRLIB.DMA2AHB_Package.ALL;
10 10
11 11 LIBRARY lpp;
12 12 USE lpp.lpp_waveform_pkg.ALL;
13 13
14 14 LIBRARY techmap;
15 15 USE techmap.gencomp.ALL;
16 16
17 17 ENTITY lpp_waveform IS
18 18
19 19 GENERIC (
20 20 hindex : INTEGER := 2;
21 21 tech : INTEGER := inferred;
22 22 data_size : INTEGER := 160;
23 23 nb_burst_available_size : INTEGER := 11;
24 24 nb_snapshot_param_size : INTEGER := 11;
25 25 delta_snapshot_size : INTEGER := 16;
26 26 delta_f2_f0_size : INTEGER := 10;
27 27 delta_f2_f1_size : INTEGER := 10);
28 28
29 29 PORT (
30 30 clk : IN STD_LOGIC;
31 31 rstn : IN STD_LOGIC;
32 32
33 33 -- AMBA AHB Master Interface
34 34 AHB_Master_In : IN AHB_Mst_In_Type;
35 35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
36 36
37 37 coarse_time_0 : IN STD_LOGIC;
38 38
39 39 --config
40 40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
41 41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
42 42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
43 43
44 44 enable_f0 : IN STD_LOGIC;
45 45 enable_f1 : IN STD_LOGIC;
46 46 enable_f2 : IN STD_LOGIC;
47 47 enable_f3 : IN STD_LOGIC;
48 48
49 49 burst_f0 : IN STD_LOGIC;
50 50 burst_f1 : IN STD_LOGIC;
51 51 burst_f2 : IN STD_LOGIC;
52 52
53 53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
54 54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56 56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
58 58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
59 59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 63
64 64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
65 65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
66 66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
67 67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
68 68
69 69 data_f0_in_valid : IN STD_LOGIC;
70 70 data_f1_in_valid : IN STD_LOGIC;
71 71 data_f2_in_valid : IN STD_LOGIC;
72 72 data_f3_in_valid : IN STD_LOGIC
73 73 );
74 74
75 75 END lpp_waveform;
76 76
77 77 ARCHITECTURE beh OF lpp_waveform IS
78 78 SIGNAL start_snapshot_f0 : STD_LOGIC;
79 79 SIGNAL start_snapshot_f1 : STD_LOGIC;
80 80 SIGNAL start_snapshot_f2 : STD_LOGIC;
81 81
82 82 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
83 83 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
84 84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86 86
87 87 SIGNAL data_f0_out_valid : STD_LOGIC;
88 88 SIGNAL data_f1_out_valid : STD_LOGIC;
89 89 SIGNAL data_f2_out_valid : STD_LOGIC;
90 90 SIGNAL data_f3_out_valid : STD_LOGIC;
91 91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
92 92
93 93 --
94 94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --
103 103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106
107 107 BEGIN -- beh
108 108
109 109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
110 110 GENERIC MAP (
111 111 delta_snapshot_size => delta_snapshot_size,
112 112 delta_f2_f0_size => delta_f2_f0_size,
113 113 delta_f2_f1_size => delta_f2_f1_size)
114 114 PORT MAP (
115 115 clk => clk,
116 116 rstn => rstn,
117 117 delta_snapshot => delta_snapshot,
118 118 delta_f2_f1 => delta_f2_f1,
119 119 delta_f2_f0 => delta_f2_f0,
120 120 coarse_time_0 => coarse_time_0,
121 121 data_f0_in_valid => data_f0_in_valid,
122 122 data_f2_in_valid => data_f2_in_valid,
123 123 start_snapshot_f0 => start_snapshot_f0,
124 124 start_snapshot_f1 => start_snapshot_f1,
125 125 start_snapshot_f2 => start_snapshot_f2);
126 126
127 127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
128 128 GENERIC MAP (
129 129 data_size => data_size,
130 130 nb_snapshot_param_size => nb_snapshot_param_size)
131 131 PORT MAP (
132 132 clk => clk,
133 133 rstn => rstn,
134 134 enable => enable_f0,
135 135 burst_enable => burst_f0,
136 136 nb_snapshot_param => nb_snapshot_param,
137 137 start_snapshot => start_snapshot_f0,
138 138 data_in => data_f0_in,
139 139 data_in_valid => data_f0_in_valid,
140 140 data_out => data_f0_out,
141 141 data_out_valid => data_f0_out_valid);
142 142
143 143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
144 144
145 145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
146 146 GENERIC MAP (
147 147 data_size => data_size,
148 148 nb_snapshot_param_size => nb_snapshot_param_size+1)
149 149 PORT MAP (
150 150 clk => clk,
151 151 rstn => rstn,
152 152 enable => enable_f1,
153 153 burst_enable => burst_f1,
154 154 nb_snapshot_param => nb_snapshot_param_more_one,
155 155 start_snapshot => start_snapshot_f1,
156 156 data_in => data_f1_in,
157 157 data_in_valid => data_f1_in_valid,
158 158 data_out => data_f1_out,
159 159 data_out_valid => data_f1_out_valid);
160 160
161 161 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
162 162 GENERIC MAP (
163 163 data_size => data_size,
164 164 nb_snapshot_param_size => nb_snapshot_param_size+1)
165 165 PORT MAP (
166 166 clk => clk,
167 167 rstn => rstn,
168 168 enable => enable_f2,
169 169 burst_enable => burst_f2,
170 170 nb_snapshot_param => nb_snapshot_param_more_one,
171 171 start_snapshot => start_snapshot_f2,
172 172 data_in => data_f2_in,
173 173 data_in_valid => data_f2_in_valid,
174 174 data_out => data_f2_out,
175 175 data_out_valid => data_f2_out_valid);
176 176
177 177 lpp_waveform_burst_f3: lpp_waveform_burst
178 178 GENERIC MAP (
179 179 data_size => data_size)
180 180 PORT MAP (
181 181 clk => clk,
182 182 rstn => rstn,
183 183 enable => enable_f3,
184 184 data_in => data_f3_in,
185 185 data_in_valid => data_f3_in_valid,
186 186 data_out => data_f3_out,
187 187 data_out_valid => data_f3_out_valid);
188 188
189 189
190 190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
191 191
192 192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
193 193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
194 194 PORT MAP (
195 195 HCLK => clk,
196 196 HRESETn => rstn,
197 197 valid_in => valid_in(I),
198 198 ack_in => valid_ack(I),
199 199 valid_out => valid_out(I),
200 200 error => status_new_err(I));
201 201 END GENERATE all_input_valid;
202 202
203 203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
204 204 GENERIC MAP (tech => tech)
205 205 PORT MAP (
206 206 clk => clk,
207 207 rstn => rstn,
208 208 data_f0_valid => valid_out(0),
209 209 data_f1_valid => valid_out(1),
210 210 data_f2_valid => valid_out(2),
211 211 data_f3_valid => valid_out(3),
212 212
213 213 data_valid_ack => valid_ack,
214 214
215 215 data_f0 => data_f0_out,
216 216 data_f1 => data_f1_out,
217 217 data_f2 => data_f2_out,
218 218 data_f3 => data_f3_out,
219 219
220 220 ready => ready_arb,
221 221 time_wen => time_wen,
222 222 data_wen => data_wen,
223 223 data => wdata);
224 224
225 225 ready_arb <= NOT ready;
226 226
227 227 lpp_waveform_fifo_1: lpp_waveform_fifo
228 228 GENERIC MAP (tech => tech)
229 229 PORT MAP (
230 230 clk => clk,
231 231 rstn => rstn,
232 232 ready => ready,
233 233 time_ren => time_ren, -- todo
234 234 data_ren => data_ren, -- todo
235 235 rdata => rdata, -- todo
236 236
237 237 time_wen => time_wen,
238 238 data_wen => data_wen,
239 239 wdata => wdata);
240 240
241 241 --time_ren <= (OTHERS => '1');
242 242 --data_ren <= (OTHERS => '1');
243 243
244 244 pp_waveform_dma_1: lpp_waveform_dma
245 245 GENERIC MAP (
246 246 data_size => data_size,
247 247 tech => tech,
248 248 hindex => hindex,
249 249 nb_burst_available_size => nb_burst_available_size)
250 250 PORT MAP (
251 251 HCLK => clk,
252 252 HRESETn => rstn,
253 253 AHB_Master_In => AHB_Master_In,
254 254 AHB_Master_Out => AHB_Master_Out,
255 255 data_ready => ready,
256 256 data => rdata,
257 257 data_data_ren => data_ren,
258 258 data_time_ren => time_ren,
259 259 --data_f0_in => data_f0_out,
260 260 --data_f1_in => data_f1_out,
261 261 --data_f2_in => data_f2_out,
262 262 --data_f3_in => data_f3_out,
263 263 --data_f0_in_valid => data_f0_out_valid,
264 264 --data_f1_in_valid => data_f1_out_valid,
265 265 --data_f2_in_valid => data_f2_out_valid,
266 266 --data_f3_in_valid => data_f3_out_valid,
267 267 nb_burst_available => nb_burst_available,
268 268 status_full => status_full,
269 269 status_full_ack => status_full_ack,
270 270 status_full_err => status_full_err,
271 -- status_new_err => status_new_err,
272 271 addr_data_f0 => addr_data_f0,
273 272 addr_data_f1 => addr_data_f1,
274 273 addr_data_f2 => addr_data_f2,
275 274 addr_data_f3 => addr_data_f3);
276 275
277 276 END beh;
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