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Remove "Sync Stage" between Filter and DownSampler into waveformPicker
pellion -
r205:6eb3be2045fd JC
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@@ -153,8 +153,6 PACKAGE lpp_top_lfr_pkg IS
153 PORT (
153 PORT (
154 sample : IN Samples(7 DOWNTO 0);
154 sample : IN Samples(7 DOWNTO 0);
155 sample_val : IN STD_LOGIC;
155 sample_val : IN STD_LOGIC;
156 cnv_clk : IN STD_LOGIC;
157 cnv_rstn : IN STD_LOGIC;
158 clk : IN STD_LOGIC;
156 clk : IN STD_LOGIC;
159 rstn : IN STD_LOGIC;
157 rstn : IN STD_LOGIC;
160 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
158 sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
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@@ -235,8 +235,8 BEGIN
235 sample => sample,
235 sample => sample,
236 sample_val => sample_val,
236 sample_val => sample_val,
237
237
238 cnv_clk => cnv_clk,
238 -- cnv_clk => cnv_clk,
239 cnv_rstn => cnv_rstn,
239 -- cnv_rstn => cnv_rstn,
240
240
241 clk => HCLK,
241 clk => HCLK,
242 rstn => HRESETn,
242 rstn => HRESETn,
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@@ -31,17 +31,9 ENTITY lpp_top_lfr_wf_picker_ip IS
31 Mem_use : INTEGER := use_RAM
31 Mem_use : INTEGER := use_RAM
32 );
32 );
33 PORT (
33 PORT (
34 -- ADS7886
35 -- cnv_run : IN STD_LOGIC;
36 -- cnv : OUT STD_LOGIC;
37 -- sck : OUT STD_LOGIC;
38 -- sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
39 sample : IN Samples(7 DOWNTO 0);
34 sample : IN Samples(7 DOWNTO 0);
40 sample_val : IN STD_LOGIC;
35 sample_val : IN STD_LOGIC;
41 --
36 --
42 cnv_clk : IN STD_LOGIC;
43 cnv_rstn : IN STD_LOGIC;
44 --
45 clk : IN STD_LOGIC;
37 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
47 --
39 --
@@ -141,15 +133,15 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
141 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
133 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
142 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
134 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
143 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
144 SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
136 --SIGNAL sample_filter_v2_out_reg : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
145
137
146 SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
138 --SIGNAL sample_filter_v2_out_reg_val : STD_LOGIC;
147 SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
139 --SIGNAL sample_filter_v2_out_reg_val_s : STD_LOGIC;
148 SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
140 --SIGNAL sample_filter_v2_out_reg_val_s2 : STD_LOGIC;
149 SIGNAL only_one_hot : STD_LOGIC;
141 --SIGNAL only_one_hot : STD_LOGIC;
150 SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
142 --SIGNAL sample_filter_v2_out_sync_val_t : STD_LOGIC;
151 SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
143 --SIGNAL sample_filter_v2_out_sync_val : STD_LOGIC;
152 SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
144 --SIGNAL sample_filter_v2_out_sync : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
153 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
154 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
146 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
155 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
147 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -190,11 +182,11 ARCHITECTURE tb OF lpp_top_lfr_wf_picker
190 BEGIN
182 BEGIN
191
183
192 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
193 PROCESS (cnv_clk, cnv_rstn)
185 PROCESS (clk, rstn)
194 BEGIN -- PROCESS
186 BEGIN -- PROCESS
195 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
187 IF rstn = '0' THEN -- asynchronous reset (active low)
196 sample_val_delay <= '0';
188 sample_val_delay <= '0';
197 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
189 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
198 sample_val_delay <= sample_val;
190 sample_val_delay <= sample_val;
199 END IF;
191 END IF;
200 END PROCESS;
192 END PROCESS;
@@ -222,8 +214,8 BEGIN
222 Cels_count => Cels_count,
214 Cels_count => Cels_count,
223 ChanelsCount => ChanelCount)
215 ChanelsCount => ChanelCount)
224 PORT MAP (
216 PORT MAP (
225 rstn => cnv_rstn,
217 rstn => rstn,
226 clk => cnv_clk,
218 clk => clk,
227 virg_pos => 7,
219 virg_pos => 7,
228 coefs => coefs_v2,
220 coefs => coefs_v2,
229 sample_in_val => sample_val_delay,
221 sample_in_val => sample_val_delay,
@@ -236,90 +228,90 BEGIN
236 -- RESYNC STAGE
228 -- RESYNC STAGE
237 -----------------------------------------------------------------------------
229 -----------------------------------------------------------------------------
238
230
239 all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
231 --all_sample_reg : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
240 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
232 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
241 PROCESS (cnv_clk, cnv_rstn)
233 -- PROCESS (cnv_clk, cnv_rstn)
242 BEGIN -- PROCESS
234 -- BEGIN -- PROCESS
243 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
235 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
244 sample_filter_v2_out_reg(I, J) <= '0';
236 -- sample_filter_v2_out_reg(I, J) <= '0';
245 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
237 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
246 IF sample_filter_v2_out_val = '1' THEN
238 -- IF sample_filter_v2_out_val = '1' THEN
247 sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
239 -- sample_filter_v2_out_reg(I, J) <= sample_filter_v2_out(I, J);
248 END IF;
240 -- END IF;
249 END IF;
241 -- END IF;
250 END PROCESS;
242 -- END PROCESS;
251 END GENERATE all_data_reg;
243 -- END GENERATE all_data_reg;
252 END GENERATE all_sample_reg;
244 --END GENERATE all_sample_reg;
253
245
254 PROCESS (cnv_clk, cnv_rstn)
246 --PROCESS (cnv_clk, cnv_rstn)
255 BEGIN -- PROCESS
247 --BEGIN -- PROCESS
256 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
248 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
257 sample_filter_v2_out_reg_val <= '0';
249 -- sample_filter_v2_out_reg_val <= '0';
258 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
250 -- ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
259 IF sample_filter_v2_out_val = '1' THEN
251 -- IF sample_filter_v2_out_val = '1' THEN
260 sample_filter_v2_out_reg_val <= '1';
252 -- sample_filter_v2_out_reg_val <= '1';
261 ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
253 -- ELSIF sample_filter_v2_out_reg_val_s2 = '1' THEN
262 sample_filter_v2_out_reg_val <= '0';
254 -- sample_filter_v2_out_reg_val <= '0';
263 END IF;
255 -- END IF;
264 END IF;
256 -- END IF;
265 END PROCESS;
257 --END PROCESS;
266
258
267 SYNC_FF_1 : SYNC_FF
259 --SYNC_FF_1 : SYNC_FF
268 GENERIC MAP (
260 -- GENERIC MAP (
269 NB_FF_OF_SYNC => 2)
261 -- NB_FF_OF_SYNC => 2)
270 PORT MAP (
262 -- PORT MAP (
271 clk => clk,
263 -- clk => clk,
272 rstn => rstn,
264 -- rstn => rstn,
273 A => sample_filter_v2_out_reg_val,
265 -- A => sample_filter_v2_out_reg_val,
274 A_sync => sample_filter_v2_out_reg_val_s);
266 -- A_sync => sample_filter_v2_out_reg_val_s);
275
267
276 SYNC_FF_2 : SYNC_FF
268 --SYNC_FF_2 : SYNC_FF
277 GENERIC MAP (
269 -- GENERIC MAP (
278 NB_FF_OF_SYNC => 2)
270 -- NB_FF_OF_SYNC => 2)
279 PORT MAP (
271 -- PORT MAP (
280 clk => cnv_clk,
272 -- clk => cnv_clk,
281 rstn => cnv_rstn,
273 -- rstn => cnv_rstn,
282 A => sample_filter_v2_out_reg_val_s,
274 -- A => sample_filter_v2_out_reg_val_s,
283 A_sync => sample_filter_v2_out_reg_val_s2);
275 -- A_sync => sample_filter_v2_out_reg_val_s2);
284
276
285
277
286 PROCESS (clk, rstn)
278 --PROCESS (clk, rstn)
287 BEGIN -- PROCESS
279 --BEGIN -- PROCESS
288 IF rstn = '0' THEN -- asynchronous reset (active low)
280 -- IF rstn = '0' THEN -- asynchronous reset (active low)
289 sample_filter_v2_out_sync_val_t <= '0';
281 -- sample_filter_v2_out_sync_val_t <= '0';
290 sample_filter_v2_out_sync_val <= '0';
282 -- sample_filter_v2_out_sync_val <= '0';
291 only_one_hot <= '0';
283 -- only_one_hot <= '0';
292 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
284 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
293 sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
285 -- sample_filter_v2_out_sync_val_t <= sample_filter_v2_out_reg_val_s AND NOT only_one_hot;
294 only_one_hot <= sample_filter_v2_out_reg_val_s;
286 -- only_one_hot <= sample_filter_v2_out_reg_val_s;
295 sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
287 -- sample_filter_v2_out_sync_val <= sample_filter_v2_out_sync_val_t;
296 END IF;
288 -- END IF;
297 END PROCESS;
289 --END PROCESS;
298
290
299
291
300 all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
292 --all_sample_reg2 : FOR I IN ChanelCount-1 DOWNTO 0 GENERATE
301 all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
293 -- all_data_reg : FOR J IN 17 DOWNTO 0 GENERATE
302 PROCESS (clk, cnv_rstn)
294 -- PROCESS (clk, cnv_rstn)
303 BEGIN -- PROCESS
295 -- BEGIN -- PROCESS
304 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
296 -- IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
305 sample_filter_v2_out_sync(I,J) <= '0';
297 -- sample_filter_v2_out_sync(I,J) <= '0';
306 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
298 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
307 IF sample_filter_v2_out_sync_val_t = '1' THEN
299 -- IF sample_filter_v2_out_sync_val_t = '1' THEN
308 sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
300 -- sample_filter_v2_out_sync(I,J) <= sample_filter_v2_out_reg(I,J);
309 END IF;
301 -- END IF;
310 END IF;
302 -- END IF;
311 END PROCESS;
303 -- END PROCESS;
312 END GENERATE all_data_reg;
304 -- END GENERATE all_data_reg;
313 END GENERATE all_sample_reg2;
305 --END GENERATE all_sample_reg2;
314
306
315
307
316 -----------------------------------------------------------------------------
308 -----------------------------------------------------------------------------
317 -- DATA_SHAPING
309 -- DATA_SHAPING
318 -----------------------------------------------------------------------------
310 -----------------------------------------------------------------------------
319 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
311 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
320 sample_data_shaping_f0_s(I) <= sample_filter_v2_out_sync(0, I);
312 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
321 sample_data_shaping_f1_s(I) <= sample_filter_v2_out_sync(1, I);
313 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
322 sample_data_shaping_f2_s(I) <= sample_filter_v2_out_sync(2, I);
314 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
323 END GENERATE all_data_shaping_in_loop;
315 END GENERATE all_data_shaping_in_loop;
324
316
325 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
317 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
@@ -330,7 +322,7 BEGIN
330 IF rstn = '0' THEN -- asynchronous reset (active low)
322 IF rstn = '0' THEN -- asynchronous reset (active low)
331 sample_data_shaping_out_val <= '0';
323 sample_data_shaping_out_val <= '0';
332 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
324 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
333 sample_data_shaping_out_val <= sample_filter_v2_out_sync_val;
325 sample_data_shaping_out_val <= sample_filter_v2_out_val;
334 END IF;
326 END IF;
335 END PROCESS;
327 END PROCESS;
336
328
@@ -347,22 +339,22 BEGIN
347 sample_data_shaping_out(6, j) <= '0';
339 sample_data_shaping_out(6, j) <= '0';
348 sample_data_shaping_out(7, j) <= '0';
340 sample_data_shaping_out(7, j) <= '0';
349 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
341 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
350 sample_data_shaping_out(0, j) <= sample_filter_v2_out_sync(0, j);
342 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
351 IF data_shaping_SP0 = '1' THEN
343 IF data_shaping_SP0 = '1' THEN
352 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
344 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
353 ELSE
345 ELSE
354 sample_data_shaping_out(1, j) <= sample_filter_v2_out_sync(1, j);
346 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
355 END IF;
347 END IF;
356 IF data_shaping_SP1 = '1' THEN
348 IF data_shaping_SP1 = '1' THEN
357 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
349 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
358 ELSE
350 ELSE
359 sample_data_shaping_out(2, j) <= sample_filter_v2_out_sync(2, j);
351 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
360 END IF;
352 END IF;
361 sample_data_shaping_out(3, j) <= sample_filter_v2_out_sync(3, j);
353 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
362 sample_data_shaping_out(4, j) <= sample_filter_v2_out_sync(4, j);
354 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
363 sample_data_shaping_out(5, j) <= sample_filter_v2_out_sync(5, j);
355 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
364 sample_data_shaping_out(6, j) <= sample_filter_v2_out_sync(6, j);
356 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
365 sample_data_shaping_out(7, j) <= sample_filter_v2_out_sync(7, j);
357 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
366 END IF;
358 END IF;
367 END PROCESS;
359 END PROCESS;
368 END GENERATE;
360 END GENERATE;
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@@ -242,8 +242,8 BEGIN
242 sample => sample_s,
242 sample => sample_s,
243 sample_val => sample_val,
243 sample_val => sample_val,
244
244
245 cnv_clk => HCLK,--cnv_clk,
245 -- cnv_clk => HCLK,--cnv_clk,
246 cnv_rstn => HRESETn,--cnv_rstn,
246 -- cnv_rstn => HRESETn,--cnv_rstn,
247
247
248 clk => HCLK,
248 clk => HCLK,
249 rstn => HRESETn,
249 rstn => HRESETn,
@@ -346,4 +346,4 BEGIN
346 addr_data_f3 => addr_data_f3);
346 addr_data_f3 => addr_data_f3);
347
347
348 END GENERATE wf_picker_without_filter;
348 END GENERATE wf_picker_without_filter;
349 END tb;
349 END tb; No newline at end of file
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@@ -268,7 +268,6 BEGIN -- beh
268 status_full => status_full,
268 status_full => status_full,
269 status_full_ack => status_full_ack,
269 status_full_ack => status_full_ack,
270 status_full_err => status_full_err,
270 status_full_err => status_full_err,
271 -- status_new_err => status_new_err,
272 addr_data_f0 => addr_data_f0,
271 addr_data_f0 => addr_data_f0,
273 addr_data_f1 => addr_data_f1,
272 addr_data_f1 => addr_data_f1,
274 addr_data_f2 => addr_data_f2,
273 addr_data_f2 => addr_data_f2,
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