HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r158:6e4fef3f3bb0

Add DMA Matrix IRQ GEn

pellion -

r158:6e4fef3f3bb0 JC

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r158:6e4fef3f3bb0

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lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +16 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.lpp_amba.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_top_apbreg IS
               GENERIC (
                 pindex : INTEGER := 4;
                 paddr  : INTEGER := 4;
                 pmask  : INTEGER := 16#fff#;
                 pirq   : INTEGER := 0);
               PORT (
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
                 -- AMBA APB Slave Interface
                 apbi : IN  apb_slv_in_type;
                 apbo : OUT apb_slv_out_type;
                 -- IN
                 ready_matrix_f0_0             : IN STD_LOGIC;
                 ready_matrix_f0_1             : IN STD_LOGIC;
                 ready_matrix_f1               : IN STD_LOGIC;
                 ready_matrix_f2               : IN STD_LOGIC;
                 error_anticipating_empty_fifo : IN STD_LOGIC;
                 error_bad_component_error     : IN STD_LOGIC;
                 debug_reg                     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 -- OUT
                 status_ready_matrix_f0_0             : OUT STD_LOGIC;
                 status_ready_matrix_f0_1             : OUT STD_LOGIC;
                 status_ready_matrix_f1               : OUT STD_LOGIC;
                 status_ready_matrix_f2               : OUT STD_LOGIC;
                 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
                 status_error_bad_component_error     : OUT STD_LOGIC;
                 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                 config_active_interruption_onError     : OUT STD_LOGIC;
                 addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END lpp_top_apbreg;
             ARCHITECTURE beh OF lpp_top_apbreg IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
 => apb_iobar(paddr, pmask));
               TYPE lpp_dma_regs IS RECORD
                 config_active_interruption_onNewMatrix : STD_LOGIC;
                 config_active_interruption_onError     : STD_LOGIC;
                 status_ready_matrix_f0_0               : STD_LOGIC;
                 status_ready_matrix_f0_1               : STD_LOGIC;
                 status_ready_matrix_f1                 : STD_LOGIC;
                 status_ready_matrix_f2                 : STD_LOGIC;
                 status_error_anticipating_empty_fifo   : STD_LOGIC;
                 status_error_bad_component_error       : STD_LOGIC;
                 addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               END RECORD;
               SIGNAL reg : lpp_dma_regs;
               SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN  -- beh
               status_ready_matrix_f0_0             <= reg.status_ready_matrix_f0_0;
               status_ready_matrix_f0_1             <= reg.status_ready_matrix_f0_1;
               status_ready_matrix_f1               <= reg.status_ready_matrix_f1;
               status_ready_matrix_f2               <= reg.status_ready_matrix_f2;
               status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
               status_error_bad_component_error     <= reg.status_error_bad_component_error;
               config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
               config_active_interruption_onError     <= reg.config_active_interruption_onError;
               addr_matrix_f0_0                       <= reg.addr_matrix_f0_0;
               addr_matrix_f0_1                       <= reg.addr_matrix_f0_1;
               addr_matrix_f1                         <= reg.addr_matrix_f1;
               addr_matrix_f2                         <= reg.addr_matrix_f2;
               lpp_top_apbreg : PROCESS (HCLK, HRESETn)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN  -- PROCESS lpp_dma_top
                 IF HRESETn = '0' THEN                 -- asynchronous reset (active low)
                   reg.config_active_interruption_onNewMatrix <= '0';
                   reg.config_active_interruption_onError     <= '0';
                   reg.status_ready_matrix_f0_0               <= '0';
                   reg.status_ready_matrix_f0_1               <= '0';
                   reg.status_ready_matrix_f1                 <= '0';
                   reg.status_ready_matrix_f2                 <= '0';
                   reg.status_error_anticipating_empty_fifo   <= '0';
                   reg.status_error_bad_component_error       <= '0';
                   reg.addr_matrix_f0_0                       <= (OTHERS => '0');
                   reg.addr_matrix_f0_1                       <= (OTHERS => '0');
                   reg.addr_matrix_f1                         <= (OTHERS => '0');
                   reg.addr_matrix_f2                         <= (OTHERS => '0');
                   prdata                                     <= (OTHERS => '0');
+                  apbo.pirq    <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
                   reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
                   reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
                   reg.status_ready_matrix_f1   <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
                   reg.status_ready_matrix_f2   <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
                   reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
                   reg.status_error_bad_component_error     <= reg.status_error_bad_component_error OR error_bad_component_error;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   prdata            <= (OTHERS => '0');
                   IF apbi.psel(pindex) = '1' THEN
                     -- APB DMA READ  --
                     CASE paddr(7 DOWNTO 2) IS
                       WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
                                        prdata(1) <= reg.config_active_interruption_onError;
                       WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
                                        prdata(1) <= reg.status_ready_matrix_f0_1;
                                        prdata(2) <= reg.status_ready_matrix_f1;
                                        prdata(3) <= reg.status_ready_matrix_f2;
                                        prdata(4) <= reg.status_error_anticipating_empty_fifo;
                                        prdata(5) <= reg.status_error_bad_component_error;
                       WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
                       WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
                       WHEN "000100" => prdata <= reg.addr_matrix_f1;
                       WHEN "000101" => prdata <= reg.addr_matrix_f2;
                       WHEN "000110" => prdata <= debug_reg;
                       WHEN OTHERS   => NULL;
                     END CASE;
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       -- APB DMA WRITE --
                       CASE paddr(7 DOWNTO 2) IS
                         WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
                                          reg.config_active_interruption_onError <= apbi.pwdata(1);
                         WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
                                          reg.status_ready_matrix_f0_1             <= apbi.pwdata(1);
                                          reg.status_ready_matrix_f1               <= apbi.pwdata(2);
                                          reg.status_ready_matrix_f2               <= apbi.pwdata(3);
                                          reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
                                          reg.status_error_bad_component_error     <= apbi.pwdata(5);
                         WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
                         WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
                         WHEN "000100" => reg.addr_matrix_f1   <= apbi.pwdata;
                         WHEN "000101" => reg.addr_matrix_f2   <= apbi.pwdata;
                         WHEN OTHERS   => NULL;
                       END CASE;
                     END IF;
                   END IF;
+                  apbo.pirq(pirq) <= ( reg.config_active_interruption_onNewMatrix AND ( ready_matrix_f0_0 OR
+                                                                                        ready_matrix_f0_1 OR
+                                                                                        ready_matrix_f1   OR
+                                                                                        ready_matrix_f2)
+                                       )
+                                     OR
+                                     ( reg.config_active_interruption_onError AND ( error_anticipating_empty_fifo OR
+                                                                                    error_bad_component_error)
+                                       );
                 END IF;
               END PROCESS lpp_top_apbreg;
-              apbo.pirq    <= (OTHERS => '0');
               apbo.pindex  <= pindex;
               apbo.pconfig <= pconfig;
               apbo.prdata  <= prdata;
             END beh;

lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd +4 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_demux.ALL;
             USE lpp.lpp_fft.ALL;
             use lpp.lpp_matrix.all;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_top_lfr IS
               GENERIC(
                 tech                  : INTEGER := 0;
                 hindex_SpectralMatrix : INTEGER := 2;
                 pindex                : INTEGER := 4;
                 paddr                 : INTEGER := 4;
                 pmask                 : INTEGER := 16#fff#;
                 pirq                  : INTEGER := 0
                 );
               PORT (
                 -- ADS7886
                 cnv_run  : IN  STD_LOGIC;
                 cnv      : OUT STD_LOGIC;
                 sck      : OUT STD_LOGIC;
                 sdo      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 --
                 cnv_clk  : IN  STD_LOGIC;           -- 49 MHz
                 cnv_rstn : IN  STD_LOGIC;
                 --
                 clk      : IN  STD_LOGIC;           -- 25 MHz
                 rstn     : IN  STD_LOGIC;
                 --
                 apbi     : IN  apb_slv_in_type;
                 apbo     : OUT apb_slv_out_type;
                 -- AMBA AHB Master Interface
                 AHB_DMA_SpectralMatrix_In  : IN  AHB_Mst_In_Type;
                 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
                 );
             END lpp_top_lfr;
             ARCHITECTURE tb OF lpp_top_lfr IS
               -----------------------------------------------------------------------------
               -- f0
               SIGNAL sample_f0_0_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_1_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_0_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_0_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- f1
               SIGNAL sample_f1_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f1_ren     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_full    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- f2
               SIGNAL sample_f2_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- f3
               SIGNAL sample_f3_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f3_wdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f3_ren     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f3_rdata   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f3_full    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f3_empty   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SPECTRAL MATRIX
               -----------------------------------------------------------------------------
               SIGNAL sample_ren : STD_LOGIC_VECTOR(19 DOWNTO 0);
               SIGNAL demux_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL demux_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL demux_data  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL fft_fifo_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fft_fifo_data  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL fft_fifo_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fft_fifo_reuse : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL SP_fifo_data  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL SP_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL fifo_data  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fifo_empty : STD_LOGIC;
               SIGNAL fifo_ren   : STD_LOGIC;
               SIGNAL header     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL header_val : STD_LOGIC;
               SIGNAL header_ack : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- APB REG
               -----------------------------------------------------------------------------
               SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
               SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
               SIGNAL ready_matrix_f1                        : STD_LOGIC;
               SIGNAL ready_matrix_f2                        : STD_LOGIC;
               SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
               SIGNAL error_bad_component_error              : STD_LOGIC;
               SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
               SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
               SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
               SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
               SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
               SIGNAL status_error_bad_component_error       : STD_LOGIC;
               SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
               SIGNAL config_active_interruption_onError     : STD_LOGIC;
               SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               -- CNA + FILTER
               -----------------------------------------------------------------------------
               lpp_top_acq_1 : lpp_top_acq
                 GENERIC MAP (
                   tech => tech)
                 PORT MAP (
                   cnv_run  => cnv_run,
                   cnv      => cnv,
                   sck      => sck,
                   sdo      => sdo,
                   cnv_clk  => cnv_clk,
                   cnv_rstn => cnv_rstn,
                   clk      => clk,
                   rstn     => rstn,
                   sample_f0_0_wen => sample_f0_0_wen,
                   sample_f0_1_wen => sample_f0_1_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
                   sample_f3_wen   => sample_f3_wen,
                   sample_f3_wdata => sample_f3_wdata);
               -----------------------------------------------------------------------------
               -- FIFO
               -----------------------------------------------------------------------------
               lppFIFO_f0_0 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
                   Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
                   rst   => rstn,
                   wclk  => clk,
                   rclk  => clk,
                   ReUse => (OTHERS => '0'),
                   wen   => sample_f0_0_wen,
                   ren   => sample_f0_0_ren,
                   wdata => sample_f0_wdata,
                   rdata => sample_f0_0_rdata,
                   full  => sample_f0_0_full,
                   empty => sample_f0_0_empty);
               lppFIFO_f0_1 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
                   Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
                   rst   => rstn,
                   wclk  => clk,
                   rclk  => clk,
                   ReUse => (OTHERS => '0'),
                   wen   => sample_f0_1_wen,
                   ren   => sample_f0_1_ren,
                   wdata => sample_f0_wdata,
                   rdata => sample_f0_1_rdata,
                   full  => sample_f0_1_full,
                   empty => sample_f0_1_empty);
               lppFIFO_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
                   Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
                   rst   => rstn,
                   wclk  => clk,
                   rclk  => clk,
                   ReUse => (OTHERS => '0'),
                   wen   => sample_f1_wen,
                   ren   => sample_f1_ren,
                   wdata => sample_f1_wdata,
                   rdata => sample_f1_rdata,
                   full  => sample_f1_full,
                   empty => sample_f1_empty);
               lppFIFO_f3 : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
                   Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '0')
                 PORT MAP (
                   rst   => rstn,
                   wclk  => clk,
                   rclk  => clk,
                   ReUse => (OTHERS => '0'),
                   wen   => sample_f3_wen,
                   ren   => sample_f3_ren,
                   wdata => sample_f3_wdata,
                   rdata => sample_f3_rdata,
                   full  => sample_f3_full,
                   empty => sample_f3_empty);
               -----------------------------------------------------------------------------
               -- SPECTRAL MATRIX
               -----------------------------------------------------------------------------
               sample_f0_0_ren <= sample_ren(4 DOWNTO 0);
               sample_f0_1_ren <= sample_ren(9 DOWNTO 5);
               sample_f1_ren   <= sample_ren(14 DOWNTO 10);
               sample_f3_ren   <= sample_ren(19 DOWNTO 15);
               Demultiplex_1 : Demultiplex
                 GENERIC MAP (
                   Data_sz => 16)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   Read       => demux_ren,
                   EmptyF0a   => sample_f0_0_empty,
                   EmptyF0b   => sample_f0_0_empty,
                   EmptyF1    => sample_f1_empty,
                   EmptyF2    => sample_f3_empty,
                   DataF0a    => sample_f0_0_rdata,
                   DataF0b    => sample_f0_1_rdata,
                   DataF1     => sample_f1_rdata,
                   DataF2     => sample_f3_rdata,
                   Read_DEMUX => sample_ren,
                   Empty      => demux_empty,
                   Data       => demux_data);
               FFT_1 : FFT
                 GENERIC MAP (
                   Data_sz => 16,
                   NbData  => 256)
                 PORT MAP (
                   clkm         => clk,
                   rstn         => rstn,
                   FifoIN_Empty => demux_empty,
                   FifoIN_Data  => demux_data,
                   FifoOUT_Full => fft_fifo_full,
                   Read         => demux_ren,
                   Write        => fft_fifo_wen,
                   ReUse        => fft_fifo_reuse,
                   Data         => fft_fifo_data);
               lppFIFO_fft : lppFIFOxN
                 GENERIC MAP (
                   tech         => tech,
                   Data_sz      => 16,
                   FifoCnt      => 5,
                   Enable_ReUse => '1')
                 PORT MAP (
                   rst   => rstn,
                   wclk  => clk,
                   rclk  => clk,
                   ReUse => fft_fifo_reuse,
                   wen   => fft_fifo_wen,
                   ren   => SP_fifo_ren,
                   wdata => fft_fifo_data,
                   rdata => SP_fifo_data,
                   full  => fft_fifo_full,
                   empty => OPEN);
               MatriceSpectrale_1: MatriceSpectrale
                 GENERIC MAP (
                   Input_SZ  => 16,
                   Result_SZ => 32)
                 PORT MAP (
                   clkm         => clk,
                   rstn         => rstn,
                   FifoIN_Full  => fft_fifo_full,
                   FifoOUT_Full => ,                 -- TODO
                   Data_IN      => SP_fifo_data,
                   ACQ          => ,                 -- TODO
                   FlagError    => ,                 -- TODO
                   Pong         => ,                 -- TODO
                   Write        => ,                 -- TODO
                   Read         => SP_fifo_ren,
                   Data_OUT     => );                -- TODO
               -----------------------------------------------------------------------------
               -- DMA SPECTRAL MATRIX
               -----------------------------------------------------------------------------
               lpp_dma_ip_1 : lpp_dma_ip
                 GENERIC MAP (
                   tech   => tech,
                   hindex => hindex_SpectralMatrix)
                 PORT MAP (
                   HCLK           => clk,
                   HRESETn        => rstn,
                   AHB_Master_In  => AHB_DMA_SpectralMatrix_In,
                   AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
                   -- Connect to Spectral Matrix --
                   fifo_data  => fifo_data,
                   fifo_empty => fifo_empty,
                   fifo_ren   => fifo_ren,
                   header     => header,
                   header_val => header_val,
                   header_ack => header_ack,
                   -- APB REG
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0_0                       => addr_matrix_f0_0,
                   addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2);
               lpp_top_apbreg_1 : lpp_top_apbreg
                 GENERIC MAP (
                   pindex => pindex,
                   paddr  => paddr,
                   pmask  => pmask,
                   pirq   => pirq)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0_0                       => addr_matrix_f0_0,
                   addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2);
-              --TODO : add the irq alert for DMA matrix transfert ending
+              --DONE : add the irq alert for DMA matrix transfert ending
               --TODO : add 5 bit register into APB to control the DATA SHIPING
+              --TODO : data shiping
               --TODO : add Spectral Matrix (FFT + SP)
               --TODO : add DMA for WaveForms Picker
               --TODO : add APB Reg to control WaveForms Picker
               --TODO : add WaveForms Picker
             END tb;

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