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Updated MINI-LFR Board and design with EM constraint files.
Jeandet Alexis -
r635:6428e5d35e0a simu_with_Leon3
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
42 set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
43 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
44 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
45 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
47 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
48 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
49 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
61 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
62 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
63 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
65 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
66 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
67 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
71 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
72 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
73 address[7] SRAM_A[8] SRAM_A[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
75 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
76 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
77 address[7] SRAM_A[8] SRAM_A[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
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@@ -1,4 +1,4
1 # Actel Physical design constraints file
1 # Actel Physical design constraints file
2 2 # Generated file
3 3
4 4 # Version: 9.1 SP3 9.1.3.4
@@ -15,12 +15,12
15 15 # I/O constraints
16 16 #
17 17
18 set_io clk_50 \
18 set_io clk100MHz \
19 19 -pinname F7 \
20 20 -fixed yes \
21 21 -DIRECTION Inout
22 22
23 set_io clk_49 \
23 set_io clk49_152MHz \
24 24 -pinname K14 \
25 25 -fixed yes \
26 26 -DIRECTION Inout
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@@ -1,114 +1,114
1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
73 address[7] address[8] address[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \
77 address[7] address[8] address[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 -----------------------------------------------------------------------------
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
53 -- clk_50 frequency is 100 Mhz !
54 clk_50 : IN STD_LOGIC;
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
56 -----------------------------------------------------------------------------
57 clk_49 : IN STD_LOGIC;
58 reset : IN STD_LOGIC;
59 --BPs
60 BP0 : IN STD_LOGIC;
61 BP1 : IN STD_LOGIC;
62 --LEDs
63 LED0 : OUT STD_LOGIC;
64 LED1 : OUT STD_LOGIC;
65 LED2 : OUT STD_LOGIC;
66 --UARTs
67 TXD1 : IN STD_LOGIC;
68 RXD1 : OUT STD_LOGIC;
69 nCTS1 : OUT STD_LOGIC;
70 nRTS1 : IN STD_LOGIC;
71
72 TXD2 : IN STD_LOGIC;
73 RXD2 : OUT STD_LOGIC;
74 nCTS2 : OUT STD_LOGIC;
75 nDTR2 : IN STD_LOGIC;
76 nRTS2 : IN STD_LOGIC;
77 nDCD2 : OUT STD_LOGIC;
78
79 --EXT CONNECTOR
80 IO0 : INOUT STD_LOGIC;
81 IO1 : INOUT STD_LOGIC;
82 IO2 : INOUT STD_LOGIC;
83 IO3 : INOUT STD_LOGIC;
84 IO4 : INOUT STD_LOGIC;
85 IO5 : INOUT STD_LOGIC;
86 IO6 : INOUT STD_LOGIC;
87 IO7 : INOUT STD_LOGIC;
88 IO8 : INOUT STD_LOGIC;
89 IO9 : INOUT STD_LOGIC;
90 IO10 : INOUT STD_LOGIC;
91 IO11 : INOUT STD_LOGIC;
92
93 --SPACE WIRE
94 SPW_EN : OUT STD_LOGIC; -- 0 => off
95 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
96 SPW_NOM_SIN : IN STD_LOGIC;
97 SPW_NOM_DOUT : OUT STD_LOGIC;
98 SPW_NOM_SOUT : OUT STD_LOGIC;
99 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
100 SPW_RED_SIN : IN STD_LOGIC;
101 SPW_RED_DOUT : OUT STD_LOGIC;
102 SPW_RED_SOUT : OUT STD_LOGIC;
103 -- MINI LFR ADC INPUTS
104 ADC_nCS : OUT STD_LOGIC;
105 ADC_CLK : OUT STD_LOGIC;
106 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
107
108 -- SRAM
109 SRAM_nWE : OUT STD_LOGIC;
110 SRAM_CE : OUT STD_LOGIC;
111 SRAM_nOE : OUT STD_LOGIC;
112 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
113 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
114 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
115 );
116
117 END MINI_LFR_top;
118
119
120 ARCHITECTURE beh OF MINI_LFR_top IS
121
122 --==========================================================================
123 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
124 -- when enabled, chip enable polarity should be reversed and bank size also
125 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
126 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
127 --==========================================================================
128 CONSTANT USE_IAP_MEMCTRL : integer := 1;
129 --==========================================================================
130
131 SIGNAL clk_50_s : STD_LOGIC := '0';
132 SIGNAL clk_25 : STD_LOGIC := '0';
133 SIGNAL clk_24 : STD_LOGIC := '0';
134 -----------------------------------------------------------------------------
135 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
137 --
138 SIGNAL errorn : STD_LOGIC;
139 -- UART AHB ---------------------------------------------------------------
140 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
141 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
142
143 -- UART APB ---------------------------------------------------------------
144 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
145 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
146 --
147 SIGNAL I00_s : STD_LOGIC;
148
149 -- CONSTANTS
150 CONSTANT CFG_PADTECH : INTEGER := inferred;
151 --
152 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
153 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
154 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
155
156 SIGNAL apbi_ext : apb_slv_in_type;
157 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
158 SIGNAL ahbi_s_ext : ahb_slv_in_type;
159 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
160 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
161 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
162
163 -- Spacewire signals
164 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
165 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
167 SIGNAL spw_rxtxclk : STD_ULOGIC;
168 SIGNAL spw_rxclkn : STD_ULOGIC;
169 SIGNAL spw_clk : STD_LOGIC;
170 SIGNAL swni : grspw_in_type;
171 SIGNAL swno : grspw_out_type;
172 -- SIGNAL clkmn : STD_ULOGIC;
173 -- SIGNAL txclk : STD_ULOGIC;
174
175 --GPIO
176 SIGNAL gpioi : gpio_in_type;
177 SIGNAL gpioo : gpio_out_type;
178
179 -- AD Converter ADS7886
180 SIGNAL sample : Samples14v(7 DOWNTO 0);
181 SIGNAL sample_s : Samples(7 DOWNTO 0);
182 SIGNAL sample_val : STD_LOGIC;
183 SIGNAL ADC_nCS_sig : STD_LOGIC;
184 SIGNAL ADC_CLK_sig : STD_LOGIC;
185 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
186
187 SIGNAL bias_fail_sw_sig : STD_LOGIC;
188
189 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
191 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
192 -----------------------------------------------------------------------------
193
194 SIGNAL LFR_soft_rstn : STD_LOGIC;
195 SIGNAL LFR_rstn : STD_LOGIC;
196
197
198 SIGNAL rstn_25 : STD_LOGIC;
199 SIGNAL rstn_25_d1 : STD_LOGIC;
200 SIGNAL rstn_25_d2 : STD_LOGIC;
201 SIGNAL rstn_25_d3 : STD_LOGIC;
202
203 SIGNAL rstn_24 : STD_LOGIC;
204 SIGNAL rstn_24_d1 : STD_LOGIC;
205 SIGNAL rstn_24_d2 : STD_LOGIC;
206 SIGNAL rstn_24_d3 : STD_LOGIC;
207
208 SIGNAL rstn_50 : STD_LOGIC;
209 SIGNAL rstn_50_d1 : STD_LOGIC;
210 SIGNAL rstn_50_d2 : STD_LOGIC;
211 SIGNAL rstn_50_d3 : STD_LOGIC;
212
213 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
214 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
215
216 --
217 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
218
219 --
220 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
221 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
222
223 SIGNAL nSRAM_READY : STD_LOGIC;
224
225 BEGIN -- beh
226
227 -----------------------------------------------------------------------------
228 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
229 -- clk_50 frequency is 100 Mhz !
230 PROCESS (clk_50, reset)
231 BEGIN -- PROCESS
232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
233 clk_50_s <= NOT clk_50_s;
234 END IF;
235 END PROCESS;
236 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
237 -----------------------------------------------------------------------------
238
239 PROCESS (clk_50_s, reset)
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 clk_25 <= '0';
243 rstn_25 <= '0';
244 rstn_25_d1 <= '0';
245 rstn_25_d2 <= '0';
246 rstn_25_d3 <= '0';
247 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
248 clk_25 <= NOT clk_25;
249 rstn_25_d1 <= '1';
250 rstn_25_d2 <= rstn_25_d1;
251 rstn_25_d3 <= rstn_25_d2;
252 rstn_25 <= rstn_25_d3;
253 END IF;
254 END PROCESS;
255
256 PROCESS (clk_49, reset)
257 BEGIN -- PROCESS
258 IF reset = '0' THEN -- asynchronous reset (active low)
259 clk_24 <= '0';
260 rstn_24_d1 <= '0';
261 rstn_24_d2 <= '0';
262 rstn_24_d3 <= '0';
263 rstn_24 <= '0';
264 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
265 clk_24 <= NOT clk_24;
266 rstn_24_d1 <= '1';
267 rstn_24_d2 <= rstn_24_d1;
268 rstn_24_d3 <= rstn_24_d2;
269 rstn_24 <= rstn_24_d3;
270 END IF;
271 END PROCESS;
272
273 -----------------------------------------------------------------------------
274
275 PROCESS (clk_25, rstn_25)
276 BEGIN -- PROCESS
277 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 LED0 <= '0';
279 LED1 <= '0';
280 LED2 <= '0';
281 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
282 LED0 <= '0';
283 LED1 <= '1';
284 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
285 END IF;
286 END PROCESS;
287
288 PROCESS (clk_24, rstn_24)
289 BEGIN -- PROCESS
290 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
291 I00_s <= '0';
292 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
293 I00_s <= NOT I00_s;
294 END IF;
295 END PROCESS;
296
297 --UARTs
298 nCTS1 <= '1';
299 nCTS2 <= '1';
300 nDCD2 <= '1';
301
302 --
303
304 leon3_soc_1 : leon3_soc
305 GENERIC MAP (
306 fabtech => apa3e,
307 memtech => apa3e,
308 padtech => inferred,
309 clktech => inferred,
310 disas => 0,
311 dbguart => 0,
312 pclow => 2,
313 clk_freq => 25000,
314 IS_RADHARD => 0,
315 NB_CPU => 1,
316 ENABLE_FPU => 1,
317 FPU_NETLIST => 0,
318 ENABLE_DSU => 1,
319 ENABLE_AHB_UART => 0,
320 ENABLE_APB_UART => 1,
321 ENABLE_IRQMP => 1,
322 ENABLE_GPT => 1,
323 NB_AHB_MASTER => NB_AHB_MASTER,
324 NB_AHB_SLAVE => NB_AHB_SLAVE,
325 NB_APB_SLAVE => NB_APB_SLAVE,
326 ADDRESS_SIZE => 20,
327 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
328 BYPASS_EDAC_MEMCTRLR => '0',
329 SRBANKSZ => 9)
330 PORT MAP (
331 clk => clk_25,
332 reset => rstn_25,
333 errorn => errorn,
334 ahbrxd => OPEN,--TXD1,
335 ahbtxd => OPEN,--RXD1,
336 urxd1 => TXD2,
337 utxd1 => RXD2,
338 address => SRAM_A,
339 data => SRAM_DQ,
340 nSRAM_BE0 => SRAM_nBE(0),
341 nSRAM_BE1 => SRAM_nBE(1),
342 nSRAM_BE2 => SRAM_nBE(2),
343 nSRAM_BE3 => SRAM_nBE(3),
344 nSRAM_WE => SRAM_nWE,
345 nSRAM_CE => SRAM_CE_s,
346 nSRAM_OE => SRAM_nOE,
347 nSRAM_READY => nSRAM_READY,
348 SRAM_MBE => OPEN,
349 apbi_ext => apbi_ext,
350 apbo_ext => apbo_ext,
351 ahbi_s_ext => ahbi_s_ext,
352 ahbo_s_ext => ahbo_s_ext,
353 ahbi_m_ext => ahbi_m_ext,
354 ahbo_m_ext => ahbo_m_ext);
355
356 PROCESS (clk_25, rstn_25)
357 BEGIN -- PROCESS
358 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
359 nSRAM_READY <= '1';
360 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
361 nSRAM_READY <= '1';
362 IF IO0 = '1' THEN
363 nSRAM_READY <= '0';
364 END IF;
365 END IF;
366 END PROCESS;
367
368
369
370 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
371 SRAM_CE <= not SRAM_CE_s(0);
372 END GENERATE;
373
374 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
375 SRAM_CE <= SRAM_CE_s(0);
376 END GENERATE;
377 -------------------------------------------------------------------------------
378 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
379 -------------------------------------------------------------------------------
380 apb_lfr_management_1 : apb_lfr_management
381 GENERIC MAP (
382 tech => apa3e,
383 pindex => 6,
384 paddr => 6,
385 pmask => 16#fff#,
386 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
387 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
388 PORT MAP (
389 clk25MHz => clk_25,
390 resetn_25MHz => rstn_25, -- TODO
391 -- clk24_576MHz => clk_24, -- 49.152MHz/2
392 -- resetn_24_576MHz => rstn_24, -- TODO
393 grspw_tick => swno.tickout,
394 apbi => apbi_ext,
395 apbo => apbo_ext(6),
396 HK_sample => sample_hk,
397 HK_val => sample_val,
398 HK_sel => HK_SEL,
399 DAC_SDO => OPEN,
400 DAC_SCK => OPEN,
401 DAC_SYNC => OPEN,
402 DAC_CAL_EN => OPEN,
403 coarse_time => coarse_time,
404 fine_time => fine_time,
405 LFR_soft_rstn => LFR_soft_rstn
406 );
407
408 -----------------------------------------------------------------------
409 --- SpaceWire --------------------------------------------------------
410 -----------------------------------------------------------------------
411
412 SPW_EN <= '1';
413
414 spw_clk <= clk_50_s;
415 spw_rxtxclk <= spw_clk;
416 spw_rxclkn <= NOT spw_rxtxclk;
417
418 -- PADS for SPW1
419 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
420 PORT MAP (SPW_NOM_DIN, dtmp(0));
421 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
422 PORT MAP (SPW_NOM_SIN, stmp(0));
423 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
424 PORT MAP (SPW_NOM_DOUT, swno.d(0));
425 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_NOM_SOUT, swno.s(0));
427 -- PADS FOR SPW2
428 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
429 PORT MAP (SPW_RED_SIN, dtmp(1));
430 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
431 PORT MAP (SPW_RED_DIN, stmp(1));
432 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
433 PORT MAP (SPW_RED_DOUT, swno.d(1));
434 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
435 PORT MAP (SPW_RED_SOUT, swno.s(1));
436
437 -- GRSPW PHY
438 --spw1_input: if CFG_SPW_GRSPW = 1 generate
439 spw_inputloop : FOR j IN 0 TO 1 GENERATE
440 spw_phy0 : grspw_phy
441 GENERIC MAP(
442 tech => apa3e,
443 rxclkbuftype => 1,
444 scantest => 0)
445 PORT MAP(
446 rxrst => swno.rxrst,
447 di => dtmp(j),
448 si => stmp(j),
449 rxclko => spw_rxclk(j),
450 do => swni.d(j),
451 ndo => swni.nd(j*5+4 DOWNTO j*5),
452 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
453 END GENERATE spw_inputloop;
454
455 swni.rmapnodeaddr <= (OTHERS => '0');
456
457 -- SPW core
458 sw0 : grspwm GENERIC MAP(
459 tech => apa3e,
460 hindex => 1,
461 pindex => 5,
462 paddr => 5,
463 pirq => 11,
464 sysfreq => 25000, -- CPU_FREQ
465 rmap => 1,
466 rmapcrc => 1,
467 fifosize1 => 16,
468 fifosize2 => 16,
469 rxclkbuftype => 1,
470 rxunaligned => 0,
471 rmapbufs => 4,
472 ft => 0,
473 netlist => 0,
474 ports => 2,
475 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
476 memtech => apa3e,
477 destkey => 2,
478 spwcore => 1
479 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
480 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
481 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
482 )
483 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
484 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
485 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
486 swni, swno);
487
488 swni.tickin <= '0';
489 swni.rmapen <= '1';
490 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
491 swni.tickinraw <= '0';
492 swni.timein <= (OTHERS => '0');
493 swni.dcrstval <= (OTHERS => '0');
494 swni.timerrstval <= (OTHERS => '0');
495
496 -------------------------------------------------------------------------------
497 -- LFR ------------------------------------------------------------------------
498 -------------------------------------------------------------------------------
499
500
501 LFR_rstn <= LFR_soft_rstn AND rstn_25;
502 --LFR_rstn <= rstn_25;
503
504 lpp_lfr_1 : lpp_lfr
505 GENERIC MAP (
506 Mem_use => use_RAM,
507 nb_data_by_buffer_size => 32,
508 nb_snapshot_param_size => 32,
509 delta_vector_size => 32,
510 delta_vector_size_f0_2 => 7, -- log2(96)
511 pindex => 15,
512 paddr => 15,
513 pmask => 16#fff#,
514 pirq_ms => 6,
515 pirq_wfp => 14,
516 hindex => 2,
517 top_lfr_version => X"000159") -- aa.bb.cc version
518 PORT MAP (
519 clk => clk_25,
520 rstn => LFR_rstn,
521 sample_B => sample_s(2 DOWNTO 0),
522 sample_E => sample_s(7 DOWNTO 3),
523 sample_val => sample_val,
524 apbi => apbi_ext,
525 apbo => apbo_ext(15),
526 ahbi => ahbi_m_ext,
527 ahbo => ahbo_m_ext(2),
528 coarse_time => coarse_time,
529 fine_time => fine_time,
530 data_shaping_BW => bias_fail_sw_sig,
531 debug_vector => lfr_debug_vector,
532 debug_vector_ms => lfr_debug_vector_ms
533 );
534
535 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
536 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
537 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
538 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
539 -- IO0 <= rstn_25;
540 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
541 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
542 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
543 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
544 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
545 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
546 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
547
548 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
549 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
550 END GENERATE all_sample;
551
552 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
553 GENERIC MAP(
554 ChannelCount => 8,
555 SampleNbBits => 14,
556 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
557 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
558 PORT MAP (
559 -- CONV
560 cnv_clk => clk_24,
561 cnv_rstn => rstn_24,
562 cnv => ADC_nCS_sig,
563 -- DATA
564 clk => clk_25,
565 rstn => rstn_25,
566 sck => ADC_CLK_sig,
567 sdo => ADC_SDO_sig,
568 -- SAMPLE
569 sample => sample,
570 sample_val => sample_val);
571
572 --IO10 <= ADC_SDO_sig(5);
573 --IO9 <= ADC_SDO_sig(4);
574 --IO8 <= ADC_SDO_sig(3);
575
576 ADC_nCS <= ADC_nCS_sig;
577 ADC_CLK <= ADC_CLK_sig;
578 ADC_SDO_sig <= ADC_SDO;
579
580 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
581 "0010001000100010" WHEN HK_SEL = "01" ELSE
582 "0100010001000100" WHEN HK_SEL = "10" ELSE
583 (OTHERS => '0');
584
585
586 ----------------------------------------------------------------------
587 --- GPIO -----------------------------------------------------------
588 ----------------------------------------------------------------------
589
590 grgpio0 : grgpio
591 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
592 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
593
594 gpioi.sig_en <= (OTHERS => '0');
595 gpioi.sig_in <= (OTHERS => '0');
596 gpioi.din <= (OTHERS => '0');
597 PROCESS (clk_25, rstn_25)
598 BEGIN -- PROCESS
599 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
600 IO8 <= '0';
601 IO9 <= '0';
602 IO10 <= '0';
603 IO11 <= '0';
604 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
605 CASE gpioo.dout(2 DOWNTO 0) IS
606 WHEN "011" =>
607 IO8 <= observation_reg(8);
608 IO9 <= observation_reg(9);
609 IO10 <= observation_reg(10);
610 IO11 <= observation_reg(11);
611 WHEN "001" =>
612 IO8 <= observation_reg(8 + 12);
613 IO9 <= observation_reg(9 + 12);
614 IO10 <= observation_reg(10 + 12);
615 IO11 <= observation_reg(11 + 12);
616 WHEN "010" =>
617 IO8 <= '0';
618 IO9 <= '0';
619 IO10 <= '0';
620 IO11 <= '0';
621 WHEN "000" =>
622 IO8 <= observation_vector_0(8);
623 IO9 <= observation_vector_0(9);
624 IO10 <= observation_vector_0(10);
625 IO11 <= observation_vector_0(11);
626 WHEN "100" =>
627 IO8 <= observation_vector_1(8);
628 IO9 <= observation_vector_1(9);
629 IO10 <= observation_vector_1(10);
630 IO11 <= observation_vector_1(11);
631 WHEN OTHERS => NULL;
632 END CASE;
633
634 END IF;
635 END PROCESS;
636 -----------------------------------------------------------------------------
637 --
638 -----------------------------------------------------------------------------
639 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
640 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
641 apbo_ext(I) <= apb_none;
642 END GENERATE apbo_ext_not_used;
643 END GENERATE all_apbo_ext;
644
645
646 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
647 ahbo_s_ext(I) <= ahbs_none;
648 END GENERATE all_ahbo_ext;
649
650 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
651 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
652 ahbo_m_ext(I) <= ahbm_none;
653 END GENERATE ahbo_m_ext_not_used;
654 END GENERATE all_ahbo_m_ext;
655
656 END beh;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk100MHz : IN STD_LOGIC;
52 clk49_152MHz : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
125
126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
129 -----------------------------------------------------------------------------
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 --
133 SIGNAL errorn : STD_LOGIC;
134 -- UART AHB ---------------------------------------------------------------
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
137
138 -- UART APB ---------------------------------------------------------------
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
141 --
142 SIGNAL I00_s : STD_LOGIC;
143
144 -- CONSTANTS
145 CONSTANT CFG_PADTECH : INTEGER := inferred;
146 --
147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
150
151 SIGNAL apbi_ext : apb_slv_in_type;
152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
157
158 -- Spacewire signals
159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL spw_rxtxclk : STD_ULOGIC;
163 SIGNAL spw_rxclkn : STD_ULOGIC;
164 SIGNAL spw_clk : STD_LOGIC;
165 SIGNAL swni : grspw_in_type;
166 SIGNAL swno : grspw_out_type;
167 -- SIGNAL clkmn : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
169
170 --GPIO
171 SIGNAL gpioi : gpio_in_type;
172 SIGNAL gpioo : gpio_out_type;
173
174 -- AD Converter ADS7886
175 SIGNAL sample : Samples14v(7 DOWNTO 0);
176 SIGNAL sample_s : Samples(7 DOWNTO 0);
177 SIGNAL sample_val : STD_LOGIC;
178 SIGNAL ADC_nCS_sig : STD_LOGIC;
179 SIGNAL ADC_CLK_sig : STD_LOGIC;
180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
181
182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
183
184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
187 -----------------------------------------------------------------------------
188
189 SIGNAL LFR_soft_rstn : STD_LOGIC;
190 SIGNAL LFR_rstn : STD_LOGIC;
191
192
193 SIGNAL rstn_25 : STD_LOGIC;
194 SIGNAL rstn_25_d1 : STD_LOGIC;
195 SIGNAL rstn_25_d2 : STD_LOGIC;
196 SIGNAL rstn_25_d3 : STD_LOGIC;
197
198 SIGNAL rstn_24 : STD_LOGIC;
199 SIGNAL rstn_24_d1 : STD_LOGIC;
200 SIGNAL rstn_24_d2 : STD_LOGIC;
201 SIGNAL rstn_24_d3 : STD_LOGIC;
202
203 SIGNAL rstn_50 : STD_LOGIC;
204 SIGNAL rstn_50_d1 : STD_LOGIC;
205 SIGNAL rstn_50_d2 : STD_LOGIC;
206 SIGNAL rstn_50_d3 : STD_LOGIC;
207
208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
210
211 --
212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
213
214 --
215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
217
218 SIGNAL nSRAM_READY : STD_LOGIC;
219
220 BEGIN -- beh
221
222 -----------------------------------------------------------------------------
223 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
224 -- clk_50 frequency is 100 Mhz !
225 PROCESS (clk100MHz, reset)
226 BEGIN -- PROCESS
227 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
228 clk_50_s <= NOT clk_50_s;
229 END IF;
230 END PROCESS;
231 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
232 -----------------------------------------------------------------------------
233
234 PROCESS (clk_50_s, reset)
235 BEGIN -- PROCESS
236 IF reset = '0' THEN -- asynchronous reset (active low)
237 clk_25 <= '0';
238 rstn_25 <= '0';
239 rstn_25_d1 <= '0';
240 rstn_25_d2 <= '0';
241 rstn_25_d3 <= '0';
242 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
243 clk_25 <= NOT clk_25;
244 rstn_25_d1 <= '1';
245 rstn_25_d2 <= rstn_25_d1;
246 rstn_25_d3 <= rstn_25_d2;
247 rstn_25 <= rstn_25_d3;
248 END IF;
249 END PROCESS;
250
251 PROCESS (clk49_152MHz, reset)
252 BEGIN -- PROCESS
253 IF reset = '0' THEN -- asynchronous reset (active low)
254 clk_24 <= '0';
255 rstn_24_d1 <= '0';
256 rstn_24_d2 <= '0';
257 rstn_24_d3 <= '0';
258 rstn_24 <= '0';
259 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
260 clk_24 <= NOT clk_24;
261 rstn_24_d1 <= '1';
262 rstn_24_d2 <= rstn_24_d1;
263 rstn_24_d3 <= rstn_24_d2;
264 rstn_24 <= rstn_24_d3;
265 END IF;
266 END PROCESS;
267
268 -----------------------------------------------------------------------------
269
270 PROCESS (clk_25, rstn_25)
271 BEGIN -- PROCESS
272 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
273 LED0 <= '0';
274 LED1 <= '0';
275 LED2 <= '0';
276 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
277 LED0 <= '0';
278 LED1 <= '1';
279 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
280 END IF;
281 END PROCESS;
282
283 PROCESS (clk49_152MHz, rstn_24)
284 BEGIN -- PROCESS
285 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
286 I00_s <= '0';
287 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
288 I00_s <= NOT I00_s;
289 END IF;
290 END PROCESS;
291
292 --UARTs
293 nCTS1 <= '1';
294 nCTS2 <= '1';
295 nDCD2 <= '1';
296 -- No AHB UART
297 RXD1 <= TXD1;
298
299 --
300
301 leon3_soc_1 : leon3_soc
302 GENERIC MAP (
303 fabtech => apa3e,
304 memtech => apa3e,
305 padtech => inferred,
306 clktech => inferred,
307 disas => 0,
308 dbguart => 0,
309 pclow => 2,
310 clk_freq => 25000,
311 IS_RADHARD => 0,
312 NB_CPU => 1,
313 ENABLE_FPU => 1,
314 FPU_NETLIST => 0,
315 ENABLE_DSU => 1,
316 ENABLE_AHB_UART => 0,
317 ENABLE_APB_UART => 1,
318 ENABLE_IRQMP => 1,
319 ENABLE_GPT => 1,
320 NB_AHB_MASTER => NB_AHB_MASTER,
321 NB_AHB_SLAVE => NB_AHB_SLAVE,
322 NB_APB_SLAVE => NB_APB_SLAVE,
323 ADDRESS_SIZE => 20,
324 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
325 BYPASS_EDAC_MEMCTRLR => '0',
326 SRBANKSZ => 9)
327 PORT MAP (
328 clk => clk_25,
329 reset => rstn_25,
330 errorn => errorn,
331 ahbrxd => OPEN,--TXD1,
332 ahbtxd => OPEN,--RXD1,
333 urxd1 => TXD2,
334 utxd1 => RXD2,
335 address => SRAM_A,
336 data => SRAM_DQ,
337 nSRAM_BE0 => SRAM_nBE(0),
338 nSRAM_BE1 => SRAM_nBE(1),
339 nSRAM_BE2 => SRAM_nBE(2),
340 nSRAM_BE3 => SRAM_nBE(3),
341 nSRAM_WE => SRAM_nWE,
342 nSRAM_CE => SRAM_CE_s,
343 nSRAM_OE => SRAM_nOE,
344 nSRAM_READY => nSRAM_READY,
345 SRAM_MBE => OPEN,
346 apbi_ext => apbi_ext,
347 apbo_ext => apbo_ext,
348 ahbi_s_ext => ahbi_s_ext,
349 ahbo_s_ext => ahbo_s_ext,
350 ahbi_m_ext => ahbi_m_ext,
351 ahbo_m_ext => ahbo_m_ext);
352
353 PROCESS (clk_25, rstn_25)
354 BEGIN -- PROCESS
355 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
356 nSRAM_READY <= '1';
357 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
358 nSRAM_READY <= '1';
359 IF IO0 = '1' THEN
360 nSRAM_READY <= '0';
361 END IF;
362 END IF;
363 END PROCESS;
364
365
366
367 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
368 SRAM_CE <= not SRAM_CE_s(0);
369 END GENERATE;
370
371 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
372 SRAM_CE <= SRAM_CE_s(0);
373 END GENERATE;
374 -------------------------------------------------------------------------------
375 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
376 -------------------------------------------------------------------------------
377 apb_lfr_management_1 : apb_lfr_management
378 GENERIC MAP (
379 tech => apa3e,
380 pindex => 6,
381 paddr => 6,
382 pmask => 16#fff#,
383 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
384 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
385 PORT MAP (
386 clk25MHz => clk_25,
387 resetn_25MHz => rstn_25, -- TODO
388 -- clk24_576MHz => clk_24, -- 49.152MHz/2
389 -- resetn_24_576MHz => rstn_24, -- TODO
390 grspw_tick => swno.tickout,
391 apbi => apbi_ext,
392 apbo => apbo_ext(6),
393 HK_sample => sample_hk,
394 HK_val => sample_val,
395 HK_sel => HK_SEL,
396 DAC_SDO => OPEN,
397 DAC_SCK => OPEN,
398 DAC_SYNC => OPEN,
399 DAC_CAL_EN => OPEN,
400 coarse_time => coarse_time,
401 fine_time => fine_time,
402 LFR_soft_rstn => LFR_soft_rstn
403 );
404
405 -----------------------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
407 -----------------------------------------------------------------------
408
409 SPW_EN <= '1';
410
411 spw_clk <= clk_50_s;
412 spw_rxtxclk <= spw_clk;
413 spw_rxclkn <= NOT spw_rxtxclk;
414
415 -- PADS for SPW1
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SIN, stmp(0));
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 -- PADS FOR SPW2
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 PORT MAP (SPW_RED_SIN, dtmp(1));
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 PORT MAP (SPW_RED_DIN, stmp(1));
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
433
434 -- GRSPW PHY
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 spw_phy0 : grspw_phy
438 GENERIC MAP(
439 tech => apa3e,
440 rxclkbuftype => 1,
441 scantest => 0)
442 PORT MAP(
443 rxrst => swno.rxrst,
444 di => dtmp(j),
445 si => stmp(j),
446 rxclko => spw_rxclk(j),
447 do => swni.d(j),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 END GENERATE spw_inputloop;
451
452 swni.rmapnodeaddr <= (OTHERS => '0');
453
454 -- SPW core
455 sw0 : grspwm GENERIC MAP(
456 tech => apa3e,
457 hindex => 1,
458 pindex => 5,
459 paddr => 5,
460 pirq => 11,
461 sysfreq => 25000, -- CPU_FREQ
462 rmap => 1,
463 rmapcrc => 1,
464 fifosize1 => 16,
465 fifosize2 => 16,
466 rxclkbuftype => 1,
467 rxunaligned => 0,
468 rmapbufs => 4,
469 ft => 0,
470 netlist => 0,
471 ports => 2,
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 memtech => apa3e,
474 destkey => 2,
475 spwcore => 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 )
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 swni, swno);
484
485 swni.tickin <= '0';
486 swni.rmapen <= '1';
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 swni.tickinraw <= '0';
489 swni.timein <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
492
493 -------------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
496
497
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 --LFR_rstn <= rstn_25;
500
501 lpp_lfr_1 : lpp_lfr
502 GENERIC MAP (
503 Mem_use => use_RAM,
504 nb_data_by_buffer_size => 32,
505 nb_snapshot_param_size => 32,
506 delta_vector_size => 32,
507 delta_vector_size_f0_2 => 7, -- log2(96)
508 pindex => 15,
509 paddr => 15,
510 pmask => 16#fff#,
511 pirq_ms => 6,
512 pirq_wfp => 14,
513 hindex => 2,
514 top_lfr_version => X"000159") -- aa.bb.cc version
515 PORT MAP (
516 clk => clk_25,
517 rstn => LFR_rstn,
518 sample_B => sample_s(2 DOWNTO 0),
519 sample_E => sample_s(7 DOWNTO 3),
520 sample_val => sample_val,
521 apbi => apbi_ext,
522 apbo => apbo_ext(15),
523 ahbi => ahbi_m_ext,
524 ahbo => ahbo_m_ext(2),
525 coarse_time => coarse_time,
526 fine_time => fine_time,
527 data_shaping_BW => bias_fail_sw_sig,
528 debug_vector => lfr_debug_vector,
529 debug_vector_ms => lfr_debug_vector_ms
530 );
531
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 -- IO0 <= rstn_25;
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 END GENERATE all_sample;
548
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 GENERIC MAP(
551 ChannelCount => 8,
552 SampleNbBits => 14,
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 PORT MAP (
556 -- CONV
557 cnv_clk => clk_24,
558 cnv_rstn => rstn_24,
559 cnv => ADC_nCS_sig,
560 -- DATA
561 clk => clk_25,
562 rstn => rstn_25,
563 sck => ADC_CLK_sig,
564 sdo => ADC_SDO_sig,
565 -- SAMPLE
566 sample => sample,
567 sample_val => sample_val);
568
569 --IO10 <= ADC_SDO_sig(5);
570 --IO9 <= ADC_SDO_sig(4);
571 --IO8 <= ADC_SDO_sig(3);
572
573 ADC_nCS <= ADC_nCS_sig;
574 ADC_CLK <= ADC_CLK_sig;
575 ADC_SDO_sig <= ADC_SDO;
576
577 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
578 "0010001000100010" WHEN HK_SEL = "01" ELSE
579 "0100010001000100" WHEN HK_SEL = "10" ELSE
580 (OTHERS => '0');
581
582
583 ----------------------------------------------------------------------
584 --- GPIO -----------------------------------------------------------
585 ----------------------------------------------------------------------
586
587 grgpio0 : grgpio
588 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
589 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
590
591 gpioi.sig_en <= (OTHERS => '0');
592 gpioi.sig_in <= (OTHERS => '0');
593 gpioi.din <= (OTHERS => '0');
594 PROCESS (clk_25, rstn_25)
595 BEGIN -- PROCESS
596 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
597 IO8 <= '0';
598 IO9 <= '0';
599 IO10 <= '0';
600 IO11 <= '0';
601 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
602 CASE gpioo.dout(2 DOWNTO 0) IS
603 WHEN "011" =>
604 IO8 <= observation_reg(8);
605 IO9 <= observation_reg(9);
606 IO10 <= observation_reg(10);
607 IO11 <= observation_reg(11);
608 WHEN "001" =>
609 IO8 <= observation_reg(8 + 12);
610 IO9 <= observation_reg(9 + 12);
611 IO10 <= observation_reg(10 + 12);
612 IO11 <= observation_reg(11 + 12);
613 WHEN "010" =>
614 IO8 <= '0';
615 IO9 <= '0';
616 IO10 <= '0';
617 IO11 <= '0';
618 WHEN "000" =>
619 IO8 <= observation_vector_0(8);
620 IO9 <= observation_vector_0(9);
621 IO10 <= observation_vector_0(10);
622 IO11 <= observation_vector_0(11);
623 WHEN "100" =>
624 IO8 <= observation_vector_1(8);
625 IO9 <= observation_vector_1(9);
626 IO10 <= observation_vector_1(10);
627 IO11 <= observation_vector_1(11);
628 WHEN OTHERS => NULL;
629 END CASE;
630
631 END IF;
632 END PROCESS;
633 -----------------------------------------------------------------------------
634 --
635 -----------------------------------------------------------------------------
636 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
637 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
638 apbo_ext(I) <= apb_none;
639 END GENERATE apbo_ext_not_used;
640 END GENERATE all_apbo_ext;
641
642
643 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
644 ahbo_s_ext(I) <= ahbs_none;
645 END GENERATE all_ahbo_ext;
646
647 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
648 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
649 ahbo_m_ext(I) <= ahbm_none;
650 END GENERATE ahbo_m_ext_not_used;
651 END GENERATE all_ahbo_m_ext;
652
653 END beh;
Show file before | Show file after | Hide comments
@@ -13,11 +13,9 SYNPOPT="set_option -pipe 0; set_option
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 ##PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 PDC=$(VHDLIB)/boards/$(BOARD)/no_uart.pdc
19 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
21 19 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 20 CLEAN=soft-clean
23 21
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