@@ -0,0 +1,85 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | library IEEE; | |||
|
23 | use IEEE.numeric_std.all; | |||
|
24 | use IEEE.std_logic_1164.all; | |||
|
25 | ||||
|
26 | entity Starter is | |||
|
27 | port( | |||
|
28 | clk : in std_logic; | |||
|
29 | raz : in std_logic; | |||
|
30 | empty1 : in std_logic; | |||
|
31 | empty2 : in std_logic; | |||
|
32 | Conjugate : in std_logic; | |||
|
33 | Start : out std_logic | |||
|
34 | ); | |||
|
35 | end Starter; | |||
|
36 | ||||
|
37 | ||||
|
38 | architecture ar_Starter of Starter is | |||
|
39 | ||||
|
40 | begin | |||
|
41 | process(clk,raz) | |||
|
42 | begin | |||
|
43 | ||||
|
44 | if(raz='0')then | |||
|
45 | Start <= '0'; | |||
|
46 | ||||
|
47 | elsif(clk'event and clk='1')then | |||
|
48 | ||||
|
49 | if(Conjugate='1')then | |||
|
50 | if(empty1='1')then | |||
|
51 | Start <= '0'; | |||
|
52 | else | |||
|
53 | Start <= '1'; | |||
|
54 | end if; | |||
|
55 | else | |||
|
56 | if(empty1='1' or empty2='1')then | |||
|
57 | Start <= '0'; | |||
|
58 | else | |||
|
59 | Start <= '1'; | |||
|
60 | end if; | |||
|
61 | ||||
|
62 | end if; | |||
|
63 | end if; | |||
|
64 | end process; | |||
|
65 | ||||
|
66 | end ar_Starter; | |||
|
67 | ||||
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68 | ||||
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69 | ||||
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70 | ||||
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71 | ||||
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72 | ||||
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73 | ||||
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74 | ||||
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75 | ||||
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77 | ||||
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@@ -1,359 +1,189 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 |
|
25 | |||
26 | entity SelectInputs is |
|
26 | entity SelectInputs is | |
27 | generic( |
|
27 | generic( | |
28 | Input_SZ : integer := 16); |
|
28 | Input_SZ : integer := 16); | |
29 | port( |
|
29 | port( | |
30 | clk : in std_logic; |
|
30 | clk : in std_logic; | |
31 | raz : in std_logic; |
|
31 | raz : in std_logic; | |
32 | Read : in std_logic; |
|
32 | Read : in std_logic; | |
33 | B1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
33 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |
34 | B2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
34 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |
35 | B3 : in std_logic_vector(Input_SZ-1 downto 0); |
|
35 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |
36 | E1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
36 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |
37 | E2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
37 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |
38 | Conjugate : out std_logic; |
|
38 | Conjugate : out std_logic; | |
39 | Take : out std_logic; |
|
39 | Take : out std_logic; | |
40 |
ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 |
|
40 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |
41 |
|
|
41 | Statu : out std_logic_vector(3 downto 0); | |
42 |
OP |
|
42 | OP1 : out std_logic_vector(Input_SZ-1 downto 0); | |
43 | ); |
|
43 | OP2 : out std_logic_vector(Input_SZ-1 downto 0) | |
44 | end SelectInputs; |
|
44 | ); | |
45 |
|
45 | end SelectInputs; | ||
46 |
|
46 | |||
47 | architecture ar_SelectInputs of SelectInputs is |
|
47 | ||
|
48 | architecture ar_SelectInputs of SelectInputs is | |||
48 |
|
49 | |||
49 | signal Read_reg : std_logic; |
|
50 | signal Read_reg : std_logic; | |
50 |
signal i : integer range |
|
51 | signal i : integer range 0 to 128; | |
|
52 | signal j : integer range 0 to 15; | |||
|
53 | signal Read_int : std_logic_vector(4 downto 0); | |||
51 |
|
54 | |||
52 |
type state is (stX,st |
|
55 | type state is (stX,sta,stb,st1,st2,idl1,idl2); | |
53 | signal ect : state; |
|
56 | signal ect : state; | |
54 |
|
57 | |||
55 | begin |
|
58 | begin | |
56 | process(clk,raz) |
|
59 | process(clk,raz) | |
57 | begin |
|
60 | begin | |
58 |
|
61 | |||
59 | if(raz='0')then |
|
62 | if(raz='0')then | |
60 | Take <= '0'; |
|
63 | Take <= '0'; | |
61 | i <= 0; |
|
64 | i <= 0; | |
|
65 | j <= 0; | |||
62 | Read_reg <= '0'; |
|
66 | Read_reg <= '0'; | |
63 | ect <= stX; |
|
67 | ect <= stX; | |
64 |
|
68 | |||
65 | elsif(clk'event and clk='1')then |
|
69 | elsif(clk'event and clk='1')then | |
66 | Read_reg <= Read; |
|
70 | Read_reg <= Read; | |
67 |
|
71 | |||
68 | case ect is |
|
72 | case ect is | |
|
73 | ||||
69 | when stX => |
|
74 | when stX => | |
70 |
|
|
75 | i <= 1; | |
71 |
|
|
76 | if(Read_reg='0' and Read='1')then | |
72 |
|
|
77 | if(j=15)then | |
|
78 | j <= 1; | |||
|
79 | else | |||
|
80 | j<= j+1; | |||
|
81 | end if; | |||
|
82 | ect <= idl1; | |||
73 | end if; |
|
83 | end if; | |
74 | ------------------------------------------------------------------------------- |
|
84 | ||
75 |
|
|
85 | when idl1 => | |
76 |
|
|
86 | ect <= st1; | |
|
87 | ||||
|
88 | when st1 => | |||
|
89 | Take <= '1'; | |||
|
90 | ect <= sta; | |||
|
91 | ||||
|
92 | when sta => | |||
77 | if(Read_reg='0' and Read='1')then |
|
93 | if(Read_reg='0' and Read='1')then | |
78 |
ect <= |
|
94 | ect <= idl2; | |
79 | end if; |
|
95 | end if; | |
80 |
|
96 | |||
81 |
when |
|
97 | when idl2 => | |
|
98 | ect <= st2; | |||
|
99 | ||||
|
100 | when st2 => | |||
82 | Take <= '0'; |
|
101 | Take <= '0'; | |
83 |
|
|
102 | ect <= stb; | |
|
103 | ||||
|
104 | when stb => | |||
|
105 | if(i=128)then | |||
84 |
|
|
106 | ect <= stX; | |
85 | elsif(Read_reg='0' and Read='1')then |
|
107 | elsif(Read_reg='0' and Read='1')then | |
86 | i <= i+1; |
|
108 | i <= i+1; | |
87 |
ect <= |
|
109 | ect <= idl1; | |
88 | end if; |
|
110 | end if; | |
89 | ------------------------------------------------------------------------------- |
|
111 | ||
90 | -- when st2a => |
|
|||
91 | -- Take <= '1'; |
|
|||
92 | -- if(Read_reg='0' and Read='1')then |
|
|||
93 | -- ect <= st2b; |
|
|||
94 | -- end if; |
|
|||
95 | -- |
|
|||
96 | -- when st2b => |
|
|||
97 | -- Take <= '0'; |
|
|||
98 | -- if(Read_reg='0' and Read='1')then |
|
|||
99 | -- ect <= st3a; |
|
|||
100 | -- end if; |
|
|||
101 | --------------------------------------------------------------------------------- |
|
|||
102 | -- when st3a => |
|
|||
103 | -- Take <= '1'; |
|
|||
104 | -- if(Read_reg='0' and Read='1')then |
|
|||
105 | -- ect <= st3b; |
|
|||
106 | -- end if; |
|
|||
107 | -- |
|
|||
108 | -- when st3b => |
|
|||
109 | -- Take <= '0'; |
|
|||
110 | -- if(Read_reg='0' and Read='1')then |
|
|||
111 | -- ect <= st4a; |
|
|||
112 | -- end if; |
|
|||
113 | --------------------------------------------------------------------------------- |
|
|||
114 | -- when st4a => |
|
|||
115 | -- Take <= '1'; |
|
|||
116 | -- if(Read_reg='0' and Read='1')then |
|
|||
117 | -- ect <= st4b; |
|
|||
118 | -- end if; |
|
|||
119 | -- |
|
|||
120 | -- when st4b => |
|
|||
121 | -- Take <= '0'; |
|
|||
122 | -- if(Read_reg='0' and Read='1')then |
|
|||
123 | -- ect <= st5a; |
|
|||
124 | -- end if; |
|
|||
125 | --------------------------------------------------------------------------------- |
|
|||
126 | -- |
|
|||
127 | -- when st5a => |
|
|||
128 | -- Take <= '1'; |
|
|||
129 | -- if(Read_reg='0' and Read='1')then |
|
|||
130 | -- ect <= st5b; |
|
|||
131 | -- end if; |
|
|||
132 | -- |
|
|||
133 | -- when st5b => |
|
|||
134 | -- Take <= '0'; |
|
|||
135 | -- if(Read_reg='0' and Read='1')then |
|
|||
136 | -- ect <= st6a; |
|
|||
137 | -- end if; |
|
|||
138 | --------------------------------------------------------------------------------- |
|
|||
139 | -- when st6a => |
|
|||
140 | -- Take <= '1'; |
|
|||
141 | -- if(Read_reg='0' and Read='1')then |
|
|||
142 | -- ect <= st6b; |
|
|||
143 | -- end if; |
|
|||
144 | -- |
|
|||
145 | -- when st6b => |
|
|||
146 | -- Take <= '0'; |
|
|||
147 | -- if(Read_reg='0' and Read='1')then |
|
|||
148 | -- ect <= st7a; |
|
|||
149 | -- end if; |
|
|||
150 | --------------------------------------------------------------------------------- |
|
|||
151 | -- when st7a => |
|
|||
152 | -- Take <= '1'; |
|
|||
153 | -- if(Read_reg='0' and Read='1')then |
|
|||
154 | -- ect <= st7b; |
|
|||
155 | -- end if; |
|
|||
156 | -- |
|
|||
157 | -- when st7b => |
|
|||
158 | -- Take <= '0'; |
|
|||
159 | -- if(Read_reg='0' and Read='1')then |
|
|||
160 | -- ect <= st8a; |
|
|||
161 | -- end if; |
|
|||
162 | --------------------------------------------------------------------------------- |
|
|||
163 | -- when st8a => |
|
|||
164 | -- Take <= '1'; |
|
|||
165 | -- if(Read_reg='0' and Read='1')then |
|
|||
166 | -- ect <= st8b; |
|
|||
167 | -- end if; |
|
|||
168 | -- |
|
|||
169 | -- when st8b => |
|
|||
170 | -- Take <= '0'; |
|
|||
171 | -- if(Read_reg='0' and Read='1')then |
|
|||
172 | -- ect <= st9a; |
|
|||
173 | -- end if; |
|
|||
174 | --------------------------------------------------------------------------------- |
|
|||
175 | -- when st9a => |
|
|||
176 | -- Take <= '1'; |
|
|||
177 | -- if(Read_reg='0' and Read='1')then |
|
|||
178 | -- ect <= st9b; |
|
|||
179 | -- end if; |
|
|||
180 | -- |
|
|||
181 | -- when st9b => |
|
|||
182 | -- Take <= '0'; |
|
|||
183 | -- if(Read_reg='0' and Read='1')then |
|
|||
184 | -- ect <= st10a; |
|
|||
185 | -- end if; |
|
|||
186 | --------------------------------------------------------------------------------- |
|
|||
187 | -- when st10a => |
|
|||
188 | -- Take <= '1'; |
|
|||
189 | -- if(Read_reg='0' and Read='1')then |
|
|||
190 | -- ect <= st10b; |
|
|||
191 | -- end if; |
|
|||
192 | -- |
|
|||
193 | -- when st10b => |
|
|||
194 | -- Take <= '0'; |
|
|||
195 | -- if(Read_reg='0' and Read='1')then |
|
|||
196 | -- ect <= st11a; |
|
|||
197 | -- end if; |
|
|||
198 | --------------------------------------------------------------------------------- |
|
|||
199 | -- when st11a => |
|
|||
200 | -- Take <= '1'; |
|
|||
201 | -- if(Read_reg='0' and Read='1')then |
|
|||
202 | -- ect <= st11b; |
|
|||
203 | -- end if; |
|
|||
204 | -- |
|
|||
205 | -- when st11b => |
|
|||
206 | -- Take <= '0'; |
|
|||
207 | -- if(Read_reg='0' and Read='1')then |
|
|||
208 | -- ect <= st12a; |
|
|||
209 | -- end if; |
|
|||
210 | --------------------------------------------------------------------------------- |
|
|||
211 | -- when st12a => |
|
|||
212 | -- Take <= '1'; |
|
|||
213 | -- if(Read_reg='0' and Read='1')then |
|
|||
214 | -- ect <= st12b; |
|
|||
215 | -- end if; |
|
|||
216 | -- |
|
|||
217 | -- when st12b => |
|
|||
218 | -- Take <= '0'; |
|
|||
219 | -- if(Read_reg='0' and Read='1')then |
|
|||
220 | -- ect <= st13a; |
|
|||
221 | -- end if; |
|
|||
222 | --------------------------------------------------------------------------------- |
|
|||
223 | -- when st13a => |
|
|||
224 | -- Take <= '1'; |
|
|||
225 | -- if(Read_reg='0' and Read='1')then |
|
|||
226 | -- ect <= st13b; |
|
|||
227 | -- end if; |
|
|||
228 | -- |
|
|||
229 | -- when st13b => |
|
|||
230 | -- Take <= '0'; |
|
|||
231 | -- if(Read_reg='0' and Read='1')then |
|
|||
232 | -- ect <= st14a; |
|
|||
233 | -- end if; |
|
|||
234 | --------------------------------------------------------------------------------- |
|
|||
235 | -- when st14a => |
|
|||
236 | -- Take <= '1'; |
|
|||
237 | -- if(Read_reg='0' and Read='1')then |
|
|||
238 | -- ect <= st14b; |
|
|||
239 | -- end if; |
|
|||
240 | -- |
|
|||
241 | -- when st14b => |
|
|||
242 | -- Take <= '0'; |
|
|||
243 | -- if(Read_reg='0' and Read='1')then |
|
|||
244 | -- ect <= st15a; |
|
|||
245 | -- end if; |
|
|||
246 | --------------------------------------------------------------------------------- |
|
|||
247 | -- when st15a => |
|
|||
248 | -- Take <= '1'; |
|
|||
249 | -- if(Read_reg='0' and Read='1')then |
|
|||
250 | -- ect <= st7_b; |
|
|||
251 | -- end if; |
|
|||
252 | -- |
|
|||
253 | -- when st15b => |
|
|||
254 | -- Take <= '0'; |
|
|||
255 | -- if(Read_reg='0' and Read='1')then |
|
|||
256 | -- ect <= stX; |
|
|||
257 | -- end if; |
|
|||
258 | ------------------------------------------------------------------------------- |
|
|||
259 | end case; |
|
112 | end case; | |
260 | end if; |
|
113 | end if; | |
261 | end process; |
|
114 | end process; | |
262 |
|
115 | |||
263 | with i select |
|
116 | Statu <= std_logic_vector(to_unsigned(j,4)); | |
264 | ReadFIFO <= "10000" when 1, |
|
117 | ||
|
118 | with j select | |||
|
119 | Read_int <= "10000" when 1, | |||
265 | "11000" when 2, |
|
120 | "11000" when 2, | |
266 | "01000" when 3, |
|
121 | "01000" when 3, | |
267 | "10100" when 4, |
|
122 | "10100" when 4, | |
268 | "01100" when 5, |
|
123 | "01100" when 5, | |
269 | "00100" when 6, |
|
124 | "00100" when 6, | |
270 | "10010" when 7, |
|
125 | "10010" when 7, | |
271 | "01010" when 8, |
|
126 | "01010" when 8, | |
272 | "00110" when 9, |
|
127 | "00110" when 9, | |
273 | "00010" when 10, |
|
128 | "00010" when 10, | |
274 | "10001" when 11, |
|
129 | "10001" when 11, | |
275 | "01001" when 12, |
|
130 | "01001" when 12, | |
276 | "00101" when 13, |
|
131 | "00101" when 13, | |
277 | "00011" when 14, |
|
132 | "00011" when 14, | |
278 | "00001" when 15, |
|
133 | "00001" when 15, | |
279 |
"00000" when others; |
|
134 | "00000" when others; | |
280 |
|
135 | |||
281 |
|
|
136 | with ect select | |
282 |
|
|
137 | ReadFIFO <= Read_int when idl1, | |
283 |
|
|
138 | Read_int when idl2, | |
284 |
|
|
139 | "00000" when others; | |
285 | -- Read when st7, |
|
|||
286 | -- Read when st11, |
|
|||
287 | -- '0' when others; |
|
|||
288 | -- |
|
|||
289 | --with ect select |
|
|||
290 | -- ReadB3 <= Read when st3, |
|
|||
291 | -- Read when st4, |
|
|||
292 | -- Read when st5, |
|
|||
293 | -- Read when st8, |
|
|||
294 | -- Read when st12, |
|
|||
295 | -- '0' when others; |
|
|||
296 | -- |
|
|||
297 | --with ect select |
|
|||
298 | -- ReadE1 <= Read when st6, |
|
|||
299 | -- Read when st7, |
|
|||
300 | -- Read when st8, |
|
|||
301 | -- Read when st9, |
|
|||
302 | -- Read when st13, |
|
|||
303 | -- '0' when others; |
|
|||
304 | -- |
|
|||
305 | --with ect select |
|
|||
306 | -- ReadE2 <= Read when st10, |
|
|||
307 | -- Read when st11, |
|
|||
308 | -- Read when st12, |
|
|||
309 | -- Read when st13, |
|
|||
310 | -- Read when st14, |
|
|||
311 | -- '0' when others; |
|
|||
312 |
|
140 | |||
313 | with i select |
|
141 | ||
|
142 | with j select | |||
314 | OP1 <= B1 when 1, |
|
143 | OP1 <= B1 when 1, | |
315 | B1 when 2, |
|
144 | B1 when 2, | |
316 | B1 when 4, |
|
145 | B1 when 4, | |
317 | B1 when 7, |
|
146 | B1 when 7, | |
318 | B1 when 11, |
|
147 | B1 when 11, | |
319 | B2 when 3, |
|
148 | B2 when 3, | |
320 | B2 when 5, |
|
149 | B2 when 5, | |
321 | B2 when 8, |
|
150 | B2 when 8, | |
322 | B2 when 12, |
|
151 | B2 when 12, | |
323 | B3 when 6, |
|
152 | B3 when 6, | |
324 | B3 when 9, |
|
153 | B3 when 9, | |
325 | B3 when 13, |
|
154 | B3 when 13, | |
326 | E1 when 10, |
|
155 | E1 when 10, | |
327 | E1 when 14, |
|
156 | E1 when 14, | |
328 | E2 when 15, |
|
157 | E2 when 15, | |
329 | X"FFFF" when others; |
|
158 | X"FFFF" when others; | |
330 |
|
159 | |||
331 | with i select |
|
160 | ||
|
161 | with j select | |||
332 | OP2 <= B1 when 1, |
|
162 | OP2 <= B1 when 1, | |
333 | B2 when 2, |
|
163 | B2 when 2, | |
334 | B2 when 3, |
|
164 | B2 when 3, | |
335 | B3 when 4, |
|
165 | B3 when 4, | |
336 | B3 when 5, |
|
166 | B3 when 5, | |
337 | B3 when 6, |
|
167 | B3 when 6, | |
338 | E1 when 7, |
|
168 | E1 when 7, | |
339 | E1 when 8, |
|
169 | E1 when 8, | |
340 | E1 when 9, |
|
170 | E1 when 9, | |
341 | E1 when 10, |
|
171 | E1 when 10, | |
342 | E2 when 11, |
|
172 | E2 when 11, | |
343 | E2 when 12, |
|
173 | E2 when 12, | |
344 | E2 when 13, |
|
174 | E2 when 13, | |
345 | E2 when 14, |
|
175 | E2 when 14, | |
346 | E2 when 15, |
|
176 | E2 when 15, | |
347 | X"FFFF" when others; |
|
177 | X"FFFF" when others; | |
348 |
|
178 | |||
349 | with i select |
|
179 | ||
|
180 | with j select | |||
350 | Conjugate <= '1' when 1, |
|
181 | Conjugate <= '1' when 1, | |
351 | '1' when 3, |
|
182 | '1' when 3, | |
352 | '1' when 6, |
|
183 | '1' when 6, | |
353 | '1' when 10, |
|
184 | '1' when 10, | |
354 | '1' when 15, |
|
185 | '1' when 15, | |
355 |
'0' when others; |
|
186 | '0' when others; | |
356 |
|
187 | |||
357 |
|
188 | |||
358 | --RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1; |
|
|||
359 | end ar_SelectInputs; No newline at end of file |
|
189 | end ar_SelectInputs; |
@@ -1,74 +1,86 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 | use lpp.lpp_matrix.all; |
|
25 | use lpp.lpp_matrix.all; | |
26 |
|
26 | |||
27 | entity SpectralMatrix is |
|
27 | entity SpectralMatrix is | |
28 | generic( |
|
28 | generic( | |
29 | Input_SZ : integer := 16; |
|
29 | Input_SZ : integer := 16; | |
30 | Result_SZ : integer := 32); |
|
30 | Result_SZ : integer := 32); | |
31 | port( |
|
31 | port( | |
32 | clk : in std_logic; |
|
32 | clk : in std_logic; | |
33 | reset : in std_logic; |
|
33 | reset : in std_logic; | |
34 | B1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
34 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |
35 | B2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
35 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |
36 | B3 : in std_logic_vector(Input_SZ-1 downto 0); |
|
36 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |
37 | E1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
37 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |
38 | E2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
38 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |
|
39 | Empty : in std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |||
|
40 | Statu : out std_logic_vector(3 downto 0); | |||
39 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 |
|
41 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |
40 |
|
|
42 | OP11 : out std_logic_vector(Input_SZ-1 downto 0); | |
|
43 | starting : out std_logic; | |||
|
44 | Conj : out std_logic; | |||
|
45 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |||
41 | ); |
|
46 | ); | |
42 | end SpectralMatrix; |
|
47 | end SpectralMatrix; | |
43 |
|
48 | |||
44 |
|
49 | |||
45 | architecture ar_SpectralMatrix of SpectralMatrix is |
|
50 | architecture ar_SpectralMatrix of SpectralMatrix is | |
46 |
|
51 | |||
47 | signal Read : std_logic; |
|
52 | signal Read : std_logic; | |
48 | signal Take : std_logic; |
|
53 | signal Take : std_logic; | |
49 | signal Received : std_logic; |
|
54 | signal Received : std_logic; | |
50 | signal Valid : std_logic; |
|
55 | signal Valid : std_logic; | |
51 | signal Conjugate : std_logic; |
|
56 | signal Conjugate : std_logic; | |
|
57 | signal Start : std_logic; | |||
52 | signal OP1 : std_logic_vector(Input_SZ-1 downto 0); |
|
58 | signal OP1 : std_logic_vector(Input_SZ-1 downto 0); | |
53 | signal OP2 : std_logic_vector(Input_SZ-1 downto 0); |
|
59 | signal OP2 : std_logic_vector(Input_SZ-1 downto 0); | |
54 | signal Resultat : std_logic_vector(Result_SZ-1 downto 0); |
|
60 | signal Resultat : std_logic_vector(Result_SZ-1 downto 0); | |
55 |
|
61 | |||
|
62 | ||||
56 | begin |
|
63 | begin | |
|
64 | OP11 <= OP1; | |||
|
65 | starting <= Start; | |||
|
66 | conj <= Conjugate; | |||
57 |
|
67 | |||
|
68 | ST0 : Starter | |||
|
69 | port map(clk,reset,Empty(4),Empty(3),Conjugate,Start); | |||
58 |
|
70 | |||
59 | IN0 : SelectInputs |
|
71 | IN0 : SelectInputs | |
60 | generic map(Input_SZ) |
|
72 | generic map(Input_SZ) | |
61 |
port map(clk,r |
|
73 | port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2); | |
62 |
|
74 | |||
63 |
|
75 | |||
64 | CALC0 : Matrix |
|
76 | CALC0 : Matrix | |
65 | generic map(Input_SZ) |
|
77 | generic map(Input_SZ) | |
66 |
port map(clk,r |
|
78 | port map(clk,Start,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat); | |
67 |
|
79 | |||
68 |
|
80 | |||
69 | RES0 : GetResult |
|
81 | RES0 : GetResult | |
70 | generic map(Result_SZ) |
|
82 | generic map(Result_SZ) | |
71 |
port map(clk,r |
|
83 | port map(clk,Start,Valid,Conjugate,Resultat,Received,Result); | |
72 |
|
84 | |||
73 |
|
85 | |||
74 | end ar_SpectralMatrix; No newline at end of file |
|
86 | end ar_SpectralMatrix; |
@@ -1,189 +1,207 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on |
|
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | |
31 |
|
31 | |||
32 | package lpp_matrix is |
|
32 | package lpp_matrix is | |
33 |
|
33 | |||
34 | component APB_Matrix is |
|
34 | component APB_Matrix is | |
35 | generic ( |
|
35 | generic ( | |
36 | pindex : integer := 0; |
|
36 | pindex : integer := 0; | |
37 | paddr : integer := 0; |
|
37 | paddr : integer := 0; | |
38 | pmask : integer := 16#fff#; |
|
38 | pmask : integer := 16#fff#; | |
39 | pirq : integer := 0; |
|
39 | pirq : integer := 0; | |
40 | abits : integer := 8); |
|
40 | abits : integer := 8); | |
41 | port ( |
|
41 | port ( | |
42 | clk : in std_logic; --! Horloge du composant |
|
42 | clk : in std_logic; --! Horloge du composant | |
43 | rst : in std_logic; --! Reset general du composant |
|
43 | rst : in std_logic; --! Reset general du composant | |
44 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
44 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
45 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
45 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
46 | ); |
|
46 | ); | |
47 | end component; |
|
47 | end component; | |
48 |
|
48 | |||
49 |
|
49 | |||
50 | component SpectralMatrix is |
|
50 | component SpectralMatrix is | |
51 | generic( |
|
51 | generic( | |
52 | Input_SZ : integer := 16; |
|
52 | Input_SZ : integer := 16; | |
53 | Result_SZ : integer := 32); |
|
53 | Result_SZ : integer := 32); | |
54 | port( |
|
54 | port( | |
55 | clk : in std_logic; |
|
55 | clk : in std_logic; | |
56 | reset : in std_logic; |
|
56 | reset : in std_logic; | |
57 | B1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
57 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |
58 | B2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
58 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |
59 | B3 : in std_logic_vector(Input_SZ-1 downto 0); |
|
59 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |
60 | E1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
60 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |
61 | E2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
61 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |
|
62 | Empty : in std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |||
|
63 | Statu : out std_logic_vector(3 downto 0); | |||
62 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 |
|
64 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |
|
65 | OP11 : out std_logic_vector(Input_SZ-1 downto 0); | |||
|
66 | starting : out std_logic; | |||
|
67 | Conj : out std_logic; | |||
63 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
68 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
64 | ); |
|
69 | ); | |
65 | end component; |
|
70 | end component; | |
66 |
|
71 | |||
67 |
|
72 | |||
68 | component Matrix is |
|
73 | component Matrix is | |
69 | generic( |
|
74 | generic( | |
70 | Input_SZ : integer := 16); |
|
75 | Input_SZ : integer := 16); | |
71 | port( |
|
76 | port( | |
72 | clk : in std_logic; |
|
77 | clk : in std_logic; | |
73 | raz : in std_logic; |
|
78 | raz : in std_logic; | |
74 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
79 | IN1 : in std_logic_vector(Input_SZ-1 downto 0); | |
75 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
80 | IN2 : in std_logic_vector(Input_SZ-1 downto 0); | |
76 | Take : in std_logic; |
|
81 | Take : in std_logic; | |
77 | Received : in std_logic; |
|
82 | Received : in std_logic; | |
78 | Conjugate : in std_logic; |
|
83 | Conjugate : in std_logic; | |
79 | Valid : out std_logic; |
|
84 | Valid : out std_logic; | |
80 | Read : out std_logic; |
|
85 | Read : out std_logic; | |
81 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) |
|
86 | Result : out std_logic_vector(2*Input_SZ-1 downto 0) | |
82 | ); |
|
87 | ); | |
83 | end component; |
|
88 | end component; | |
84 |
|
89 | |||
85 |
|
90 | |||
86 | component ALU_Driver is |
|
91 | component ALU_Driver is | |
87 | generic( |
|
92 | generic( | |
88 | Input_SZ_1 : integer := 16; |
|
93 | Input_SZ_1 : integer := 16; | |
89 | Input_SZ_2 : integer := 16); |
|
94 | Input_SZ_2 : integer := 16); | |
90 | port( |
|
95 | port( | |
91 | clk : in std_logic; |
|
96 | clk : in std_logic; | |
92 | reset : in std_logic; |
|
97 | reset : in std_logic; | |
93 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
98 | IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
94 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
99 | IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
95 | Take : in std_logic; |
|
100 | Take : in std_logic; | |
96 | Received : in std_logic; |
|
101 | Received : in std_logic; | |
97 | Conjugate : in std_logic; |
|
102 | Conjugate : in std_logic; | |
98 | Valid : out std_logic; |
|
103 | Valid : out std_logic; | |
99 | Read : out std_logic; |
|
104 | Read : out std_logic; | |
100 | CTRL : out std_logic_vector(4 downto 0); |
|
105 | CTRL : out std_logic_vector(4 downto 0); | |
101 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); |
|
106 | OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); | |
102 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) |
|
107 | OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) | |
103 | ); |
|
108 | ); | |
104 | end component; |
|
109 | end component; | |
105 |
|
110 | |||
106 |
|
111 | |||
107 | component ALU_v2 is |
|
112 | component ALU_v2 is | |
108 | generic( |
|
113 | generic( | |
109 | Arith_en : integer := 1; |
|
114 | Arith_en : integer := 1; | |
110 | Logic_en : integer := 1; |
|
115 | Logic_en : integer := 1; | |
111 | Input_SZ_1 : integer := 16; |
|
116 | Input_SZ_1 : integer := 16; | |
112 | Input_SZ_2 : integer := 9); |
|
117 | Input_SZ_2 : integer := 9); | |
113 | port( |
|
118 | port( | |
114 | clk : in std_logic; |
|
119 | clk : in std_logic; | |
115 | reset : in std_logic; |
|
120 | reset : in std_logic; | |
116 | ctrl : in std_logic_vector(4 downto 0); |
|
121 | ctrl : in std_logic_vector(4 downto 0); | |
117 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); |
|
122 | OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); | |
118 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); |
|
123 | OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); | |
119 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) |
|
124 | RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) | |
120 | ); |
|
125 | ); | |
121 | end component; |
|
126 | end component; | |
122 |
|
127 | |||
123 |
|
128 | |||
124 | component MAC_v2 is |
|
129 | component MAC_v2 is | |
125 | generic( |
|
130 | generic( | |
126 | Input_SZ_A : integer := 8; |
|
131 | Input_SZ_A : integer := 8; | |
127 | Input_SZ_B : integer := 8); |
|
132 | Input_SZ_B : integer := 8); | |
128 | port( |
|
133 | port( | |
129 | clk : in std_logic; |
|
134 | clk : in std_logic; | |
130 | reset : in std_logic; |
|
135 | reset : in std_logic; | |
131 | clr_MAC : in std_logic; |
|
136 | clr_MAC : in std_logic; | |
132 | MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); |
|
137 | MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); | |
133 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); |
|
138 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
134 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); |
|
139 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
135 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) |
|
140 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
136 | ); |
|
141 | ); | |
137 | end component; |
|
142 | end component; | |
138 |
|
143 | |||
139 |
|
144 | |||
140 | component TwoComplementer is |
|
145 | component TwoComplementer is | |
141 | generic( |
|
146 | generic( | |
142 | Input_SZ : integer := 16); |
|
147 | Input_SZ : integer := 16); | |
143 | port( |
|
148 | port( | |
144 | clk : in std_logic; |
|
149 | clk : in std_logic; | |
145 | reset : in std_logic; |
|
150 | reset : in std_logic; | |
146 | clr : in std_logic; |
|
151 | clr : in std_logic; | |
147 | TwoComp : in std_logic; |
|
152 | TwoComp : in std_logic; | |
148 | OP : in std_logic_vector(Input_SZ-1 downto 0); |
|
153 | OP : in std_logic_vector(Input_SZ-1 downto 0); | |
149 | RES : out std_logic_vector(Input_SZ-1 downto 0) |
|
154 | RES : out std_logic_vector(Input_SZ-1 downto 0) | |
150 | ); |
|
155 | ); | |
151 | end component; |
|
156 | end component; | |
152 |
|
157 | |||
153 |
|
158 | |||
154 | component GetResult is |
|
159 | component GetResult is | |
155 | generic( |
|
160 | generic( | |
156 | Result_SZ : integer := 32); |
|
161 | Result_SZ : integer := 32); | |
157 | port( |
|
162 | port( | |
158 | clk : in std_logic; |
|
163 | clk : in std_logic; | |
159 | raz : in std_logic; |
|
164 | raz : in std_logic; | |
160 | Valid : in std_logic; |
|
165 | Valid : in std_logic; | |
161 | Conjugate : in std_logic; |
|
166 | Conjugate : in std_logic; | |
162 | Res : in std_logic_vector(Result_SZ-1 downto 0); |
|
167 | Res : in std_logic_vector(Result_SZ-1 downto 0); | |
163 | Received : out std_logic; |
|
168 | Received : out std_logic; | |
164 | Result : out std_logic_vector(Result_SZ-1 downto 0) |
|
169 | Result : out std_logic_vector(Result_SZ-1 downto 0) | |
165 | ); |
|
170 | ); | |
166 | end component; |
|
171 | end component; | |
167 |
|
172 | |||
168 |
|
173 | |||
169 | component SelectInputs is |
|
174 | component SelectInputs is | |
170 | generic( |
|
175 | generic( | |
171 | Input_SZ : integer := 16); |
|
176 | Input_SZ : integer := 16); | |
172 | port( |
|
177 | port( | |
173 | clk : in std_logic; |
|
178 | clk : in std_logic; | |
174 | raz : in std_logic; |
|
179 | raz : in std_logic; | |
175 | Read : in std_logic; |
|
180 | Read : in std_logic; | |
176 | B1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
181 | B1 : in std_logic_vector(Input_SZ-1 downto 0); | |
177 | B2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
182 | B2 : in std_logic_vector(Input_SZ-1 downto 0); | |
178 | B3 : in std_logic_vector(Input_SZ-1 downto 0); |
|
183 | B3 : in std_logic_vector(Input_SZ-1 downto 0); | |
179 | E1 : in std_logic_vector(Input_SZ-1 downto 0); |
|
184 | E1 : in std_logic_vector(Input_SZ-1 downto 0); | |
180 | E2 : in std_logic_vector(Input_SZ-1 downto 0); |
|
185 | E2 : in std_logic_vector(Input_SZ-1 downto 0); | |
181 | Conjugate : out std_logic; |
|
186 | Conjugate : out std_logic; | |
182 | Take : out std_logic; |
|
187 | Take : out std_logic; | |
183 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 |
|
188 | ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 | |
|
189 | Statu : out std_logic_vector(3 downto 0); | |||
184 | OP1 : out std_logic_vector(Input_SZ-1 downto 0); |
|
190 | OP1 : out std_logic_vector(Input_SZ-1 downto 0); | |
185 | OP2 : out std_logic_vector(Input_SZ-1 downto 0) |
|
191 | OP2 : out std_logic_vector(Input_SZ-1 downto 0) | |
186 | ); |
|
192 | ); | |
187 | end component; |
|
193 | end component; | |
188 |
|
194 | |||
|
195 | ||||
|
196 | component Starter is | |||
|
197 | port( | |||
|
198 | clk : in std_logic; | |||
|
199 | raz : in std_logic; | |||
|
200 | empty1 : in std_logic; | |||
|
201 | empty2 : in std_logic; | |||
|
202 | Conjugate : in std_logic; | |||
|
203 | Start : out std_logic | |||
|
204 | ); | |||
|
205 | end component; | |||
|
206 | ||||
189 | end; No newline at end of file |
|
207 | end; |
@@ -1,83 +1,85 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
27 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 | use lpp.lpp_memory.all; |
|
31 | use lpp.lpp_memory.all; | |
32 |
|
32 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba |
|
33 | --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba | |
34 |
|
34 | |||
35 | entity APB_FifoWrite is |
|
35 | entity APB_FifoWrite is | |
36 | generic ( |
|
36 | generic ( | |
37 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
38 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
39 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
40 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
41 | abits : integer := 8; |
|
41 | abits : integer := 8; | |
42 | Data_sz : integer := 16; |
|
42 | Data_sz : integer := 16; | |
43 | Addr_sz : integer := 8; |
|
43 | Addr_sz : integer := 8; | |
44 | addr_max_int : integer := 256); |
|
44 | addr_max_int : integer := 256); | |
45 | port ( |
|
45 | port ( | |
46 | clk : in std_logic; --! Horloge du composant |
|
46 | clk : in std_logic; --! Horloge du composant | |
47 | rst : in std_logic; --! Reset general du composant |
|
47 | rst : in std_logic; --! Reset general du composant | |
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
|
48 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
49 | ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP |
|
49 | ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP | |
|
50 | Empty : out std_logic; --! Flag, Memoire vide | |||
50 | DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire |
|
51 | DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire | |
51 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus |
|
52 | apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus | |
52 | ); |
|
53 | ); | |
53 | end APB_FifoWrite; |
|
54 | end APB_FifoWrite; | |
54 |
|
55 | |||
55 | --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA |
|
56 | --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA | |
56 |
|
57 | |||
57 | architecture ar_APB_FifoWrite of APB_FifoWrite is |
|
58 | architecture ar_APB_FifoWrite of APB_FifoWrite is | |
58 |
|
59 | |||
59 | signal Low : std_logic:='0'; |
|
60 | signal Low : std_logic:='0'; | |
60 | signal WriteEnable : std_logic; |
|
61 | signal WriteEnable : std_logic; | |
61 | signal FlagEmpty : std_logic; |
|
62 | signal FlagEmpty : std_logic; | |
62 | signal FlagFull : std_logic; |
|
63 | signal FlagFull : std_logic; | |
63 | signal ReUse : std_logic; |
|
64 | signal ReUse : std_logic; | |
64 | signal Lock : std_logic; |
|
65 | signal Lock : std_logic; | |
65 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); |
|
66 | signal DataIn : std_logic_vector(Data_sz-1 downto 0); | |
66 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); |
|
67 | signal DataOut : std_logic_vector(Data_sz-1 downto 0); | |
67 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); |
|
68 | signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); | |
68 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); |
|
69 | signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); | |
69 |
|
70 | |||
70 | begin |
|
71 | begin | |
71 |
|
72 | |||
72 | APB : ApbDriver |
|
73 | APB : ApbDriver | |
73 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) |
|
74 | generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) | |
74 | port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); |
|
75 | port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); | |
75 |
|
76 | |||
76 |
|
77 | |||
77 | FIFO : Top_FIFO |
|
78 | FIFO : Top_FIFO | |
78 | generic map(Data_sz,Addr_sz,addr_max_int) |
|
79 | generic map(Data_sz,Addr_sz,addr_max_int) | |
79 | port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); |
|
80 | port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); | |
80 |
|
81 | |||
81 | DATA <= DataOut; |
|
82 | DATA <= DataOut; | |
|
83 | Empty <= FlagEmpty; | |||
82 |
|
84 | |||
83 | end ar_APB_FifoWrite; No newline at end of file |
|
85 | end ar_APB_FifoWrite; |
@@ -1,94 +1,93 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 |
|
25 | |||
26 | --! Programme de la FIFO de lecture |
|
26 | --! Programme de la FIFO de lecture | |
27 |
|
27 | |||
28 | entity Fifo_Read is |
|
28 | entity Fifo_Read is | |
29 | generic( |
|
29 | generic( | |
30 | Addr_sz : integer := 8; |
|
30 | Addr_sz : integer := 8; | |
31 | addr_max_int : integer := 256); |
|
31 | addr_max_int : integer := 256); | |
32 | port( |
|
32 | port( | |
33 | clk,raz : in std_logic; --! Horloge et reset general du composant |
|
33 | clk,raz : in std_logic; --! Horloge et reset general du composant | |
34 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire |
|
34 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire | |
35 | ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but |
|
35 | ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but | |
36 | Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire |
|
36 | Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire | |
37 | empty : out std_logic; --! Flag, M�moire vide |
|
37 | empty : out std_logic; --! Flag, M�moire vide | |
38 | Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire |
|
38 | Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la m�moire | |
39 | ); |
|
39 | ); | |
40 | end Fifo_Read; |
|
40 | end Fifo_Read; | |
41 |
|
41 | |||
42 | --! @details En aval de la SRAM Gaisler |
|
42 | --! @details En aval de la SRAM Gaisler | |
43 |
|
43 | |||
44 | architecture ar_Fifo_Read of Fifo_Read is |
|
44 | architecture ar_Fifo_Read of Fifo_Read is | |
45 |
|
45 | |||
46 | signal Rad_int : integer range 0 to addr_max_int; |
|
46 | signal Rad_int : integer range 0 to addr_max_int; | |
47 | signal Rad_int_reg : integer range 0 to addr_max_int; |
|
47 | signal Rad_int_reg : integer range 0 to addr_max_int; | |
48 | signal Wad_int : integer range 0 to addr_max_int; |
|
48 | signal Wad_int : integer range 0 to addr_max_int; | |
49 | signal Wad_int_reg : integer range 0 to addr_max_int; |
|
49 | signal Wad_int_reg : integer range 0 to addr_max_int; | |
50 | signal flag_reg : std_logic; |
|
50 | signal flag_reg : std_logic; | |
51 |
|
51 | |||
52 | begin |
|
52 | begin | |
53 | process (clk,raz) |
|
53 | process (clk,raz) | |
54 | begin |
|
54 | begin | |
55 | if(raz='0')then |
|
55 | if(raz='0')then | |
56 | Rad_int <= 0; |
|
56 | Rad_int <= 0; | |
57 | empty <= '1'; |
|
57 | empty <= '1'; | |
58 |
|
58 | |||
59 | elsif(clk' event and clk='1')then |
|
59 | elsif(clk' event and clk='1')then | |
60 | Wad_int_reg <= Wad_int; |
|
60 | Wad_int_reg <= Wad_int; | |
61 | Rad_int_reg <= Rad_int; |
|
61 | Rad_int_reg <= Rad_int; | |
62 | flag_reg <= flag_RE; |
|
62 | flag_reg <= flag_RE; | |
63 |
|
63 | |||
64 |
|
64 | |||
65 | if(flag_reg ='0' and flag_RE='1')then |
|
65 | if(flag_reg ='0' and flag_RE='1')then | |
66 | if(Rad_int=addr_max_int-1)then |
|
66 | if(Rad_int=addr_max_int-1)then | |
67 | Rad_int <= 0; |
|
67 | Rad_int <= 0; | |
68 |
|
|
68 | else | |
69 | Rad_int <= Rad_int+1; |
|
69 | Rad_int <= Rad_int+1; | |
70 | end if; |
|
70 | end if; | |
71 | end if; |
|
71 | end if; | |
72 |
|
72 | |||
73 | if(ReUse='1')then |
|
73 | if(ReUse='1')then | |
74 | Rad_int <= 0; |
|
|||
75 |
|
|
74 | empty <= '0'; | |
76 | else |
|
75 | else | |
77 | if(Rad_int_reg /= Rad_int)then |
|
76 | if(Rad_int_reg /= Rad_int)then | |
78 | if(Rad_int=Wad_int)then |
|
77 | if(Rad_int=Wad_int)then | |
79 | empty <= '1'; |
|
78 | empty <= '1'; | |
80 | else |
|
79 | else | |
81 | empty <= '0'; |
|
80 | empty <= '0'; | |
82 | end if; |
|
81 | end if; | |
83 | elsif(Wad_int_reg /= Wad_int)then |
|
82 | elsif(Wad_int_reg /= Wad_int)then | |
84 | empty <= '0'; |
|
83 | empty <= '0'; | |
85 | end if; |
|
84 | end if; | |
86 |
|
|
85 | end if; | |
87 |
|
86 | |||
88 | end if; |
|
87 | end if; | |
89 | end process; |
|
88 | end process; | |
90 |
|
89 | |||
91 | Wad_int <= to_integer(unsigned(Waddr)); |
|
90 | Wad_int <= to_integer(unsigned(Waddr)); | |
92 | Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); |
|
91 | Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); | |
93 |
|
92 | |||
94 | end ar_Fifo_Read; No newline at end of file |
|
93 | end ar_Fifo_Read; |
@@ -1,125 +1,135 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | library techmap; |
|
25 | library techmap; | |
26 | use techmap.gencomp.all; |
|
26 | use techmap.gencomp.all; | |
27 | use work.config.all; |
|
27 | use work.config.all; | |
28 | use lpp.lpp_memory.all; |
|
28 | use lpp.lpp_memory.all; | |
29 |
|
29 | |||
30 | --! Programme de la FIFO |
|
30 | --! Programme de la FIFO | |
31 |
|
31 | |||
32 | entity Top_FIFO is |
|
32 | entity Top_FIFO is | |
33 | generic( |
|
33 | generic( | |
34 | Data_sz : integer := 16; |
|
34 | Data_sz : integer := 16; | |
35 | Addr_sz : integer := 8; |
|
35 | Addr_sz : integer := 8; | |
36 | addr_max_int : integer := 256 |
|
36 | addr_max_int : integer := 256 | |
37 | ); |
|
37 | ); | |
38 | port( |
|
38 | port( | |
39 | clk,raz : in std_logic; --! Horloge et reset general du composant |
|
39 | clk,raz : in std_logic; --! Horloge et reset general du composant | |
40 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire |
|
40 | flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire | |
41 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire |
|
41 | flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire | |
42 | ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but |
|
42 | ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but | |
|
43 | Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire | |||
43 | Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant |
|
44 | Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant | |
44 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture |
|
45 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture | |
45 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture |
|
46 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture | |
46 | full : out std_logic; --! Flag, M�moire pleine |
|
47 | full : out std_logic; --! Flag, M�moire pleine | |
47 | empty : out std_logic; --! Flag, M�moire vide |
|
48 | empty : out std_logic; --! Flag, M�moire vide | |
48 | Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant |
|
49 | Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant | |
49 | ); |
|
50 | ); | |
50 | end Top_FIFO; |
|
51 | end Top_FIFO; | |
51 |
|
52 | |||
52 | --! @details Une m�moire SRAM de chez Gaisler est utilis�e, |
|
53 | --! @details Une m�moire SRAM de chez Gaisler est utilis�e, | |
53 | --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire |
|
54 | --! associ�e a deux Drivers, un pour �crire l'autre pour lire cette m�moire | |
54 |
|
55 | |||
55 | architecture ar_Top_FIFO of Top_FIFO is |
|
56 | architecture ar_Top_FIFO of Top_FIFO is | |
56 |
|
57 | |||
57 | component syncram_2p |
|
58 | component syncram_2p | |
58 | generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0); |
|
59 | generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0); | |
59 | port ( |
|
60 | port ( | |
60 | rclk : in std_ulogic; |
|
61 | rclk : in std_ulogic; | |
61 | renable : in std_ulogic; |
|
62 | renable : in std_ulogic; | |
62 | raddress : in std_logic_vector((abits -1) downto 0); |
|
63 | raddress : in std_logic_vector((abits -1) downto 0); | |
63 | dataout : out std_logic_vector((dbits -1) downto 0); |
|
64 | dataout : out std_logic_vector((dbits -1) downto 0); | |
64 | wclk : in std_ulogic; |
|
65 | wclk : in std_ulogic; | |
65 | write : in std_ulogic; |
|
66 | write : in std_ulogic; | |
66 | waddress : in std_logic_vector((abits -1) downto 0); |
|
67 | waddress : in std_logic_vector((abits -1) downto 0); | |
67 | datain : in std_logic_vector((dbits -1) downto 0)); |
|
68 | datain : in std_logic_vector((dbits -1) downto 0)); | |
68 | end component; |
|
69 | end component; | |
69 |
|
70 | |||
70 | signal Raddr : std_logic_vector(addr_sz-1 downto 0); |
|
71 | signal Raddr : std_logic_vector(addr_sz-1 downto 0); | |
71 | signal Waddr : std_logic_vector(addr_sz-1 downto 0); |
|
72 | signal Waddr : std_logic_vector(addr_sz-1 downto 0); | |
72 | signal Data_int : std_logic_vector(Data_sz-1 downto 0); |
|
73 | --signal Data_int : std_logic_vector(Data_sz-1 downto 0); | |
73 | signal s_empty : std_logic; |
|
74 | signal s_empty : std_logic; | |
74 | signal s_full : std_logic; |
|
75 | signal s_full : std_logic; | |
|
76 | signal s_full2 : std_logic; | |||
75 | signal s_flag_RE : std_logic; |
|
77 | signal s_flag_RE : std_logic; | |
76 | signal s_flag_WR : std_logic; |
|
78 | signal s_flag_WR : std_logic; | |
77 |
|
79 | |||
78 | begin |
|
80 | begin | |
79 |
|
81 | |||
80 | WR : Fifo_Write |
|
82 | WR : Fifo_Write | |
81 | generic map(Addr_sz,addr_max_int) |
|
83 | generic map(Addr_sz,addr_max_int) | |
82 | port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr); |
|
84 | port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr); | |
83 |
|
85 | |||
84 |
|
86 | |||
85 | SRAM : syncram_2p |
|
87 | SRAM : syncram_2p | |
86 | generic map(CFG_MEMTECH,Addr_sz,Data_sz) |
|
88 | generic map(CFG_MEMTECH,Addr_sz,Data_sz) | |
87 |
port map(clk,s_flag_RE,Raddr,Data_ |
|
89 | port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in); | |
88 |
|
90 | |||
89 |
|
91 | |||
90 | link : Link_Reg |
|
92 | -- link : Link_Reg | |
91 | generic map(Data_sz) |
|
93 | -- generic map(Data_sz) | |
92 | port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out); |
|
94 | -- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out); | |
|
95 | ||||
93 |
|
96 | |||
94 | RE : Fifo_Read |
|
97 | RE : Fifo_Read | |
95 | generic map(Addr_sz,addr_max_int) |
|
98 | generic map(Addr_sz,addr_max_int) | |
96 | port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr); |
|
99 | port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr); | |
97 |
|
100 | |||
98 | process(clk,raz) |
|
101 | process(clk,raz) | |
99 | begin |
|
102 | begin | |
100 | if(raz='0')then |
|
103 | if(raz='0')then | |
101 | s_flag_RE <= '0'; |
|
104 | s_flag_RE <= '0'; | |
102 | s_flag_WR <= '0'; |
|
105 | s_flag_WR <= '0'; | |
|
106 | s_full2 <= s_full; | |||
103 |
|
107 | |||
104 | elsif(clk'event and clk='1')then |
|
108 | elsif(clk'event and clk='1')then | |
105 | if(s_full='0')then |
|
109 | if(s_full2='0')then | |
106 | s_flag_WR <= Flag_WR; |
|
110 | s_flag_WR <= Flag_WR; | |
107 |
|
|
111 | else | |
108 | s_flag_WR <= '0'; |
|
112 | s_flag_WR <= '0'; | |
109 | end if; |
|
113 | end if; | |
110 |
|
114 | |||
111 | if(s_empty='0')then |
|
115 | if(s_empty='0')then | |
112 | s_flag_RE <= Flag_RE; |
|
116 | s_flag_RE <= Flag_RE; | |
113 | else |
|
117 | else | |
114 | s_flag_RE <= '0'; |
|
118 | s_flag_RE <= '0'; | |
115 | end if; |
|
119 | end if; | |
116 |
|
|
120 | ||
|
121 | if(Lock='1')then | |||
|
122 | s_full2 <= '1'; | |||
|
123 | else | |||
|
124 | s_full2 <= s_full; | |||
|
125 | end if; | |||
|
126 | ||||
117 | end if; |
|
127 | end if; | |
118 | end process; |
|
128 | end process; | |
119 |
|
129 | |||
120 | full <= s_full; |
|
130 | full <= s_full2; | |
121 | empty <= s_empty; |
|
131 | empty <= s_empty; | |
122 | Addr_RE <= Raddr; |
|
132 | Addr_RE <= Raddr; | |
123 | Addr_WR <= Waddr; |
|
133 | Addr_WR <= Waddr; | |
124 |
|
134 | |||
125 | end ar_Top_FIFO; No newline at end of file |
|
135 | end ar_Top_FIFO; |
@@ -1,242 +1,243 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on |
|
30 | --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on | |
31 |
|
31 | |||
32 | package lpp_memory is |
|
32 | package lpp_memory is | |
33 |
|
33 | |||
34 | --===========================================================| |
|
34 | --===========================================================| | |
35 | --=================== FIFO Compl�te =========================| |
|
35 | --=================== FIFO Compl�te =========================| | |
36 | --===========================================================| |
|
36 | --===========================================================| | |
37 |
|
37 | |||
38 | component APB_FIFO is |
|
38 | component APB_FIFO is | |
39 | generic ( |
|
39 | generic ( | |
40 | pindex : integer := 0; |
|
40 | pindex : integer := 0; | |
41 | paddr : integer := 0; |
|
41 | paddr : integer := 0; | |
42 | pmask : integer := 16#fff#; |
|
42 | pmask : integer := 16#fff#; | |
43 | pirq : integer := 0; |
|
43 | pirq : integer := 0; | |
44 | abits : integer := 8; |
|
44 | abits : integer := 8; | |
45 | Data_sz : integer := 16; |
|
45 | Data_sz : integer := 16; | |
46 | Addr_sz : integer := 8; |
|
46 | Addr_sz : integer := 8; | |
47 | addr_max_int : integer := 256); |
|
47 | addr_max_int : integer := 256); | |
48 | port ( |
|
48 | port ( | |
49 | clk : in std_logic; |
|
49 | clk : in std_logic; | |
50 | rst : in std_logic; |
|
50 | rst : in std_logic; | |
51 | apbi : in apb_slv_in_type; |
|
51 | apbi : in apb_slv_in_type; | |
52 | apbo : out apb_slv_out_type |
|
52 | apbo : out apb_slv_out_type | |
53 | ); |
|
53 | ); | |
54 | end component; |
|
54 | end component; | |
55 |
|
55 | |||
56 |
|
56 | |||
57 | component ApbDriver is |
|
57 | component ApbDriver is | |
58 | generic ( |
|
58 | generic ( | |
59 | pindex : integer := 0; |
|
59 | pindex : integer := 0; | |
60 | paddr : integer := 0; |
|
60 | paddr : integer := 0; | |
61 | pmask : integer := 16#fff#; |
|
61 | pmask : integer := 16#fff#; | |
62 | pirq : integer := 0; |
|
62 | pirq : integer := 0; | |
63 | abits : integer := 8; |
|
63 | abits : integer := 8; | |
64 | LPP_DEVICE : integer; |
|
64 | LPP_DEVICE : integer; | |
65 | Data_sz : integer := 16; |
|
65 | Data_sz : integer := 16; | |
66 | Addr_sz : integer := 8; |
|
66 | Addr_sz : integer := 8; | |
67 | addr_max_int : integer := 256); |
|
67 | addr_max_int : integer := 256); | |
68 | port ( |
|
68 | port ( | |
69 | clk : in std_logic; |
|
69 | clk : in std_logic; | |
70 | rst : in std_logic; |
|
70 | rst : in std_logic; | |
71 | ReadEnable : in std_logic; |
|
71 | ReadEnable : in std_logic; | |
72 | WriteEnable : in std_logic; |
|
72 | WriteEnable : in std_logic; | |
73 | FlagEmpty : in std_logic; |
|
73 | FlagEmpty : in std_logic; | |
74 | FlagFull : in std_logic; |
|
74 | FlagFull : in std_logic; | |
75 | ReUse : out std_logic; |
|
75 | ReUse : out std_logic; | |
76 | Lock : out std_logic; |
|
76 | Lock : out std_logic; | |
77 | DataIn : out std_logic_vector(Data_sz-1 downto 0); |
|
77 | DataIn : out std_logic_vector(Data_sz-1 downto 0); | |
78 | DataOut : in std_logic_vector(Data_sz-1 downto 0); |
|
78 | DataOut : in std_logic_vector(Data_sz-1 downto 0); | |
79 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); |
|
79 | AddrIn : in std_logic_vector(Addr_sz-1 downto 0); | |
80 | AddrOut : in std_logic_vector(Addr_sz-1 downto 0); |
|
80 | AddrOut : in std_logic_vector(Addr_sz-1 downto 0); | |
81 | apbi : in apb_slv_in_type; |
|
81 | apbi : in apb_slv_in_type; | |
82 | apbo : out apb_slv_out_type |
|
82 | apbo : out apb_slv_out_type | |
83 | ); |
|
83 | ); | |
84 | end component; |
|
84 | end component; | |
85 |
|
85 | |||
86 |
|
86 | |||
87 | component Top_FIFO is |
|
87 | component Top_FIFO is | |
88 | generic( |
|
88 | generic( | |
89 | Data_sz : integer := 16; |
|
89 | Data_sz : integer := 16; | |
90 | Addr_sz : integer := 8; |
|
90 | Addr_sz : integer := 8; | |
91 | addr_max_int : integer := 256 |
|
91 | addr_max_int : integer := 256 | |
92 | ); |
|
92 | ); | |
93 | port( |
|
93 | port( | |
94 | clk,raz : in std_logic; |
|
94 | clk,raz : in std_logic; | |
95 | flag_RE : in std_logic; |
|
95 | flag_RE : in std_logic; | |
96 | flag_WR : in std_logic; |
|
96 | flag_WR : in std_logic; | |
97 | ReUse : in std_logic; |
|
97 | ReUse : in std_logic; | |
98 | Lock : in std_logic; |
|
98 | Lock : in std_logic; | |
99 | Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
99 | Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
100 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); |
|
100 | Addr_RE : out std_logic_vector(addr_sz-1 downto 0); | |
101 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); |
|
101 | Addr_WR : out std_logic_vector(addr_sz-1 downto 0); | |
102 | full : out std_logic; |
|
102 | full : out std_logic; | |
103 | empty : out std_logic; |
|
103 | empty : out std_logic; | |
104 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
104 | Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
105 | ); |
|
105 | ); | |
106 | end component; |
|
106 | end component; | |
107 |
|
107 | |||
108 |
|
108 | |||
109 | component Fifo_Read is |
|
109 | component Fifo_Read is | |
110 | generic( |
|
110 | generic( | |
111 | Addr_sz : integer := 8; |
|
111 | Addr_sz : integer := 8; | |
112 | addr_max_int : integer := 256); |
|
112 | addr_max_int : integer := 256); | |
113 | port( |
|
113 | port( | |
114 | clk : in std_logic; |
|
114 | clk : in std_logic; | |
115 | raz : in std_logic; |
|
115 | raz : in std_logic; | |
116 | flag_RE : in std_logic; |
|
116 | flag_RE : in std_logic; | |
117 | ReUse : in std_logic; |
|
117 | ReUse : in std_logic; | |
118 | Waddr : in std_logic_vector(addr_sz-1 downto 0); |
|
118 | Waddr : in std_logic_vector(addr_sz-1 downto 0); | |
119 | empty : out std_logic; |
|
119 | empty : out std_logic; | |
120 | Raddr : out std_logic_vector(addr_sz-1 downto 0) |
|
120 | Raddr : out std_logic_vector(addr_sz-1 downto 0) | |
121 | ); |
|
121 | ); | |
122 | end component; |
|
122 | end component; | |
123 |
|
123 | |||
124 |
|
124 | |||
125 | component Fifo_Write is |
|
125 | component Fifo_Write is | |
126 | generic( |
|
126 | generic( | |
127 | Addr_sz : integer := 8; |
|
127 | Addr_sz : integer := 8; | |
128 | addr_max_int : integer := 256); |
|
128 | addr_max_int : integer := 256); | |
129 | port( |
|
129 | port( | |
130 | clk : in std_logic; |
|
130 | clk : in std_logic; | |
131 | raz : in std_logic; |
|
131 | raz : in std_logic; | |
132 | flag_WR : in std_logic; |
|
132 | flag_WR : in std_logic; | |
133 | Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
133 | Raddr : in std_logic_vector(addr_sz-1 downto 0); | |
134 | full : out std_logic; |
|
134 | full : out std_logic; | |
135 | Waddr : out std_logic_vector(addr_sz-1 downto 0) |
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135 | Waddr : out std_logic_vector(addr_sz-1 downto 0) | |
136 | ); |
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136 | ); | |
137 | end component; |
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137 | end component; | |
138 |
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138 | |||
139 |
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139 | |||
140 | component Link_Reg is |
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140 | component Link_Reg is | |
141 | generic(Data_sz : integer := 16); |
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141 | generic(Data_sz : integer := 16); | |
142 | port( |
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142 | port( | |
143 | clk,raz : in std_logic; |
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143 | clk,raz : in std_logic; | |
144 | Data_one : in std_logic_vector(Data_sz-1 downto 0); |
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144 | Data_one : in std_logic_vector(Data_sz-1 downto 0); | |
145 | Data_two : in std_logic_vector(Data_sz-1 downto 0); |
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145 | Data_two : in std_logic_vector(Data_sz-1 downto 0); | |
146 | ReUse : in std_logic; |
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146 | ReUse : in std_logic; | |
147 | flag_RE : in std_logic; |
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147 | flag_RE : in std_logic; | |
148 | flag_WR : in std_logic; |
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148 | flag_WR : in std_logic; | |
149 | empty : in std_logic; |
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149 | empty : in std_logic; | |
150 | Data_out : out std_logic_vector(Data_sz-1 downto 0) |
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150 | Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
151 | ); |
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151 | ); | |
152 | end component; |
|
152 | end component; | |
153 |
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153 | |||
154 | --===========================================================| |
|
154 | --===========================================================| | |
155 | --================= Demi FIFO Ecriture ======================| |
|
155 | --================= Demi FIFO Ecriture ======================| | |
156 | --===========================================================| |
|
156 | --===========================================================| | |
157 |
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157 | |||
158 | component APB_FifoWrite is |
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158 | component APB_FifoWrite is | |
159 | generic ( |
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159 | generic ( | |
160 | pindex : integer := 0; |
|
160 | pindex : integer := 0; | |
161 | paddr : integer := 0; |
|
161 | paddr : integer := 0; | |
162 | pmask : integer := 16#fff#; |
|
162 | pmask : integer := 16#fff#; | |
163 | pirq : integer := 0; |
|
163 | pirq : integer := 0; | |
164 | abits : integer := 8; |
|
164 | abits : integer := 8; | |
165 | Data_sz : integer := 16; |
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165 | Data_sz : integer := 16; | |
166 | Addr_sz : integer := 8; |
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166 | Addr_sz : integer := 8; | |
167 | addr_max_int : integer := 256); |
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167 | addr_max_int : integer := 256); | |
168 | port ( |
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168 | port ( | |
169 | clk : in std_logic; |
|
169 | clk : in std_logic; | |
170 | rst : in std_logic; |
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170 | rst : in std_logic; | |
171 | apbi : in apb_slv_in_type; |
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171 | apbi : in apb_slv_in_type; | |
172 | ReadEnable : in std_logic; |
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172 | ReadEnable : in std_logic; | |
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173 | Empty : out std_logic; | |||
173 | DATA : out std_logic_vector(Data_sz-1 downto 0); |
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174 | DATA : out std_logic_vector(Data_sz-1 downto 0); | |
174 | apbo : out apb_slv_out_type |
|
175 | apbo : out apb_slv_out_type | |
175 | ); |
|
176 | ); | |
176 | end component; |
|
177 | end component; | |
177 |
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178 | |||
178 |
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179 | |||
179 | --component Top_FifoWrite is |
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180 | --component Top_FifoWrite is | |
180 | -- generic( |
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181 | -- generic( | |
181 | -- Data_sz : integer := 16; |
|
182 | -- Data_sz : integer := 16; | |
182 | -- Addr_sz : integer := 8; |
|
183 | -- Addr_sz : integer := 8; | |
183 | -- addr_max_int : integer := 256); |
|
184 | -- addr_max_int : integer := 256); | |
184 | -- port( |
|
185 | -- port( | |
185 | -- clk : in std_logic; |
|
186 | -- clk : in std_logic; | |
186 | -- raz : in std_logic; |
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187 | -- raz : in std_logic; | |
187 | -- flag_RE : in std_logic; |
|
188 | -- flag_RE : in std_logic; | |
188 | -- flag_WR : in std_logic; |
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189 | -- flag_WR : in std_logic; | |
189 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
190 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
190 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); |
|
191 | -- Raddr : in std_logic_vector(addr_sz-1 downto 0); | |
191 | -- full : out std_logic; |
|
192 | -- full : out std_logic; | |
192 | -- empty : out std_logic; |
|
193 | -- empty : out std_logic; | |
193 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); |
|
194 | -- Waddr : out std_logic_vector(addr_sz-1 downto 0); | |
194 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
195 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
195 | -- ); |
|
196 | -- ); | |
196 | --end component; |
|
197 | --end component; | |
197 |
|
198 | |||
198 | --===========================================================| |
|
199 | --===========================================================| | |
199 | --================== Demi FIFO Lecture ======================| |
|
200 | --================== Demi FIFO Lecture ======================| | |
200 | --===========================================================| |
|
201 | --===========================================================| | |
201 |
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202 | |||
202 | component APB_FifoRead is |
|
203 | component APB_FifoRead is | |
203 | generic ( |
|
204 | generic ( | |
204 | pindex : integer := 0; |
|
205 | pindex : integer := 0; | |
205 | paddr : integer := 0; |
|
206 | paddr : integer := 0; | |
206 | pmask : integer := 16#fff#; |
|
207 | pmask : integer := 16#fff#; | |
207 | pirq : integer := 0; |
|
208 | pirq : integer := 0; | |
208 | abits : integer := 8; |
|
209 | abits : integer := 8; | |
209 | Data_sz : integer := 16; |
|
210 | Data_sz : integer := 16; | |
210 | Addr_sz : integer := 8; |
|
211 | Addr_sz : integer := 8; | |
211 | addr_max_int : integer := 256); |
|
212 | addr_max_int : integer := 256); | |
212 | port ( |
|
213 | port ( | |
213 | clk : in std_logic; |
|
214 | clk : in std_logic; | |
214 | rst : in std_logic; |
|
215 | rst : in std_logic; | |
215 | apbi : in apb_slv_in_type; |
|
216 | apbi : in apb_slv_in_type; | |
216 |
WriteEnable : in std_logic; |
|
217 | WriteEnable : in std_logic; | |
217 | DATA : out std_logic_vector(Data_sz-1 downto 0); |
|
218 | DATA : out std_logic_vector(Data_sz-1 downto 0); | |
218 | apbo : out apb_slv_out_type |
|
219 | apbo : out apb_slv_out_type | |
219 | ); |
|
220 | ); | |
220 | end component; |
|
221 | end component; | |
221 |
|
222 | |||
222 |
|
223 | |||
223 | --component Top_FifoRead is |
|
224 | --component Top_FifoRead is | |
224 | -- generic( |
|
225 | -- generic( | |
225 | -- Data_sz : integer := 16; |
|
226 | -- Data_sz : integer := 16; | |
226 | -- Addr_sz : integer := 8; |
|
227 | -- Addr_sz : integer := 8; | |
227 | -- addr_max_int : integer := 256); |
|
228 | -- addr_max_int : integer := 256); | |
228 | -- port( |
|
229 | -- port( | |
229 | -- clk : in std_logic; |
|
230 | -- clk : in std_logic; | |
230 | -- raz : in std_logic; |
|
231 | -- raz : in std_logic; | |
231 | -- flag_RE : in std_logic; |
|
232 | -- flag_RE : in std_logic; | |
232 | -- flag_WR : in std_logic; |
|
233 | -- flag_WR : in std_logic; | |
233 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); |
|
234 | -- Data_in : in std_logic_vector(Data_sz-1 downto 0); | |
234 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); |
|
235 | -- Waddr : in std_logic_vector(addr_sz-1 downto 0); | |
235 | -- full : out std_logic; |
|
236 | -- full : out std_logic; | |
236 | -- empty : out std_logic; |
|
237 | -- empty : out std_logic; | |
237 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); |
|
238 | -- Raddr : out std_logic_vector(addr_sz-1 downto 0); | |
238 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) |
|
239 | -- Data_out : out std_logic_vector(Data_sz-1 downto 0) | |
239 | -- ); |
|
240 | -- ); | |
240 | --end component; |
|
241 | --end component; | |
241 |
|
242 | |||
242 | end; |
|
243 | end; |
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