# HG changeset patch # User martin # Date 2011-06-01 08:47:17 # Node ID 5e578edcbc3c465df0c92a1e595cdb85d3e506b7 # Parent b47c0d90d4d80394eff085676dc5e36cb3767bbc Spectral Matrix Okai, with 5 input fifo diff --git a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd +++ /dev/null @@ -1,212 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.iir_filter.all; -use lpp.general_purpose.all; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; - -entity APB_IIR_CEL is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 3; - Cels_count : integer := 5; - virgPos : integer := 3; - Mem_use : integer := use_RAM - ); - port ( - rst : in std_logic; - clk : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - sample_clk : in std_logic; - sample_clk_out : out std_logic; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0) - ); -end; - - -architecture AR_APB_IIR_CEL of APB_IIR_CEL is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - - - -type FILTERreg is record - regin : in_IIR_CEL_reg; - regout : out_IIR_CEL_reg; -end record; - -signal Rdata : std_logic_vector(31 downto 0); -signal r : FILTERreg; -signal filter_reset : std_logic:='0'; -signal smp_cnt : integer :=0; -signal sample_clk_out_R : std_logic; - - -type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); -type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; - -type CoefsRegT is record - numCoefs : CoefTblT; - denCoefs : CoefTblT; -end record; - -signal CoefsReg : CoefsRegT; - -begin - -filter_reset <= rst and r.regin.config(0); -sample_clk_out <= sample_clk_out_R; - -filter : IIR_CEL_FILTER -generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) -port map( - reset => filter_reset, - clk => clk, - sample_clk => sample_clk, - regs_in => r.regin, - regs_out => r.regout, - sample_in => sample_in, - sample_out => sample_out - ); - -process(rst,sample_clk) -begin -if rst = '0' then - smp_cnt <= 0; - sample_clk_out_R <= '0'; -elsif sample_clk'event and sample_clk = '1' then - if smp_cnt = 1 then - smp_cnt <= 0; - sample_clk_out_R <= not sample_clk_out_R; - else - smp_cnt <= smp_cnt +1; - end if; -end if; -end process; - - -process(rst,clk) -begin - if rst = '0' then - r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5)); - - elsif clk'event and clk = '1' then - - ---APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(7 downto 2) is - when "000000" => - r.regin.config(0) <= apbi.pwdata(0); - when "000001" => - r.regin.virgPos <= apbi.pwdata(4 downto 0); - when others => - for i in 0 to Cels_count-1 loop - if conv_integer(apbi.paddr(7 downto 5)) = i+1 then - case apbi.paddr(4 downto 2) is - when "000" => - CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when "001" => - CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when "010" => - CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when "011" => - CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when "100" => - CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when "101" => - CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0)); - when others => - end case; - end if; - end loop; - end case; - end if; - ---APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(7 downto 2) is - when "000000" => - - when "000001" => - Rdata(4 downto 0) <= r.regin.virgPos; - when others => - for i in 0 to Cels_count-1 loop - if conv_integer(apbi.paddr(7 downto 5)) = i+1 then - case apbi.paddr(4 downto 2) is - when "000" => - Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0)); - when "001" => - Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1)); - when "010" => - Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2)); - when "011" => - Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0)); - when "100" => - Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1)); - when "101" => - Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2)); - when others => - end case; - end if; - end loop; - end case; - end if; - - end if; - apbo.pconfig <= pconfig; -end process; - -apbo.prdata <= Rdata when apbi.penable = '1' ; - --- pragma translate_off - bootmsg : report_version - generic map ("apbuart" & tost(pindex) & - ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) & - ", irq " & tost(pirq)); --- pragma translate_on - - - -end ar_APB_IIR_CEL; - diff --git a/lib/lpp/dsp/iir_filter/FILTER.vhd b/lib/lpp/dsp/iir_filter/FILTER.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/FILTER.vhd +++ /dev/null @@ -1,107 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.FILTERcfg.all; -use lpp.general_purpose.all; ---Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs) ---exemple 26MHz sys clock and 6 chanels @ 110ksmps/s ---Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs - -entity FILTER is -generic(Smpl_SZ : integer := 16; - ChanelsCNT : integer := 3 -); -port( - - reset : in std_logic; - clk : in std_logic; - sample_clk : in std_logic; - Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); - Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) -); -end entity; - - - - - -architecture ar_FILTER of FILTER is - - - - -signal ALU_ctrl : std_logic_vector(3 downto 0); -signal Sample : std_logic_vector(Smpl_SZ-1 downto 0); -signal Coef : std_logic_vector(Coef_SZ-1 downto 0); -signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0); - -begin - ---============================================================== ---=========================A L U================================ ---============================================================== -ALU1 : entity ALU -generic map( - Arith_en => 1, - Logic_en => 0, - Input_SZ_1 => Smpl_SZ, - Input_SZ_2 => Coef_SZ - -) -port map( - clk => clk, - reset => reset, - ctrl => ALU_ctrl, - OP1 => Sample, - OP2 => Coef, - RES => ALU_OUT -); ---============================================================== - ---============================================================== ---===============F I L T E R C O N T R O L E R================ ---============================================================== -filterctrlr1 : FilterCTRLR -port map( - reset => reset, - clk => clk, - sample_clk => sample_clk, - ALU_Ctrl => ALU_ctrl, - sample_in => sample_Tbl, - coef => Coef, - sample => Sample -); ---============================================================== - -chanelCut : for i in 0 to ChanelsCNT-1 generate - sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ); -end generate; - - - - -end ar_FILTER; - diff --git a/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd b/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/FILTER_RAM_CTRLR.vhd +++ /dev/null @@ -1,228 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.FILTERcfg.all; -use lpp.general_purpose.all; - ---TODO am�liorer la flexibilit� de la config de la RAM. - -entity FILTER_RAM_CTRLR is -port( - reset : in std_logic; - clk : in std_logic; - run : in std_logic; - GO_0 : in std_logic; - B_A : in std_logic; - writeForce : in std_logic; - next_blk : in std_logic; - sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); - sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) -); -end FILTER_RAM_CTRLR; - - -architecture ar_FILTER_RAM_CTRLR of FILTER_RAM_CTRLR is - -signal WD : std_logic_vector(35 downto 0); -signal WD_D : std_logic_vector(35 downto 0); -signal RD : std_logic_vector(35 downto 0); -signal WEN, REN : std_logic; -signal WADDR_back : std_logic_vector(7 downto 0); -signal WADDR_back_D: std_logic_vector(7 downto 0); -signal RADDR : std_logic_vector(7 downto 0); -signal WADDR : std_logic_vector(7 downto 0); -signal WADDR_D : std_logic_vector(7 downto 0); -signal run_D : std_logic; -signal run_D_inv : std_logic; -signal run_inv : std_logic; -signal next_blk_D : std_logic; -signal MUX2_inst1_sel : std_logic; - - -begin - -sample_out <= RD(Smpl_SZ-1 downto 0); - -MUX2_inst1_sel <= run_D and not next_blk; -run_D_inv <= not run_D; -run_inv <= not run; -WEN <= run_D_inv and not writeForce; -REN <= run_inv ;--and not next_blk; - - ---============================================================== ---=========================R A M================================ ---============================================================== -memRAM : if Mem_use = use_RAM generate -RAMblk :RAM - port map( - WD => WD_D, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => reset - ) ; -end generate; - -memCEL : if Mem_use = use_CEL generate -RAMblk :RAM_CEL - port map( - WD => WD_D, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => reset - ) ; -end generate; ---============================================================== ---============================================================== - - -ADDRcntr_inst : ADDRcntr -port map( - clk => clk, - reset => reset, - count => run, - clr => GO_0, - Q => RADDR -); - - - -MUX2_inst1 :MUX2 -generic map(Input_SZ => Smpl_SZ) -port map( - sel => MUX2_inst1_sel, - IN1 => sample_in, - IN2 => RD(Smpl_SZ-1 downto 0), - RES => WD(Smpl_SZ-1 downto 0) -); - - -MUX2_inst2 :MUX2 -generic map(Input_SZ => 8) -port map( - sel => next_blk_D, - IN1 => WADDR_D, - IN2 => WADDR_back_D, - RES => WADDR -); - - -next_blkRreg :REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => next_blk, - Q(0) => next_blk_D -); - -WADDR_backreg :REG -generic map(size => 8) -port map( - reset => reset, - clk => B_A, - D => RADDR, - Q => WADDR_back -); - -WADDR_backreg2 :REG -generic map(size => 8) -port map( - reset => reset, - clk => B_A, - D => WADDR_back, - Q => WADDR_back_D -); - -WDRreg :REG -generic map(size => Smpl_SZ) -port map( - reset => reset, - clk => clk, - D => WD(Smpl_SZ-1 downto 0), - Q => WD_D(Smpl_SZ-1 downto 0) -); - -RunRreg :REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => run, - Q(0) => run_D -); - - - -ADDRreg :REG -generic map(size => 8) -port map( - reset => reset, - clk => clk, - D => RADDR, - Q => WADDR_D -); - - - -end ar_FILTER_RAM_CTRLR; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd b/lib/lpp/dsp/iir_filter/FILTERcfg.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/FILTERcfg.vhd +++ /dev/null @@ -1,196 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - - -package FILTERcfg is - - - - ---===========================================================| ---========F I L T E R C O N F I G V A L U E S=============| ---===========================================================| ---____________________________ ---Bus Width and chanels number| ---____________________________| -constant ChanelsCNT : integer := 6; -constant Smpl_SZ : integer := 16; -constant Coef_SZ : integer := 9; -constant Scalefac_SZ: integer := 3; -constant Cels_count : integer := 5; - -constant Mem_use : integer := 1; - - - ---============================================================ --- create each initial values for each coefs ============ ---!!!!!!!!!!It should be interfaced with a software !!!!!!!!!! ---============================================================ ---constant b0 : coefT := coefT(TO_SIGNED(-30,Coef_SZ)); ---constant b1 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); ---constant b2 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); ---constant b3 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); ---constant b4 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); ---constant b5 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); ---constant b6 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); --- ---constant a0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a1 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); ---constant a2 : coefT := coefT(TO_SIGNED(-193,Coef_SZ)); ---constant a3 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); ---constant a4 : coefT := coefT(TO_SIGNED(-62,Coef_SZ)); --- --- ---constant b0_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); ---constant b0_1 : coefT := coefT(TO_SIGNED(-66,Coef_SZ)); ---constant b0_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); --- ---constant b1_0 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); ---constant b1_1 : coefT := coefT(TO_SIGNED(-57,Coef_SZ)); ---constant b1_2 : coefT := coefT(TO_SIGNED(58,Coef_SZ)); --- ---constant b2_0 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); ---constant b2_1 : coefT := coefT(TO_SIGNED(-17,Coef_SZ)); ---constant b2_2 : coefT := coefT(TO_SIGNED(29,Coef_SZ)); --- ---constant b3_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); ---constant b3_1 : coefT := coefT(TO_SIGNED(4,Coef_SZ)); ---constant b3_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); --- ---constant b4_0 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); ---constant b4_1 : coefT := coefT(TO_SIGNED(24,Coef_SZ)); ---constant b4_2 : coefT := coefT(TO_SIGNED(15,Coef_SZ)); --- ---constant b5_0 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); ---constant b5_1 : coefT := coefT(TO_SIGNED(-153,Coef_SZ)); ---constant b5_2 : coefT := coefT(TO_SIGNED(-171,Coef_SZ)); --- ---constant b6_0 : coefT := coefT(TO_SIGNED(-144,Coef_SZ)); ---constant b6_1 : coefT := coefT(TO_SIGNED(-72,Coef_SZ)); ---constant b6_2 : coefT := coefT(TO_SIGNED(-25,Coef_SZ)); --- --- ---constant a0_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a0_1 : coefT := coefT(TO_SIGNED(189,Coef_SZ)); ---constant a0_2 : coefT := coefT(TO_SIGNED(-111,Coef_SZ)); --- ---constant a1_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a1_1 : coefT := coefT(TO_SIGNED(162,Coef_SZ)); ---constant a1_2 : coefT := coefT(TO_SIGNED(-81,Coef_SZ)); --- ---constant a2_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a2_1 : coefT := coefT(TO_SIGNED(136,Coef_SZ)); ---constant a2_2 : coefT := coefT(TO_SIGNED(-55,Coef_SZ)); --- ---constant a3_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a3_1 : coefT := coefT(TO_SIGNED(114,Coef_SZ)); ---constant a3_2 : coefT := coefT(TO_SIGNED(-33,Coef_SZ)); --- ---constant a4_0 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a4_1 : coefT := coefT(TO_SIGNED(100,Coef_SZ)); ---constant a4_2 : coefT := coefT(TO_SIGNED(-20,Coef_SZ)); --- ---constant a5_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); ---constant a5_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a5_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); ---constant a6_0 : coefT := coefT(TO_SIGNED(60,Coef_SZ)); ---constant a6_1 : coefT := coefT(TO_SIGNED(-128,Coef_SZ)); ---constant a6_2 : coefT := coefT(TO_SIGNED(87,Coef_SZ)); --- --- ---constant celb0 : coef_celT := (b0_0,b0_1,b0_2); ---constant celb1 : coef_celT := (b1_0,b1_1,b1_2); ---constant celb2 : coef_celT := (b2_0,b2_1,b2_2); ---constant celb3 : coef_celT := (b3_0,b3_1,b3_2); ---constant celb4 : coef_celT := (b4_0,b4_1,b4_2); ---constant celb5 : coef_celT := (b5_0,b5_1,b5_2); ---constant celb6 : coef_celT := (b6_0,b6_1,b6_2); --- ---constant cela0 : coef_celT := (a0_0,a0_1,a0_2); ---constant cela1 : coef_celT := (a1_0,a1_1,a1_2); ---constant cela2 : coef_celT := (a2_0,a2_1,a2_2); ---constant cela3 : coef_celT := (a3_0,a3_1,a3_2); ---constant cela4 : coef_celT := (a4_0,a4_1,a4_2); ---constant cela5 : coef_celT := (a5_0,a5_1,a5_2); ---constant cela6 : coef_celT := (a6_0,a6_1,a6_2); --- --- --- ---constant NumCoefs_cel : coefs_celT(0 to Cels_count-1) := (celb0,celb1,celb2,celb3,celb4); ---constant DenCoefs_cel : coefs_celT(0 to Cels_count-1) := (cela0,cela1,cela2,cela3,cela4); ---constant virgPos : integer := 7; --- --- --- --- --- --- --- ---signal NumeratorCoefs : coefsT(0 to 6) := (b0,b1,b2,b3,b4,b5,b6); ---signal DenominatorCoefs : coefsT(0 to 4) := (a0,a1,a2,a3,a4); --- --- ---signal sample_Tbl : samplT; - - -end; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd b/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/FilterCTRLR.vhd +++ /dev/null @@ -1,265 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.FILTERcfg.all; -use lpp.general_purpose.all; - ---TODO am�liorer la gestion de la RAM et de la flexibilit� du filtre - -entity FilterCTRLR is -port( - reset : in std_logic; - clk : in std_logic; - sample_clk : in std_logic; - ALU_Ctrl : out std_logic_vector(3 downto 0); - sample_in : in samplT; - coef : out std_logic_vector(Coef_SZ-1 downto 0); - sample : out std_logic_vector(Smpl_SZ-1 downto 0) -); -end FilterCTRLR; - - -architecture ar_FilterCTRLR of FilterCTRLR is - -constant NUMCoefsCnt : integer:= NumeratorCoefs'high; -constant DENCoefsCnt : integer:= DenominatorCoefs'high; - -signal NcoefCnt : integer range 0 to NumeratorCoefs'high:=0; -signal DcoefCnt : integer range 0 to DenominatorCoefs'high:=0; - -signal chanelCnt : integer range 0 to 15:=0; - -signal WD : std_logic_vector(35 downto 0); -signal WD_D : std_logic_vector(35 downto 0); -signal RD : std_logic_vector(35 downto 0); -signal WEN, REN,WEN_D : std_logic; -signal WADDR_back : std_logic_vector(7 downto 0); -signal ADDR : std_logic_vector(7 downto 0); -signal ADDR_D : std_logic_vector(7 downto 0); -signal clk_inv : std_logic; - -type Rotate_BuffT is array(ChanelsCNT-1 downto 0) of std_logic_vector(Smpl_SZ-1 downto 0); -signal in_Rotate_Buff : Rotate_BuffT; -signal out_Rotate_Buff : Rotate_BuffT; - -signal sample_clk_old : std_logic; - -type stateT is (waiting,computeNUM,computeDEN,NextChanel); -signal state : stateT; - -begin -clk_inv <= not clk; - -process(clk,reset) -begin -if reset = '0' then - state <= waiting; - WEN <= '1'; - REN <= '1'; - ADDR <= (others => '0'); - WD <= (others => '0'); - NcoefCnt <= 0; - DcoefCnt <= 0; - chanelCnt <= 0; - ALU_Ctrl <= clr_mac; - sample_clk_old <= '0'; - coef <= (others => '0'); - sample <= (others => '0'); -rst:for i in 0 to ChanelsCNT-1 loop - in_Rotate_Buff(i) <= (others => '0'); - end loop; -elsif clk'event and clk = '1' then - - sample_clk_old <= sample_clk; - ---================================================================= ---===============DATA processing=================================== ---================================================================= - case state is - when waiting=> - - if sample_clk_old = '0' and sample_clk = '1' then - ALU_Ctrl <= MAC_op; - sample <= in_Rotate_Buff(0); - coef <= std_logic_vector(NumeratorCoefs(0)); - else - ALU_Ctrl <= clr_mac; -loadinput: for i in 0 to ChanelsCNT-1 loop - in_Rotate_Buff(i) <= sample_in(i); - end loop; - end if; - - when computeNUM=> - ALU_Ctrl <= MAC_op; - sample <= RD(Smpl_SZ-1 downto 0); - coef <= std_logic_vector(NumeratorCoefs(NcoefCnt)); - - when computeDEN=> - ALU_Ctrl <= MAC_op; - sample <= RD(Smpl_SZ-1 downto 0); - coef <= std_logic_vector(DenominatorCoefs(DcoefCnt)); - - when NextChanel=> -rotate : for i in 0 to ChanelsCNT-2 loop - in_Rotate_Buff(i) <= in_Rotate_Buff(i+1); - end loop; -rotatetoo: if ChanelsCNT > 1 then - sample <= in_Rotate_Buff(1); - coef <= std_logic_vector(NumeratorCoefs(0)); - end if; - end case; - ---================================================================= ---===============RAM read write==================================== ---================================================================= - case state is - when waiting=> - if sample_clk_old = '0' and sample_clk = '1' then - REN <= '0'; - else - REN <= '1'; - end if; - ADDR <= (others => '0'); - WD(Smpl_SZ-1 downto 0) <= in_Rotate_Buff(0); - WEN <= '1'; - - when computeNUM=> - WD <= RD; - REN <= '0'; - WEN <= '0'; - ADDR <= std_logic_vector(unsigned(ADDR)+1); - when computeDEN=> - WD <= RD; - REN <= '0'; - WEN <= '0'; - ADDR <= std_logic_vector(unsigned(ADDR)+1); - when NextChanel=> - REN <= '1'; - WEN <= '1'; - end case; ---================================================================= - - ---================================================================= ---===============FSM Management==================================== ---================================================================= - case state is - when waiting=> - if sample_clk_old = '0' and sample_clk = '1' then - state <= computeNUM; - end if; - DcoefCnt <= 0; - NcoefCnt <= 1; - chanelCnt<= 0; - when computeNUM=> - if NcoefCnt = NumCoefsCnt then - state <= computeDEN; - NcoefCnt <= 1; - else - NcoefCnt <= NcoefCnt+1; - end if; - when computeDEN=> - if DcoefCnt = DENCoefsCnt then - state <= NextChanel; - DcoefCnt <= 0; - else - DcoefCnt <= DcoefCnt+1; - end if; - when NextChanel=> - if chanelCnt = (ChanelsCNT-1) then - state <= waiting; - else - chanelCnt<= chanelCnt+1; - state <= computeNUM; - end if; - end case; ---================================================================= - -end if; -end process; - -ADDRreg : REG -generic map(size => 8) -port map( - reset => reset, - clk => clk, - D => ADDR, - Q => ADDR_D -); - -WDreg :REG -generic map(size => 36) -port map( - reset => reset, - clk => clk, - D => WD, - Q => WD_D -); - -WRreg :REG -generic map(size => 1) -port map( - reset => reset, - clk => clk, - D(0) => WEN, - Q(0) => WEN_D -); ---============================================================== ---=========================R A M================================ ---============================================================== -memRAM : if Mem_use = use_RAM generate -RAMblk :RAM - port map( - WD => WD_D, - RD => RD, - WEN => WEN_D, - REN => REN, - WADDR => ADDR_D, - RADDR => ADDR, - RWCLK => clk_inv, - RESET => reset - ) ; -end generate; - -memCEL : if Mem_use = use_CEL generate -RAMblk :RAM - port map( - WD => WD_D, - RD => RD, - WEN => WEN_D, - REN => REN, - WADDR => ADDR_D, - RADDR => ADDR, - RWCLK => clk_inv, - RESET => reset - ) ; -end generate; - ---============================================================== - - - -end ar_FilterCTRLR; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd +++ /dev/null @@ -1,326 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- - -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.general_purpose.all; - ---TODO amliorer la gestion de la RAM et de la flexibilit du filtre - -entity IIR_CEL_CTRLR is -generic(Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 3; - Cels_count : integer := 5; - Mem_use : integer := use_RAM -); -port( - reset : in std_logic; - clk : in std_logic; - sample_clk : in std_logic; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - virg_pos : in integer; - coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) -); -end IIR_CEL_CTRLR; - - - - -architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is - -subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0); - -signal smpl_clk_old : std_logic := '0'; -signal WD_sel : std_logic := '0'; -signal Read : std_logic := '0'; -signal SVG_ADDR : std_logic := '0'; -signal count : std_logic := '0'; -signal Write : std_logic := '0'; -signal WADDR_sel : std_logic := '0'; -signal GO_0 : std_logic := '0'; - -signal RAM_sample_in : sampleVect; -signal RAM_sample_in_bk: sampleVect; -signal RAM_sample_out : sampleVect; -signal ALU_ctrl : std_logic_vector(3 downto 0); -signal ALU_sample_in : sampleVect; -signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0); -signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0); -signal curentCel : integer range 0 to Cels_count-1 := 0; -signal curentChan : integer range 0 to ChanelsCount-1 := 0; - - -type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect; - -signal sample_in_BUFF : sampleBuffT; -signal sample_out_BUFF : sampleBuffT; - -type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); -type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; - -type CoefsRegT is record - numCoefs : CoefTblT; - denCoefs : CoefTblT; -end record; - -signal CoefsReg : CoefsRegT; - -type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan); - -signal IIR_CEL_STATE : fsmIIR_CEL_T; - -begin - - -coefsConnectL0: for z in 0 to Cels_count-1 generate - coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate - coefsConnectL2: for x in 0 to Coef_SZ-1 generate - CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); - CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); - end generate; - end generate; -end generate; - - -RAM_CTRLR2inst : RAM_CTRLR2 -generic map(Sample_SZ,Mem_use) -port map( - reset => reset, - clk => clk, - WD_sel => WD_sel, - Read => Read, - WADDR_sel => WADDR_sel, - count => count, - SVG_ADDR => SVG_ADDR, - Write => Write, - GO_0 => GO_0, - sample_in => RAM_sample_in, - sample_out => RAM_sample_out -); - - - -ALU_inst :ALU -generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ) -port map( - clk => clk, - reset => reset, - ctrl => ALU_ctrl, - OP1 => ALU_sample_in, - OP2 => ALU_coef_in, - RES => ALU_out -); - - - - - - -WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1'; -Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; -WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0'; -count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0'; -SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0'; ---Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0'; -Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0'; - -GO_0 <= '1' when IIR_CEL_STATE = waiting else '0'; - - - - - - - -process(clk,reset) -variable result : std_logic_vector(Sample_SZ-1 downto 0); - -begin - -if reset = '0' then - - smpl_clk_old <= '0'; - RAM_sample_in <= (others=> '0'); - ALU_ctrl <= IDLE; - ALU_sample_in <= (others=> '0'); - ALU_Coef_in <= (others=> '0'); - RAM_sample_in_bk<= (others=> '0'); - curentCel <= 0; - curentChan <= 0; - IIR_CEL_STATE <= waiting; -resetL0 : for i in 0 to ChanelsCount-1 loop - sample_in_BUFF(i) <= (others => '0'); - sample_out_BUFF(i) <= (others => '0'); - resetL1: for j in 0 to Sample_SZ-1 loop - sample_out(i,j) <= '0'; - end loop; - end loop; - -elsif clk'event and clk = '1' then - - smpl_clk_old <= sample_clk; - - case IIR_CEL_STATE is - - when waiting => - if sample_clk = '1' and smpl_clk_old = '0' then - IIR_CEL_STATE <= pipe1; - RAM_sample_in <= std_logic_vector(sample_in_BUFF(0)); - ALU_sample_in <= std_logic_vector(sample_in_BUFF(0)); - - else - ALU_ctrl <= IDLE; - smplConnectL0: for i in 0 to ChanelsCount-1 loop - smplConnectL1: for j in 0 to Sample_SZ-1 loop - sample_in_BUFF(i)(j) <= sample_in(i,j); - sample_out(i,j) <= sample_out_BUFF(i)(j); - end loop; - end loop; - end if; - curentCel <= 0; - curentChan <= 0; - - when pipe1 => - IIR_CEL_STATE <= computeb1; - ALU_ctrl <= MAC_op; - ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0)); - - when computeb1 => - - ALU_ctrl <= MAC_op; - ALU_sample_in <= RAM_sample_out; - ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1)); - IIR_CEL_STATE <= computeb2; - RAM_sample_in <= RAM_sample_in_bk; - when computeb2 => - ALU_sample_in <= RAM_sample_out; - ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2)); - IIR_CEL_STATE <= computea1; - - - when computea1 => - ALU_sample_in <= RAM_sample_out; - ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1)); - IIR_CEL_STATE <= computea2; - - - when computea2 => - ALU_sample_in <= RAM_sample_out; - ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2)); - IIR_CEL_STATE <= next_cel; - - - when next_cel => - ALU_ctrl <= clr_mac; - IIR_CEL_STATE <= pipe2; - - when pipe2 => - IIR_CEL_STATE <= pipe3; - - - when pipe3 => - - result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos); - - sample_out_BUFF(0) <= result; - RAM_sample_in_bk <= result; - RAM_sample_in <= result; - if curentCel = Cels_count-1 then - IIR_CEL_STATE <= next_chan; - curentCel <= 0; - else - curentCel <= curentCel + 1; - IIR_CEL_STATE <= pipe1; - ALU_sample_in <= result; - end if; - when next_chan => - -rotate : for i in 1 to ChanelsCount-1 loop - sample_in_BUFF(i-1) <= sample_in_BUFF(i); - sample_out_BUFF(i-1) <= sample_out_BUFF(i); - end loop; - sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0); - sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0); - - if curentChan = (ChanelsCount-1) then - IIR_CEL_STATE <= waiting; - ALU_ctrl <= clr_mac; - elsif ChanelsCount>1 then - curentChan <= curentChan + 1; - IIR_CEL_STATE <= pipe1; - ALU_sample_in <= sample_in_BUFF(1); - RAM_sample_in <= sample_in_BUFF(1); - end if; - end case; - -end if; -end process; - - - - - - -end ar_IIR_CEL_CTRLR; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd +++ /dev/null @@ -1,95 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.general_purpose.all; - ---TODO amliorer la gestion de la RAM et de la flexibilit du filtre - -entity IIR_CEL_FILTER is -generic(Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 3; - Cels_count : integer := 5; - Mem_use : integer := use_RAM); -port( - reset : in std_logic; - clk : in std_logic; - sample_clk : in std_logic; - regs_in : in in_IIR_CEL_reg; - regs_out : in out_IIR_CEL_reg; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) - -); -end IIR_CEL_FILTER; - - - - -architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is - -signal virg_pos : integer; -begin - -virg_pos <= to_integer(unsigned(regs_in.virgPos)); - -CTRLR : IIR_CEL_CTRLR -generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) -port map( - reset => reset, - clk => clk, - sample_clk => sample_clk, - sample_in => sample_in, - sample_out => sample_out, - virg_pos => virg_pos, - coefs => coefs -); - - - - - -end ar_IIR_CEL_FILTER; - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/RAM.vhd b/lib/lpp/dsp/iir_filter/RAM.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/RAM.vhd +++ /dev/null @@ -1,64 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity RAM is - port( WD : in std_logic_vector(35 downto 0); RD : out - std_logic_vector(35 downto 0);WEN, REN : in std_logic; - WADDR : in std_logic_vector(7 downto 0); RADDR : in - std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic - ) ; -end RAM; - - -architecture DEF_ARCH of RAM is -type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); -signal RAMarray : RAMarrayT:=(others => X"000000000"); -signal RD_int : std_logic_vector(35 downto 0); - -begin - -RD_int <= RAMarray(to_integer(unsigned(RADDR))); - - -process(RWclk,reset) -begin -if reset = '0' then - RD <= (X"000000000"); -rst:for i in 0 to 255 loop - RAMarray(i) <= (others => '0'); - end loop; - -elsif RWclk'event and RWclk = '1' then - if REN = '0' then - RD <= RD_int; - end if; - - if WEN = '0' then - RAMarray(to_integer(unsigned(WADDR))) <= WD; - end if; - -end if; -end process; -end DEF_ARCH; diff --git a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd b/lib/lpp/dsp/iir_filter/RAM_CEL.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/RAM_CEL.vhd +++ /dev/null @@ -1,93 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.numeric_std.all; - -entity RAM_CEL is - port( WD : in std_logic_vector(35 downto 0); RD : out - std_logic_vector(35 downto 0);WEN, REN : in std_logic; - WADDR : in std_logic_vector(7 downto 0); RADDR : in - std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic - ) ; -end RAM_CEL; - - - -architecture ar_RAM_CEL of RAM_CEL is -type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); -signal RAMarray : RAMarrayT:=(others => X"000000000"); -signal RD_int : std_logic_vector(35 downto 0); - -begin - -RD_int <= RAMarray(to_integer(unsigned(RADDR))); - - -process(RWclk,reset) -begin -if reset = '0' then - RD <= (X"000000000"); -rst:for i in 0 to 255 loop - RAMarray(i) <= (others => '0'); - end loop; - -elsif RWclk'event and RWclk = '1' then - if REN = '0' then - RD <= RD_int; - end if; - - if WEN = '0' then - RAMarray(to_integer(unsigned(WADDR))) <= WD; - end if; - -end if; -end process; -end ar_RAM_CEL; - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +++ /dev/null @@ -1,213 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; -library lpp; -use lpp.iir_filter.all; -use lpp.FILTERcfg.all; -use lpp.general_purpose.all; - ---TODO amliorer la flexibilit de la config de la RAM. - -entity RAM_CTRLR2 is -generic( - Input_SZ_1 : integer := 16; - Mem_use : integer := use_RAM -); -port( - reset : in std_logic; - clk : in std_logic; - WD_sel : in std_logic; - Read : in std_logic; - WADDR_sel : in std_logic; - count : in std_logic; - SVG_ADDR : in std_logic; - Write : in std_logic; - GO_0 : in std_logic; - sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); - sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) -); -end RAM_CTRLR2; - - -architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is - -signal WD : std_logic_vector(35 downto 0); -signal WD_D : std_logic_vector(35 downto 0); -signal RD : std_logic_vector(35 downto 0); -signal WEN, REN : std_logic; -signal WADDR_back : std_logic_vector(7 downto 0); -signal WADDR_back_D: std_logic_vector(7 downto 0); -signal RADDR : std_logic_vector(7 downto 0); -signal WADDR : std_logic_vector(7 downto 0); -signal WADDR_D : std_logic_vector(7 downto 0); - - - -begin - -sample_out <= RD(Input_SZ_1-1 downto 0); - - -WEN <= not Write; -REN <= not read; - - ---============================================================== ---=========================R A M================================ ---============================================================== -memRAM : if Mem_use = use_RAM generate -RAMblk :RAM - port map( - WD => WD_D, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => reset - ) ; -end generate; - -memCEL : if Mem_use = use_CEL generate -RAMblk :RAM_CEL - port map( - WD => WD_D, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => reset - ) ; -end generate; ---============================================================== ---============================================================== - - -ADDRcntr_inst : ADDRcntr -port map( - clk => clk, - reset => reset, - count => count, - clr => GO_0, - Q => RADDR -); - - - -MUX2_inst1 :MUX2 -generic map(Input_SZ => Input_SZ_1) -port map( - sel => WD_sel, - IN1 => sample_in, - IN2 => RD(Input_SZ_1-1 downto 0), - RES => WD(Input_SZ_1-1 downto 0) -); - - -MUX2_inst2 :MUX2 -generic map(Input_SZ => 8) -port map( - sel => WADDR_sel, - IN1 => WADDR_D, - IN2 => WADDR_back_D, - RES => WADDR -); - - - - -WADDR_backreg :REG -generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2) -port map( - reset => reset, - clk => SVG_ADDR, - D => RADDR, - Q => WADDR_back -); - -WADDR_backreg2 :REG -generic map(size => 8) -port map( - reset => reset, - clk => SVG_ADDR, - D => WADDR_back, - Q => WADDR_back_D -); - -WDRreg :REG -generic map(size => Input_SZ_1) -port map( - reset => reset, - clk => clk, - D => WD(Input_SZ_1-1 downto 0), - Q => WD_D(Input_SZ_1-1 downto 0) -); - - - - -ADDRreg :REG -generic map(size => 8) -port map( - reset => reset, - clk => clk, - D => RADDR, - Q => WADDR_D -); - - - -end ar_RAM_CTRLR2; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd b/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/TestbenshMAC.vhd +++ /dev/null @@ -1,116 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - - - -entity TestbenshMAC is -end TestbenshMAC; - - - - -architecture ar_TestbenshMAC of TestbenshMAC is - - - -constant OP1sz : integer := 16; -constant OP2sz : integer := 12; ---IDLE =00 MAC =01 MULT =10 ADD =11 -constant IDLE : std_logic_vector(1 downto 0) := "00"; -constant MAC : std_logic_vector(1 downto 0) := "01"; -constant MULT : std_logic_vector(1 downto 0) := "10"; -constant ADD : std_logic_vector(1 downto 0) := "11"; - -signal clk : std_logic:='0'; -signal reset : std_logic:='0'; -signal clrMAC : std_logic:='0'; -signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE; -signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); -signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); -signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); - - - - -begin - - -MAC1 : entity LPP_IIR_FILTER.MAC -generic map( - Input_SZ_A => OP1sz, - Input_SZ_B => OP2sz - -) -port map( - clk => clk, - reset => reset, - clr_MAC => clrMAC, - MAC_MUL_ADD => MAC_MUL_ADD, - OP1 => Operand1, - OP2 => Operand2, - RES => Resultat -); - -clk <= not clk after 25 ns; - -process -begin -wait for 40 ns; -reset <= '1'; -wait for 11 ns; -Operand1 <= X"0001"; -Operand2 <= X"001"; -MAC_MUL_ADD <= ADD; -wait for 50 ns; -Operand1 <= X"0001"; -Operand2 <= X"100"; -wait for 50 ns; -Operand1 <= X"0001"; -Operand2 <= X"001"; -MAC_MUL_ADD <= MULT; -wait for 50 ns; -Operand1 <= X"0002"; -Operand2 <= X"002"; -wait for 50 ns; -clrMAC <= '1'; -wait for 50 ns; -clrMAC <= '0'; -Operand1 <= X"0001"; -Operand2 <= X"003"; -MAC_MUL_ADD <= MAC; -wait; -end process; -end ar_TestbenshMAC; - - - - - - - - - - - diff --git a/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd b/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/Top_Filtre_IIR.vhd +++ /dev/null @@ -1,18 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/iir_filter.vhd +++ /dev/null @@ -1,225 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; - - - - -package iir_filter is - - ---===========================================================| ---================A L U C O N T R O L======================| ---===========================================================| -constant IDLE : std_logic_vector(3 downto 0) := "0000"; -constant MAC_op : std_logic_vector(3 downto 0) := "0001"; -constant MULT : std_logic_vector(3 downto 0) := "0010"; -constant ADD : std_logic_vector(3 downto 0) := "0011"; -constant clr_mac : std_logic_vector(3 downto 0) := "0100"; - ---____ ---RAM | ---____| -constant use_RAM : integer := 1; -constant use_CEL : integer := 0; - - ---===========================================================| ---=============C O E F S ====================================| ---===========================================================| --- create a specific type of data for coefs to avoid errors | ---===========================================================| - -type scaleValT is array(natural range <>) of integer; - -type samplT is array(natural range <>,natural range <>) of std_logic; - -type in_IIR_CEL_reg is record - config : std_logic_vector(31 downto 0); - virgPos : std_logic_vector(4 downto 0); -end record; - -type out_IIR_CEL_reg is record - config : std_logic_vector(31 downto 0); - status : std_logic_vector(31 downto 0); -end record; - - - -component APB_IIR_CEL is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 3; - Cels_count : integer := 5; - virgPos : integer := 3; - Mem_use : integer := use_RAM - ); - port ( - rst : in std_logic; - clk : in std_logic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - sample_clk : in std_logic; - sample_clk_out : out std_logic; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0) - ); -end component; - - ---component FILTER is ---generic(Smpl_SZ : integer := 16; --- ChanelsCNT : integer := 3 ---); ---port( --- --- reset : in std_logic; --- clk : in std_logic; --- sample_clk : in std_logic; --- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); --- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) ---); ---end component; - - - ---component FilterCTRLR is ---port( --- reset : in std_logic; --- clk : in std_logic; --- sample_clk : in std_logic; --- ALU_Ctrl : out std_logic_vector(3 downto 0); --- sample_in : in samplT; --- coef : out std_logic_vector(Coef_SZ-1 downto 0); --- sample : out std_logic_vector(Smpl_SZ-1 downto 0) ---); ---end component; - - ---component FILTER_RAM_CTRLR is ---port( --- reset : in std_logic; --- clk : in std_logic; --- run : in std_logic; --- GO_0 : in std_logic; --- B_A : in std_logic; --- writeForce : in std_logic; --- next_blk : in std_logic; --- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0); --- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0) ---); ---end component; - - -component IIR_CEL_CTRLR is -generic(Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 3; - Cels_count : integer := 5; - Mem_use : integer := use_RAM -); -port( - reset : in std_logic; - clk : in std_logic; - sample_clk : in std_logic; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - virg_pos : in integer; - coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) -); -end component; - - -component RAM is - port( WD : in std_logic_vector(35 downto 0); RD : out - std_logic_vector(35 downto 0);WEN, REN : in std_logic; - WADDR : in std_logic_vector(7 downto 0); RADDR : in - std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic - ) ; -end component; - - -component RAM_CEL is - port( WD : in std_logic_vector(35 downto 0); RD : out - std_logic_vector(35 downto 0);WEN, REN : in std_logic; - WADDR : in std_logic_vector(7 downto 0); RADDR : in - std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic - ) ; -end component; - -component IIR_CEL_FILTER is -generic(Sample_SZ : integer := 16; - ChanelsCount : integer := 1; - Coef_SZ : integer := 9; - CoefCntPerCel: integer := 3; - Cels_count : integer := 5; - Mem_use : integer := use_RAM); -port( - reset : in std_logic; - clk : in std_logic; - sample_clk : in std_logic; - regs_in : in in_IIR_CEL_reg; - regs_out : in out_IIR_CEL_reg; - sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) - -); -end component; - - -component RAM_CTRLR2 is -generic( - Input_SZ_1 : integer := 16; - Mem_use : integer := use_RAM -); -port( - reset : in std_logic; - clk : in std_logic; - WD_sel : in std_logic; - Read : in std_logic; - WADDR_sel : in std_logic; - count : in std_logic; - SVG_ADDR : in std_logic; - Write : in std_logic; - GO_0 : in std_logic; - sample_in : in std_logic_vector(Input_SZ_1-1 downto 0); - sample_out : out std_logic_vector(Input_SZ_1-1 downto 0) -); -end component; - - -end; diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt deleted file mode 100644 --- a/lib/lpp/dsp/iir_filter/vhdlsyn.txt +++ /dev/null @@ -1,12 +0,0 @@ -APB_IIR_CEL.vhd -FILTER.vhd -FILTER_RAM_CTRLR.vhd -FILTERcfg.vhd -FilterCTRLR.vhd -IIR_CEL_CTRLR.vhd -IIR_CEL_FILTER.vhd -RAM.vhd -RAM_CEL.vhd -RAM_CTRLR2.vhd -Top_Filtre_IIR.vhd -iir_filter.vhd diff --git a/lib/lpp/lpp_matrix/SelectInputs.vhd b/lib/lpp/lpp_matrix/SelectInputs.vhd --- a/lib/lpp/lpp_matrix/SelectInputs.vhd +++ b/lib/lpp/lpp_matrix/SelectInputs.vhd @@ -1,34 +1,34 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr -------------------------------------------------------------------------------- -library IEEE; -use IEEE.numeric_std.all; -use IEEE.std_logic_1164.all; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + entity SelectInputs is -generic( - Input_SZ : integer := 16); -port( - clk : in std_logic; - raz : in std_logic; +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; + raz : in std_logic; Read : in std_logic; B1 : in std_logic_vector(Input_SZ-1 downto 0); B2 : in std_logic_vector(Input_SZ-1 downto 0); @@ -37,21 +37,24 @@ port( E2 : in std_logic_vector(Input_SZ-1 downto 0); Conjugate : out std_logic; Take : out std_logic; - ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 - OP1 : out std_logic_vector(Input_SZ-1 downto 0); - OP2 : out std_logic_vector(Input_SZ-1 downto 0) -); -end SelectInputs; - - -architecture ar_SelectInputs of SelectInputs is + ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + Statu : out std_logic_vector(3 downto 0); + OP1 : out std_logic_vector(Input_SZ-1 downto 0); + OP2 : out std_logic_vector(Input_SZ-1 downto 0) +); +end SelectInputs; + + +architecture ar_SelectInputs of SelectInputs is signal Read_reg : std_logic; -signal i : integer range 1 to 15; +signal i : integer range 0 to 128; +signal j : integer range 0 to 15; +signal Read_int : std_logic_vector(4 downto 0); -type state is (stX,st1a,st1b); +type state is (stX,sta,stb,st1,st2,idl1,idl2); signal ect : state; - + begin process(clk,raz) begin @@ -59,6 +62,7 @@ begin if(raz='0')then Take <= '0'; i <= 0; + j <= 0; Read_reg <= '0'; ect <= stX; @@ -66,202 +70,53 @@ begin Read_reg <= Read; case ect is + when stX => - i <= 1; + i <= 1; if(Read_reg='0' and Read='1')then - ect <= st1a; + if(j=15)then + j <= 1; + else + j<= j+1; + end if; + ect <= idl1; end if; -------------------------------------------------------------------------------- - when st1a => - Take <= '1'; + + when idl1 => + ect <= st1; + + when st1 => + Take <= '1'; + ect <= sta; + + when sta => if(Read_reg='0' and Read='1')then - ect <= st1b; + ect <= idl2; end if; - when st1b => + when idl2 => + ect <= st2; + + when st2 => Take <= '0'; - if(i=15)then + ect <= stb; + + when stb => + if(i=128)then ect <= stX; elsif(Read_reg='0' and Read='1')then i <= i+1; - ect <= st1a; + ect <= idl1; end if; -------------------------------------------------------------------------------- --- when st2a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st2b; --- end if; --- --- when st2b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st3a; --- end if; ---------------------------------------------------------------------------------- --- when st3a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st3b; --- end if; --- --- when st3b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st4a; --- end if; ---------------------------------------------------------------------------------- --- when st4a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st4b; --- end if; --- --- when st4b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st5a; --- end if; ---------------------------------------------------------------------------------- --- --- when st5a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st5b; --- end if; --- --- when st5b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st6a; --- end if; ---------------------------------------------------------------------------------- --- when st6a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st6b; --- end if; --- --- when st6b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st7a; --- end if; ---------------------------------------------------------------------------------- --- when st7a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st7b; --- end if; --- --- when st7b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st8a; --- end if; ---------------------------------------------------------------------------------- --- when st8a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st8b; --- end if; --- --- when st8b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st9a; --- end if; ---------------------------------------------------------------------------------- --- when st9a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st9b; --- end if; --- --- when st9b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st10a; --- end if; ---------------------------------------------------------------------------------- --- when st10a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st10b; --- end if; --- --- when st10b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st11a; --- end if; ---------------------------------------------------------------------------------- --- when st11a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st11b; --- end if; --- --- when st11b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st12a; --- end if; ---------------------------------------------------------------------------------- --- when st12a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st12b; --- end if; --- --- when st12b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st13a; --- end if; ---------------------------------------------------------------------------------- --- when st13a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st13b; --- end if; --- --- when st13b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st14a; --- end if; ---------------------------------------------------------------------------------- --- when st14a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st14b; --- end if; --- --- when st14b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= st15a; --- end if; ---------------------------------------------------------------------------------- --- when st15a => --- Take <= '1'; --- if(Read_reg='0' and Read='1')then --- ect <= st7_b; --- end if; --- --- when st15b => --- Take <= '0'; --- if(Read_reg='0' and Read='1')then --- ect <= stX; --- end if; -------------------------------------------------------------------------------- + end case; end if; end process; -with i select - ReadFIFO <= "10000" when 1, +Statu <= std_logic_vector(to_unsigned(j,4)); + +with j select + Read_int <= "10000" when 1, "11000" when 2, "01000" when 3, "10100" when 4, @@ -276,41 +131,15 @@ with i select "00101" when 13, "00011" when 14, "00001" when 15, - "00000" when others; + "00000" when others; ---with ect select --- ReadB2 <= Read when st1, --- Read when st2, --- Read when st4, --- Read when st7, --- Read when st11, --- '0' when others; --- ---with ect select --- ReadB3 <= Read when st3, --- Read when st4, --- Read when st5, --- Read when st8, --- Read when st12, --- '0' when others; --- ---with ect select --- ReadE1 <= Read when st6, --- Read when st7, --- Read when st8, --- Read when st9, --- Read when st13, --- '0' when others; --- ---with ect select --- ReadE2 <= Read when st10, --- Read when st11, --- Read when st12, --- Read when st13, --- Read when st14, --- '0' when others; +with ect select + ReadFIFO <= Read_int when idl1, + Read_int when idl2, + "00000" when others; -with i select + +with j select OP1 <= B1 when 1, B1 when 2, B1 when 4, @@ -328,7 +157,8 @@ with i select E2 when 15, X"FFFF" when others; -with i select + +with j select OP2 <= B1 when 1, B2 when 2, B2 when 3, @@ -346,14 +176,14 @@ with i select E2 when 15, X"FFFF" when others; -with i select + +with j select Conjugate <= '1' when 1, '1' when 3, '1' when 6, '1' when 10, '1' when 15, - '0' when others; + '0' when others; ---RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1; end ar_SelectInputs; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd --- a/lib/lpp/lpp_matrix/SpectralMatrix.vhd +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -36,8 +36,13 @@ port( B3 : in std_logic_vector(Input_SZ-1 downto 0); E1 : in std_logic_vector(Input_SZ-1 downto 0); E2 : in std_logic_vector(Input_SZ-1 downto 0); + Empty : in std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + Statu : out std_logic_vector(3 downto 0); ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 - Result : out std_logic_vector(Result_SZ-1 downto 0) + OP11 : out std_logic_vector(Input_SZ-1 downto 0); + starting : out std_logic; + Conj : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) ); end SpectralMatrix; @@ -49,26 +54,33 @@ signal Take : std_logic; signal Received : std_logic; signal Valid : std_logic; signal Conjugate : std_logic; +signal Start : std_logic; signal OP1 : std_logic_vector(Input_SZ-1 downto 0); signal OP2 : std_logic_vector(Input_SZ-1 downto 0); signal Resultat : std_logic_vector(Result_SZ-1 downto 0); + begin +OP11 <= OP1; +starting <= Start; +conj <= Conjugate; +ST0 : Starter + port map(clk,reset,Empty(4),Empty(3),Conjugate,Start); IN0 : SelectInputs generic map(Input_SZ) - port map(clk,reset,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,OP1,OP2); + port map(clk,Start,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,Statu,OP1,OP2); CALC0 : Matrix generic map(Input_SZ) - port map(clk,reset,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat); + port map(clk,Start,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat); RES0 : GetResult generic map(Result_SZ) - port map(clk,reset,Valid,Conjugate,Resultat,Received,Result); + port map(clk,Start,Valid,Conjugate,Resultat,Received,Result); end ar_SpectralMatrix; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/Starter.vhd b/lib/lpp/lpp_matrix/Starter.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/Starter.vhd @@ -0,0 +1,85 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity Starter is +port( + clk : in std_logic; + raz : in std_logic; + empty1 : in std_logic; + empty2 : in std_logic; + Conjugate : in std_logic; + Start : out std_logic +); +end Starter; + + +architecture ar_Starter of Starter is + +begin + process(clk,raz) + begin + + if(raz='0')then + Start <= '0'; + + elsif(clk'event and clk='1')then + + if(Conjugate='1')then + if(empty1='1')then + Start <= '0'; + else + Start <= '1'; + end if; + else + if(empty1='1' or empty2='1')then + Start <= '0'; + else + Start <= '1'; + end if; + + end if; + end if; + end process; + +end ar_Starter; + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -59,7 +59,12 @@ port( B3 : in std_logic_vector(Input_SZ-1 downto 0); E1 : in std_logic_vector(Input_SZ-1 downto 0); E2 : in std_logic_vector(Input_SZ-1 downto 0); + Empty : in std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + Statu : out std_logic_vector(3 downto 0); ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + OP11 : out std_logic_vector(Input_SZ-1 downto 0); + starting : out std_logic; + Conj : out std_logic; Result : out std_logic_vector(Result_SZ-1 downto 0) ); end component; @@ -181,9 +186,22 @@ port( Conjugate : out std_logic; Take : out std_logic; ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + Statu : out std_logic_vector(3 downto 0); OP1 : out std_logic_vector(Input_SZ-1 downto 0); OP2 : out std_logic_vector(Input_SZ-1 downto 0) ); end component; + +component Starter is +port( + clk : in std_logic; + raz : in std_logic; + empty1 : in std_logic; + empty2 : in std_logic; + Conjugate : in std_logic; + Start : out std_logic +); +end component; + end; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ b/lib/lpp/lpp_memory/APB_FifoWrite.vhd @@ -47,6 +47,7 @@ entity APB_FifoWrite is rst : in std_logic; --! Reset general du composant apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP + Empty : out std_logic; --! Flag, Memoire vide DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); @@ -79,5 +80,6 @@ begin port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); DATA <= DataOut; +Empty <= FlagEmpty; end ar_APB_FifoWrite; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Fifo_Read.vhd b/lib/lpp/lpp_memory/Fifo_Read.vhd --- a/lib/lpp/lpp_memory/Fifo_Read.vhd +++ b/lib/lpp/lpp_memory/Fifo_Read.vhd @@ -64,14 +64,13 @@ begin if(flag_reg ='0' and flag_RE='1')then if(Rad_int=addr_max_int-1)then - Rad_int <= 0; + Rad_int <= 0; else Rad_int <= Rad_int+1; end if; end if; - if(ReUse='1')then - Rad_int <= 0; + if(ReUse='1')then empty <= '0'; else if(Rad_int_reg /= Rad_int)then @@ -82,7 +81,7 @@ begin end if; elsif(Wad_int_reg /= Wad_int)then empty <= '0'; - end if; + end if; end if; end if; diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ b/lib/lpp/lpp_memory/Top_FIFO.vhd @@ -40,6 +40,7 @@ entity Top_FIFO is flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire ReUse : in std_logic; --! Flag, Permet de relire la m�moire du d�but + Lock : in std_logic; --! Permet de bloquer l'�criture dans la m�moire Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture @@ -69,9 +70,10 @@ end component; signal Raddr : std_logic_vector(addr_sz-1 downto 0); signal Waddr : std_logic_vector(addr_sz-1 downto 0); -signal Data_int : std_logic_vector(Data_sz-1 downto 0); +--signal Data_int : std_logic_vector(Data_sz-1 downto 0); signal s_empty : std_logic; signal s_full : std_logic; +signal s_full2 : std_logic; signal s_flag_RE : std_logic; signal s_flag_WR : std_logic; @@ -84,12 +86,13 @@ begin SRAM : syncram_2p generic map(CFG_MEMTECH,Addr_sz,Data_sz) - port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in); + port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in); - link : Link_Reg - generic map(Data_sz) - port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out); +-- link : Link_Reg +-- generic map(Data_sz) +-- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out); + RE : Fifo_Read generic map(Addr_sz,addr_max_int) @@ -100,10 +103,11 @@ begin if(raz='0')then s_flag_RE <= '0'; s_flag_WR <= '0'; + s_full2 <= s_full; elsif(clk'event and clk='1')then - if(s_full='0')then - s_flag_WR <= Flag_WR; + if(s_full2='0')then + s_flag_WR <= Flag_WR; else s_flag_WR <= '0'; end if; @@ -113,11 +117,17 @@ begin else s_flag_RE <= '0'; end if; - + + if(Lock='1')then + s_full2 <= '1'; + else + s_full2 <= s_full; + end if; + end if; end process; -full <= s_full; +full <= s_full2; empty <= s_empty; Addr_RE <= Raddr; Addr_WR <= Waddr; diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -170,6 +170,7 @@ component APB_FifoWrite is rst : in std_logic; apbi : in apb_slv_in_type; ReadEnable : in std_logic; + Empty : out std_logic; DATA : out std_logic_vector(Data_sz-1 downto 0); apbo : out apb_slv_out_type ); @@ -213,7 +214,7 @@ component APB_FifoRead is clk : in std_logic; rst : in std_logic; apbi : in apb_slv_in_type; - WriteEnable : in std_logic; + WriteEnable : in std_logic; DATA : out std_logic_vector(Data_sz-1 downto 0); apbo : out apb_slv_out_type ); diff --git a/push_action.sh b/push_action.sh --- a/push_action.sh +++ b/push_action.sh @@ -1,1 +1,1 @@ -touch test11 +touch test1