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1 | # Top Level Design Parameters | |||
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2 | ||||
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3 | # Clocks | |||
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4 | ||||
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5 | create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz | |||
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6 | #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz | |||
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7 | #create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25_int:Q | |||
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8 | #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q | |||
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9 | create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} | |||
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10 | ||||
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11 | ||||
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12 | # False Paths Between Clocks | |||
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14 | ||||
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15 | # False Path Constraints | |||
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17 | ||||
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18 | # Maximum Delay Constraints | |||
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19 | ||||
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20 | ||||
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21 | # Multicycle Constraints | |||
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22 | ||||
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23 | ||||
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24 | # Virtual Clocks | |||
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25 | # Output Load Constraints | |||
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26 | # Driving Cell Constraints | |||
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27 | # Wire Loads | |||
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28 | # set_wire_load_mode top | |||
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29 | ||||
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30 | # Other Constraints | |||
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