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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

MS + WFP : synthese ok...
pellion -
r364:5a38901d72d5 JC
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@@ -397,6 +397,7 vcom_lpp:
397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
398 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
398 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
400 @echo "vcom lpp done"
401 @echo "vcom lpp done"
401
402
402 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
403 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
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@@ -13,7 +13,6 add wave -noupdate -group FIFO_f0_A /tb/
13 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
13 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
14 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
14 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
15 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
15 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
16 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/more_16data
17 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
16 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
17 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
19 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
@@ -26,7 +25,6 add wave -noupdate -expand -group FIFO_f
26 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
25 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
27 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
26 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
28 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
27 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
29 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/more_16data
30 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
28 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
31 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
29 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
32 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
30 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
@@ -37,28 +35,15 add wave -noupdate -expand -group FIFO_f
37 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
35 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
38 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
36 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
39 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
37 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
40 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifoload
41 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_im
42 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifid_re
43 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifid_valid
44 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifinreset
45 add wave -noupdate /tb/lpp_lfr_ms_1/corefft_1/ifistart
46 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
38 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
47 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
39 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
48 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
40 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
49 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifiread_y
50 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifopong
51 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_rdy
52 add wave -noupdate -expand -group FFT_RESULT_INTERFACE /tb/lpp_lfr_ms_1/corefft_1/ifoy_valid
53 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_im
54 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/ifoy_re
55 add wave -noupdate -expand -group FFT_RESULT_INTERFACE -radix hexadecimal /tb/lpp_lfr_ms_1/corefft_1/lpp_fifo_1/memcel/cram/ramarray
56 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
41 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
57 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
42 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
58 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
43 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
59 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
44 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
60 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
45 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
61 add wave -noupdate -expand -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
46 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
62 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
47 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
63 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
48 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
64 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
49 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
@@ -98,10 +83,8 add wave -noupdate -expand -group FIF0_0
98 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
83 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
99 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
84 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
100 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
85 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
101 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_new
102 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
86 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
103 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
87 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
104 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_new
105 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
88 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
106 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
89 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
107 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
90 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
@@ -115,12 +98,8 add wave -noupdate -expand -group DMA_OU
115 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
98 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
116 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
99 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
117 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
100 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
118 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_0
119 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f0_1
120 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
101 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
121 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
102 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
122 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_0
123 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f0_1
124 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
103 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
125 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
104 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
126 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
105 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
@@ -130,8 +109,36 add wave -noupdate -radix unsigned /tb/l
130 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
109 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
131 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
110 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
132 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
111 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
112 add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error
113 add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full
114 add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write
115 add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
116 add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
117 add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
118 add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
119 add wave -noupdate -expand -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
120 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
121 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
122 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
123 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
124 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
125 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
126 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
127 add wave -noupdate -expand -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
128 add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(152) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(153) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(154) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(155) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(156) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(157) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(158) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(159) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(160) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(161) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(162) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(163) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(164) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(165) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(166) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(167) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(168) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(169) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(170) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(171) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(172) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(173) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(174) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(175) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(176) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(177) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(178) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(179) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(180) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(181) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(182) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(183) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(184) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(185) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(186) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(187) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(188) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(189) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(190) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(191) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(192) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(193) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(194) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(195) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(196) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(197) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(198) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(199) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(200) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(201) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(202) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(203) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(204) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(205) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(206) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(207) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(208) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(209) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(210) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(211) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(212) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(213) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(214) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(215) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(216) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(217) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(218) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(219) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(220) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(221) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(222) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(223) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(224) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(225) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(226) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(227) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(228) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(229) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(230) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(231) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(232) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(233) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(234) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(235) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(236) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(237) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(238) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(239) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(240) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(241) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(242) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(243) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(244) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(245) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(246) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(247) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(248) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(249) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(250) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(251) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(252) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(253) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(254) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(255) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
129 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
130 add wave -noupdate -expand -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
131 add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
132 add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
133 add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
134 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
135 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
136 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
137 add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
138 add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
139 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
133 TreeUpdate [SetDefaultTree]
140 TreeUpdate [SetDefaultTree]
134 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44837900611 ps} 0} {{Cursor 3} {10445420000 ps} 0} {{Cursor 4} {61378464308 ps} 0} {{Cursor 5} {99992359332 ps} 0}
141 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {10435060000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {99992359332 ps} 0}
135 configure wave -namecolwidth 469
142 configure wave -namecolwidth 469
136 configure wave -valuecolwidth 112
143 configure wave -valuecolwidth 112
137 configure wave -justifyvalue left
144 configure wave -justifyvalue left
@@ -146,6 +153,6 configure wave -griddelta 40
146 configure wave -timeline 0
153 configure wave -timeline 0
147 configure wave -timelineunits ps
154 configure wave -timelineunits ps
148 update
155 update
149 WaveRestoreZoom {10380584292 ps} {10668763932 ps}
156 WaveRestoreZoom {10434939916 ps} {10435778196 ps}
150 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
157 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
151 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
158 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -53,6 +53,10 END MAC;
53
53
54 ARCHITECTURE ar_MAC OF MAC IS
54 ARCHITECTURE ar_MAC OF MAC IS
55
55
56
57 SIGNAL clr_MAC_s : STD_LOGIC;
58 SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
59
56 SIGNAL add, mult : STD_LOGIC;
60 SIGNAL add, mult : STD_LOGIC;
57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58
62
@@ -77,8 +81,8 ARCHITECTURE ar_MAC OF MAC IS
77 SIGNAL MACMUX2sel_D : STD_LOGIC;
81 SIGNAL MACMUX2sel_D : STD_LOGIC;
78 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
82 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
79 SIGNAL clr_MAC_D : STD_LOGIC;
83 SIGNAL clr_MAC_D : STD_LOGIC;
80 SIGNAL clr_MAC_D_D : STD_LOGIC;
84 -- SIGNAL clr_MAC_D_D : STD_LOGIC;
81 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
85 -- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
82
86
83 SIGNAL load_mult_result : STD_LOGIC;
87 SIGNAL load_mult_result : STD_LOGIC;
84 SIGNAL load_mult_result_D : STD_LOGIC;
88 SIGNAL load_mult_result_D : STD_LOGIC;
@@ -93,7 +97,7 BEGIN
93 --==============================================================
97 --==============================================================
94 MAC_CONTROLER1 : MAC_CONTROLER
98 MAC_CONTROLER1 : MAC_CONTROLER
95 PORT MAP(
99 PORT MAP(
96 ctrl => MAC_MUL_ADD,
100 ctrl => MAC_MUL_ADD_s,
97 MULT => mult,
101 MULT => mult,
98 ADD => add,
102 ADD => add,
99 LOAD_ADDER => load_mult_result,
103 LOAD_ADDER => load_mult_result,
@@ -163,7 +167,7 BEGIN
163 PORT MAP(
167 PORT MAP(
164 clk => clk,
168 clk => clk,
165 reset => reset,
169 reset => reset,
166 clr => clr_MAC,
170 clr => '0',--clr_MAC,
167 TwoComp => Comp_2C(0),
171 TwoComp => Comp_2C(0),
168 OP => OP1,
172 OP => OP1,
169 RES => OP1_2C
173 RES => OP1_2C
@@ -176,16 +180,39 BEGIN
176 PORT MAP(
180 PORT MAP(
177 clk => clk,
181 clk => clk,
178 reset => reset,
182 reset => reset,
179 clr => clr_MAC,
183 clr => '0',--clr_MAC,
180 TwoComp => Comp_2C(1),
184 TwoComp => Comp_2C(1),
181 OP => OP2,
185 OP => OP2,
182 RES => OP2_2C
186 RES => OP2_2C
183 );
187 );
188
189
190 clr_MACREG_comp : MAC_REG
191 GENERIC MAP(size => 1)
192 PORT MAP(
193 reset => reset,
194 clk => clk,
195 D(0) => clr_MAC,
196 Q(0) => clr_MAC_s
197 );
198
199 MAC_MUL_ADD_REG : MAC_REG
200 GENERIC MAP(size => 2)
201 PORT MAP(
202 reset => reset,
203 clk => clk,
204 D => MAC_MUL_ADD,
205 Q => MAC_MUL_ADD_s
206 );
207
184 END GENERATE gen_comp;
208 END GENERATE gen_comp;
185
209
186 no_gen_comp : IF COMP_EN = 1 GENERATE
210 no_gen_comp : IF COMP_EN = 1 GENERATE
187 OP2_2C <= OP2;
211 OP2_2C <= OP2;
188 OP1_2C <= OP1;
212 OP1_2C <= OP1;
213
214 clr_MAC_s <= clr_MAC;
215 MAC_MUL_ADD_s <= MAC_MUL_ADD;
189 END GENERATE no_gen_comp;
216 END GENERATE no_gen_comp;
190 --==============================================================
217 --==============================================================
191
218
@@ -194,7 +221,7 BEGIN
194 PORT MAP(
221 PORT MAP(
195 reset => reset,
222 reset => reset,
196 clk => clk,
223 clk => clk,
197 D(0) => clr_MAC,
224 D(0) => clr_MAC_s,
198 Q(0) => clr_MAC_D
225 Q(0) => clr_MAC_D
199 );
226 );
200
227
Show file before | Show file after | Hide comments
@@ -1,10 +1,4
1 lpp_memory.vhd
1 lpp_memory.vhd
2 lpp_FIFO.vhd
2 lpp_FIFO.vhd
3 FillFifo.vhd
4 Bridge.vhd
5 APB_FIFO.vhd
6 Bridge.vhd
7 SSRAM_plugin.vhd
8 lppFIFOx5.vhd
9 lppFIFOxN.vhd
3 lppFIFOxN.vhd
10
4
Show file before | Show file after | Hide comments
@@ -54,7 +54,7 ARCHITECTURE beh OF MS_calculation IS
54
54
55 SIGNAL res_wen : STD_LOGIC;
55 SIGNAL res_wen : STD_LOGIC;
56 SIGNAL res_wen_reg1 : STD_LOGIC;
56 SIGNAL res_wen_reg1 : STD_LOGIC;
57 -- SIGNAL res_wen_reg2 : STD_LOGIC;
57 SIGNAL res_wen_reg2 : STD_LOGIC;
58 --SIGNAL res_wen_reg3 : STD_LOGIC;
58 --SIGNAL res_wen_reg3 : STD_LOGIC;
59
59
60 BEGIN
60 BEGIN
@@ -75,6 +75,7 BEGIN
75 res_wen <= '1';
75 res_wen <= '1';
76
76
77 ELSIF clk'EVENT AND clk = '1' THEN
77 ELSIF clk'EVENT AND clk = '1' THEN
78 ALU_CTRL <= ALU_CTRL_NOP;
78 correlation_begin <= '0';
79 correlation_begin <= '0';
79 fifo_in_ren <= "11";
80 fifo_in_ren <= "11";
80 res_wen <= '1';
81 res_wen <= '1';
@@ -189,7 +190,7 BEGIN
189 Logic_en => 0,
190 Logic_en => 0,
190 Input_SZ_1 => 16,
191 Input_SZ_1 => 16,
191 Input_SZ_2 => 16,
192 Input_SZ_2 => 16,
192 COMP_EN => 1)
193 COMP_EN => 0) -- 0> Enable and 1> Disable
193 PORT MAP (
194 PORT MAP (
194 clk => clk,
195 clk => clk,
195 reset => rstn,
196 reset => rstn,
@@ -209,14 +210,14 BEGIN
209 BEGIN
210 BEGIN
210 IF rstn = '0' THEN
211 IF rstn = '0' THEN
211 res_wen_reg1 <= '1';
212 res_wen_reg1 <= '1';
212 --res_wen_reg2 <= '1';
213 res_wen_reg2 <= '1';
213 --res_wen_reg3 <= '1';
214 --res_wen_reg3 <= '1';
214 fifo_out_wen <= '1';
215 fifo_out_wen <= '1';
215 ELSIF clk'event AND clk = '1' THEN
216 ELSIF clk'event AND clk = '1' THEN
216 res_wen_reg1 <= res_wen;
217 res_wen_reg1 <= res_wen;
217 --res_wen_reg2 <= res_wen_reg1;
218 res_wen_reg2 <= res_wen_reg1;
218 --res_wen_reg3 <= res_wen_reg2;
219 --res_wen_reg3 <= res_wen_reg2;
219 fifo_out_wen <= res_wen_reg1;
220 fifo_out_wen <= res_wen_reg2;
220 END IF;
221 END IF;
221 END PROCESS;
222 END PROCESS;
222
223
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@@ -31,6 +31,6 BEGIN -- beh
31 END IF;
31 END IF;
32 END PROCESS;
32 END PROCESS;
33
33
34 time_out <= time_in;
34 time_out <= time_reg;
35
35
36 END beh;
36 END beh;
Show file before | Show file after | Hide comments
@@ -726,8 +726,8 BEGIN
726 sample_f0_wdata => sample_f0_wdata,
726 sample_f0_wdata => sample_f0_wdata,
727 sample_f1_wen => sample_f1_wen,
727 sample_f1_wen => sample_f1_wen,
728 sample_f1_wdata => sample_f1_wdata,
728 sample_f1_wdata => sample_f1_wdata,
729 sample_f3_wen => sample_f3_wen,
729 sample_f2_wen => sample_f3_wen, -- TODO verify that it's the good data
730 sample_f3_wdata => sample_f3_wdata,
730 sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data
731
731
732 dma_addr => data_ms_addr, --
732 dma_addr => data_ms_addr, --
733 dma_data => data_ms_data, --
733 dma_data => data_ms_data, --
@@ -736,28 +736,26 BEGIN
736 dma_ren => data_ms_ren, --
736 dma_ren => data_ms_ren, --
737 dma_done => data_ms_done, --
737 dma_done => data_ms_done, --
738
738
739 ready_matrix_f0_0 => ready_matrix_f0_0,
739 ready_matrix_f0 => ready_matrix_f0_0,-- TODO rename
740 ready_matrix_f0_1 => ready_matrix_f0_1,
741 ready_matrix_f1 => ready_matrix_f1,
740 ready_matrix_f1 => ready_matrix_f1,
742 ready_matrix_f2 => ready_matrix_f2,
741 ready_matrix_f2 => ready_matrix_f2,
743 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
742 --error_anticipating_empty_fifo => error_anticipating_empty_fifo,
744 error_bad_component_error => error_bad_component_error,
743 error_bad_component_error => error_bad_component_error,
745 debug_reg => observation_reg, --debug_reg,
744 error_buffer_full => OPEN, -- TODO
746 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
745 error_input_fifo_write => OPEN, -- TODO
747 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
746 debug_reg => observation_reg,
747 status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename
748 status_ready_matrix_f1 => status_ready_matrix_f1,
748 status_ready_matrix_f1 => status_ready_matrix_f1,
749 status_ready_matrix_f2 => status_ready_matrix_f2,
749 status_ready_matrix_f2 => status_ready_matrix_f2,
750 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
750 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,-- TODO
751 status_error_bad_component_error => status_error_bad_component_error,
751 -- status_error_bad_component_error => status_error_bad_component_error,-- TODO
752 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
752 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
753 config_active_interruption_onError => config_active_interruption_onError,
753 config_active_interruption_onError => config_active_interruption_onError,
754 addr_matrix_f0_0 => addr_matrix_f0_0,
754 addr_matrix_f0 => addr_matrix_f0_0,-- TODO rename
755 addr_matrix_f0_1 => addr_matrix_f0_1,
756 addr_matrix_f1 => addr_matrix_f1,
755 addr_matrix_f1 => addr_matrix_f1,
757 addr_matrix_f2 => addr_matrix_f2,
756 addr_matrix_f2 => addr_matrix_f2,
758
757
759 matrix_time_f0_0 => matrix_time_f0_0,
758 matrix_time_f0 => matrix_time_f0_0,-- TODO rename
760 matrix_time_f0_1 => matrix_time_f0_1,
761 matrix_time_f1 => matrix_time_f1,
759 matrix_time_f1 => matrix_time_f1,
762 matrix_time_f2 => matrix_time_f2);
760 matrix_time_f2 => matrix_time_f2);
763
761
Show file before | Show file after | Hide comments
@@ -155,7 +155,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
155 SIGNAL fft_data_valid : STD_LOGIC;
155 SIGNAL fft_data_valid : STD_LOGIC;
156 SIGNAL fft_ready : STD_LOGIC;
156 SIGNAL fft_ready : STD_LOGIC;
157 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
158 SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
160 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
160 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
161 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
161 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
@@ -184,10 +184,11 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
184 SIGNAL SM_correlation_done : STD_LOGIC;
184 SIGNAL SM_correlation_done : STD_LOGIC;
185 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
185 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
186 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
186 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
187 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
187 SIGNAL SM_correlation_begin : STD_LOGIC;
188 SIGNAL SM_correlation_begin : STD_LOGIC;
188
189
189 SIGNAL temp_ongoing : STD_LOGIC;
190 -- SIGNAL temp_ongoing : STD_LOGIC;
190 SIGNAL temp_auto : STD_LOGIC;
191 -- SIGNAL temp_auto : STD_LOGIC;
191
192
192 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
193 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
193 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -209,15 +210,15 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
209 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
210 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
210
211
211 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
212 SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 -- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
214 SIGNAL HEAD_SM_Wen : STD_LOGIC;
215 --SIGNAL HEAD_SM_Wen : STD_LOGIC;
215 SIGNAL HEAD_Valid : STD_LOGIC;
216 --SIGNAL HEAD_Valid : STD_LOGIC;
216 SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL HEAD_Empty : STD_LOGIC;
218 --SIGNAL HEAD_Empty : STD_LOGIC;
218 SIGNAL HEAD_Read : STD_LOGIC;
219 --SIGNAL HEAD_Read : STD_LOGIC;
219 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
220 SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
221 -- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
221 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
222 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
222 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
223 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
223 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
224 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
@@ -225,9 +226,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
225 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
226 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
226 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
227 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
227 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
228 SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL DMA_Header_Val : STD_LOGIC;
230 --SIGNAL DMA_Header_Val : STD_LOGIC;
230 SIGNAL DMA_Header_Ack : STD_LOGIC;
231 --SIGNAL DMA_Header_Ack : STD_LOGIC;
231
232
232 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
233 -- TIME REG & INFOs
234 -- TIME REG & INFOs
@@ -250,8 +251,8 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
250
251
251 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
252 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
252 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
253 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
253 SIGNAL status_component_fifo_0_new : STD_LOGIC;
254 -- SIGNAL status_component_fifo_0_new : STD_LOGIC;
254 SIGNAL status_component_fifo_1_new : STD_LOGIC;
255 -- SIGNAL status_component_fifo_1_new : STD_LOGIC;
255 SIGNAL status_component_fifo_0_end : STD_LOGIC;
256 SIGNAL status_component_fifo_0_end : STD_LOGIC;
256 SIGNAL status_component_fifo_1_end : STD_LOGIC;
257 SIGNAL status_component_fifo_1_end : STD_LOGIC;
257
258
@@ -582,35 +583,19 BEGIN
582 -----------------------------------------------------------------------------
583 -----------------------------------------------------------------------------
583 -- FFT
584 -- FFT
584 -----------------------------------------------------------------------------
585 -----------------------------------------------------------------------------
585 CoreFFT_1 : CoreFFT
586 lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT
586 GENERIC MAP (
587 LOGPTS => gLOGPTS,
588 LOGLOGPTS => gLOGLOGPTS,
589 WSIZE => gWSIZE,
590 TWIDTH => gTWIDTH,
591 DWIDTH => gDWIDTH,
592 TDWIDTH => gTDWIDTH,
593 RND_MODE => gRND_MODE,
594 SCALE_MODE => gSCALE_MODE,
595 PTS => gPTS,
596 HALFPTS => gHALFPTS,
597 inBuf_RWDLY => gInBuf_RWDLY)
598 PORT MAP (
587 PORT MAP (
599 clk => clk,
588 clk => clk,
600 ifiStart => '1',
589 rstn => rstn,
601 ifiNreset => rstn,
590 sample_valid => sample_valid,
602
591 fft_read => fft_read,
603 ifiD_valid => sample_valid, -- IN
592 sample_data => sample_data,
604 ifiRead_y => fft_read,
593 sample_load => sample_load,
605 ifiD_im => (OTHERS => '0'), -- IN
594 fft_pong => fft_pong,
606 ifiD_re => sample_data, -- IN
595 fft_data_im => fft_data_im,
607 ifoLoad => sample_load, -- IN
596 fft_data_re => fft_data_re,
608
597 fft_data_valid => fft_data_valid,
609 ifoPong => fft_pong,
598 fft_ready => fft_ready);
610 ifoY_im => fft_data_im,
611 ifoY_re => fft_data_re,
612 ifoY_valid => fft_data_valid,
613 ifoY_rdy => fft_ready);
614
599
615 -----------------------------------------------------------------------------
600 -----------------------------------------------------------------------------
616 -- in fft_data_im & fft_data_re
601 -- in fft_data_im & fft_data_re
@@ -736,7 +721,8 BEGIN
736 ren => MEM_IN_SM_ren,
721 ren => MEM_IN_SM_ren,
737 rdata => MEM_IN_SM_rData,
722 rdata => MEM_IN_SM_rData,
738 full => MEM_IN_SM_Full,
723 full => MEM_IN_SM_Full,
739 empty => MEM_IN_SM_Empty);
724 empty => MEM_IN_SM_Empty,
725 almost_full => OPEN);
740
726
741
727
742 --all_lock: FOR I IN 4 DOWNTO 0 GENERATE
728 --all_lock: FOR I IN 4 DOWNTO 0 GENERATE
@@ -802,19 +788,21 BEGIN
802 current_matrix_wait_empty <= '1';
788 current_matrix_wait_empty <= '1';
803 status_component_fifo_0 <= (OTHERS => '0');
789 status_component_fifo_0 <= (OTHERS => '0');
804 status_component_fifo_1 <= (OTHERS => '0');
790 status_component_fifo_1 <= (OTHERS => '0');
805 status_component_fifo_0_new <= '0';
791 -- status_component_fifo_0_new <= '0';
806 status_component_fifo_1_new <= '0';
792 -- status_component_fifo_1_new <= '0';
807 status_component_fifo_0_end <= '0';
793 status_component_fifo_0_end <= '0';
808 status_component_fifo_1_end <= '0';
794 status_component_fifo_1_end <= '0';
809 SM_correlation_done_reg1 <= '0';
795 SM_correlation_done_reg1 <= '0';
810 SM_correlation_done_reg2 <= '0';
796 SM_correlation_done_reg2 <= '0';
797 SM_correlation_done_reg3 <= '0';
811
798
812 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
799 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
813 SM_correlation_done_reg1 <= SM_correlation_done;
800 SM_correlation_done_reg1 <= SM_correlation_done;
814 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
801 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
802 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
815
803
816 status_component_fifo_0_new <= '0';
804 -- status_component_fifo_0_new <= '0';
817 status_component_fifo_1_new <= '0';
805 -- status_component_fifo_1_new <= '0';
818 status_component_fifo_0_end <= '0';
806 status_component_fifo_0_end <= '0';
819 status_component_fifo_1_end <= '0';
807 status_component_fifo_1_end <= '0';
820
808
@@ -822,15 +810,15 BEGIN
822
810
823 IF SM_correlation_begin = '1' THEN
811 IF SM_correlation_begin = '1' THEN
824 IF current_matrix_write = '0' THEN
812 IF current_matrix_write = '0' THEN
825 status_component_fifo_0_new <= '1';
813 -- status_component_fifo_0_new <= '1';
826 status_component_fifo_0 <= status_component;
814 status_component_fifo_0 <= status_component;
827 ELSE
815 ELSE
828 status_component_fifo_1_new <= '1';
816 -- status_component_fifo_1_new <= '1';
829 status_component_fifo_1 <= status_component;
817 status_component_fifo_1 <= status_component;
830 END IF;
818 END IF;
831 END IF;
819 END IF;
832
820
833 IF SM_correlation_done_reg2 = '1' THEN
821 IF SM_correlation_done_reg3 = '1' THEN
834 IF current_matrix_write = '0' THEN
822 IF current_matrix_write = '0' THEN
835 status_component_fifo_0_end <= '1';
823 status_component_fifo_0_end <= '1';
836 ELSE
824 ELSE
@@ -854,6 +842,7 BEGIN
854 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
842 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
855 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
843 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
856 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
844 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
845 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
857 '1' WHEN current_matrix_wait_empty = '1' ELSE
846 '1' WHEN current_matrix_wait_empty = '1' ELSE
858 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
847 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
859 MEM_OUT_SM_Full(1);
848 MEM_OUT_SM_Full(1);
Show file before | Show file after | Hide comments
@@ -114,7 +114,7 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs
114 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
114 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL header_check_ok : STD_LOGIC;
115 SIGNAL header_check_ok : STD_LOGIC;
116 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 SIGNAL send_matrix : STD_LOGIC;
117 -- SIGNAL send_matrix : STD_LOGIC;
118 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
@@ -124,17 +124,17 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs
124 -- SIGNAL component_send_ko : STD_LOGIC;
124 -- SIGNAL component_send_ko : STD_LOGIC;
125 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 SIGNAL fifo_ren_trash : STD_LOGIC;
126 SIGNAL fifo_ren_trash : STD_LOGIC;
127 SIGNAL component_fifo_ren : STD_LOGIC;
127 -- SIGNAL component_fifo_ren : STD_LOGIC;
128
128
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 SIGNAL log_empty_fifo : STD_LOGIC;
132 SIGNAL log_empty_fifo : STD_LOGIC;
133 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
134 SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
134 --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 SIGNAL header_reg_val : STD_LOGIC;
135 --SIGNAL header_reg_val : STD_LOGIC;
136 SIGNAL header_reg_ack : STD_LOGIC;
136 --SIGNAL header_reg_ack : STD_LOGIC;
137 SIGNAL header_error : STD_LOGIC;
137 -- SIGNAL header_error : STD_LOGIC;
138
138
139 SIGNAL matrix_buffer_ready : STD_LOGIC;
139 SIGNAL matrix_buffer_ready : STD_LOGIC;
140 BEGIN
140 BEGIN
@@ -159,6 +159,7 BEGIN
159 addr_matrix_f2 WHEN matrix_type = "10" ELSE
159 addr_matrix_f2 WHEN matrix_type = "10" ELSE
160 (OTHERS => '0');
160 (OTHERS => '0');
161
161
162 debug_reg_s(31 DOWNTO 3) <= (OTHERS => '0');
162 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
163 -- DMA control
164 -- DMA control
164 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
@@ -181,12 +182,14 BEGIN
181 address <= (OTHERS => '0');
182 address <= (OTHERS => '0');
182
183
183 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
184 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
184 debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
185
185
186 log_empty_fifo <= '0';
186 log_empty_fifo <= '0';
187
187
188 matrix_time_f0 <= (OTHERS => '0');
189 matrix_time_f1 <= (OTHERS => '0');
190 matrix_time_f2 <= (OTHERS => '0');
191
188 ELSIF HCLK'EVENT AND HCLK = '1' THEN
192 ELSIF HCLK'EVENT AND HCLK = '1' THEN
189 debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
190
193
191 ready_matrix_f0 <= '0';
194 ready_matrix_f0 <= '0';
192 -- ready_matrix_f0_1 <= '0';
195 -- ready_matrix_f0_1 <= '0';
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@@ -13,7 +13,60 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
17 -- TEMP
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
21 Mem_use : INTEGER);
22 PORT (
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
16
38
39
40
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
55 -----------------------------------------------------------------------------
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
65 );
66 END COMPONENT;
67
68
69 -----------------------------------------------------------------------------
17 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
18 GENERIC (
71 GENERIC (
19 Mem_use : INTEGER
72 Mem_use : INTEGER
@@ -119,7 +172,21 PACKAGE lpp_lfr_pkg IS
119 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
172 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
120 );
173 );
121 END COMPONENT;
174 END COMPONENT;
122
175
176 COMPONENT lpp_lfr_ms_FFT
177 PORT (
178 clk : IN STD_LOGIC;
179 rstn : IN STD_LOGIC;
180 sample_valid : IN STD_LOGIC;
181 fft_read : IN STD_LOGIC;
182 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
183 sample_load : OUT STD_LOGIC;
184 fft_pong : OUT STD_LOGIC;
185 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
186 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
187 fft_data_valid : OUT STD_LOGIC;
188 fft_ready : OUT STD_LOGIC);
189 END COMPONENT;
123
190
124 COMPONENT lpp_lfr_filter
191 COMPONENT lpp_lfr_filter
125 GENERIC (
192 GENERIC (
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@@ -3,6 +3,8 lpp_lfr_pkg.vhd
3 lpp_lfr_filter.vhd
3 lpp_lfr_filter.vhd
4 lpp_lfr_apbreg.vhd
4 lpp_lfr_apbreg.vhd
5 lpp_lfr_ms_fsmdma.vhd
5 lpp_lfr_ms_fsmdma.vhd
6 lpp_lfr_ms_FFT.vhd
6 lpp_lfr_ms.vhd
7 lpp_lfr_ms.vhd
8 lpp_lfr_ms_test_synt.vhd
7 lpp_lfr_WFP_nMS.vhd
9 lpp_lfr_WFP_nMS.vhd
8 lpp_lfr.vhd
10 lpp_lfr.vhd
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