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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44
45 ENTITY leon3ft_soc IS
46 GENERIC (
47 fabtech : INTEGER := apa3e;
48 memtech : INTEGER := apa3e;
49 padtech : INTEGER := inferred;
50 clktech : INTEGER := inferred;
51 disas : INTEGER := 0; -- Enable disassembly to console
52 dbguart : INTEGER := 0; -- Print UART on console
53 pclow : INTEGER := 2;
54 --
55 clk_freq : INTEGER := 25000; --kHz
56 --
57 NB_CPU : INTEGER := 1;
58 ENABLE_FPU : INTEGER := 1;
59 FPU_NETLIST : INTEGER := 1;
60 ENABLE_DSU : INTEGER := 1;
61 ENABLE_AHB_UART : INTEGER := 1;
62 ENABLE_APB_UART : INTEGER := 1;
63 ENABLE_IRQMP : INTEGER := 1;
64 ENABLE_GPT : INTEGER := 1;
65 --
66 NB_AHB_MASTER : INTEGER := 11;
67 NB_AHB_SLAVE : INTEGER := 1;
68 NB_APB_SLAVE : INTEGER := 2
69 );
70 PORT (
71 clk : IN STD_ULOGIC;
72 reset : IN STD_ULOGIC;
73
74 errorn : OUT STD_ULOGIC;
75
76 -- UART AHB ---------------------------------------------------------------
77 ahbrxd : IN STD_ULOGIC; -- DSU rx data
78 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
79
80 -- UART APB ---------------------------------------------------------------
81 urxd1 : IN STD_ULOGIC; -- UART1 rx data
82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83
84 -- RAM --------------------------------------------------------------------
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 nSRAM_BE0 : OUT STD_LOGIC;
88 nSRAM_BE1 : OUT STD_LOGIC;
89 nSRAM_BE2 : OUT STD_LOGIC;
90 nSRAM_BE3 : OUT STD_LOGIC;
91 nSRAM_WE : OUT STD_LOGIC;
92 nSRAM_CE : OUT STD_LOGIC;
93 nSRAM_OE : OUT STD_LOGIC;
94
95 -- APB --------------------------------------------------------------------
96 apbi_ext : OUT apb_slv_in_type;
97 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
98 -- AHB_Slave --------------------------------------------------------------
99 ahbi_s_ext : OUT ahb_slv_in_type;
100 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
101 -- AHB_Master -------------------------------------------------------------
102 ahbi_m_ext : OUT AHB_Mst_In_Type;
103 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
104
105 );
106 END;
107
108 ARCHITECTURE Behavioral OF leon3ft_soc IS
109
110 -----------------------------------------------------------------------------
111 -- CONFIG -------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
114 -- Clock generator
115 CONSTANT CFG_CLKMUL : INTEGER := (1);
116 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
117 CONSTANT CFG_OCLKDIV : INTEGER := (1);
118 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
119 -- LEON3 processor core
120 CONSTANT CFG_LEON3 : INTEGER := 1;
121 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
122 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
123 CONSTANT CFG_V8 : INTEGER := 0;
124 CONSTANT CFG_MAC : INTEGER := 0;
125 CONSTANT CFG_SVT : INTEGER := 0;
126 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
127 CONSTANT CFG_LDDEL : INTEGER := (1);
128 CONSTANT CFG_NWP : INTEGER := (0);
129 CONSTANT CFG_PWD : INTEGER := 1*2;
130 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
131 -- 1*(8 + 16 * 0) => grfpu-light
132 -- 1*(8 + 16 * 1) => netlist
133 -- 0*(8 + 16 * 0) => No FPU
134 -- 0*(8 + 16 * 1) => No FPU;
135 CONSTANT CFG_ICEN : INTEGER := 1;
136 CONSTANT CFG_ISETS : INTEGER := 1;
137 CONSTANT CFG_ISETSZ : INTEGER := 4;
138 CONSTANT CFG_ILINE : INTEGER := 4;
139 CONSTANT CFG_IREPL : INTEGER := 0;
140 CONSTANT CFG_ILOCK : INTEGER := 0;
141 CONSTANT CFG_ILRAMEN : INTEGER := 0;
142 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
143 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
144 CONSTANT CFG_DCEN : INTEGER := 1;
145 CONSTANT CFG_DSETS : INTEGER := 1;
146 CONSTANT CFG_DSETSZ : INTEGER := 4;
147 CONSTANT CFG_DLINE : INTEGER := 4;
148 CONSTANT CFG_DREPL : INTEGER := 0;
149 CONSTANT CFG_DLOCK : INTEGER := 0;
150 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
151 CONSTANT CFG_DLRAMEN : INTEGER := 0;
152 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
153 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
154 CONSTANT CFG_MMUEN : INTEGER := 0;
155 CONSTANT CFG_ITLBNUM : INTEGER := 2;
156 CONSTANT CFG_DTLBNUM : INTEGER := 2;
157 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
158 CONSTANT CFG_TLB_REP : INTEGER := 1;
159
160 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
161 CONSTANT CFG_ITBSZ : INTEGER := 0;
162 CONSTANT CFG_ATBSZ : INTEGER := 0;
163
164 -- AMBA settings
165 CONSTANT CFG_DEFMST : INTEGER := (0);
166 CONSTANT CFG_RROBIN : INTEGER := 1;
167 CONSTANT CFG_SPLIT : INTEGER := 0;
168 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
169 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
170
171 -- DSU UART
172 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
173
174 -- LEON2 memory controller
175 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
176
177 -- UART 1
178 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
179 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
180
181 -- LEON3 interrupt controller
182 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
183
184 -- Modular timer
185 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
186 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
187 CONSTANT CFG_GPT_SW : INTEGER := (8);
188 CONSTANT CFG_GPT_TW : INTEGER := (32);
189 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
190 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
191 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
192 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
193 -----------------------------------------------------------------------------
194
195 -----------------------------------------------------------------------------
196 -- SIGNALs
197 -----------------------------------------------------------------------------
198 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
199 -- CLK & RST --
200 SIGNAL clk2x : STD_ULOGIC;
201 SIGNAL clkmn : STD_ULOGIC;
202 SIGNAL clkm : STD_ULOGIC;
203 SIGNAL rstn : STD_ULOGIC;
204 SIGNAL rstraw : STD_ULOGIC;
205 SIGNAL pciclk : STD_ULOGIC;
206 SIGNAL sdclkl : STD_ULOGIC;
207 SIGNAL cgi : clkgen_in_type;
208 SIGNAL cgo : clkgen_out_type;
209 --- AHB / APB
210 SIGNAL apbi : apb_slv_in_type;
211 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
212 SIGNAL ahbsi : ahb_slv_in_type;
213 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
214 SIGNAL ahbmi : ahb_mst_in_type;
215 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
216 --UART
217 SIGNAL ahbuarti : uart_in_type;
218 SIGNAL ahbuarto : uart_out_type;
219 SIGNAL apbuarti : uart_in_type;
220 SIGNAL apbuarto : uart_out_type;
221 --MEM CTRLR
222 SIGNAL memi : memory_in_type;
223 SIGNAL memo : memory_out_type;
224 SIGNAL wpo : wprot_out_type;
225 SIGNAL sdo : sdram_out_type;
226 --IRQ
227 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
228 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
229 --Timer
230 SIGNAL gpti : gptimer_in_type;
231 SIGNAL gpto : gptimer_out_type;
232 --DSU
233 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
234 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
235 SIGNAL dsui : dsu_in_type;
236 SIGNAL dsuo : dsu_out_type;
237 -----------------------------------------------------------------------------
238
239 SIGNAL nSRAM_CE_s : STD_LOGIC;
240 BEGIN
241
242
243 ----------------------------------------------------------------------
244 --- Reset and Clock generation -------------------------------------
245 ----------------------------------------------------------------------
246
247 cgi.pllctrl <= "00";
248 cgi.pllrst <= rstraw;
249
250 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
251
252 clkgen0 : clkgen -- clock generator
253 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
254 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
255 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
256
257 ----------------------------------------------------------------------
258 --- LEON3 processor / DSU / IRQ ------------------------------------
259 ----------------------------------------------------------------------
260
261 l3 : IF CFG_LEON3 = 1 GENERATE
262 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
263 u0 : leon3ft
264 GENERIC MAP (
265 hindex => i, --: integer;
266 fabtech => fabtech,
267 memtech => memtech,
268 nwindows => CFG_NWIN,
269 dsu => CFG_DSU,
270 fpu => CFG_FPU,
271 v8 => CFG_V8,
272 cp => 0,
273 mac => CFG_MAC,
274 pclow => pclow,
275 notag => 0,
276 nwp => CFG_NWP,
277 icen => CFG_ICEN,
278 irepl => CFG_IREPL,
279 isets => CFG_ISETS,
280 ilinesize => CFG_ILINE,
281 isetsize => CFG_ISETSZ,
282 isetlock => CFG_ILOCK,
283 dcen => CFG_DCEN,
284 drepl => CFG_DREPL,
285 dsets => CFG_DSETS,
286 dlinesize => CFG_DLINE,
287 dsetsize => CFG_DSETSZ,
288 dsetlock => CFG_DLOCK,
289 dsnoop => CFG_DSNOOP,
290 ilram => CFG_ILRAMEN,
291 ilramsize => CFG_ILRAMSZ,
292 ilramstart => CFG_ILRAMADDR,
293 dlram => CFG_DLRAMEN,
294 dlramsize => CFG_DLRAMSZ,
295 dlramstart => CFG_DLRAMADDR,
296 mmuen => CFG_MMUEN,
297 itlbnum => CFG_ITLBNUM,
298 dtlbnum => CFG_DTLBNUM,
299 tlb_type => CFG_TLB_TYPE,
300 tlb_rep => CFG_TLB_REP,
301 lddel => CFG_LDDEL,
302 disas => disas,
303 tbuf => CFG_ITBSZ,
304 pwd => CFG_PWD,
305 svt => CFG_SVT,
306 rstaddr => CFG_RSTADDR,
307 smp => CFG_NCPU-1,
308 iuft => 2, --: integer range 0 to 4;
309 fpft => 1, --: integer range 0 to 4;
310 cmft => 1, --: integer range 0 to 1;
311 iuinj => 0, --: integer;
312 ceinj => 0, --: integer range 0 to 3;
313 cached => 0, --: integer;
314 netlist => 0, --: integer;
315 scantest => 0, --: integer;
316 mmupgsz => 0, --: integer range 0 to 5;
317 bp => 1) --: integer);
318 PORT MAP (
319 clk => clkm,
320 rstn => rstn,
321 ahbi => ahbmi,
322 ahbo => ahbmo(i),
323 ahbsi => ahbsi,
324 ahbso => ahbso,
325 irqi => irqi(i),
326 irqo => irqo(i),
327 dbgi => dbgi(i),
328 dbgo => dbgo(i),
329 gclk => clkm
330 );
331
332 END GENERATE;
333
334
335 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
336
337 dsugen : IF CFG_DSU = 1 GENERATE
338 dsu0 : dsu3 -- LEON3 Debug Support Unit
339 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
340 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
341 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
342 dsui.enable <= '1';
343 dsui.break <= '0';
344 END GENERATE;
345 END GENERATE;
346
347 nodsu : IF CFG_DSU = 0 GENERATE
348 ahbso(2) <= ahbs_none;
349 dsuo.tstop <= '0';
350 dsuo.active <= '0';
351 END GENERATE;
352
353 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
354 irqctrl0 : irqmp -- interrupt controller
355 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
356 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
357 END GENERATE;
358 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
359 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
360 irqi(i).irl <= "0000";
361 END GENERATE;
362 apbo(2) <= apb_none;
363 END GENERATE;
364
365 ----------------------------------------------------------------------
366 --- Memory controllers ---------------------------------------------
367 ----------------------------------------------------------------------
368 memctrlr : mctrl GENERIC MAP (
369 hindex => 0,
370 pindex => 0,
371 paddr => 0,
372 srbanks => 1
373 )
374 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
375
376 memi.brdyn <= '1';
377 memi.bexcn <= '1';
378 memi.writen <= '1';
379 memi.wrn <= "1111";
380 memi.bwidth <= "10";
381
382 bdr : FOR i IN 0 TO 3 GENERATE
383 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
384 PORT MAP (
385 data(31-i*8 DOWNTO 24-i*8),
386 memo.data(31-i*8 DOWNTO 24-i*8),
387 memo.bdrive(i),
388 memi.data(31-i*8 DOWNTO 24-i*8));
389 END GENERATE;
390
391 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
392 PORT MAP (address, memo.address(21 DOWNTO 2));
393 nSRAM_CE_s <= NOT(memo.ramsn(0));
394 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
395 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
396 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
397 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
398 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
399 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
400 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
401
402 ----------------------------------------------------------------------
403 --- AHB CONTROLLER -------------------------------------------------
404 ----------------------------------------------------------------------
405 ahb0 : ahbctrl -- AHB arbiter/multiplexer
406 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
407 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
408 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
409 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
410
411 ----------------------------------------------------------------------
412 --- AHB UART -------------------------------------------------------
413 ----------------------------------------------------------------------
414 dcomgen : IF CFG_AHB_UART = 1 GENERATE
415 dcom0 : ahbuart
416 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
417 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
418 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
419 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
420 END GENERATE;
421 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
422
423 ----------------------------------------------------------------------
424 --- APB Bridge -----------------------------------------------------
425 ----------------------------------------------------------------------
426 apb0 : apbctrl -- AHB/APB bridge
427 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
428 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
429
430 ----------------------------------------------------------------------
431 --- GPT Timer ------------------------------------------------------
432 ----------------------------------------------------------------------
433 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
434 timer0 : gptimer -- timer unit
435 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
436 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
437 nbits => CFG_GPT_TW)
438 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
439 gpti.dhalt <= dsuo.tstop;
440 gpti.extclk <= '0';
441 END GENERATE;
442 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
443
444
445 ----------------------------------------------------------------------
446 --- APB UART -------------------------------------------------------
447 ----------------------------------------------------------------------
448 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
449 uart1 : apbuart -- UART 1
450 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
451 fifosize => CFG_UART1_FIFO)
452 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
453 apbuarti.rxd <= urxd1;
454 apbuarti.extclk <= '0';
455 utxd1 <= apbuarto.txd;
456 apbuarti.ctsn <= '0';
457 END GENERATE;
458 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
459
460 -------------------------------------------------------------------------------
461 -- AMBA BUS -------------------------------------------------------------------
462 -------------------------------------------------------------------------------
463
464 -- APB --------------------------------------------------------------------
465 apbi_ext <= apbi;
466 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
467 max_16_apb : IF I + 5 < 16 GENERATE
468 apbo(I+5) <= apbo_ext(I+5);
469 END GENERATE max_16_apb;
470 END GENERATE all_apb;
471 -- AHB_Slave --------------------------------------------------------------
472 ahbi_s_ext <= ahbsi;
473 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
474 max_16_ahbs : IF I + 3 < 16 GENERATE
475 ahbso(I+3) <= ahbo_s_ext(I+3);
476 END GENERATE max_16_ahbs;
477 END GENERATE all_ahbs;
478 -- AHB_Master -------------------------------------------------------------
479 ahbi_m_ext <= ahbmi;
480 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
481 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
482 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
483 END GENERATE max_16_ahbm;
484 END GENERATE all_ahbm;
485
486
487
488 END Behavioral;
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