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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 library ieee;
22 use ieee.std_logic_1164.all;
23 library grlib;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library gaisler;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
33 library esa;
34 use esa.memoryctrl.all;
35 use work.config.all;
36 library lpp;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
48
49 entity leon3mp is
50 generic (
51 fabtech : integer := CFG_FABTECH;
52 memtech : integer := CFG_MEMTECH;
53 padtech : integer := CFG_PADTECH;
54 clktech : integer := CFG_CLKTECH;
55 disas : integer := CFG_DISAS; -- Enable disassembly to console
56 dbguart : integer := CFG_DUART; -- Print UART on console
57 pclow : integer := CFG_PCLOW
58 );
59 port (
60 clk50MHz : in std_ulogic;
61 reset : in std_ulogic;
62 ramclk : out std_logic;
63
64 ahbrxd : in std_ulogic; -- DSU rx data
65 ahbtxd : out std_ulogic; -- DSU tx data
66 dsubre : in std_ulogic;
67 dsuact : out std_ulogic;
68 urxd1 : in std_ulogic; -- UART1 rx data
69 utxd1 : out std_ulogic; -- UART1 tx data
70 errorn : out std_ulogic;
71
72 address : out std_logic_vector(18 downto 0);
73 data : inout std_logic_vector(31 downto 0);
74 gpio : inout std_logic_vector(6 downto 0); -- I/O port
75
76 nBWa : out std_logic;
77 nBWb : out std_logic;
78 nBWc : out std_logic;
79 nBWd : out std_logic;
80 nBWE : out std_logic;
81 nADSC : out std_logic;
82 nADSP : out std_logic;
83 nADV : out std_logic;
84 nGW : out std_logic;
85 nCE1 : out std_logic;
86 CE2 : out std_logic;
87 nCE3 : out std_logic;
88 nOE : out std_logic;
89 MODE : out std_logic;
90 SSRAM_CLK : out std_logic;
91 ZZ : out std_logic;
92 ---------------------------------------------------------------------
93 --- AJOUT TEST ------------------------In/Out-----------------------
94 ---------------------------------------------------------------------
95 -- UART
96 UART_RXD : in std_logic;
97 UART_TXD : out std_logic;
98 -- ADC
99 -- ADC_in : in AD7688_in(4 downto 0);
100 -- ADC_out : out AD7688_out;
101 -- Bias_Fails : out std_logic;
102 -- CNA
103 -- DAC_SYNC : out std_logic;
104 -- DAC_SCLK : out std_logic;
105 -- DAC_DATA : out std_logic;
106 -- Diver
107 SPW1_EN : out std_logic;
108 SPW2_EN : out std_logic;
109 TEST : out std_logic_vector(3 downto 0);
110
111 BP : in std_logic;
112 ---------------------------------------------------------------------
113 led : out std_logic_vector(1 downto 0)
114 );
115 end;
116
117 architecture Behavioral of leon3mp is
118
119 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
120 CFG_GRETH+CFG_AHB_JTAG;
121 constant maxahbm : integer := maxahbmsp;
122
123 --Clk & Rst gοΏ½nοΏ½
124 signal vcc : std_logic_vector(4 downto 0);
125 signal gnd : std_logic_vector(4 downto 0);
126 signal resetnl : std_ulogic;
127 signal clk2x : std_ulogic;
128 signal lclk : std_ulogic;
129 signal lclk2x : std_ulogic;
130 signal clkm : std_ulogic;
131 signal rstn : std_ulogic;
132 signal rstraw : std_ulogic;
133 signal pciclk : std_ulogic;
134 signal sdclkl : std_ulogic;
135 signal cgi : clkgen_in_type;
136 signal cgo : clkgen_out_type;
137 --- AHB / APB
138 signal apbi : apb_slv_in_type;
139 signal apbo : apb_slv_out_vector := (others => apb_none);
140 signal ahbsi : ahb_slv_in_type;
141 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
142 signal ahbmi : ahb_mst_in_type;
143 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
144 --UART
145 signal ahbuarti : uart_in_type;
146 signal ahbuarto : uart_out_type;
147 signal apbuarti : uart_in_type;
148 signal apbuarto : uart_out_type;
149 --MEM CTRLR
150 signal memi : memory_in_type;
151 signal memo : memory_out_type;
152 signal wpo : wprot_out_type;
153 signal sdo : sdram_out_type;
154 --IRQ
155 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
156 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
157 --Timer
158 signal gpti : gptimer_in_type;
159 signal gpto : gptimer_out_type;
160 --GPIO
161 signal gpioi : gpio_in_type;
162 signal gpioo : gpio_out_type;
163 --DSU
164 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
165 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
166 signal dsui : dsu_in_type;
167 signal dsuo : dsu_out_type;
168
169 ---------------------------------------------------------------------
170 --- AJOUT TEST ------------------------Signaux----------------------
171 ---------------------------------------------------------------------
172 -- FIFOs
173 signal FifoIN_Full : std_logic_vector(0 downto 0);--
174 signal FifoIN_Empty : std_logic_vector(0 downto 0);--
175 signal FifoIN_Data : std_logic_vector(15 downto 0);--
176
177 signal FifoINT_Full : std_logic_vector(4 downto 0);
178 signal FifoINT_Data : std_logic_vector(79 downto 0);
179
180 signal FifoOUT_FullV : std_logic;
181 signal FifoOUT_Full : std_logic_vector(0 downto 0);--
182 signal Matrix_WriteV : std_logic_vector(0 downto 0);
183
184 -- MATRICE SPECTRALE
185 signal Matrix_Write : std_logic;
186 signal Matrix_Read : std_logic_vector(1 downto 0);
187 signal Matrix_Result : std_logic_vector(31 downto 0);
188
189 signal TopSM_Start : std_logic;
190 signal TopSM_Statu : std_logic_vector(3 downto 0);
191 signal TopSM_Read : std_logic_vector(4 downto 0);
192 signal TopSM_Data1 : std_logic_vector(15 downto 0);
193 signal TopSM_Data2 : std_logic_vector(15 downto 0);
194
195 signal Disp_FlagError : std_logic;
196 signal Disp_Pong : std_logic;
197 signal Disp_Write : std_logic_vector(1 downto 0);
198 signal Disp_Data : std_logic_vector(63 downto 0);
199 signal Dma_acq : std_logic;
200
201 -- FFT
202 signal Drive_Write : std_logic;
203 signal Drive_Read : std_logic_vector(0 downto 0);--
204 signal Drive_DataRE : std_logic_vector(15 downto 0);
205 signal Drive_DataIM : std_logic_vector(15 downto 0);
206
207 signal Start : std_logic;
208 signal RstnFFT : std_logic;
209 signal FFT_Load : std_logic;
210 signal FFT_Ready : std_logic;
211 signal FFT_Valid : std_logic;
212 signal FFT_DataRE : std_logic_vector(15 downto 0);
213 signal FFT_DataIM : std_logic_vector(15 downto 0);
214
215 signal Link_Read : std_logic;
216 signal Link_Write : std_logic_vector(0 downto 0);--
217 signal Link_ReUse : std_logic_vector(0 downto 0);--
218 signal Link_Data : std_logic_vector(15 downto 0);--
219
220 -- ADC
221 signal SmplClk : std_logic;
222 signal ADC_DataReady : std_logic;
223 signal ADC_SmplOut : Samples_out(4 downto 0);
224 signal enableADC : std_logic;
225
226 signal WG_Write : std_logic_vector(4 downto 0);
227 signal WG_ReUse : std_logic_vector(4 downto 0);
228 signal WG_DATA : std_logic_vector(79 downto 0);
229 signal s_out : std_logic_vector(79 downto 0);
230
231 signal fuller : std_logic_vector(4 downto 0);
232 signal reader : std_logic_vector(4 downto 0);
233 signal try : std_logic_vector(1 downto 0);
234 signal TXDint : std_logic;
235
236 -- IIR Filter
237 signal sample_clk_out : std_logic;
238
239 signal Rd : std_logic_vector(0 downto 0);--
240 signal Ept : std_logic_vector(0 downto 0);--
241
242 signal Bwr : std_logic_vector(0 downto 0);
243 signal Bre : std_logic_vector(0 downto 0);
244 signal DataTMP : std_logic_vector(15 downto 0);
245 signal FullUp : std_logic_vector(0 downto 0);
246 signal EmptyUp : std_logic_vector(0 downto 0);
247 signal FullDown : std_logic_vector(0 downto 0);
248 signal EmptyDown : std_logic_vector(0 downto 0);
249 ---------------------------------------------------------------------
250 constant IOAEN : integer := CFG_CAN;
251 constant boardfreq : integer := 50000;
252
253 begin
254
255 ---------------------------------------------------------------------
256 --- AJOUT TEST -------------------------------------IPs-------------
257 ---------------------------------------------------------------------
258 led(1 downto 0) <= gpio(1 downto 0);
259
260 --- COM USB ---------------------------------------------------------
261 -- MemIn0 : APB_FifoWrite
262 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
263 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
264 --
265 -- BUF0 : APB_USB
266 -- generic map (6,6,DataMax => 1024)
267 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
268 --
269 -- MemOut0 : APB_FifoRead
270 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
271 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
272 --
273 --slrd <= usb_Read;
274 --slwr <= usb_Write;
275
276 --- CNA -------------------------------------------------------------
277
278 -- CONV : APB_CNA
279 -- generic map (5,5)
280 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
281
282 --TEST(0) <= SmplClk;
283 --TEST(1) <= WG_Write(0);
284 --TEST(2) <= Fuller(0);
285 --TEST(3) <= s_out(s_out'length-1);
286
287
288 SPW1_EN <= '1';
289 SPW2_EN <= '0';
290
291 --- CAN -------------------------------------------------------------
292
293 -- Divider : Clk_divider
294 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
295 -- Port map(clkm,rstn,SmplClk);
296 --
297 -- ADC : AD7688_drvr
298 -- generic map (ChanelCount => 5, clkkHz => 24_576)
299 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
300 --
301 -- WG : WriteGen_ADC
302 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
303 --
304 --enableADC <= gpio(0);
305 --Bias_Fails <= '0';
306 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
307 --
308 --
309 -- MemIn1 : APB_FIFO
310 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
311 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
312
313 --- FFT -------------------------------------------------------------
314
315 MemIn : APB_FIFO
316 generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
317 port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
318 -- MemIn : APB_FIFO
319 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
320 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others =>'1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
321 --
322 test(0) <= gpio(1);
323 Start <= '0';
324 rstnFFT <= gpio(0);
325 --
326 DRIVE : FFTamont
327 generic map(Data_sz => 16,NbData => 256)
328 port map(clkm,rstn,FFT_Load,FifoIN_Empty(0),FifoIN_Data,Drive_Write,Drive_Read(0),Drive_DataRE,Drive_DataIM);
329 -- DRIVE : Driver_FFT
330 -- generic map(Data_sz => 16)
331 -- port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Full,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
332 --
333 FFT : CoreFFT
334 generic map(
335 LOGPTS => gLOGPTS,
336 LOGLOGPTS => gLOGLOGPTS,
337 WSIZE => gWSIZE,
338 TWIDTH => gTWIDTH,
339 DWIDTH => gDWIDTH,
340 TDWIDTH => gTDWIDTH,
341 RND_MODE => gRND_MODE,
342 SCALE_MODE => gSCALE_MODE,
343 PTS => gPTS,
344 HALFPTS => gHALFPTS,
345 inBuf_RWDLY => gInBuf_RWDLY)
346 port map(clkm,start,rstnFFT,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
347 --
348 -- LINK : Linker_FFT
349 -- generic map(Data_sz => 16)
350 -- port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);--FifoOUT_Full/FifoINT_Full
351 LINK : FFTaval
352 generic map(Data_sz => 16,NbData => 256)
353 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full(0),FFT_DataRE,FFT_DataIM,Link_Read,Link_Write(0),Link_ReUse(0),Link_Data);
354 --
355 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
356 --
357 MemOut : APB_FIFO
358 generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
359 port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
360
361
362 --TEST(0) <= FifoOUT_Full(0);
363 --TEST(1) <= Link_Write(0);
364
365 -- MemInt : lppFIFOx5
366 -- generic map(Data_sz => 16, Enable_ReUse => '1')
367 -- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
368 --
369 --Matrix_WriteV(0) <= not Matrix_Write;
370 --FifoOUT_FullV <= FifoOUT_Full(0);
371 --
372 ---- MemInt : lppFIFOxN
373 ---- generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
374 ---- port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
375 --
376 -- TopSM : TopMatrix_PDR
377 -- generic map (Input_SZ => 16)
378 -- port map (clkm,rstn,FifoINT_Data,FifoINT_Full,Matrix_Read,Matrix_Write,TopSM_Data1,TopSM_Data2,TopSM_Start,TopSM_Read,TopSM_Statu);
379 --
380 -- SM : SpectralMatrix
381 -- generic map (Input_SZ => 16, Result_SZ => 32)
382 -- port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
383
384
385 --***************************************TEST DEMI-FIFO********************************************************************************
386 -- MemIn : APB_FIFO
387 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
388 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
389 --
390 -- Pont : Bridge
391 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
392 --
393 -- MemOut : APB_FIFO
394 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
395 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
396 --*************************************************************************************************************************************
397
398
399
400
401
402
403
404
405
406
407
408 --Dma_acq <= '1';
409 --
410 -- DISP : Dispatch
411 -- generic map(Data_SZ => 32)
412 -- port map(clkm,reset,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError);
413 --
414 ----- FIFO -------------------------------------------------------------
415 --
416 -- MemOut : APB_FIFO
417 -- generic map (pindex => 15, paddr => 15, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
418 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(15));
419 --
420 Memtest : APB_FIFO
421 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
422 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
423
424 --- UART -------------------------------------------------------------
425
426 COM0 : APB_UART
427 generic map (pindex => 4, paddr => 4)
428 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
429
430 --- DELAY ------------------------------------------------------------
431
432 -- Delay0 : APB_Delay
433 -- generic map (pindex => 4, paddr => 4)
434 -- port map (clkm,rstn,apbi,apbo(4));
435
436 --- IIR Filter -------------------------------------------------------
437 --Test(0) <= sample_clk_out;
438 --
439 --
440 -- IIR1: APB_IIR_Filter
441 -- generic map(
442 -- tech => CFG_MEMTECH,
443 -- pindex => 8,
444 -- paddr => 8,
445 -- Sample_SZ => Sample_SZ,
446 -- ChanelsCount => ChanelsCount,
447 -- Coef_SZ => Coef_SZ,
448 -- CoefCntPerCel => CoefCntPerCel,
449 -- Cels_count => Cels_count,
450 -- virgPos => virgPos
451 -- )
452 -- port map(
453 -- rst => rstn,
454 -- clk => clkm,
455 -- apbi => apbi,
456 -- apbo => apbo(8),
457 -- sample_clk_out => sample_clk_out,
458 -- GOtest => Test(1),
459 -- CoefsInitVal => (others => '1')
460 -- );
461 ----------------------------------------------------------------------
462
463 ----------------------------------------------------------------------
464 --- Reset and Clock generation -------------------------------------
465 ----------------------------------------------------------------------
466
467 vcc <= (others => '1'); gnd <= (others => '0');
468 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
469
470 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
471
472
473 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
474
475 clkgen0 : clkgen -- clock generator
476 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
477 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
478 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
479
480 ramclk <= clkm;
481 process(lclk2x)
482 begin
483 if lclk2x'event and lclk2x = '1' then
484 lclk <= not lclk;
485 end if;
486 end process;
487
488 ----------------------------------------------------------------------
489 --- LEON3 processor / DSU / IRQ ------------------------------------
490 ----------------------------------------------------------------------
491
492 l3 : if CFG_LEON3 = 1 generate
493 cpu : for i in 0 to CFG_NCPU-1 generate
494 u0 : leon3s -- LEON3 processor
495 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
496 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
497 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
498 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
499 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
500 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
501 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
502 irqi(i), irqo(i), dbgi(i), dbgo(i));
503 end generate;
504 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
505
506 dsugen : if CFG_DSU = 1 generate
507 dsu0 : dsu3 -- LEON3 Debug Support Unit
508 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
509 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
510 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
511 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
512 dsui.enable <= '1';
513 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
514 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
515 end generate;
516 end generate;
517
518 nodsu : if CFG_DSU = 0 generate
519 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
520 end generate;
521
522 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
523 irqctrl0 : irqmp -- interrupt controller
524 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
525 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
526 end generate;
527 irq3 : if CFG_IRQ3_ENABLE = 0 generate
528 x : for i in 0 to CFG_NCPU-1 generate
529 irqi(i).irl <= "0000";
530 end generate;
531 apbo(2) <= apb_none;
532 end generate;
533
534 ----------------------------------------------------------------------
535 --- Memory controllers ---------------------------------------------
536 ----------------------------------------------------------------------
537
538 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
539 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
540
541 memi.brdyn <= '1'; memi.bexcn <= '1';
542 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
543
544 bdr : for i in 0 to 3 generate
545 data_pad : iopadv generic map (tech => padtech, width => 8)
546 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
547 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
548 end generate;
549
550
551 addr_pad : outpadv generic map (width => 19, tech => padtech)
552 port map (address, memo.address(20 downto 2));
553
554
555 SSRAM_0:entity ssram_plugin
556 generic map (tech => padtech)
557 port map
558 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
559
560 ----------------------------------------------------------------------
561 --- AHB CONTROLLER -------------------------------------------------
562 ----------------------------------------------------------------------
563
564 ahb0 : ahbctrl -- AHB arbiter/multiplexer
565 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
566 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
567 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
568 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
569
570 ----------------------------------------------------------------------
571 --- AHB UART -------------------------------------------------------
572 ----------------------------------------------------------------------
573
574 dcomgen : if CFG_AHB_UART = 1 generate
575 dcom0: ahbuart -- Debug UART
576 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
577 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
578 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
579 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
580 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
581 end generate;
582 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
583
584 ----------------------------------------------------------------------
585 --- APB Bridge -----------------------------------------------------
586 ----------------------------------------------------------------------
587
588 apb0 : apbctrl -- AHB/APB bridge
589 generic map (hindex => 1, haddr => CFG_APBADDR)
590 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
591
592 ----------------------------------------------------------------------
593 --- GPT Timer ------------------------------------------------------
594 ----------------------------------------------------------------------
595
596 gpt : if CFG_GPT_ENABLE /= 0 generate
597 timer0 : gptimer -- timer unit
598 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
599 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
600 nbits => CFG_GPT_TW)
601 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
602 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
603 -- led(4) <= gpto.wdog;
604 end generate;
605 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
606
607
608 ----------------------------------------------------------------------
609 --- APB UART -------------------------------------------------------
610 ----------------------------------------------------------------------
611
612 ua1 : if CFG_UART1_ENABLE /= 0 generate
613 uart1 : apbuart -- UART 1
614 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
615 fifosize => CFG_UART1_FIFO)
616 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
617 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
618 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
619 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
620 end generate;
621 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
622
623 ----------------------------------------------------------------------
624 --- GPIO -----------------------------------------------------------
625 ----------------------------------------------------------------------
626
627 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
628 grgpio0: grgpio
629 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
630 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
631
632 pio_pads : for i in 0 to 6 generate
633 pio_pad : iopad generic map (tech => padtech)
634 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
635 end generate;
636 end generate;
637
638
639 end Behavioral; No newline at end of file
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@@ -1,95 +1,100
1 -- FFTamont.vhd
1 -- FFTamont.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5
5
6 entity FFTamont is
6 entity FFTamont is
7 generic(
7 generic(
8 Data_sz : integer range 1 to 32 := 16
8 Data_sz : integer range 1 to 32 := 16;
9 NbData : integer range 1 to 512 := 256
9 );
10 );
10 port(
11 port(
11 clk : in std_logic;
12 clk : in std_logic;
12 rstn : in std_logic;
13 rstn : in std_logic;
13 Load : in std_logic;
14 Load : in std_logic;
14 Empty : in std_logic;
15 Empty : in std_logic;
15 Full : in std_logic;
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
17 Valid : out std_logic;
17 Valid : out std_logic;
18 Read : out std_logic;
18 Read : out std_logic;
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
21 );
21 );
22 end entity;
22 end entity;
23
23
24
24
25 architecture ar_FFTamont of FFTamont is
25 architecture ar_FFTamont of FFTamont is
26
26
27 type etat is (eX,e0,e1,e2);
27 type etat is (eX,e0,e1,e2);
28 signal ect : etat;
28 signal ect : etat;
29
29
30 signal DataCount : integer;
30
31
31 begin
32 begin
32
33
33 process(clk,rstn)
34 process(clk,rstn)
34 begin
35 begin
35 if(rstn='0')then
36 if(rstn='0')then
36 ect <= eX;
37 ect <= e0;
37 Read <= '1';
38 Read <= '1';
38 Valid <= '0';
39 Valid <= '0';
39 Data_re <= (others => '0');
40 Data_re <= (others => '0');
40 Data_im <= (others => '0');
41 Data_im <= (others => '0');
42 DataCount <= 0;
41
43
42 elsif(clk'event and clk='1')then
44 elsif(clk'event and clk='1')then
43
45
44 case ect is
46 case ect is
45
47
46 when eX =>
48 when e0 =>
47 if(Full='1')then
49 if(Load='1' and Empty='0')then
48 ect <= e0;
50 Read <= '0';
51 ect <= eX;
49 end if;
52 end if;
50
53
51 when e0 =>
54 when eX =>
52 Valid <= '0';
55 ect <= e1;
53 if(Load='1' and Empty='0')then
54 Read <= '0';
55 ect <= e1;
56 elsif(Empty='1')then
57 ect <= eX;
58 end if;
59
56
60 when e1 =>
57 when e1 =>
61 Read <= '1';
62 Data_re <= DATA;
58 Data_re <= DATA;
63 Data_im <= (others => '0');
59 Data_im <= (others => '0');
64 Valid <= '1';
60 Valid <= '1';
65 ect <= e0;
61 if(DataCount=NbData-2)then
62 Read <= '1';
63 DataCount <= DataCount + 1;
64 elsif(DataCount=NbData)then
65 Valid <= '0';
66 DataCount <= 0;
67 ect <= e0;
68 else
69 DataCount <= DataCount + 1;
70 end if;
66
71
67 when e2 =>
72 when others =>
68 null;
73 null;
69
74
70 end case;
75 end case;
71 end if;
76 end if;
72 end process;
77 end process;
73
78
74 end architecture;
79 end architecture;
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Show file before | Show file after | Hide comments
@@ -1,90 +1,90
1 -- FFTaval.vhd
1 -- FFTaval.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5
5
6 entity FFTaval is
6 entity FFTaval is
7 generic(
7 generic(
8 Data_sz : integer range 1 to 32 := 8
8 Data_sz : integer range 1 to 32 := 8;
9 NbData : integer range 1 to 512 := 256
9 );
10 );
10 port(
11 port(
11 clk : in std_logic;
12 clk : in std_logic;
12 rstn : in std_logic;
13 rstn : in std_logic;
13 Ready : in std_logic;
14 Ready : in std_logic;
14 Valid : in std_logic;
15 Valid : in std_logic;
15 Full : in std_logic;
16 Full : in std_logic;
16 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Read : out std_logic;
19 Read : out std_logic;
19 Write : out std_logic;
20 Write : out std_logic;
20 ReUse : out std_logic;
21 ReUse : out std_logic;
21 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 );
23 );
23 end entity;
24 end entity;
24
25
25
26
26 architecture ar_FFTaval of FFTaval is
27 architecture ar_FFTaval of FFTaval is
27
28
28 type etat is (eX,e0,e1,e2,e3);
29 type etat is (eX,e0,e1,e2,e3);
29 signal ect : etat;
30 signal ect : etat;
30
31
31 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32
33
33 signal sReady : std_logic;
34 signal sRead : std_logic;
35 signal DataCount : integer;
34
36
35 begin
37 begin
36
38
37 process(clk,rstn)
39 process(clk,rstn)
38 begin
40 begin
39 if(rstn='0')then
41 if(rstn='0')then
40 ect <= e0;
42 ect <= e0;
41 Read <= '0';
43 sRead <= '0';
42 Write <= '1';
44 Write <= '1';
43 Reuse <= '0';
45 Reuse <= '0';
46 DataCount <= 0;
44
47
45 elsif(clk'event and clk='1')then
48 elsif(clk'event and clk='1')then
46 sReady <= Ready;
49
50 if(Ready='1')then
51 sRead <= not sRead;
52 else
53 sRead <= '0';
54 end if;
47
55
56 if(DataCount=NbData or Ready='0')then
57 DataCount <= 0;
58 elsif(Valid='1')then
59 DataCount <= DataCount+1;
60 end if;
61
62
48 case ect is
63 case ect is
49
64
50 when e0 =>
65 when e0 =>
51 Write <= '1';
66 Write <= '1';
52 if(sReady='0' and Ready='1' and full='0')then
53 Read <= '1';
54 ect <= e1;
55 end if;
56
57 when e1 =>
58 Read <= '0';
59 if(Valid='1' and full='0')then
67 if(Valid='1' and full='0')then
60 DataTmp <= Data_im;
68 DataTmp <= Data_im;
61 DATA <= Data_re;
69 DATA <= Data_re;
62 Write <= '0';
70 Write <= '0';
63 ect <= e2;
71 ect <= e1;
64 elsif(full='1')then
72 elsif(full='1')then
65 ReUse <= '1';
73 ReUse <= '1';
66 ect <= e0;
67 end if;
74 end if;
68
75
69 when e2 =>
76 when e1 =>
70 DATA <= DataTmp;
77 DATA <= DataTmp;
71 ect <= e3;
78 ect <= e0;
72
73 when e3 =>
74 Write <= '1';
75 if(Ready='1' and full='0')then
76 Read <= '1';
77 ect <= e1;
78 end if;
79
79
80 when eX =>
80 when others =>
81 null;
81 null;
82
82
83 end case;
83 end case;
84 end if;
84 end if;
85 end process;
85 end process;
86
86
87
87 Read <= sRead;
88
88
89 end architecture;
89 end architecture;
90
90
Show file before | Show file after | Hide comments
@@ -1,242 +1,243
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
32 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
33
33
34 package lpp_fft is
34 package lpp_fft is
35
35
36 component APB_FFT is
36 component APB_FFT is
37 generic (
37 generic (
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Data_sz : integer := 16
43 Data_sz : integer := 16
44 );
44 );
45 port (
45 port (
46 clk : in std_logic;
46 clk : in std_logic;
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type;
48 apbi : in apb_slv_in_type;
49 apbo : out apb_slv_out_type
49 apbo : out apb_slv_out_type
50 );
50 );
51 end component;
51 end component;
52
52
53
53
54 component APB_FFT_half is
54 component APB_FFT_half is
55 generic (
55 generic (
56 pindex : integer := 0;
56 pindex : integer := 0;
57 paddr : integer := 0;
57 paddr : integer := 0;
58 pmask : integer := 16#fff#;
58 pmask : integer := 16#fff#;
59 pirq : integer := 0;
59 pirq : integer := 0;
60 abits : integer := 8;
60 abits : integer := 8;
61 Data_sz : integer := 16
61 Data_sz : integer := 16
62 );
62 );
63 port (
63 port (
64 clk : in std_logic; --! Horloge du composant
64 clk : in std_logic; --! Horloge du composant
65 rst : in std_logic; --! Reset general du composant
65 rst : in std_logic; --! Reset general du composant
66 Ren : in std_logic;
66 Ren : in std_logic;
67 ready : out std_logic;
67 ready : out std_logic;
68 valid : out std_logic;
68 valid : out std_logic;
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 OUTfill : out std_logic;
71 OUTfill : out std_logic;
72 OUTwrite : out std_logic;
72 OUTwrite : out std_logic;
73 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
73 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 );
75 );
76 end component;
76 end component;
77
77
78
78
79 component Flag_Extremum is
79 component Flag_Extremum is
80 port(
80 port(
81 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
81 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
82 load : in std_logic; --! Signal en provenance de CoreFFT
82 load : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
86 );
86 );
87 end component;
87 end component;
88
88
89
89
90 component Linker_FFT is
90 component Linker_FFT is
91 generic(
91 generic(
92 Data_sz : integer range 1 to 32 := 16
92 Data_sz : integer range 1 to 32 := 16
93 );
93 );
94 port(
94 port(
95 clk : in std_logic;
95 clk : in std_logic;
96 rstn : in std_logic;
96 rstn : in std_logic;
97 Ready : in std_logic;
97 Ready : in std_logic;
98 Valid : in std_logic;
98 Valid : in std_logic;
99 Full : in std_logic_vector(4 downto 0);
99 Full : in std_logic_vector(4 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 Read : out std_logic;
102 Read : out std_logic;
103 Write : out std_logic_vector(4 downto 0);
103 Write : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 );
106 );
107 end component;
107 end component;
108
108
109
109
110 component Driver_FFT is
110 component Driver_FFT is
111 generic(
111 generic(
112 Data_sz : integer range 1 to 32 := 16
112 Data_sz : integer range 1 to 32 := 16
113 );
113 );
114 port(
114 port(
115 clk : in std_logic;
115 clk : in std_logic;
116 rstn : in std_logic;
116 rstn : in std_logic;
117 Load : in std_logic;
117 Load : in std_logic;
118 Empty : in std_logic_vector(4 downto 0);
118 Empty : in std_logic_vector(4 downto 0);
119 Full : in std_logic_vector(4 downto 0);
119 Full : in std_logic_vector(4 downto 0);
120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
121 Valid : out std_logic;
121 Valid : out std_logic;
122 Read : out std_logic_vector(4 downto 0);
122 Read : out std_logic_vector(4 downto 0);
123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
125 );
125 );
126 end component;
126 end component;
127
127
128 component FFTamont is
128 component FFTamont is
129 generic(
129 generic(
130 Data_sz : integer range 1 to 32 := 16
130 Data_sz : integer range 1 to 32 := 16;
131 NbData : integer range 1 to 512 := 256
131 );
132 );
132 port(
133 port(
133 clk : in std_logic;
134 clk : in std_logic;
134 rstn : in std_logic;
135 rstn : in std_logic;
135 Load : in std_logic;
136 Load : in std_logic;
136 Empty : in std_logic;
137 Empty : in std_logic;
137 Full : in std_logic;
138 DATA : in std_logic_vector(Data_sz-1 downto 0);
138 DATA : in std_logic_vector(Data_sz-1 downto 0);
139 Valid : out std_logic;
139 Valid : out std_logic;
140 Read : out std_logic;
140 Read : out std_logic;
141 Data_re : out std_logic_vector(Data_sz-1 downto 0);
141 Data_re : out std_logic_vector(Data_sz-1 downto 0);
142 Data_im : out std_logic_vector(Data_sz-1 downto 0)
142 Data_im : out std_logic_vector(Data_sz-1 downto 0)
143 );
143 );
144 end component;
144 end component;
145
145
146 component FFTaval is
146 component FFTaval is
147 generic(
147 generic(
148 Data_sz : integer range 1 to 32 := 8
148 Data_sz : integer range 1 to 32 := 8;
149 NbData : integer range 1 to 512 := 256
149 );
150 );
150 port(
151 port(
151 clk : in std_logic;
152 clk : in std_logic;
152 rstn : in std_logic;
153 rstn : in std_logic;
153 Ready : in std_logic;
154 Ready : in std_logic;
154 Valid : in std_logic;
155 Valid : in std_logic;
155 Full : in std_logic;
156 Full : in std_logic;
156 Data_re : in std_logic_vector(Data_sz-1 downto 0);
157 Data_re : in std_logic_vector(Data_sz-1 downto 0);
157 Data_im : in std_logic_vector(Data_sz-1 downto 0);
158 Data_im : in std_logic_vector(Data_sz-1 downto 0);
158 Read : out std_logic;
159 Read : out std_logic;
159 Write : out std_logic;
160 Write : out std_logic;
160 ReUse : out std_logic;
161 ReUse : out std_logic;
161 DATA : out std_logic_vector(Data_sz-1 downto 0)
162 DATA : out std_logic_vector(Data_sz-1 downto 0)
162 );
163 );
163 end component;
164 end component;
164 --==============================================================|
165 --==============================================================|
165 --================== IP VHDL de la FFT actel ===================|
166 --================== IP VHDL de la FFT actel ===================|
166 --================ non partagοΏ½ dans la VHD_Lib =================|
167 --================ non partagοΏ½ dans la VHD_Lib =================|
167 --==============================================================|
168 --==============================================================|
168
169
169 component CoreFFT IS
170 component CoreFFT IS
170 GENERIC (
171 GENERIC (
171 LOGPTS : integer := gLOGPTS;
172 LOGPTS : integer := gLOGPTS;
172 LOGLOGPTS : integer := gLOGLOGPTS;
173 LOGLOGPTS : integer := gLOGLOGPTS;
173 WSIZE : integer := gWSIZE;
174 WSIZE : integer := gWSIZE;
174 TWIDTH : integer := gTWIDTH;
175 TWIDTH : integer := gTWIDTH;
175 DWIDTH : integer := gDWIDTH;
176 DWIDTH : integer := gDWIDTH;
176 TDWIDTH : integer := gTDWIDTH;
177 TDWIDTH : integer := gTDWIDTH;
177 RND_MODE : integer := gRND_MODE;
178 RND_MODE : integer := gRND_MODE;
178 SCALE_MODE : integer := gSCALE_MODE;
179 SCALE_MODE : integer := gSCALE_MODE;
179 PTS : integer := gPTS;
180 PTS : integer := gPTS;
180 HALFPTS : integer := gHALFPTS;
181 HALFPTS : integer := gHALFPTS;
181 inBuf_RWDLY : integer := gInBuf_RWDLY );
182 inBuf_RWDLY : integer := gInBuf_RWDLY );
182 PORT (
183 PORT (
183 clk,ifiStart,ifiNreset : IN std_logic;
184 clk,ifiStart,ifiNreset : IN std_logic;
184 ifiD_valid, ifiRead_y : IN std_logic;
185 ifiD_valid, ifiRead_y : IN std_logic;
185 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
186 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
186 ifoLoad, ifoPong : OUT std_logic;
187 ifoLoad, ifoPong : OUT std_logic;
187 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
188 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
188 ifoY_valid, ifoY_rdy : OUT std_logic);
189 ifoY_valid, ifoY_rdy : OUT std_logic);
189 END component;
190 END component;
190
191
191
192
192 component actar is
193 component actar is
193 port( DataA : in std_logic_vector(15 downto 0); DataB : in
194 port( DataA : in std_logic_vector(15 downto 0); DataB : in
194 std_logic_vector(15 downto 0); Mult : out
195 std_logic_vector(15 downto 0); Mult : out
195 std_logic_vector(31 downto 0);Clock : in std_logic) ;
196 std_logic_vector(31 downto 0);Clock : in std_logic) ;
196 end component;
197 end component;
197
198
198 component actram is
199 component actram is
199 port( DI : in std_logic_vector(31 downto 0); DO : out
200 port( DI : in std_logic_vector(31 downto 0); DO : out
200 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
201 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
201 WADDR : in std_logic_vector(6 downto 0); RADDR : in
202 WADDR : in std_logic_vector(6 downto 0); RADDR : in
202 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
203 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
203 std_logic) ;
204 std_logic) ;
204 end component;
205 end component;
205
206
206 component switch IS
207 component switch IS
207 GENERIC ( DWIDTH : integer := 32 );
208 GENERIC ( DWIDTH : integer := 32 );
208 PORT (
209 PORT (
209 clk, sel, validIn : IN std_logic;
210 clk, sel, validIn : IN std_logic;
210 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
211 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
211 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
212 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
212 validOut : OUT std_logic);
213 validOut : OUT std_logic);
213 END component;
214 END component;
214
215
215 component twid_rA IS
216 component twid_rA IS
216 GENERIC (LOGPTS : integer := 8;
217 GENERIC (LOGPTS : integer := 8;
217 LOGLOGPTS : integer := 3 );
218 LOGLOGPTS : integer := 3 );
218 PORT (clk : IN std_logic;
219 PORT (clk : IN std_logic;
219 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
220 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
220 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
221 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
221 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
222 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
222 END component;
223 END component;
223
224
224 component counter IS
225 component counter IS
225 GENERIC (
226 GENERIC (
226 WIDTH : integer := 7;
227 WIDTH : integer := 7;
227 TERMCOUNT : integer := 127 );
228 TERMCOUNT : integer := 127 );
228 PORT (
229 PORT (
229 clk, nGrst, rst, cntEn : IN std_logic;
230 clk, nGrst, rst, cntEn : IN std_logic;
230 tc : OUT std_logic;
231 tc : OUT std_logic;
231 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
232 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
232 END component;
233 END component;
233
234
234
235
235 component twiddle IS
236 component twiddle IS
236 PORT (
237 PORT (
237 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
238 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
238 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
239 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
239 END component;
240 END component;
240
241
241
242
242 end; No newline at end of file
243 end;
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@@ -1,7 +1,7
1 fifo_test_dma.vhd
2 fifo_latency_correction.vhd
1 fifo_latency_correction.vhd
3 lpp_dma_send_1word.vhd
2 lpp_dma.vhd
3 lpp_dma_apbreg.vhd
4 lpp_dma_fsm.vhd
5 lpp_dma_pkg.vhd
4 lpp_dma_send_16word.vhd
6 lpp_dma_send_16word.vhd
5 lpp_dma_apbreg.vhd
7 lpp_dma_send_1word.vhd
6 lpp_dma.vhd
7 lpp_dma_pkg.vhd
Show file before | Show file after | Hide comments
@@ -1,78 +1,53
1 -- Bridge.vhd
1 -- Bridge.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5
5
6 entity Bridge is
6 entity Bridge is
7 generic(
7 port(
8 Data_sz : integer range 1 to 32 := 16
8 clk : in std_logic;
9 );
9 raz : in std_logic;
10 port(
10 EmptyUp : in std_logic;
11 clk : in std_logic;
11 FullDwn : in std_logic;
12 raz : in std_logic;
12 WriteDwn : out std_logic;
13 Start : in std_logic;
13 ReadUp : out std_logic
14 FullUp : in std_logic;
14 );
15 EmptyUp : in std_logic;
16 FullDown : in std_logic;
17 EmptyDown : in std_logic;
18 Write : out std_logic;
19 Read : out std_logic
20 );
21 end entity;
15 end entity;
22
16
23
17
24 architecture ar_Bridge of Bridge is
18 architecture ar_Bridge of Bridge is
25
19
26 type etat is (eX,e1,e2,e3);
20 type etat is (e0,e1);
27 signal ect : etat;
21 signal ect : etat;
28
22
29 signal i : integer;
30
31 begin
23 begin
32
24
33 process(clk,raz)
25 process(clk,raz)
34 begin
26 begin
35 if(raz='0')then
27 if(raz='0')then
36 Write <= '1';
28 WriteDwn <= '1';
37 Read <= '1';
29 ReadUp <= '1';
38 i <= 0;
30 ect <= e0;
39 ect <= eX;
31
40
41 elsif(clk'event and clk='1')then
32 elsif(clk'event and clk='1')then
42
33
43 case ect is
34 case ect is
44
35
45 when eX =>
36 when e0 =>
46 if(FullUp='1' and EmptyDown='1' and start='0')then
37 WriteDwn <= '1';
47 ect <= e1;
38 if(EmptyUp='0' and FullDwn='0')then
48 end if;
39 ReadUp <= '0';
40 ect <= e1;
41 end if;
49
42
50 when e1 =>
43 when e1 =>
51 Write <= '1';
44 ReadUp <= '1';
52 if(EmptyUp='0')then
45 WriteDwn <= '0';
53 Read <= '0';
46 ect <= e0;
54 ect <= e2;
47
55 else
48 end case;
56 Read <= '1';
49
57 ect <= e3;
58 end if;
59
60 when e2 =>
61 Read <= '1';
62 if(FullDown='0')then
63 Write <= '0';
64 ect <= e1;
65 else
66 Write <= '1';
67 ect <= e3;
68 end if;
69
70 when e3 =>
71 null;
72
73 end case;
74 end if;
50 end if;
75 end process;
51 end process;
76
52
77
78 end architecture; No newline at end of file
53 end architecture;
Show file before | Show file after | Hide comments
@@ -1,182 +1,176
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 library gaisler;
29 library gaisler;
30 use gaisler.misc.all;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
31 use gaisler.memctrl.all;
32 library techmap;
32 library techmap;
33 use techmap.gencomp.all;
33 use techmap.gencomp.all;
34
34
35 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
35 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36
36
37 package lpp_memory is
37 package lpp_memory is
38
38
39 component APB_FIFO is
39 component APB_FIFO is
40 generic (
40 generic (
41 tech : integer := apa3;
41 tech : integer := apa3;
42 pindex : integer := 0;
42 pindex : integer := 0;
43 paddr : integer := 0;
43 paddr : integer := 0;
44 pmask : integer := 16#fff#;
44 pmask : integer := 16#fff#;
45 pirq : integer := 0;
45 pirq : integer := 0;
46 abits : integer := 8;
46 abits : integer := 8;
47 FifoCnt : integer := 2;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
50 Enable_ReUse : std_logic := '0';
51 R : integer := 1;
51 R : integer := 1;
52 W : integer := 1
52 W : integer := 1
53 );
53 );
54 port (
54 port (
55 clk : in std_logic; --! Horloge du composant
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
57 rclk : in std_logic;
58 wclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
68 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
70 );
71 end component;
71 end component;
72
72
73
73
74 component lpp_fifo is
74 component lpp_fifo is
75 generic(
75 generic(
76 tech : integer := 0;
76 tech : integer := 0;
77 Enable_ReUse : std_logic := '0';
77 Enable_ReUse : std_logic := '0';
78 DataSz : integer range 1 to 32 := 8;
78 DataSz : integer range 1 to 32 := 8;
79 abits : integer range 2 to 12 := 8
79 abits : integer range 2 to 12 := 8
80 );
80 );
81 port(
81 port(
82 rstn : in std_logic;
82 rstn : in std_logic;
83 ReUse : in std_logic; --27/01/12
83 ReUse : in std_logic; --27/01/12
84 rclk : in std_logic;
84 rclk : in std_logic;
85 ren : in std_logic;
85 ren : in std_logic;
86 rdata : out std_logic_vector(DataSz-1 downto 0);
86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 empty : out std_logic;
87 empty : out std_logic;
88 raddr : out std_logic_vector(abits-1 downto 0);
88 raddr : out std_logic_vector(abits-1 downto 0);
89 wclk : in std_logic;
89 wclk : in std_logic;
90 wen : in std_logic;
90 wen : in std_logic;
91 wdata : in std_logic_vector(DataSz-1 downto 0);
91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 full : out std_logic;
92 full : out std_logic;
93 waddr : out std_logic_vector(abits-1 downto 0)
93 waddr : out std_logic_vector(abits-1 downto 0)
94 );
94 );
95 end component;
95 end component;
96
96
97
97
98 component lppFIFOxN is
98 component lppFIFOxN is
99 generic(
99 generic(
100 tech : integer := 0;
100 tech : integer := 0;
101 Data_sz : integer range 1 to 32 := 8;
101 Data_sz : integer range 1 to 32 := 8;
102 FifoCnt : integer := 1;
102 FifoCnt : integer := 1;
103 Enable_ReUse : std_logic := '0'
103 Enable_ReUse : std_logic := '0'
104 );
104 );
105 port(
105 port(
106 rst : in std_logic;
106 rst : in std_logic;
107 wclk : in std_logic;
107 wclk : in std_logic;
108 rclk : in std_logic;
108 rclk : in std_logic;
109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
110 wen : in std_logic_vector(FifoCnt-1 downto 0);
110 wen : in std_logic_vector(FifoCnt-1 downto 0);
111 ren : in std_logic_vector(FifoCnt-1 downto 0);
111 ren : in std_logic_vector(FifoCnt-1 downto 0);
112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 full : out std_logic_vector(FifoCnt-1 downto 0);
114 full : out std_logic_vector(FifoCnt-1 downto 0);
115 empty : out std_logic_vector(FifoCnt-1 downto 0)
115 empty : out std_logic_vector(FifoCnt-1 downto 0)
116 );
116 );
117 end component;
117 end component;
118
118
119 component lppFIFOx5 is
119 component lppFIFOx5 is
120 generic(
120 generic(
121 tech : integer := 0;
121 tech : integer := 0;
122 Data_sz : integer range 1 to 32 := 16;
122 Data_sz : integer range 1 to 32 := 16;
123 Addr_sz : integer range 2 to 12 := 8;
123 Addr_sz : integer range 2 to 12 := 8;
124 Enable_ReUse : std_logic := '0'
124 Enable_ReUse : std_logic := '0'
125 );
125 );
126 port(
126 port(
127 rst : in std_logic;
127 rst : in std_logic;
128 wclk : in std_logic;
128 wclk : in std_logic;
129 rclk : in std_logic;
129 rclk : in std_logic;
130 ReUse : in std_logic_vector(4 downto 0);
130 ReUse : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
135 full : out std_logic_vector(4 downto 0);
135 full : out std_logic_vector(4 downto 0);
136 empty : out std_logic_vector(4 downto 0)
136 empty : out std_logic_vector(4 downto 0)
137 );
137 );
138 end component;
138 end component;
139
139
140 component Bridge is
140 component Bridge is
141 generic(
141 port(
142 Data_sz : integer range 1 to 32 := 16
142 clk : in std_logic;
143 );
143 raz : in std_logic;
144 port(
144 EmptyUp : in std_logic;
145 clk : in std_logic;
145 FullDwn : in std_logic;
146 raz : in std_logic;
146 WriteDwn : out std_logic;
147 Start : in std_logic;
147 ReadUp : out std_logic
148 FullUp : in std_logic;
148 );
149 EmptyUp : in std_logic;
150 FullDown : in std_logic;
151 EmptyDown : in std_logic;
152 Write : out std_logic;
153 Read : out std_logic
154 );
155 end component;
149 end component;
156
150
157 component ssram_plugin is
151 component ssram_plugin is
158 generic (tech : integer := 0);
152 generic (tech : integer := 0);
159 port
153 port
160 (
154 (
161 clk : in std_logic;
155 clk : in std_logic;
162 mem_ctrlr_o : in memory_out_type;
156 mem_ctrlr_o : in memory_out_type;
163 SSRAM_CLK : out std_logic;
157 SSRAM_CLK : out std_logic;
164 nBWa : out std_logic;
158 nBWa : out std_logic;
165 nBWb : out std_logic;
159 nBWb : out std_logic;
166 nBWc : out std_logic;
160 nBWc : out std_logic;
167 nBWd : out std_logic;
161 nBWd : out std_logic;
168 nBWE : out std_logic;
162 nBWE : out std_logic;
169 nADSC : out std_logic;
163 nADSC : out std_logic;
170 nADSP : out std_logic;
164 nADSP : out std_logic;
171 nADV : out std_logic;
165 nADV : out std_logic;
172 nGW : out std_logic;
166 nGW : out std_logic;
173 nCE1 : out std_logic;
167 nCE1 : out std_logic;
174 CE2 : out std_logic;
168 CE2 : out std_logic;
175 nCE3 : out std_logic;
169 nCE3 : out std_logic;
176 nOE : out std_logic;
170 nOE : out std_logic;
177 MODE : out std_logic;
171 MODE : out std_logic;
178 ZZ : out std_logic
172 ZZ : out std_logic
179 );
173 );
180 end component;
174 end component;
181
175
182 end;
176 end;
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