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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 --UPDATE
23 23 -------------------------------------------------------------------------------
24 24 -- 14-03-2013 - Jean-christophe Pellion
25 25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 26 -------------------------------------------------------------------------------
27 27
28 28 LIBRARY ieee;
29 29 USE ieee.std_logic_1164.ALL;
30 30
31 31
32 32
33 33 PACKAGE general_purpose IS
34 34
35 35
36 36
37 37 COMPONENT Clk_divider IS
38 38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 39 TargetFreq_Hz : INTEGER := 50000);
40 40 PORT (clk : IN STD_LOGIC;
41 41 reset : IN STD_LOGIC;
42 42 clk_divided : OUT STD_LOGIC);
43 43 END COMPONENT;
44 44
45 45
46 46 COMPONENT Clk_divider2 IS
47 47 generic(N : integer := 16);
48 48 port(
49 49 clk_in : in std_logic;
50 50 clk_out : out std_logic);
51 51 END COMPONENT;
52 52
53 53 COMPONENT Adder IS
54 54 GENERIC(
55 55 Input_SZ_A : INTEGER := 16;
56 56 Input_SZ_B : INTEGER := 16
57 57
58 58 );
59 59 PORT(
60 60 clk : IN STD_LOGIC;
61 61 reset : IN STD_LOGIC;
62 62 clr : IN STD_LOGIC;
63 63 load : IN STD_LOGIC;
64 64 add : IN STD_LOGIC;
65 65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 68 );
69 69 END COMPONENT;
70 70
71 71 COMPONENT ADDRcntr IS
72 72 PORT(
73 73 clk : IN STD_LOGIC;
74 74 reset : IN STD_LOGIC;
75 75 count : IN STD_LOGIC;
76 76 clr : IN STD_LOGIC;
77 77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 78 );
79 79 END COMPONENT;
80 80
81 81 COMPONENT ALU IS
82 82 GENERIC(
83 83 Arith_en : INTEGER := 1;
84 84 Logic_en : INTEGER := 1;
85 85 Input_SZ_1 : INTEGER := 16;
86 86 Input_SZ_2 : INTEGER := 9
87 87
88 88 );
89 89 PORT(
90 90 clk : IN STD_LOGIC;
91 91 reset : IN STD_LOGIC;
92 92 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
93 93 comp : IN STD_LOGIC_VECTOR(1 downto 0);
94 94 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
95 95 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
96 96 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
97 97 );
98 98 END COMPONENT;
99 99
100 100 ---------------------------------------------------------
101 101 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
102 102 ---------------------------------------------------------
103 103 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
104 104 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
105 105 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
106 106 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
107 107 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
108 108 ---------------------------------------------------------
109 109
110 110 COMPONENT MAC IS
111 111 GENERIC(
112 112 Input_SZ_A : INTEGER := 8;
113 113 Input_SZ_B : INTEGER := 8
114
115 114 );
116 115 PORT(
117 116 clk : IN STD_LOGIC;
118 117 reset : IN STD_LOGIC;
119 118 clr_MAC : IN STD_LOGIC;
120 119 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 120 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 121 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
123 122 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
124 123 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
125 124 );
126 125 END COMPONENT;
127 126
128 127 COMPONENT TwoComplementer is
129 128 generic(
130 129 Input_SZ : integer := 16);
131 130 port(
132 131 clk : in std_logic; --! Horloge du composant
133 132 reset : in std_logic; --! Reset general du composant
134 133 clr : in std_logic; --! Un reset sp�cifique au programme
135 134 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
136 135 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
137 136 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
138 137 );
139 138 end COMPONENT;
140 139
141 140 COMPONENT MAC_CONTROLER IS
142 141 PORT(
143 142 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
144 143 MULT : OUT STD_LOGIC;
145 144 ADD : OUT STD_LOGIC;
146 145 LOAD_ADDER : out std_logic;
147 146 MACMUX_sel : OUT STD_LOGIC;
148 147 MACMUX2_sel : OUT STD_LOGIC
149 148 );
150 149 END COMPONENT;
151 150
152 151 COMPONENT MAC_MUX IS
153 152 GENERIC(
154 153 Input_SZ_A : INTEGER := 16;
155 154 Input_SZ_B : INTEGER := 16
156 155
157 156 );
158 157 PORT(
159 158 sel : IN STD_LOGIC;
160 159 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
161 160 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 161 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
163 162 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
164 163 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
165 164 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
166 165 );
167 166 END COMPONENT;
168 167
169 168
170 169 COMPONENT MAC_MUX2 IS
171 170 GENERIC(Input_SZ : INTEGER := 16);
172 171 PORT(
173 172 sel : IN STD_LOGIC;
174 173 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
175 174 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
176 175 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
177 176 );
178 177 END COMPONENT;
179 178
180 179
181 180 COMPONENT MAC_REG IS
182 181 GENERIC(size : INTEGER := 16);
183 182 PORT(
184 183 reset : IN STD_LOGIC;
185 184 clk : IN STD_LOGIC;
186 185 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
187 186 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
188 187 );
189 188 END COMPONENT;
190 189
191 190
192 191 COMPONENT MUX2 IS
193 192 GENERIC(Input_SZ : INTEGER := 16);
194 193 PORT(
195 194 sel : IN STD_LOGIC;
196 195 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
197 196 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
198 197 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
199 198 );
200 199 END COMPONENT;
201 200
202 201 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
203 202 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
204 203
205 204 COMPONENT MUXN
206 205 GENERIC (
207 206 Input_SZ : INTEGER;
208 207 NbStage : INTEGER);
209 208 PORT (
210 209 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
211 210 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
212 211 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
213 212 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
214 213 END COMPONENT;
215 214
216 215
217 216
218 217 COMPONENT Multiplier IS
219 218 GENERIC(
220 219 Input_SZ_A : INTEGER := 16;
221 220 Input_SZ_B : INTEGER := 16
222 221
223 222 );
224 223 PORT(
225 224 clk : IN STD_LOGIC;
226 225 reset : IN STD_LOGIC;
227 226 mult : IN STD_LOGIC;
228 227 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
229 228 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
230 229 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
231 230 );
232 231 END COMPONENT;
233 232
234 233 COMPONENT REG IS
235 234 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
236 235 PORT(
237 236 reset : IN STD_LOGIC;
238 237 clk : IN STD_LOGIC;
239 238 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
240 239 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
241 240 );
242 241 END COMPONENT;
243 242
244 243
245 244
246 245 COMPONENT RShifter IS
247 246 GENERIC(
248 247 Input_SZ : INTEGER := 16;
249 248 shift_SZ : INTEGER := 4
250 249 );
251 250 PORT(
252 251 clk : IN STD_LOGIC;
253 252 reset : IN STD_LOGIC;
254 253 shift : IN STD_LOGIC;
255 254 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
256 255 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
257 256 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
258 257 );
259 258 END COMPONENT;
260 259
261 260 COMPONENT SYNC_FF
262 261 GENERIC (
263 262 NB_FF_OF_SYNC : INTEGER);
264 263 PORT (
265 264 clk : IN STD_LOGIC;
266 265 rstn : IN STD_LOGIC;
267 266 A : IN STD_LOGIC;
268 267 A_sync : OUT STD_LOGIC);
269 268 END COMPONENT;
270 269
271 270 END;
Show file before | Show file after | Hide comments
@@ -1,17 +1,18
1 1 ADDRcntr.vhd
2 2 ALU.vhd
3 3 Adder.vhd
4 4 Clk_Divider2.vhd
5 5 Clk_divider.vhd
6 6 MAC.vhd
7 7 MAC_CONTROLER.vhd
8 8 MAC_MUX.vhd
9 9 MAC_MUX2.vhd
10 10 MAC_REG.vhd
11 11 MUX2.vhd
12 12 MUXN.vhd
13 13 Multiplier.vhd
14 14 REG.vhd
15 15 SYNC_FF.vhd
16 16 Shifter.vhd
17 17 general_purpose.vhd
18 TwoComplementer.vhd
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