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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 COMPONENT lpp_lfr_apbreg_tb
117 GENERIC (
118 pindex : INTEGER;
119 paddr : INTEGER;
120 pmask : INTEGER);
121 PORT (
122 HCLK : IN STD_ULOGIC;
123 HRESETn : IN STD_ULOGIC;
124 apbi : IN apb_slv_in_type;
125 apbo : OUT apb_slv_out_type;
126 MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
127 MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
128 MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
129 MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
130 MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
131 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
132 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
133 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
134 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
135 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
136 END COMPONENT;
137
138 COMPONENT lpp_lfr_ms_tb
139 GENERIC (
140 Mem_use : INTEGER);
141 PORT (
142 clk : IN STD_LOGIC;
143 rstn : IN STD_LOGIC;
144 MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
145 MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
146 MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
147 MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
148 MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
149 MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
150 MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
151 MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
152 MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC;
153 MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
154 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
155 observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
156 observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
157 END COMPONENT;
158
159
160 SIGNAL clk_50_s : STD_LOGIC := '0';
161 SIGNAL clk_25 : STD_LOGIC := '0';
162 SIGNAL clk_24 : STD_LOGIC := '0';
163 -----------------------------------------------------------------------------
164 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
166 --
167 SIGNAL errorn : STD_LOGIC;
168 -- UART AHB ---------------------------------------------------------------
169 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
170 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
171
172 -- UART APB ---------------------------------------------------------------
173 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
174 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
175 --
176 SIGNAL I00_s : STD_LOGIC;
177
178 -- CONSTANTS
179 CONSTANT CFG_PADTECH : INTEGER := inferred;
180 --
181 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
182 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
183 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
184
185 SIGNAL apbi_ext : apb_slv_in_type;
186 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
187 SIGNAL ahbi_s_ext : ahb_slv_in_type;
188 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
189 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
190 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
191
192 -- Spacewire signals
193 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
194 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
195 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
196 SIGNAL spw_rxtxclk : STD_ULOGIC;
197 SIGNAL spw_rxclkn : STD_ULOGIC;
198 SIGNAL spw_clk : STD_LOGIC;
199 SIGNAL swni : grspw_in_type;
200 SIGNAL swno : grspw_out_type;
201 -- SIGNAL clkmn : STD_ULOGIC;
202 -- SIGNAL txclk : STD_ULOGIC;
203
204 --GPIO
205 SIGNAL gpioi : gpio_in_type;
206 SIGNAL gpioo : gpio_out_type;
207
208 -- AD Converter ADS7886
209 SIGNAL sample : Samples14v(7 DOWNTO 0);
210 SIGNAL sample_s : Samples(7 DOWNTO 0);
211 SIGNAL sample_val : STD_LOGIC;
212 SIGNAL ADC_nCS_sig : STD_LOGIC;
213 SIGNAL ADC_CLK_sig : STD_LOGIC;
214 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
215
216 SIGNAL bias_fail_sw_sig : STD_LOGIC;
217
218 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
220 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
221 -----------------------------------------------------------------------------
222
223
224 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
226 --
227 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
228 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
229 --
230 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
232
233
234 ---------------------------------------------------------------------------
235 --
236 ---------------------------------------------------------------------------
237 SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
239 SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC;
241 SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
242 -----------------------------------------------------------------------------
243 --
244 -----------------------------------------------------------------------------
245 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
246 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
247 SIGNAL MEM_IN_SM_Full_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
248 SIGNAL MEM_IN_SM_Empty_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
249 SIGNAL MEM_IN_SM_locked_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
250
251
252
253
254 BEGIN -- beh
255
256 -----------------------------------------------------------------------------
257 -- CLK
258 -----------------------------------------------------------------------------
259
260 PROCESS(clk_50)
261 BEGIN
262 IF clk_50'EVENT AND clk_50 = '1' THEN
263 clk_50_s <= NOT clk_50_s;
264 END IF;
265 END PROCESS;
266
267 PROCESS(clk_50_s)
268 BEGIN
269 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
270 clk_25 <= NOT clk_25;
271 END IF;
272 END PROCESS;
273
274 PROCESS(clk_49)
275 BEGIN
276 IF clk_49'EVENT AND clk_49 = '1' THEN
277 clk_24 <= NOT clk_24;
278 END IF;
279 END PROCESS;
280
281 -----------------------------------------------------------------------------
282
283 PROCESS (clk_25, reset)
284 BEGIN -- PROCESS
285 IF reset = '0' THEN -- asynchronous reset (active low)
286 LED0 <= '0';
287 LED1 <= '0';
288 LED2 <= '0';
289 --IO1 <= '0';
290 --IO2 <= '1';
291 --IO3 <= '0';
292 --IO4 <= '0';
293 --IO5 <= '0';
294 --IO6 <= '0';
295 --IO7 <= '0';
296 --IO8 <= '0';
297 --IO9 <= '0';
298 --IO10 <= '0';
299 --IO11 <= '0';
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 LED0 <= '0';
302 LED1 <= '1';
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 --IO1 <= '1';
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 --IO3 <= ADC_SDO(0);
307 --IO4 <= ADC_SDO(1);
308 --IO5 <= ADC_SDO(2);
309 --IO6 <= ADC_SDO(3);
310 --IO7 <= ADC_SDO(4);
311 --IO8 <= ADC_SDO(5);
312 --IO9 <= ADC_SDO(6);
313 --IO10 <= ADC_SDO(7);
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 END IF;
316 END PROCESS;
317
318 PROCESS (clk_24, reset)
319 BEGIN -- PROCESS
320 IF reset = '0' THEN -- asynchronous reset (active low)
321 I00_s <= '0';
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 I00_s <= NOT I00_s;
324 END IF;
325 END PROCESS;
326 -- IO0 <= I00_s;
327
328 --UARTs
329 nCTS1 <= '1';
330 nCTS2 <= '1';
331 nDCD2 <= '1';
332
333 --EXT CONNECTOR
334
335 --SPACE WIRE
336
337 leon3_soc_1 : leon3_soc
338 GENERIC MAP (
339 fabtech => apa3e,
340 memtech => apa3e,
341 padtech => inferred,
342 clktech => inferred,
343 disas => 0,
344 dbguart => 0,
345 pclow => 2,
346 clk_freq => 25000,
347 NB_CPU => 1,
348 ENABLE_FPU => 1,
349 FPU_NETLIST => 0,
350 ENABLE_DSU => 1,
351 ENABLE_AHB_UART => 1,
352 ENABLE_APB_UART => 1,
353 ENABLE_IRQMP => 1,
354 ENABLE_GPT => 1,
355 NB_AHB_MASTER => NB_AHB_MASTER,
356 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 NB_APB_SLAVE => NB_APB_SLAVE)
358 PORT MAP (
359 clk => clk_25,
360 reset => reset,
361 errorn => errorn,
362 ahbrxd => TXD1,
363 ahbtxd => RXD1,
364 urxd1 => TXD2,
365 utxd1 => RXD2,
366 address => SRAM_A,
367 data => SRAM_DQ,
368 nSRAM_BE0 => SRAM_nBE(0),
369 nSRAM_BE1 => SRAM_nBE(1),
370 nSRAM_BE2 => SRAM_nBE(2),
371 nSRAM_BE3 => SRAM_nBE(3),
372 nSRAM_WE => SRAM_nWE,
373 nSRAM_CE => SRAM_CE,
374 nSRAM_OE => SRAM_nOE,
375
376 apbi_ext => apbi_ext,
377 apbo_ext => apbo_ext,
378 ahbi_s_ext => ahbi_s_ext,
379 ahbo_s_ext => ahbo_s_ext,
380 ahbi_m_ext => ahbi_m_ext,
381 ahbo_m_ext => ahbo_m_ext);
382
383 -------------------------------------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 -------------------------------------------------------------------------------
386 apb_lfr_time_management_1 : apb_lfr_time_management
387 GENERIC MAP (
388 pindex => 6,
389 paddr => 6,
390 pmask => 16#fff#,
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 PORT MAP (
394 clk25MHz => clk_25,
395 clk24_576MHz => clk_24, -- 49.152MHz/2
396 resetn => reset,
397 grspw_tick => swno.tickout,
398 apbi => apbi_ext,
399 apbo => apbo_ext(6),
400 coarse_time => coarse_time,
401 fine_time => fine_time);
402
403 -----------------------------------------------------------------------
404 --- SpaceWire --------------------------------------------------------
405 -----------------------------------------------------------------------
406
407 SPW_EN <= '1';
408
409 spw_clk <= clk_50_s;
410 spw_rxtxclk <= spw_clk;
411 spw_rxclkn <= NOT spw_rxtxclk;
412
413 -- PADS for SPW1
414 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_NOM_DIN, dtmp(0));
416 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_SIN, stmp(0));
418 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_DOUT, swno.d(0));
420 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_SOUT, swno.s(0));
422 -- PADS FOR SPW2
423 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
424 PORT MAP (SPW_RED_SIN, dtmp(1));
425 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 PORT MAP (SPW_RED_DIN, stmp(1));
427 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
428 PORT MAP (SPW_RED_DOUT, swno.d(1));
429 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_RED_SOUT, swno.s(1));
431
432 -- GRSPW PHY
433 --spw1_input: if CFG_SPW_GRSPW = 1 generate
434 spw_inputloop : FOR j IN 0 TO 1 GENERATE
435 spw_phy0 : grspw_phy
436 GENERIC MAP(
437 tech => apa3e,
438 rxclkbuftype => 1,
439 scantest => 0)
440 PORT MAP(
441 rxrst => swno.rxrst,
442 di => dtmp(j),
443 si => stmp(j),
444 rxclko => spw_rxclk(j),
445 do => swni.d(j),
446 ndo => swni.nd(j*5+4 DOWNTO j*5),
447 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
448 END GENERATE spw_inputloop;
449
450 -- SPW core
451 sw0 : grspwm GENERIC MAP(
452 tech => apa3e,
453 hindex => 1,
454 pindex => 5,
455 paddr => 5,
456 pirq => 11,
457 sysfreq => 25000, -- CPU_FREQ
458 rmap => 1,
459 rmapcrc => 1,
460 fifosize1 => 16,
461 fifosize2 => 16,
462 rxclkbuftype => 1,
463 rxunaligned => 0,
464 rmapbufs => 4,
465 ft => 0,
466 netlist => 0,
467 ports => 2,
468 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
469 memtech => apa3e,
470 destkey => 2,
471 spwcore => 1
472 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
473 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
474 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
475 )
476 PORT MAP(reset, clk_25, spw_rxclk(0),
477 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
478 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
479 swni, swno);
480
481 swni.tickin <= '0';
482 swni.rmapen <= '1';
483 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
484 swni.tickinraw <= '0';
485 swni.timein <= (OTHERS => '0');
486 swni.dcrstval <= (OTHERS => '0');
487 swni.timerrstval <= (OTHERS => '0');
488
489 -------------------------------------------------------------------------------
490 -- LFR ------------------------------------------------------------------------
491 -------------------------------------------------------------------------------
492
493 lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
494 GENERIC MAP (
495 pindex => 15,
496 paddr => 15,
497 pmask => 16#fff#)
498 PORT MAP (
499 HCLK => clk_25,
500 HRESETn => reset,
501 apbi => apbi_ext,
502 apbo => apbo_ext(15),
503
504 MEM_IN_SM_wData => MEM_IN_SM_wData,
505 MEM_IN_SM_wen => MEM_IN_SM_wen,
506 MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
507 MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
508 MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
509
510 MEM_OUT_SM_ren => MEM_OUT_SM_ren ,
511 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
512 MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad ,
513 MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 ,
514 MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad);
515
516 lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb
517 GENERIC MAP (
518 Mem_use =>use_RAM)
519 PORT MAP (
520 clk => clk_25,
521 rstn => reset,
522
523 MEM_IN_SM_wData => MEM_IN_SM_wData,
524 MEM_IN_SM_wen => MEM_IN_SM_wen,
525 MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
526 MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
527 MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
528
529 MEM_OUT_SM_Read => MEM_OUT_SM_ren ,
530 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
531 MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad ,
532 MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 ,
533 MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad,
534
535 error_input_fifo_write => OPEN,
536 observation_vector_0 => observation_vector_0,
537 observation_vector_1 => observation_vector_1);
538
539 -----------------------------------------------------------------------------
540
541
542
543
544
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 END GENERATE all_sample;
548
549
550
551 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
552 GENERIC MAP(
553 ChannelCount => 8,
554 SampleNbBits => 14,
555 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
556 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
557 PORT MAP (
558 -- CONV
559 cnv_clk => clk_24,
560 cnv_rstn => reset,
561 cnv => ADC_nCS_sig,
562 -- DATA
563 clk => clk_25,
564 rstn => reset,
565 sck => ADC_CLK_sig,
566 sdo => ADC_SDO_sig,
567 -- SAMPLE
568 sample => sample,
569 sample_val => sample_val);
570
571 --IO10 <= ADC_SDO_sig(5);
572 --IO9 <= ADC_SDO_sig(4);
573 --IO8 <= ADC_SDO_sig(3);
574
575 ADC_nCS <= ADC_nCS_sig;
576 ADC_CLK <= ADC_CLK_sig;
577 ADC_SDO_sig <= ADC_SDO;
578
579 ----------------------------------------------------------------------
580 --- GPIO -----------------------------------------------------------
581 ----------------------------------------------------------------------
582
583 grgpio0 : grgpio
584 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
585 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
586
587 --pio_pad_0 : iopad
588 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
590 --pio_pad_1 : iopad
591 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
593 --pio_pad_2 : iopad
594 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
596 --pio_pad_3 : iopad
597 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
599 --pio_pad_4 : iopad
600 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
602 --pio_pad_5 : iopad
603 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
605 --pio_pad_6 : iopad
606 -- GENERIC MAP (tech => CFG_PADTECH)
607 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
608 --pio_pad_7 : iopad
609 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
611
612 PROCESS (clk_25, reset)
613 BEGIN -- PROCESS
614 IF reset = '0' THEN -- asynchronous reset (active low)
615 IO0 <= '0';
616 IO1 <= '0';
617 IO2 <= '0';
618 IO3 <= '0';
619 IO4 <= '0';
620 IO5 <= '0';
621 IO6 <= '0';
622 IO7 <= '0';
623 IO8 <= '0';
624 IO9 <= '0';
625 IO10 <= '0';
626 IO11 <= '0';
627 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
628 CASE gpioo.dout(2 DOWNTO 0) IS
629 WHEN "011" =>
630 IO0 <= observation_reg(0);
631 IO1 <= observation_reg(1);
632 IO2 <= observation_reg(2);
633 IO3 <= observation_reg(3);
634 IO4 <= observation_reg(4);
635 IO5 <= observation_reg(5);
636 IO6 <= observation_reg(6);
637 IO7 <= observation_reg(7);
638 IO8 <= observation_reg(8);
639 IO9 <= observation_reg(9);
640 IO10 <= observation_reg(10);
641 IO11 <= observation_reg(11);
642 WHEN "001" =>
643 IO0 <= observation_reg(0 + 12);
644 IO1 <= observation_reg(1 + 12);
645 IO2 <= observation_reg(2 + 12);
646 IO3 <= observation_reg(3 + 12);
647 IO4 <= observation_reg(4 + 12);
648 IO5 <= observation_reg(5 + 12);
649 IO6 <= observation_reg(6 + 12);
650 IO7 <= observation_reg(7 + 12);
651 IO8 <= observation_reg(8 + 12);
652 IO9 <= observation_reg(9 + 12);
653 IO10 <= observation_reg(10 + 12);
654 IO11 <= observation_reg(11 + 12);
655 WHEN "010" =>
656 IO0 <= observation_reg(0 + 12 + 12);
657 IO1 <= observation_reg(1 + 12 + 12);
658 IO2 <= observation_reg(2 + 12 + 12);
659 IO3 <= observation_reg(3 + 12 + 12);
660 IO4 <= observation_reg(4 + 12 + 12);
661 IO5 <= observation_reg(5 + 12 + 12);
662 IO6 <= observation_reg(6 + 12 + 12);
663 IO7 <= observation_reg(7 + 12 + 12);
664 IO8 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2);
665 IO9 <= ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5);
666 IO10 <= ADC_SDO(6) OR ADC_SDO(7) ;
667 IO11 <= '0';
668 WHEN "000" =>
669 IO0 <= observation_vector_0(0);
670 IO1 <= observation_vector_0(1);
671 IO2 <= observation_vector_0(2);
672 IO3 <= observation_vector_0(3);
673 IO4 <= observation_vector_0(4);
674 IO5 <= observation_vector_0(5);
675 IO6 <= observation_vector_0(6);
676 IO7 <= observation_vector_0(7);
677 IO8 <= observation_vector_0(8);
678 IO9 <= observation_vector_0(9);
679 IO10 <= observation_vector_0(10);
680 IO11 <= observation_vector_0(11);
681 WHEN "100" =>
682 IO0 <= observation_vector_1(0);
683 IO1 <= observation_vector_1(1);
684 IO2 <= observation_vector_1(2);
685 IO3 <= observation_vector_1(3);
686 IO4 <= observation_vector_1(4);
687 IO5 <= observation_vector_1(5);
688 IO6 <= observation_vector_1(6);
689 IO7 <= observation_vector_1(7);
690 IO8 <= observation_vector_1(8);
691 IO9 <= observation_vector_1(9);
692 IO10 <= observation_vector_1(10);
693 IO11 <= observation_vector_1(11);
694 WHEN OTHERS => NULL;
695 END CASE;
696
697 END IF;
698 END PROCESS;
699
700 END beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd lpp_lfr_apbreg.vhd lpp_lfr_ms_validation.vhd
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
18
19 TECHLIBS = proasic3e
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
31 ./lpp_cna \
32 ./lpp_uart \
33 ./lpp_usb \
34 ./dsp/lpp_fft_rtax \
35 ./lpp_sim/CY7C1061DV33 \
36
37 FILESKIP =i2cmst.vhd \
38 APB_MULTI_DIODE.vhd \
39 APB_SIMPLE_DIODE.vhd \
40 Top_MatrixSpec.vhd \
41 APB_FFT.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 );
26 END;
27
28 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
29
30 BEGIN
31
32 -----------------------------------------------------------------------------
33
34 lppFIFOxN_f0_a : lppFIFOxN
35 GENERIC MAP (
36 tech => 0,
37 Mem_use => Mem_use,
38 Data_sz => 16,
39 Addr_sz => 8,
40 FifoCnt => 5)
41 PORT MAP (
42 clk => clk,
43 rstn => rstn,
44
45 ReUse => (OTHERS => '0'),
46
47 wen => sample_f0_A_wen,
48 wdata => sample_f0_wdata,
49
50 ren => sample_f0_A_ren,
51 rdata => sample_f0_A_rdata,
52
53 empty => sample_f0_A_empty,
54 full => sample_f0_A_full,
55 almost_full => OPEN);
56
57 -----------------------------------------------------------------------------
58
59 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
60 PORT MAP (
61 clk => clk,
62 rstn => rstn,
63 sample_valid => sample_valid, -- WRITE in
64 fft_read => fft_read, -- READ in
65 sample_data => sample_data, -- WRITE in
66 sample_load => sample_load, -- WRITE out
67 fft_pong => fft_pong, -- READ out
68 fft_data_im => fft_data_im, -- READ out
69 fft_data_re => fft_data_re, -- READ out
70 fft_data_valid => fft_data_valid, -- READ out
71 fft_ready => fft_ready); -- READ out
72
73 -----------------------------------------------------------------------------
74
75 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 ENTITY lpp_lfr_apbreg_tb IS
39 GENERIC (
40 pindex : INTEGER := 4;
41 paddr : INTEGER := 4;
42 pmask : INTEGER := 16#fff#);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 ---------------------------------------------------------------------------
53 MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
54 MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
55 MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
56 MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
57 MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
58 ---------------------------------------------------------------------------
59 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
61 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
62 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
63 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
64 ---------------------------------------------------------------------------
65 );
66
67 END lpp_lfr_apbreg_tb;
68
69 ARCHITECTURE beh OF lpp_lfr_apbreg_tb IS
70
71 CONSTANT REVISION : INTEGER := 1;
72
73 CONSTANT pconfig : apb_config_type := (
74 0 => ahb_device_reg (VENDOR_LPP, 16#19#, 0, REVISION, 1),
75 1 => apb_iobar(paddr, pmask));
76
77 TYPE reg_debug_fft IS RECORD
78 MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
79 MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 --
81 out_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
82 END RECORD;
83 SIGNAL reg_ftt : reg_debug_fft;
84
85 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
86
87 BEGIN -- beh
88
89 ---------------------------------------------------------------------------
90 MEM_IN_SM_wen <= reg_ftt.MEM_IN_SM_wen;
91 MEM_IN_SM_wData <= reg_ftt.MEM_IN_SM_wData;
92 ---------------------------------------------------------------------------
93 MEM_OUT_SM_ren <= reg_ftt.out_ren;
94 ---------------------------------------------------------------------------
95
96 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
97 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
98 BEGIN
99 IF HRESETn = '0' THEN
100 reg_ftt.MEM_IN_SM_wData <= (OTHERS => '0');
101 reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1');
102
103 reg_ftt.out_ren <= (OTHERS => '1');
104
105 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
106
107 reg_ftt.MEM_IN_SM_wen <= (OTHERS => '1');
108 reg_ftt.out_ren <= (OTHERS => '1');
109
110 paddr := "000000";
111 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
112 prdata <= (OTHERS => '0');
113 IF apbi.psel(pindex) = '1' THEN
114 -- APB DMA READ --
115 CASE paddr(7 DOWNTO 2) IS
116 --0
117 WHEN "000000" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*1-1 DOWNTO 32*0);
118 WHEN "000001" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*2-1 DOWNTO 32*1);
119 WHEN "000010" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2);
120 WHEN "000011" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3);
121 WHEN "000100" => prdata(31 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4);
122 WHEN "000101" => prdata( 4 DOWNTO 0) <= reg_ftt.MEM_IN_SM_wen;
123 prdata( 9 DOWNTO 5) <= MEM_IN_SM_Full_out;
124 prdata(14 DOWNTO 10) <= MEM_IN_SM_Empty_out;
125 prdata(19 DOWNTO 15) <= MEM_IN_SM_locked_out;
126
127 WHEN "000110" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*1-1 DOWNTO 32*0);
128 WHEN "000111" => prdata(31 DOWNTO 0) <= MEM_OUT_SM_Data_out(32*2-1 DOWNTO 32*1);
129
130 WHEN "001000" => prdata(1 DOWNTO 0) <= reg_ftt.out_ren;
131 prdata(3 DOWNTO 2) <= MEM_OUT_SM_Full;
132 prdata(5 DOWNTO 4) <= MEM_OUT_SM_Empty;
133 prdata(6) <= MEM_OUT_SM_Full_2;
134 WHEN OTHERS => NULL;
135
136 END CASE;
137 IF (apbi.pwrite AND apbi.penable) = '1' THEN
138 -- APB DMA WRITE --
139 CASE paddr(7 DOWNTO 2) IS
140 WHEN "000000" => reg_ftt.MEM_IN_SM_wData(32*1-1 DOWNTO 32*0) <= apbi.pwdata(31 DOWNTO 0);
141 WHEN "000001" => reg_ftt.MEM_IN_SM_wData(32*2-1 DOWNTO 32*1) <= apbi.pwdata(31 DOWNTO 0);
142 WHEN "000010" => reg_ftt.MEM_IN_SM_wData(32*3-1 DOWNTO 32*2) <= apbi.pwdata(31 DOWNTO 0);
143 WHEN "000011" => reg_ftt.MEM_IN_SM_wData(32*4-1 DOWNTO 32*3) <= apbi.pwdata(31 DOWNTO 0);
144 WHEN "000100" => reg_ftt.MEM_IN_SM_wData(32*5-1 DOWNTO 32*4) <= apbi.pwdata(31 DOWNTO 0);
145 WHEN "000101" => reg_ftt.MEM_IN_SM_wen <= apbi.pwdata(4 DOWNTO 0);
146
147 WHEN "001000" => reg_ftt.out_ren <= apbi.pwdata(1 DOWNTO 0);
148
149 WHEN OTHERS => NULL;
150 END CASE;
151 END IF;
152 END IF;
153
154 END IF;
155 END PROCESS lpp_lfr_apbreg;
156
157 apbo.pindex <= pindex;
158 apbo.pconfig <= pconfig;
159 apbo.prdata <= prdata;
160
161 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms_tb IS
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
20 );
21 PORT (
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
25 ---------------------------------------------------------------------------
26 --
27 ---------------------------------------------------------------------------
28 MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
29 MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33
34 ---------------------------------------------------------------------------
35 --
36 ---------------------------------------------------------------------------
37 MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
38 MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
39 MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
40 MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC;
41 MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
42
43 ---------------------------------------------------------------------------
44 --
45 ---------------------------------------------------------------------------
46 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
47 --
48 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
49 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
50 );
51 END;
52
53 ARCHITECTURE Behavioral OF lpp_lfr_ms_tb IS
54
55 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
56 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
57 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
59 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
60
61 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
62 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
64 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66
67 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
68 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
70 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
71
72 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
73
74 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
75 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
78
79 SIGNAL error_wen_f0 : STD_LOGIC;
80 SIGNAL error_wen_f1 : STD_LOGIC;
81 SIGNAL error_wen_f2 : STD_LOGIC;
82
83 SIGNAL one_sample_f1_full : STD_LOGIC;
84 SIGNAL one_sample_f1_wen : STD_LOGIC;
85 SIGNAL one_sample_f2_full : STD_LOGIC;
86 SIGNAL one_sample_f2_wen : STD_LOGIC;
87
88 -----------------------------------------------------------------------------
89 -- FSM / SWITCH SELECT CHANNEL
90 -----------------------------------------------------------------------------
91 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
92 SIGNAL state_fsm_select_channel : fsm_select_channel;
93 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
94
95 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99
100 -----------------------------------------------------------------------------
101 -- FSM LOAD FFT
102 -----------------------------------------------------------------------------
103 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
104 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
105 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
106
107 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
108 SIGNAL sample_load : STD_LOGIC;
109 SIGNAL sample_valid : STD_LOGIC;
110 SIGNAL sample_valid_r : STD_LOGIC;
111 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
112
113
114 -----------------------------------------------------------------------------
115 -- FFT
116 -----------------------------------------------------------------------------
117 SIGNAL fft_read : STD_LOGIC;
118 SIGNAL fft_pong : STD_LOGIC;
119 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fft_data_valid : STD_LOGIC;
122 SIGNAL fft_ready : STD_LOGIC;
123 -----------------------------------------------------------------------------
124 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 -----------------------------------------------------------------------------
126 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
127 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
128 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
129 SIGNAL current_fifo_empty : STD_LOGIC;
130 SIGNAL current_fifo_locked : STD_LOGIC;
131 SIGNAL current_fifo_full : STD_LOGIC;
132 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
133
134 -----------------------------------------------------------------------------
135 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 -- SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
138 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
139 -- SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
140 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
141 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
142 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
143 -----------------------------------------------------------------------------
144 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
145 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
147
148 SIGNAL SM_correlation_start : STD_LOGIC;
149 SIGNAL SM_correlation_auto : STD_LOGIC;
150 SIGNAL SM_correlation_done : STD_LOGIC;
151 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
152 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
153 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
154 SIGNAL SM_correlation_begin : STD_LOGIC;
155
156 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
157 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
159
160 SIGNAL current_matrix_write : STD_LOGIC;
161 SIGNAL current_matrix_wait_empty : STD_LOGIC;
162 -----------------------------------------------------------------------------
163 SIGNAL fifo_0_ready : STD_LOGIC;
164 SIGNAL fifo_1_ready : STD_LOGIC;
165 SIGNAL fifo_ongoing : STD_LOGIC;
166
167 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
168 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
169 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
171 -----------------------------------------------------------------------------
172 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 -- SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
175 -- SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
176 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
177 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
178
179 -----------------------------------------------------------------------------
180 -- TIME REG & INFOs
181 -----------------------------------------------------------------------------
182 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
183
184 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
185 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
188
189 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193
194 --SIGNAL time_update_f0_A : STD_LOGIC;
195 --SIGNAL time_update_f0_B : STD_LOGIC;
196 --SIGNAL time_update_f1 : STD_LOGIC;
197 --SIGNAL time_update_f2 : STD_LOGIC;
198 --
199 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
200 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
201 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
202
203 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
204 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
205 SIGNAL status_component_fifo_0_end : STD_LOGIC;
206 SIGNAL status_component_fifo_1_end : STD_LOGIC;
207 -----------------------------------------------------------------------------
208 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
209
210 SIGNAL fft_ready_reg : STD_LOGIC;
211 SIGNAL fft_ready_rising_down : STD_LOGIC;
212
213 SIGNAL sample_load_reg : STD_LOGIC;
214 SIGNAL sample_load_rising_down : STD_LOGIC;
215
216 -----------------------------------------------------------------------------
217 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
218 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
219 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
220 SIGNAL sample_f1_full_head_in : STD_LOGIC;
221 SIGNAL sample_f1_full_head_out : STD_LOGIC;
222 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
223
224 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
225
226 BEGIN
227
228 error_input_fifo_write <=(others => '0');
229 observation_vector_0(11 DOWNTO 0) <= (OTHERS => '0');
230
231 -- error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
232
233
234 -- switch_f0_inst : spectral_matrix_switch_f0
235 -- PORT MAP (
236 -- clk => clk,
237 -- rstn => rstn,
238
239 -- sample_wen => sample_f0_wen,
240
241 -- fifo_A_empty => sample_f0_A_empty,
242 -- fifo_A_full => sample_f0_A_full,
243 -- fifo_A_wen => sample_f0_A_wen,
244
245 -- fifo_B_empty => sample_f0_B_empty,
246 -- fifo_B_full => sample_f0_B_full,
247 -- fifo_B_wen => sample_f0_B_wen,
248
249 -- error_wen => error_wen_f0); -- TODO
250
251 -- -----------------------------------------------------------------------------
252 -- -- FIFO IN
253 -- -----------------------------------------------------------------------------
254 -- lppFIFOxN_f0_a : lppFIFOxN
255 -- GENERIC MAP (
256 -- tech => 0,
257 -- Mem_use => Mem_use,
258 -- Data_sz => 16,
259 -- Addr_sz => 8,
260 -- FifoCnt => 5)
261 -- PORT MAP (
262 -- clk => clk,
263 -- rstn => rstn,
264
265 -- ReUse => (OTHERS => '0'),
266
267 -- wen => sample_f0_A_wen,
268 -- wdata => sample_f0_wdata,
269
270 -- ren => sample_f0_A_ren,
271 -- rdata => sample_f0_A_rdata,
272
273 -- empty => sample_f0_A_empty,
274 -- full => sample_f0_A_full,
275 -- almost_full => OPEN);
276
277 -- lppFIFOxN_f0_b : lppFIFOxN
278 -- GENERIC MAP (
279 -- tech => 0,
280 -- Mem_use => Mem_use,
281 -- Data_sz => 16,
282 -- Addr_sz => 8,
283 -- FifoCnt => 5)
284 -- PORT MAP (
285 -- clk => clk,
286 -- rstn => rstn,
287
288 -- ReUse => (OTHERS => '0'),
289
290 -- wen => sample_f0_B_wen,
291 -- wdata => sample_f0_wdata,
292 -- ren => sample_f0_B_ren,
293 -- rdata => sample_f0_B_rdata,
294 -- empty => sample_f0_B_empty,
295 -- full => sample_f0_B_full,
296 -- almost_full => OPEN);
297
298 -- -----------------------------------------------------------------------------
299 -- -- sample_f1_wen in
300 -- -- sample_f1_wdata in
301 -- -- sample_f1_full OUT
302
303 -- sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
304 -- sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
305 -- sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
306
307 -- lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
308 -- PORT MAP (
309 -- clk => clk,
310 -- rstn => rstn,
311 -- in_wen => sample_f1_wen_head_in,
312 -- in_data => sample_f1_wdata,
313 -- in_full => sample_f1_full_head_in,
314 -- in_empty => sample_f1_empty_head_in,
315 -- out_wen => sample_f1_wen_head_out,
316 -- out_data => sample_f1_wdata_head,
317 -- out_full => sample_f1_full_head_out);
318
319 -- sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
320
321
322 -- lppFIFOxN_f1 : lppFIFOxN
323 -- GENERIC MAP (
324 -- tech => 0,
325 -- Mem_use => Mem_use,
326 -- Data_sz => 16,
327 -- Addr_sz => 8,
328 -- FifoCnt => 5)
329 -- PORT MAP (
330 -- clk => clk,
331 -- rstn => rstn,
332
333 -- ReUse => (OTHERS => '0'),
334
335 -- wen => sample_f1_wen_head,
336 -- wdata => sample_f1_wdata_head,
337 -- ren => sample_f1_ren,
338 -- rdata => sample_f1_rdata,
339 -- empty => sample_f1_empty,
340 -- full => sample_f1_full,
341 -- almost_full => sample_f1_almost_full);
342
343
344 -- one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
345
346 -- PROCESS (clk, rstn)
347 -- BEGIN -- PROCESS
348 -- IF rstn = '0' THEN -- asynchronous reset (active low)
349 -- one_sample_f1_full <= '0';
350 -- error_wen_f1 <= '0';
351 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
352 -- IF sample_f1_full_head_out = '0' THEN
353 -- one_sample_f1_full <= '0';
354 -- ELSE
355 -- one_sample_f1_full <= '1';
356 -- END IF;
357 -- error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
358 -- END IF;
359 -- END PROCESS;
360
361 -- -----------------------------------------------------------------------------
362
363
364 -- lppFIFOxN_f2 : lppFIFOxN
365 -- GENERIC MAP (
366 -- tech => 0,
367 -- Mem_use => Mem_use,
368 -- Data_sz => 16,
369 -- Addr_sz => 8,
370 -- FifoCnt => 5)
371 -- PORT MAP (
372 -- clk => clk,
373 -- rstn => rstn,
374
375 -- ReUse => (OTHERS => '0'),
376
377 -- wen => sample_f2_wen,
378 -- wdata => sample_f2_wdata,
379 -- ren => sample_f2_ren,
380 -- rdata => sample_f2_rdata,
381 -- empty => sample_f2_empty,
382 -- full => sample_f2_full,
383 -- almost_full => OPEN);
384
385
386 -- one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
387
388 -- PROCESS (clk, rstn)
389 -- BEGIN -- PROCESS
390 -- IF rstn = '0' THEN -- asynchronous reset (active low)
391 -- one_sample_f2_full <= '0';
392 -- error_wen_f2 <= '0';
393 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
394 -- IF sample_f2_full = "00000" THEN
395 -- one_sample_f2_full <= '0';
396 -- ELSE
397 -- one_sample_f2_full <= '1';
398 -- END IF;
399 -- error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
400 -- END IF;
401 -- END PROCESS;
402
403 -- -----------------------------------------------------------------------------
404 -- -- FSM SELECT CHANNEL
405 -- -----------------------------------------------------------------------------
406 -- PROCESS (clk, rstn)
407 -- BEGIN
408 -- IF rstn = '0' THEN
409 -- state_fsm_select_channel <= IDLE;
410 -- ELSIF clk'EVENT AND clk = '1' THEN
411 -- CASE state_fsm_select_channel IS
412 -- WHEN IDLE =>
413 -- IF sample_f1_full = "11111" THEN
414 -- state_fsm_select_channel <= SWITCH_F1;
415 -- ELSIF sample_f1_almost_full = "00000" THEN
416 -- IF sample_f0_A_full = "11111" THEN
417 -- state_fsm_select_channel <= SWITCH_F0_A;
418 -- ELSIF sample_f0_B_full = "11111" THEN
419 -- state_fsm_select_channel <= SWITCH_F0_B;
420 -- ELSIF sample_f2_full = "11111" THEN
421 -- state_fsm_select_channel <= SWITCH_F2;
422 -- END IF;
423 -- END IF;
424
425 -- WHEN SWITCH_F0_A =>
426 -- IF sample_f0_A_empty = "11111" THEN
427 -- state_fsm_select_channel <= IDLE;
428 -- END IF;
429 -- WHEN SWITCH_F0_B =>
430 -- IF sample_f0_B_empty = "11111" THEN
431 -- state_fsm_select_channel <= IDLE;
432 -- END IF;
433 -- WHEN SWITCH_F1 =>
434 -- IF sample_f1_empty = "11111" THEN
435 -- state_fsm_select_channel <= IDLE;
436 -- END IF;
437 -- WHEN SWITCH_F2 =>
438 -- IF sample_f2_empty = "11111" THEN
439 -- state_fsm_select_channel <= IDLE;
440 -- END IF;
441 -- WHEN OTHERS => NULL;
442 -- END CASE;
443
444 -- END IF;
445 -- END PROCESS;
446
447 -- PROCESS (clk, rstn)
448 -- BEGIN
449 -- IF rstn = '0' THEN
450 -- pre_state_fsm_select_channel <= IDLE;
451 -- ELSIF clk'EVENT AND clk = '1' THEN
452 -- pre_state_fsm_select_channel <= state_fsm_select_channel;
453 -- END IF;
454 -- END PROCESS;
455
456
457 -- -----------------------------------------------------------------------------
458 -- -- SWITCH SELECT CHANNEL
459 -- -----------------------------------------------------------------------------
460 -- sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
461 -- sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
462 -- sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
463 -- sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
464 -- (OTHERS => '1');
465
466 -- sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
467 -- sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
468 -- sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
469 -- sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
470 -- (OTHERS => '0');
471
472 -- sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
473 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
474 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
475 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
476
477
478 -- sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
479 -- sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
480 -- sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
481 -- sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
482
483
484 -- status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
485 -- time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
486 -- time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
487 -- time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
488
489 -- -----------------------------------------------------------------------------
490 -- -- FSM LOAD FFT
491 -- -----------------------------------------------------------------------------
492
493 -- sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
494 -- sample_ren_s WHEN sample_load = '1' ELSE
495 -- (OTHERS => '1');
496
497 -- PROCESS (clk, rstn)
498 -- BEGIN
499 -- IF rstn = '0' THEN
500 -- sample_ren_s <= (OTHERS => '1');
501 -- state_fsm_load_FFT <= IDLE;
502 -- status_MS_input <= (OTHERS => '0');
503 -- --next_state_fsm_load_FFT <= IDLE;
504 -- --sample_valid <= '0';
505 -- ELSIF clk'EVENT AND clk = '1' THEN
506 -- CASE state_fsm_load_FFT IS
507 -- WHEN IDLE =>
508 -- --sample_valid <= '0';
509 -- sample_ren_s <= (OTHERS => '1');
510 -- IF sample_full = "11111" AND sample_load = '1' THEN
511 -- state_fsm_load_FFT <= FIFO_1;
512 -- status_MS_input <= status_channel;
513 -- END IF;
514
515 -- WHEN FIFO_1 =>
516 -- sample_ren_s <= "1111" & NOT(sample_load);
517 -- IF sample_empty(0) = '1' THEN
518 -- sample_ren_s <= (OTHERS => '1');
519 -- state_fsm_load_FFT <= FIFO_2;
520 -- END IF;
521
522 -- WHEN FIFO_2 =>
523 -- sample_ren_s <= "111" & NOT(sample_load) & '1';
524 -- IF sample_empty(1) = '1' THEN
525 -- sample_ren_s <= (OTHERS => '1');
526 -- state_fsm_load_FFT <= FIFO_3;
527 -- END IF;
528
529 -- WHEN FIFO_3 =>
530 -- sample_ren_s <= "11" & NOT(sample_load) & "11";
531 -- IF sample_empty(2) = '1' THEN
532 -- sample_ren_s <= (OTHERS => '1');
533 -- state_fsm_load_FFT <= FIFO_4;
534 -- END IF;
535
536 -- WHEN FIFO_4 =>
537 -- sample_ren_s <= '1' & NOT(sample_load) & "111";
538 -- IF sample_empty(3) = '1' THEN
539 -- sample_ren_s <= (OTHERS => '1');
540 -- state_fsm_load_FFT <= FIFO_5;
541 -- END IF;
542
543 -- WHEN FIFO_5 =>
544 -- sample_ren_s <= NOT(sample_load) & "1111";
545 -- IF sample_empty(4) = '1' THEN
546 -- sample_ren_s <= (OTHERS => '1');
547 -- state_fsm_load_FFT <= IDLE;
548 -- END IF;
549 -- WHEN OTHERS => NULL;
550 -- END CASE;
551 -- END IF;
552 -- END PROCESS;
553
554 -- PROCESS (clk, rstn)
555 -- BEGIN
556 -- IF rstn = '0' THEN
557 -- sample_valid_r <= '0';
558 -- next_state_fsm_load_FFT <= IDLE;
559 -- ELSIF clk'EVENT AND clk = '1' THEN
560 -- next_state_fsm_load_FFT <= state_fsm_load_FFT;
561 -- IF sample_ren_s = "11111" THEN
562 -- sample_valid_r <= '0';
563 -- ELSE
564 -- sample_valid_r <= '1';
565 -- END IF;
566 -- END IF;
567 -- END PROCESS;
568
569 -- sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
570
571 -- sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
572 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
573 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
574 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
575 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
576
577 -- -----------------------------------------------------------------------------
578 -- -- FFT
579 -- -----------------------------------------------------------------------------
580 -- lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
581 -- PORT MAP (
582 -- clk => clk,
583 -- rstn => rstn,
584 -- sample_valid => sample_valid,
585 -- fft_read => fft_read,
586 -- sample_data => sample_data,
587 -- sample_load => sample_load,
588 -- fft_pong => fft_pong,
589 -- fft_data_im => fft_data_im,
590 -- fft_data_re => fft_data_re,
591 -- fft_data_valid => fft_data_valid,
592 -- fft_ready => fft_ready);
593
594 -- observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
595 -- fft_ongoing_counter & --9 8
596 -- sample_load_rising_down & --7
597 -- fft_ready_rising_down & --6
598 -- fft_ready & --5
599 -- fft_data_valid & --4
600 -- fft_pong & --3
601 -- sample_load & --2
602 -- fft_read & --1
603 -- sample_valid; --0
604
605 -- -----------------------------------------------------------------------------
606 -- fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
607 -- sample_load_rising_down <= sample_load_reg AND NOT sample_load;
608
609 -- PROCESS (clk, rstn)
610 -- BEGIN
611 -- IF rstn = '0' THEN
612 -- fft_ready_reg <= '0';
613 -- sample_load_reg <= '0';
614
615 -- fft_ongoing_counter <= '0';
616 -- ELSIF clk'event AND clk = '1' THEN
617 -- fft_ready_reg <= fft_ready;
618 -- sample_load_reg <= sample_load;
619
620 -- IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
621 -- fft_ongoing_counter <= '0';
622
623 ---- CASE fft_ongoing_counter IS
624 ---- WHEN "01" => fft_ongoing_counter <= "00";
625 ------ WHEN "10" => fft_ongoing_counter <= "01";
626 ---- WHEN OTHERS => NULL;
627 ---- END CASE;
628 -- ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
629 -- fft_ongoing_counter <= '1';
630 ---- CASE fft_ongoing_counter IS
631 ---- WHEN "00" => fft_ongoing_counter <= "01";
632 ------ WHEN "01" => fft_ongoing_counter <= "10";
633 ---- WHEN OTHERS => NULL;
634 ---- END CASE;
635 -- END IF;
636
637 -- END IF;
638 -- END PROCESS;
639
640 -- -----------------------------------------------------------------------------
641 -- PROCESS (clk, rstn)
642 -- BEGIN
643 -- IF rstn = '0' THEN
644 -- state_fsm_load_MS_memory <= IDLE;
645 -- current_fifo_load <= "00001";
646 -- ELSIF clk'EVENT AND clk = '1' THEN
647 -- CASE state_fsm_load_MS_memory IS
648 -- WHEN IDLE =>
649 -- IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
650 -- state_fsm_load_MS_memory <= LOAD_FIFO;
651 -- END IF;
652 -- WHEN LOAD_FIFO =>
653 -- IF current_fifo_full = '1' THEN
654 -- state_fsm_load_MS_memory <= TRASH_FFT;
655 -- END IF;
656 -- WHEN TRASH_FFT =>
657 -- IF fft_ready = '0' THEN
658 -- state_fsm_load_MS_memory <= IDLE;
659 -- current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
660 -- END IF;
661 -- WHEN OTHERS => NULL;
662 -- END CASE;
663
664 -- END IF;
665 -- END PROCESS;
666
667 -- current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
668 -- MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
669 -- MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
670 -- MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
671 -- MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
672
673 -- current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
674 -- MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
675 -- MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
676 -- MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
677 -- MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
678
679 -- current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
680 -- MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
681 -- MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
682 -- MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
683 -- MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
684
685 -- fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
686
687 -- all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
688 -- MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
689 -- AND state_fsm_load_MS_memory = LOAD_FIFO
690 -- AND current_fifo_load(I) = '1'
691 -- ELSE '1';
692 -- END GENERATE all_fifo;
693
694 -- PROCESS (clk, rstn)
695 -- BEGIN
696 -- IF rstn = '0' THEN
697 -- MEM_IN_SM_wen <= (OTHERS => '1');
698 -- ELSIF clk'EVENT AND clk = '1' THEN
699 -- MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
700 -- END IF;
701 -- END PROCESS;
702
703 -- MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
704 -- (fft_data_im & fft_data_re) &
705 -- (fft_data_im & fft_data_re) &
706 -- (fft_data_im & fft_data_re) &
707 -- (fft_data_im & fft_data_re);
708 -----------------------------------------------------------------------------
709
710 MEM_IN_SM_Full_out <= MEM_IN_SM_Full;
711 MEM_IN_SM_Empty_out <= MEM_IN_SM_Empty;
712 MEM_IN_SM_locked_out <= MEM_IN_SM_locked;
713 -----------------------------------------------------------------------------
714 Mem_In_SpectralMatrix : lppFIFOxN
715 GENERIC MAP (
716 tech => 0,
717 Mem_use => Mem_use,
718 Data_sz => 32, --16,
719 Addr_sz => 7, --8
720 FifoCnt => 5)
721 PORT MAP (
722 clk => clk,
723 rstn => rstn,
724
725 ReUse => MEM_IN_SM_ReUse,
726
727 wen => MEM_IN_SM_wen,
728 wdata => MEM_IN_SM_wData,
729
730 ren => MEM_IN_SM_ren,
731 rdata => MEM_IN_SM_rData,
732 full => MEM_IN_SM_Full,
733 empty => MEM_IN_SM_Empty,
734 almost_full => OPEN);
735
736 -----------------------------------------------------------------------------
737
738 observation_vector_1(11 DOWNTO 0) <= '0' &
739 SM_correlation_done & --4
740 SM_correlation_auto & --3
741 SM_correlation_start &
742 SM_correlation_start & --7
743 status_MS_input(1 DOWNTO 0)& --6..5
744 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
745
746 -----------------------------------------------------------------------------
747 MS_control_1 : MS_control
748 PORT MAP (
749 clk => clk,
750 rstn => rstn,
751
752 current_status_ms => status_MS_input,
753
754 fifo_in_lock => MEM_IN_SM_locked,
755 fifo_in_data => MEM_IN_SM_rdata,
756 fifo_in_full => MEM_IN_SM_Full,
757 fifo_in_empty => MEM_IN_SM_Empty,
758 fifo_in_ren => MEM_IN_SM_ren,
759 fifo_in_reuse => MEM_IN_SM_ReUse,
760
761 fifo_out_data => SM_in_data,
762 fifo_out_ren => SM_in_ren,
763 fifo_out_empty => SM_in_empty,
764
765 current_status_component => status_component,
766
767 correlation_start => SM_correlation_start,
768 correlation_auto => SM_correlation_auto,
769 correlation_done => SM_correlation_done);
770
771
772 MS_calculation_1 : MS_calculation
773 PORT MAP (
774 clk => clk,
775 rstn => rstn,
776
777 fifo_in_data => SM_in_data,
778 fifo_in_ren => SM_in_ren,
779 fifo_in_empty => SM_in_empty,
780
781 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
782 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
783 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
784
785 correlation_start => SM_correlation_start,
786 correlation_auto => SM_correlation_auto,
787 correlation_begin => SM_correlation_begin,
788 correlation_done => SM_correlation_done);
789
790 -----------------------------------------------------------------------------
791 PROCESS (clk, rstn)
792 BEGIN -- PROCESS
793 IF rstn = '0' THEN -- asynchronous reset (active low)
794 current_matrix_write <= '0';
795 current_matrix_wait_empty <= '1';
796 status_component_fifo_0 <= (OTHERS => '0');
797 status_component_fifo_1 <= (OTHERS => '0');
798 status_component_fifo_0_end <= '0';
799 status_component_fifo_1_end <= '0';
800 SM_correlation_done_reg1 <= '0';
801 SM_correlation_done_reg2 <= '0';
802 SM_correlation_done_reg3 <= '0';
803
804 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
805 SM_correlation_done_reg1 <= SM_correlation_done;
806 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
807 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
808 status_component_fifo_0_end <= '0';
809 status_component_fifo_1_end <= '0';
810 IF SM_correlation_begin = '1' THEN
811 IF current_matrix_write = '0' THEN
812 status_component_fifo_0 <= status_component;
813 ELSE
814 status_component_fifo_1 <= status_component;
815 END IF;
816 END IF;
817
818 IF SM_correlation_done_reg3 = '1' THEN
819 IF current_matrix_write = '0' THEN
820 status_component_fifo_0_end <= '1';
821 ELSE
822 status_component_fifo_1_end <= '1';
823 END IF;
824 current_matrix_wait_empty <= '1';
825 current_matrix_write <= NOT current_matrix_write;
826 END IF;
827
828 IF current_matrix_wait_empty <= '1' THEN
829 IF current_matrix_write = '0' THEN
830 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
831 ELSE
832 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
833 END IF;
834 END IF;
835
836 END IF;
837 END PROCESS;
838
839 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
840 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
841 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
842 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
843 '1' WHEN current_matrix_wait_empty = '1' ELSE
844 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
845 MEM_OUT_SM_Full(1);
846
847 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
848 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
849
850 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
851 -----------------------------------------------------------------------------
852
853 Mem_Out_SpectralMatrix : lppFIFOxN
854 GENERIC MAP (
855 tech => 0,
856 Mem_use => Mem_use,
857 Data_sz => 32,
858 Addr_sz => 8,
859 FifoCnt => 2)
860 PORT MAP (
861 clk => clk,
862 rstn => rstn,
863
864 ReUse => (OTHERS => '0'),
865
866 wen => MEM_OUT_SM_Write,
867 wdata => MEM_OUT_SM_Data_in,
868
869 ren => MEM_OUT_SM_Read,
870 rdata => MEM_OUT_SM_Data_out,
871
872 full => MEM_OUT_SM_Full,
873 empty => MEM_OUT_SM_Empty,
874 almost_full => OPEN);
875
876 MEM_OUT_SM_Full_pad <= MEM_OUT_SM_Full;
877 MEM_OUT_SM_Full_pad_2 <= MEM_OUT_SM_Full_s;
878 MEM_OUT_SM_Empty_pad <= MEM_OUT_SM_Empty;
879
880 -- -----------------------------------------------------------------------------
881 ---- MEM_OUT_SM_Read <= "00";
882 -- PROCESS (clk, rstn)
883 -- BEGIN
884 -- IF rstn = '0' THEN
885 -- fifo_0_ready <= '0';
886 -- fifo_1_ready <= '0';
887 -- fifo_ongoing <= '0';
888 -- ELSIF clk'EVENT AND clk = '1' THEN
889 -- IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
890 -- fifo_ongoing <= '1';
891 -- fifo_0_ready <= '0';
892 -- ELSIF status_component_fifo_0_end = '1' THEN
893 -- fifo_0_ready <= '1';
894 -- END IF;
895
896 -- IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
897 -- fifo_ongoing <= '0';
898 -- fifo_1_ready <= '0';
899 -- ELSIF status_component_fifo_1_end = '1' THEN
900 -- fifo_1_ready <= '1';
901 -- END IF;
902
903 -- END IF;
904 -- END PROCESS;
905
906 -- MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
907 -- '1' WHEN fifo_0_ready = '0' ELSE
908 -- FSM_DMA_fifo_ren;
909
910 -- MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
911 -- '1' WHEN fifo_1_ready = '0' ELSE
912 -- FSM_DMA_fifo_ren;
913
914 -- FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
915 -- MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
916 -- '1';
917
918 -- FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
919 -- status_component_fifo_1;
920
921 -- FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
922 -- MEM_OUT_SM_Data_out(63 DOWNTO 32);
923
924 -- -----------------------------------------------------------------------------
925 -- lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
926 -- PORT MAP (
927 -- HCLK => clk,
928 -- HRESETn => rstn,
929
930 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
931 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
932 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
933 -- fifo_data => FSM_DMA_fifo_data,
934 -- fifo_empty => FSM_DMA_fifo_empty,
935 -- fifo_ren => FSM_DMA_fifo_ren,
936
937 -- dma_addr => dma_addr,
938 -- dma_data => dma_data,
939 -- dma_valid => dma_valid,
940 -- dma_valid_burst => dma_valid_burst,
941 -- dma_ren => dma_ren,
942 -- dma_done => dma_done,
943
944 -- ready_matrix_f0 => ready_matrix_f0,
945 -- ready_matrix_f1 => ready_matrix_f1,
946 -- ready_matrix_f2 => ready_matrix_f2,
947
948 -- error_bad_component_error => error_bad_component_error,
949 -- error_buffer_full => error_buffer_full,
950
951 -- debug_reg => debug_reg,
952 -- status_ready_matrix_f0 => status_ready_matrix_f0,
953 -- status_ready_matrix_f1 => status_ready_matrix_f1,
954 -- status_ready_matrix_f2 => status_ready_matrix_f2,
955
956 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
957 -- config_active_interruption_onError => config_active_interruption_onError,
958
959 -- addr_matrix_f0 => addr_matrix_f0,
960 -- addr_matrix_f1 => addr_matrix_f1,
961 -- addr_matrix_f2 => addr_matrix_f2,
962
963 -- matrix_time_f0 => matrix_time_f0,
964 -- matrix_time_f1 => matrix_time_f1,
965 -- matrix_time_f2 => matrix_time_f2
966 -- );
967 -- -----------------------------------------------------------------------------
968
969
970
971
972
973 -- -----------------------------------------------------------------------------
974 -- -- TIME MANAGMENT
975 -- -----------------------------------------------------------------------------
976 -- all_time <= coarse_time & fine_time;
977 -- --
978 -- f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
979 -- f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
980 -- f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
981 -- f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
982
983 -- all_time_reg: FOR I IN 0 TO 3 GENERATE
984
985 -- PROCESS (clk, rstn)
986 -- BEGIN
987 -- IF rstn = '0' THEN
988 -- f_empty_reg(I) <= '1';
989 -- ELSIF clk'event AND clk = '1' THEN
990 -- f_empty_reg(I) <= f_empty(I);
991 -- END IF;
992 -- END PROCESS;
993
994 -- time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
995
996 -- s_m_t_m_f0_A : spectral_matrix_time_managment
997 -- PORT MAP (
998 -- clk => clk,
999 -- rstn => rstn,
1000 -- time_in => all_time,
1001 -- update_1 => time_update_f(I),
1002 -- time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1003 -- );
1004
1005 -- END GENERATE all_time_reg;
1006
1007 -- time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1008 -- time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1009 -- time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1010 -- time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1011
1012 -- -----------------------------------------------------------------------------
1013
1014 END Behavioral; No newline at end of file
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1 LIBRARY IEEE;
2 USE IEEE.numeric_std.ALL;
3 USE IEEE.std_logic_1164.ALL;
4
5 LIBRARY grlib;
6 USE grlib.amba.ALL;
7 USE grlib.stdlib.ALL;
8
9 LIBRARY lpp;
10 USE lpp.iir_filter.ALL;
11
12 ENTITY testbench_ms IS
13
14 END testbench_ms;
15
16 ARCHITECTURE tb OF testbench_ms IS
17 -----------------------------------------------------------------------------
18 -- COMPONENT ----------------------------------------------------------------
19 -----------------------------------------------------------------------------
20 COMPONENT lpp_lfr_apbreg_tb
21 GENERIC (
22 pindex : INTEGER;
23 paddr : INTEGER;
24 pmask : INTEGER);
25 PORT (
26 HCLK : IN STD_ULOGIC;
27 HRESETn : IN STD_ULOGIC;
28 apbi : IN apb_slv_in_type;
29 apbo : OUT apb_slv_out_type;
30 MEM_IN_SM_wData : OUT STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
31 MEM_IN_SM_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 MEM_IN_SM_Full_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 MEM_IN_SM_Empty_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 MEM_IN_SM_locked_out : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 MEM_OUT_SM_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
36 MEM_OUT_SM_Data_out : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
37 MEM_OUT_SM_Full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
38 MEM_OUT_SM_Full_2 : IN STD_LOGIC;
39 MEM_OUT_SM_Empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
40 END COMPONENT;
41
42 COMPONENT lpp_lfr_ms_tb
43 GENERIC (
44 Mem_use : INTEGER);
45 PORT (
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 MEM_IN_SM_wData : IN STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
49 MEM_IN_SM_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 MEM_IN_SM_Full_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
51 MEM_IN_SM_Empty_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
52 MEM_IN_SM_locked_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_OUT_SM_Read : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
54 MEM_OUT_SM_Data_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
55 MEM_OUT_SM_Full_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
56 MEM_OUT_SM_Full_pad_2 : OUT STD_LOGIC;
57 MEM_OUT_SM_Empty_pad : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
58 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
59 observation_vector_0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
60 observation_vector_1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
61 END COMPONENT;
62
63 -----------------------------------------------------------------------------
64 -- SIGNAL -------------------------------------------------------------------
65 -----------------------------------------------------------------------------
66 SIGNAL clk : STD_LOGIC := '0';
67 SIGNAL rstn : STD_LOGIC := '0';
68 SIGNAL apbi : apb_slv_in_type;
69 SIGNAL apbo : apb_slv_out_type;
70
71 SIGNAL MEM_OUT_SM_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
72 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
73 SIGNAL MEM_OUT_SM_Full_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
74 SIGNAL MEM_OUT_SM_Full_pad_2 : STD_LOGIC;
75 SIGNAL MEM_OUT_SM_Empty_pad : STD_LOGIC_VECTOR(1 DOWNTO 0);
76
77 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
78 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 SIGNAL MEM_IN_SM_Full_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 SIGNAL MEM_IN_SM_Empty_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL MEM_IN_SM_locked_out : STD_LOGIC_VECTOR(4 DOWNTO 0);
82
83
84 -----------------------------------------------------------------------------
85 -- FFT
86 -----------------------------------------------------------------------------
87 TYPE fft_tab_type IS ARRAY (255 DOWNTO 0) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
88 SIGNAL fft_1_re : fft_tab_type;
89 SIGNAL fft_1_im : fft_tab_type;
90 SIGNAL fft_2_re : fft_tab_type;
91 SIGNAL fft_2_im : fft_tab_type;
92 SIGNAL fft_3_re : fft_tab_type;
93 SIGNAL fft_3_im : fft_tab_type;
94 SIGNAL fft_4_re : fft_tab_type;
95 SIGNAL fft_4_im : fft_tab_type;
96 SIGNAL fft_5_re : fft_tab_type;
97 SIGNAL fft_5_im : fft_tab_type;
98
99 SIGNAL counter_1 : INTEGER;
100 SIGNAL counter_2 : INTEGER;
101 SIGNAL counter_3 : INTEGER;
102 SIGNAL counter_4 : INTEGER;
103 SIGNAL counter_5 : INTEGER;
104
105
106 BEGIN -- tb
107
108
109 clk <= NOT clk AFTER 20 ns;
110 rstn <= '1' AFTER 100 ns;
111
112 PROCESS (clk, rstn)
113 BEGIN
114 IF rstn = '0' THEN -- asynchronous reset (active low)
115 all_data: FOR i IN 255 DOWNTO 0 LOOP
116 fft_1_re(I) <= (OTHERS => '0');
117 fft_1_im(I) <= (OTHERS => '0');
118 fft_2_re(I) <= (OTHERS => '0');
119 fft_2_im(I) <= (OTHERS => '0');
120 fft_3_re(I) <= (OTHERS => '0');
121 fft_3_im(I) <= (OTHERS => '0');
122 fft_4_re(I) <= (OTHERS => '0');
123 fft_4_im(I) <= (OTHERS => '0');
124 fft_5_re(I) <= (OTHERS => '0');
125 fft_5_im(I) <= (OTHERS => '0');
126 END LOOP all_data;
127 fft_1_re(8*0) <= x"0fff";
128 fft_1_im(8*0) <= x"0010";
129 fft_2_re(8*1) <= x"0010";
130 fft_2_im(8*1+1) <= x"0040";
131 fft_3_re(8*2) <= x"0010";
132 fft_3_im(8*3) <= x"0100";
133 fft_4_re(8*4) <= x"0001";
134 fft_4_im(8*5) <= x"0111";
135 fft_5_re(8*6) <= x"0033";
136 fft_5_im(8*7) <= x"0444";
137
138 counter_1 <= 0;
139 counter_2 <= 0;
140 counter_3 <= 0;
141 counter_4 <= 0;
142 counter_5 <= 0;
143
144 MEM_IN_SM_wen <= (OTHERS => '1');
145 MEM_OUT_SM_ren <= (OTHERS => '1');
146
147 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
148 IF MEM_IN_SM_locked_out(0) = '0' AND MEM_IN_SM_Full_out(0) = '0' THEN
149 counter_1 <= counter_1 + 1;
150 MEM_IN_SM_wData(15 DOWNTO 0) <= fft_1_re(counter_1);
151 MEM_IN_SM_wData(31 DOWNTO 16) <= fft_1_im(counter_1);
152 MEM_IN_SM_wen(0) <= '0';
153 ELSE
154 counter_1 <= 0;
155 MEM_IN_SM_wData(31 DOWNTO 0) <= (OTHERS => 'X');
156 MEM_IN_SM_wen(0) <= '1';
157 END IF;
158
159 END IF;
160 END PROCESS;
161
162
163
164
165
166
167
168
169 -------------------------------------------------------------------------------
170 -- MS ------------------------------------------------------------------------
171 -------------------------------------------------------------------------------
172
173 --lpp_lfr_apbreg_1 : lpp_lfr_apbreg_tb
174 -- GENERIC MAP (
175 -- pindex => 15,
176 -- paddr => 15,
177 -- pmask => 16#fff#)
178 -- PORT MAP (
179 -- HCLK => clk,
180 -- HRESETn => rstn,
181 -- apbi => apbi,
182 -- apbo => apbo,
183
184 -- MEM_IN_SM_wData => MEM_IN_SM_wData,
185 -- MEM_IN_SM_wen => MEM_IN_SM_wen,
186 -- MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
187 -- MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
188 -- MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
189
190 -- MEM_OUT_SM_ren => MEM_OUT_SM_ren ,
191 -- MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
192 -- MEM_OUT_SM_Full => MEM_OUT_SM_Full_pad ,
193 -- MEM_OUT_SM_Full_2 => MEM_OUT_SM_Full_pad_2 ,
194 -- MEM_OUT_SM_Empty => MEM_OUT_SM_Empty_pad);
195
196 lpp_lfr_ms_tb_1 : lpp_lfr_ms_tb
197 GENERIC MAP (
198 Mem_use => use_CEL)
199 PORT MAP (
200 clk => clk,
201 rstn => rstn,
202
203 MEM_IN_SM_wData => MEM_IN_SM_wData,
204 MEM_IN_SM_wen => MEM_IN_SM_wen,
205 MEM_IN_SM_Full_out => MEM_IN_SM_Full_out,
206 MEM_IN_SM_Empty_out => MEM_IN_SM_Empty_out,
207 MEM_IN_SM_locked_out => MEM_IN_SM_locked_out,
208
209 MEM_OUT_SM_Read => MEM_OUT_SM_ren ,
210 MEM_OUT_SM_Data_out => MEM_OUT_SM_Data_out ,
211 MEM_OUT_SM_Full_pad => MEM_OUT_SM_Full_pad ,
212 MEM_OUT_SM_Full_pad_2 => MEM_OUT_SM_Full_pad_2 ,
213 MEM_OUT_SM_Empty_pad => MEM_OUT_SM_Empty_pad,
214
215 error_input_fifo_write => OPEN,
216 observation_vector_0 => OPEN,
217 observation_vector_1 => OPEN);
218
219 -----------------------------------------------------------------------------
220 END tb;
Show file before | Show file after | Hide comments
@@ -0,0 +1,41
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench_ms/clk
4 add wave -noupdate /testbench_ms/rstn
5 add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_wen
6 add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_wdata
7 add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_locked_out
8 add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_full_out
9 add wave -noupdate -expand -group IN /testbench_ms/lpp_lfr_ms_tb_1/mem_in_sm_empty_out
10 add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_read
11 add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_full_pad_2
12 add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_full_pad
13 add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_empty_pad
14 add wave -noupdate -expand -group OUT /testbench_ms/lpp_lfr_ms_tb_1/mem_out_sm_data_out
15 add wave -noupdate -subitemconfig {/testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(56) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(57) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(58) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(59) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(60) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(61) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(62) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(63) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(64) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(65) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(66) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(67) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(68) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(69) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(70) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(71) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(72) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(73) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(74) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(75) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(76) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(77) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(78) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(79) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(80) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(81) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(82) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(83) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(84) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(85) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(86) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(87) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(88) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(89) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(90) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(91) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(92) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(93) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(94) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(95) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(96) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(97) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(98) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(99) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(100) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(101) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(102) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(103) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(104) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(105) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(106) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(107) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(108) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(109) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(110) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(111) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(112) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(113) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(114) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(115) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(116) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(117) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(118) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(119) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(120) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(121) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(122) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(123) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(124) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(125) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(126) {-radix hexadecimal} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(127) {-radix hexadecimal}} /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
16 add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
17 add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
18 add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
19 add wave -noupdate /testbench_ms/lpp_lfr_ms_tb_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
20 add wave -noupdate /testbench_ms/counter_1
21 add wave -noupdate /testbench_ms/counter_2
22 add wave -noupdate /testbench_ms/counter_3
23 add wave -noupdate /testbench_ms/counter_4
24 add wave -noupdate /testbench_ms/counter_5
25 TreeUpdate [SetDefaultTree]
26 WaveRestoreCursors {{Cursor 1} {1282611 ps} 0}
27 configure wave -namecolwidth 564
28 configure wave -valuecolwidth 100
29 configure wave -justifyvalue left
30 configure wave -signalnamewidth 0
31 configure wave -snapdistance 10
32 configure wave -datasetprefix 0
33 configure wave -rowmargin 4
34 configure wave -childrowmargin 2
35 configure wave -gridoffset 0
36 configure wave -gridperiod 1
37 configure wave -griddelta 40
38 configure wave -timeline 0
39 configure wave -timelineunits ns
40 update
41 WaveRestoreZoom {0 ps} {23625 ns}
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@@ -1,51 +1,52
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 #VHDLSIMFILES=testbench.vhd
17 #VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
23 CLEAN=soft-clean
24
24
25 TECHLIBS = proasic3e
25 TECHLIBS = proasic3e
26
26
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc
28 tmtc openchip hynix ihp gleichmann micron usbhc
29
29
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
36 ./lpp_bootloader \
37 ./lpp_cna \
37 ./lpp_cna \
38 ./dsp/lpp_fft_rtax \
38 ./lpp_uart \
39 ./lpp_uart \
39 ./lpp_usb \
40 ./lpp_usb \
40
41
41 FILESKIP = i2cmst.vhd \
42 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 Top_MatrixSpec.vhd \
45 APB_FFT.vhd
46 APB_FFT.vhd
46
47
47 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/software/leon3/Makefile
49 include $(GRLIB)/software/leon3/Makefile
49
50
50 ################## project specific targets ##########################
51 ################## project specific targets ##########################
51
52
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@@ -1,46 +1,47
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
17 CLEAN=soft-clean
18
18
19 TECHLIBS = proasic3e
19 TECHLIBS = proasic3e
20
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
29 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
30 ./lpp_bootloader \
31 ./lpp_cna \
31 ./lpp_cna \
32 ./lpp_uart \
32 ./lpp_uart \
33 ./lpp_usb \
33 ./lpp_usb \
34 ./dsp/lpp_fft_rtax \
34 ./lpp_sim/CY7C1061DV33 \
35 ./lpp_sim/CY7C1061DV33 \
35
36
36 FILESKIP =i2cmst.vhd \
37 FILESKIP =i2cmst.vhd \
37 APB_MULTI_DIODE.vhd \
38 APB_MULTI_DIODE.vhd \
38 APB_SIMPLE_DIODE.vhd \
39 APB_SIMPLE_DIODE.vhd \
39 Top_MatrixSpec.vhd \
40 Top_MatrixSpec.vhd \
40 APB_FFT.vhd
41 APB_FFT.vhd
41
42
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44 include $(GRLIB)/software/leon3/Makefile
44
45
45 ################## project specific targets ##########################
46 ################## project specific targets ##########################
46
47
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@@ -1,27 +1,28
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./general_purpose
2 ./general_purpose
3 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
4 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
5 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
6 ./lpp_amba
7 ./dsp/iir_filter
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 ./dsp/lpp_fft
10 ./dsp/lpp_fft_rtax
10 ./lfr_time_management
11 ./lfr_time_management
11 ./lpp_ad_Conv
12 ./lpp_ad_Conv
12 ./lpp_bootloader
13 ./lpp_bootloader
13 ./lpp_cna
14 ./lpp_cna
14 ./lpp_spectral_matrix
15 ./lpp_spectral_matrix
15 ./lpp_demux
16 ./lpp_demux
16 ./lpp_Header
17 ./lpp_Header
17 ./lpp_matrix
18 ./lpp_matrix
18 ./lpp_memory
19 ./lpp_memory
19 ./lpp_dma
20 ./lpp_dma
20 ./lpp_uart
21 ./lpp_uart
21 ./lpp_usb
22 ./lpp_usb
22 ./lpp_waveform
23 ./lpp_waveform
23 ./lpp_top_lfr
24 ./lpp_top_lfr
24 ./lpp_Header
25 ./lpp_Header
25 ./lpp_leon3_soc
26 ./lpp_leon3_soc
26 ./lpp_debug_lfr
27 ./lpp_debug_lfr
27 ./lpp_sim/CY7C1061DV33
28 ./lpp_sim/CY7C1061DV33
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@@ -1,80 +1,127
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27
27
28 PACKAGE lpp_leon3_soc_pkg IS
28 PACKAGE lpp_leon3_soc_pkg IS
29
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
33
34 COMPONENT leon3_soc
34 COMPONENT leon3_soc
35 GENERIC (
35 GENERIC (
36 fabtech : INTEGER;
36 fabtech : INTEGER;
37 memtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
43 clk_freq : INTEGER;
44 NB_CPU : INTEGER;
44 NB_CPU : INTEGER;
45 ENABLE_FPU : INTEGER;
45 ENABLE_FPU : INTEGER;
46 FPU_NETLIST : INTEGER;
46 FPU_NETLIST : INTEGER;
47 ENABLE_DSU : INTEGER;
47 ENABLE_DSU : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
50 ENABLE_IRQMP : INTEGER;
50 ENABLE_IRQMP : INTEGER;
51 ENABLE_GPT : INTEGER;
51 ENABLE_GPT : INTEGER;
52 NB_AHB_MASTER : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER);
54 NB_APB_SLAVE : INTEGER);
55 PORT (
55 PORT (
56 clk : IN STD_ULOGIC;
56 clk : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
58 errorn : OUT STD_ULOGIC;
58 errorn : OUT STD_ULOGIC;
59 ahbrxd : IN STD_ULOGIC;
59 ahbrxd : IN STD_ULOGIC;
60 ahbtxd : OUT STD_ULOGIC;
60 ahbtxd : OUT STD_ULOGIC;
61 urxd1 : IN STD_ULOGIC;
61 urxd1 : IN STD_ULOGIC;
62 utxd1 : OUT STD_ULOGIC;
62 utxd1 : OUT STD_ULOGIC;
63 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
64 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE0 : OUT STD_LOGIC;
66 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE1 : OUT STD_LOGIC;
67 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE2 : OUT STD_LOGIC;
68 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_BE3 : OUT STD_LOGIC;
69 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_WE : OUT STD_LOGIC;
70 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_CE : OUT STD_LOGIC;
71 nSRAM_OE : OUT STD_LOGIC;
71 nSRAM_OE : OUT STD_LOGIC;
72 apbi_ext : OUT apb_slv_in_type;
72 apbi_ext : OUT apb_slv_in_type;
73 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
73 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
74 ahbi_s_ext : OUT ahb_slv_in_type;
74 ahbi_s_ext : OUT ahb_slv_in_type;
75 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
75 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
76 ahbi_m_ext : OUT AHB_Mst_In_Type;
76 ahbi_m_ext : OUT AHB_Mst_In_Type;
77 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
77 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
78 END COMPONENT;
78 END COMPONENT;
79
80
81 COMPONENT leon3ft_soc
82 GENERIC (
83 fabtech : INTEGER;
84 memtech : INTEGER;
85 padtech : INTEGER;
86 clktech : INTEGER;
87 disas : INTEGER;
88 dbguart : INTEGER;
89 pclow : INTEGER;
90 clk_freq : INTEGER;
91 NB_CPU : INTEGER;
92 ENABLE_FPU : INTEGER;
93 FPU_NETLIST : INTEGER;
94 ENABLE_DSU : INTEGER;
95 ENABLE_AHB_UART : INTEGER;
96 ENABLE_APB_UART : INTEGER;
97 ENABLE_IRQMP : INTEGER;
98 ENABLE_GPT : INTEGER;
99 NB_AHB_MASTER : INTEGER;
100 NB_AHB_SLAVE : INTEGER;
101 NB_APB_SLAVE : INTEGER);
102 PORT (
103 clk : IN STD_ULOGIC;
104 reset : IN STD_ULOGIC;
105 errorn : OUT STD_ULOGIC;
106 ahbrxd : IN STD_ULOGIC;
107 ahbtxd : OUT STD_ULOGIC;
108 urxd1 : IN STD_ULOGIC;
109 utxd1 : OUT STD_ULOGIC;
110 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
111 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
112 nSRAM_BE0 : OUT STD_LOGIC;
113 nSRAM_BE1 : OUT STD_LOGIC;
114 nSRAM_BE2 : OUT STD_LOGIC;
115 nSRAM_BE3 : OUT STD_LOGIC;
116 nSRAM_WE : OUT STD_LOGIC;
117 nSRAM_CE : OUT STD_LOGIC;
118 nSRAM_OE : OUT STD_LOGIC;
119 apbi_ext : OUT apb_slv_in_type;
120 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
121 ahbi_s_ext : OUT ahb_slv_in_type;
122 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
123 ahbi_m_ext : OUT AHB_Mst_In_Type;
124 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
125 END COMPONENT;
79
126
80 END;
127 END;
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@@ -1,2 +1,3
1 lpp_leon3_soc_pkg.vhd
1 lpp_leon3_soc_pkg.vhd
2 leon3_soc.vhd
2 leon3_soc.vhd
3 leon3ft_soc.vhd
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