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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- HK ---------------------------------------------------------------------
85 -- HK ---------------------------------------------------------------------
86 HK_smpclk : OUT STD_LOGIC;
86 HK_smpclk : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
89 ---------------------------------------------------------------------------
89 ---------------------------------------------------------------------------
90 TAG8 : OUT STD_LOGIC;
90 TAG8 : OUT STD_LOGIC;
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
92 );
92 );
93
93
94 END LFR_em;
94 END LFR_em;
95
95
96
96
97 ARCHITECTURE beh OF LFR_em IS
97 ARCHITECTURE beh OF LFR_em IS
98 SIGNAL clk_50_s : STD_LOGIC := '0';
98 SIGNAL clk_50_s : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
101 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
104
104
105 -- CONSTANTS
105 -- CONSTANTS
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
110
110
111 SIGNAL apbi_ext : apb_slv_in_type;
111 SIGNAL apbi_ext : apb_slv_in_type;
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
117
117
118 -- Spacewire signals
118 -- Spacewire signals
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
125 SIGNAL swni : grspw_in_type;
125 SIGNAL swni : grspw_in_type;
126 SIGNAL swno : grspw_out_type;
126 SIGNAL swno : grspw_out_type;
127
127
128 --GPIO
128 --GPIO
129 SIGNAL gpioi : gpio_in_type;
129 SIGNAL gpioi : gpio_in_type;
130 SIGNAL gpioo : gpio_out_type;
130 SIGNAL gpioo : gpio_out_type;
131
131
132 -- AD Converter ADS7886
132 -- AD Converter ADS7886
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
135 SIGNAL sample_val : STD_LOGIC;
135 SIGNAL sample_val : STD_LOGIC;
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
140
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142 SIGNAL rstn : STD_LOGIC;
142 SIGNAL rstn : STD_LOGIC;
143
143
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
146
146
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
150
150
151 BEGIN -- beh
151 BEGIN -- beh
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 -- CLK
154 -- CLK
155 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
157
157
158 PROCESS(clk100MHz)
158 PROCESS(clk100MHz)
159 BEGIN
159 BEGIN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
161 clk_50_s <= NOT clk_50_s;
161 clk_50_s <= NOT clk_50_s;
162 END IF;
162 END IF;
163 END PROCESS;
163 END PROCESS;
164
164
165 PROCESS(clk_50_s)
165 PROCESS(clk_50_s)
166 BEGIN
166 BEGIN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
168 clk_25 <= NOT clk_25;
168 clk_25 <= NOT clk_25;
169 END IF;
169 END IF;
170 END PROCESS;
170 END PROCESS;
171
171
172 PROCESS(clk49_152MHz)
172 PROCESS(clk49_152MHz)
173 BEGIN
173 BEGIN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 clk_24 <= NOT clk_24;
175 clk_24 <= NOT clk_24;
176 END IF;
176 END IF;
177 END PROCESS;
177 END PROCESS;
178
178
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180
180
181 PROCESS (clk_25, rstn)
181 PROCESS (clk_25, rstn)
182 BEGIN -- PROCESS
182 BEGIN -- PROCESS
183 IF rstn = '0' THEN -- asynchronous reset (active low)
183 IF rstn = '0' THEN -- asynchronous reset (active low)
184 led(0) <= '0';
184 led(0) <= '0';
185 led(1) <= '0';
185 led(1) <= '0';
186 led(2) <= '0';
186 led(2) <= '0';
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
188 led(0) <= '0';
188 led(0) <= '0';
189 led(1) <= '1';
189 led(1) <= '1';
190 led(2) <= '1';
190 led(2) <= '1';
191 END IF;
191 END IF;
192 END PROCESS;
192 END PROCESS;
193
193
194 --
194 --
195 leon3_soc_1 : leon3_soc
195 leon3_soc_1 : leon3_soc
196 GENERIC MAP (
196 GENERIC MAP (
197 fabtech => apa3e,
197 fabtech => apa3e,
198 memtech => apa3e,
198 memtech => apa3e,
199 padtech => inferred,
199 padtech => inferred,
200 clktech => inferred,
200 clktech => inferred,
201 disas => 0,
201 disas => 0,
202 dbguart => 0,
202 dbguart => 0,
203 pclow => 2,
203 pclow => 2,
204 clk_freq => 25000,
204 clk_freq => 25000,
205 IS_RADHARD => 0,
205 NB_CPU => 1,
206 NB_CPU => 1,
206 ENABLE_FPU => 1,
207 ENABLE_FPU => 1,
207 FPU_NETLIST => 0,
208 FPU_NETLIST => 0,
208 ENABLE_DSU => 1,
209 ENABLE_DSU => 1,
209 ENABLE_AHB_UART => 1,
210 ENABLE_AHB_UART => 1,
210 ENABLE_APB_UART => 1,
211 ENABLE_APB_UART => 1,
211 ENABLE_IRQMP => 1,
212 ENABLE_IRQMP => 1,
212 ENABLE_GPT => 1,
213 ENABLE_GPT => 1,
213 NB_AHB_MASTER => NB_AHB_MASTER,
214 NB_AHB_MASTER => NB_AHB_MASTER,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 NB_APB_SLAVE => NB_APB_SLAVE,
216 NB_APB_SLAVE => NB_APB_SLAVE,
216 ADDRESS_SIZE => 20,
217 ADDRESS_SIZE => 20,
217 USES_IAP_MEMCTRLR => 0)
218 USES_IAP_MEMCTRLR => 0)
218 PORT MAP (
219 PORT MAP (
219 clk => clk_25,
220 clk => clk_25,
220 reset => rstn,
221 reset => rstn,
221 errorn => OPEN,
222 errorn => OPEN,
222
223
223 ahbrxd => TAG1,
224 ahbrxd => TAG1,
224 ahbtxd => TAG3,
225 ahbtxd => TAG3,
225 urxd1 => TAG2,
226 urxd1 => TAG2,
226 utxd1 => TAG4,
227 utxd1 => TAG4,
227
228
228 address => address,
229 address => address,
229 data => data,
230 data => data,
230 nSRAM_BE0 => nSRAM_BE0,
231 nSRAM_BE0 => nSRAM_BE0,
231 nSRAM_BE1 => nSRAM_BE1,
232 nSRAM_BE1 => nSRAM_BE1,
232 nSRAM_BE2 => nSRAM_BE2,
233 nSRAM_BE2 => nSRAM_BE2,
233 nSRAM_BE3 => nSRAM_BE3,
234 nSRAM_BE3 => nSRAM_BE3,
234 nSRAM_WE => nSRAM_WE,
235 nSRAM_WE => nSRAM_WE,
235 nSRAM_CE => nSRAM_CE_s,
236 nSRAM_CE => nSRAM_CE_s,
236 nSRAM_OE => nSRAM_OE,
237 nSRAM_OE => nSRAM_OE,
237 nSRAM_READY => '0',
238 nSRAM_READY => '0',
238 SRAM_MBE => OPEN,
239 SRAM_MBE => OPEN,
239
240
240 apbi_ext => apbi_ext,
241 apbi_ext => apbi_ext,
241 apbo_ext => apbo_ext,
242 apbo_ext => apbo_ext,
242 ahbi_s_ext => ahbi_s_ext,
243 ahbi_s_ext => ahbi_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
244 ahbo_s_ext => ahbo_s_ext,
244 ahbi_m_ext => ahbi_m_ext,
245 ahbi_m_ext => ahbi_m_ext,
245 ahbo_m_ext => ahbo_m_ext);
246 ahbo_m_ext => ahbo_m_ext);
246
247
247
248
248 nSRAM_CE <= nSRAM_CE_s(0);
249 nSRAM_CE <= nSRAM_CE_s(0);
249
250
250 -------------------------------------------------------------------------------
251 -------------------------------------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 -------------------------------------------------------------------------------
253 -------------------------------------------------------------------------------
253 apb_lfr_management_1 : apb_lfr_management
254 apb_lfr_management_1 : apb_lfr_management
254 GENERIC MAP (
255 GENERIC MAP (
255 pindex => 6,
256 pindex => 6,
256 paddr => 6,
257 paddr => 6,
257 pmask => 16#fff#,
258 pmask => 16#fff#,
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
259 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
260 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
260 PORT MAP (
261 PORT MAP (
261 clk25MHz => clk_25,
262 clk25MHz => clk_25,
262 clk24_576MHz => clk_24, -- 49.152MHz/2
263 clk24_576MHz => clk_24, -- 49.152MHz/2
263 resetn => rstn,
264 resetn => rstn,
264 grspw_tick => swno.tickout,
265 grspw_tick => swno.tickout,
265 apbi => apbi_ext,
266 apbi => apbi_ext,
266 apbo => apbo_ext(6),
267 apbo => apbo_ext(6),
267
268
268 HK_sample => sample_s(8),
269 HK_sample => sample_s(8),
269 HK_val => sample_val,
270 HK_val => sample_val,
270 HK_sel => HK_SEL,
271 HK_sel => HK_SEL,
271
272
272 coarse_time => coarse_time,
273 coarse_time => coarse_time,
273 fine_time => fine_time,
274 fine_time => fine_time,
274 LFR_soft_rstn => LFR_soft_rstn
275 LFR_soft_rstn => LFR_soft_rstn
275 );
276 );
276
277
277 -----------------------------------------------------------------------
278 -----------------------------------------------------------------------
278 --- SpaceWire --------------------------------------------------------
279 --- SpaceWire --------------------------------------------------------
279 -----------------------------------------------------------------------
280 -----------------------------------------------------------------------
280
281
281 -- SPW_EN <= '1';
282 -- SPW_EN <= '1';
282
283
283 spw_clk <= clk_50_s;
284 spw_clk <= clk_50_s;
284 spw_rxtxclk <= spw_clk;
285 spw_rxtxclk <= spw_clk;
285 spw_rxclkn <= NOT spw_rxtxclk;
286 spw_rxclkn <= NOT spw_rxtxclk;
286
287
287 -- PADS for SPW1
288 -- PADS for SPW1
288 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
289 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
289 PORT MAP (spw1_din, dtmp(0));
290 PORT MAP (spw1_din, dtmp(0));
290 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
291 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
291 PORT MAP (spw1_sin, stmp(0));
292 PORT MAP (spw1_sin, stmp(0));
292 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
293 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
293 PORT MAP (spw1_dout, swno.d(0));
294 PORT MAP (spw1_dout, swno.d(0));
294 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
295 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
295 PORT MAP (spw1_sout, swno.s(0));
296 PORT MAP (spw1_sout, swno.s(0));
296 -- PADS FOR SPW2
297 -- PADS FOR SPW2
297 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
298 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
298 PORT MAP (spw2_din, dtmp(1));
299 PORT MAP (spw2_din, dtmp(1));
299 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
300 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
300 PORT MAP (spw2_sin, stmp(1));
301 PORT MAP (spw2_sin, stmp(1));
301 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
302 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
302 PORT MAP (spw2_dout, swno.d(1));
303 PORT MAP (spw2_dout, swno.d(1));
303 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
304 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
304 PORT MAP (spw2_sout, swno.s(1));
305 PORT MAP (spw2_sout, swno.s(1));
305
306
306 -- GRSPW PHY
307 -- GRSPW PHY
307 --spw1_input: if CFG_SPW_GRSPW = 1 generate
308 --spw1_input: if CFG_SPW_GRSPW = 1 generate
308 spw_inputloop : FOR j IN 0 TO 1 GENERATE
309 spw_inputloop : FOR j IN 0 TO 1 GENERATE
309 spw_phy0 : grspw_phy
310 spw_phy0 : grspw_phy
310 GENERIC MAP(
311 GENERIC MAP(
311 tech => apa3e,
312 tech => apa3e,
312 rxclkbuftype => 1,
313 rxclkbuftype => 1,
313 scantest => 0)
314 scantest => 0)
314 PORT MAP(
315 PORT MAP(
315 rxrst => swno.rxrst,
316 rxrst => swno.rxrst,
316 di => dtmp(j),
317 di => dtmp(j),
317 si => stmp(j),
318 si => stmp(j),
318 rxclko => spw_rxclk(j),
319 rxclko => spw_rxclk(j),
319 do => swni.d(j),
320 do => swni.d(j),
320 ndo => swni.nd(j*5+4 DOWNTO j*5),
321 ndo => swni.nd(j*5+4 DOWNTO j*5),
321 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
322 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
322 END GENERATE spw_inputloop;
323 END GENERATE spw_inputloop;
323
324
324 -- SPW core
325 -- SPW core
325 sw0 : grspwm GENERIC MAP(
326 sw0 : grspwm GENERIC MAP(
326 tech => apa3e,
327 tech => apa3e,
327 hindex => 1,
328 hindex => 1,
328 pindex => 5,
329 pindex => 5,
329 paddr => 5,
330 paddr => 5,
330 pirq => 11,
331 pirq => 11,
331 sysfreq => 25000, -- CPU_FREQ
332 sysfreq => 25000, -- CPU_FREQ
332 rmap => 1,
333 rmap => 1,
333 rmapcrc => 1,
334 rmapcrc => 1,
334 fifosize1 => 16,
335 fifosize1 => 16,
335 fifosize2 => 16,
336 fifosize2 => 16,
336 rxclkbuftype => 1,
337 rxclkbuftype => 1,
337 rxunaligned => 0,
338 rxunaligned => 0,
338 rmapbufs => 4,
339 rmapbufs => 4,
339 ft => 0,
340 ft => 0,
340 netlist => 0,
341 netlist => 0,
341 ports => 2,
342 ports => 2,
342 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
343 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
343 memtech => apa3e,
344 memtech => apa3e,
344 destkey => 2,
345 destkey => 2,
345 spwcore => 1
346 spwcore => 1
346 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
347 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
347 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
348 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
348 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
349 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
349 )
350 )
350 PORT MAP(rstn, clk_25, spw_rxclk(0),
351 PORT MAP(rstn, clk_25, spw_rxclk(0),
351 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
352 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
352 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
353 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
353 swni, swno);
354 swni, swno);
354
355
355 swni.tickin <= '0';
356 swni.tickin <= '0';
356 swni.rmapen <= '1';
357 swni.rmapen <= '1';
357 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
358 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
358 swni.tickinraw <= '0';
359 swni.tickinraw <= '0';
359 swni.timein <= (OTHERS => '0');
360 swni.timein <= (OTHERS => '0');
360 swni.dcrstval <= (OTHERS => '0');
361 swni.dcrstval <= (OTHERS => '0');
361 swni.timerrstval <= (OTHERS => '0');
362 swni.timerrstval <= (OTHERS => '0');
362
363
363 -------------------------------------------------------------------------------
364 -------------------------------------------------------------------------------
364 -- LFR ------------------------------------------------------------------------
365 -- LFR ------------------------------------------------------------------------
365 -------------------------------------------------------------------------------
366 -------------------------------------------------------------------------------
366 LFR_rstn <= LFR_soft_rstn AND rstn;
367 LFR_rstn <= LFR_soft_rstn AND rstn;
367
368
368 lpp_lfr_1 : lpp_lfr
369 lpp_lfr_1 : lpp_lfr
369 GENERIC MAP (
370 GENERIC MAP (
370 Mem_use => use_RAM,
371 Mem_use => use_RAM,
371 nb_data_by_buffer_size => 32,
372 nb_data_by_buffer_size => 32,
372 --nb_word_by_buffer_size => 30,
373 --nb_word_by_buffer_size => 30,
373 nb_snapshot_param_size => 32,
374 nb_snapshot_param_size => 32,
374 delta_vector_size => 32,
375 delta_vector_size => 32,
375 delta_vector_size_f0_2 => 7, -- log2(96)
376 delta_vector_size_f0_2 => 7, -- log2(96)
376 pindex => 15,
377 pindex => 15,
377 paddr => 15,
378 paddr => 15,
378 pmask => 16#fff#,
379 pmask => 16#fff#,
379 pirq_ms => 6,
380 pirq_ms => 6,
380 pirq_wfp => 14,
381 pirq_wfp => 14,
381 hindex => 2,
382 hindex => 2,
382 top_lfr_version => X"010138") -- aa.bb.cc version
383 top_lfr_version => X"010139") -- aa.bb.cc version
383 -- AA : BOARD NUMBER
384 -- AA : BOARD NUMBER
384 -- 0 => MINI_LFR
385 -- 0 => MINI_LFR
385 -- 1 => EM
386 -- 1 => EM
386 PORT MAP (
387 PORT MAP (
387 clk => clk_25,
388 clk => clk_25,
388 rstn => LFR_rstn,
389 rstn => LFR_rstn,
389 sample_B => sample_s(2 DOWNTO 0),
390 sample_B => sample_s(2 DOWNTO 0),
390 sample_E => sample_s(7 DOWNTO 3),
391 sample_E => sample_s(7 DOWNTO 3),
391 sample_val => sample_val,
392 sample_val => sample_val,
392 apbi => apbi_ext,
393 apbi => apbi_ext,
393 apbo => apbo_ext(15),
394 apbo => apbo_ext(15),
394 ahbi => ahbi_m_ext,
395 ahbi => ahbi_m_ext,
395 ahbo => ahbo_m_ext(2),
396 ahbo => ahbo_m_ext(2),
396 coarse_time => coarse_time,
397 coarse_time => coarse_time,
397 fine_time => fine_time,
398 fine_time => fine_time,
398 data_shaping_BW => bias_fail_sw,
399 data_shaping_BW => bias_fail_sw,
399 debug_vector => OPEN,
400 debug_vector => OPEN,
400 debug_vector_ms => OPEN); --,
401 debug_vector_ms => OPEN); --,
401 --observation_vector_0 => OPEN,
402 --observation_vector_0 => OPEN,
402 --observation_vector_1 => OPEN,
403 --observation_vector_1 => OPEN,
403 --observation_reg => observation_reg);
404 --observation_reg => observation_reg);
404
405
405
406
406 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
407 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
407 sample_s(I) <= sample(I) & '0' & '0';
408 sample_s(I) <= sample(I) & '0' & '0';
408 END GENERATE all_sample;
409 END GENERATE all_sample;
409 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
410 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
410
411
411 -----------------------------------------------------------------------------
412 -----------------------------------------------------------------------------
412 --
413 --
413 -----------------------------------------------------------------------------
414 -----------------------------------------------------------------------------
414 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
415 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
415 GENERIC MAP (
416 GENERIC MAP (
416 ChanelCount => 9,
417 ChanelCount => 9,
417 ncycle_cnv_high => 13,
418 ncycle_cnv_high => 13,
418 ncycle_cnv => 25,
419 ncycle_cnv => 25,
419 FILTER_ENABLED => 16#FF#)
420 FILTER_ENABLED => 16#FF#)
420 PORT MAP (
421 PORT MAP (
421 cnv_clk => clk_24,
422 cnv_clk => clk_24,
422 cnv_rstn => rstn,
423 cnv_rstn => rstn,
423 cnv => ADC_smpclk_s,
424 cnv => ADC_smpclk_s,
424 clk => clk_25,
425 clk => clk_25,
425 rstn => rstn,
426 rstn => rstn,
426 ADC_data => ADC_data,
427 ADC_data => ADC_data,
427 ADC_nOE => ADC_OEB_bar_CH_s,
428 ADC_nOE => ADC_OEB_bar_CH_s,
428 sample => sample,
429 sample => sample,
429 sample_val => sample_val);
430 sample_val => sample_val);
430
431
431 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
432 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
432
433
433 ADC_smpclk <= ADC_smpclk_s;
434 ADC_smpclk <= ADC_smpclk_s;
434 HK_smpclk <= ADC_smpclk_s;
435 HK_smpclk <= ADC_smpclk_s;
435
436
436 TAG8 <= ADC_smpclk_s;
437 TAG8 <= ADC_smpclk_s;
437
438
438 -----------------------------------------------------------------------------
439 -----------------------------------------------------------------------------
439 -- HK
440 -- HK
440 -----------------------------------------------------------------------------
441 -----------------------------------------------------------------------------
441 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
442 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
442
443
443 END beh;
444 END beh;
Show file before | Show file after | Hide comments
@@ -1,387 +1,396
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_management.ALL;
30 USE lpp.lpp_lfr_management.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32
32
33
33
34 ENTITY apb_lfr_management IS
34 ENTITY apb_lfr_management IS
35
35
36 GENERIC(
36 GENERIC(
37 pindex : INTEGER := 0; --! APB slave index
37 pindex : INTEGER := 0; --! APB slave index
38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
40 FIRST_DIVISION : INTEGER := 374;
40 FIRST_DIVISION : INTEGER := 374;
41 NB_SECOND_DESYNC : INTEGER := 60
41 NB_SECOND_DESYNC : INTEGER := 60
42 );
42 );
43
43
44 PORT (
44 PORT (
45 clk25MHz : IN STD_LOGIC; --! Clock
45 clk25MHz : IN STD_LOGIC; --! Clock
46 clk24_576MHz : IN STD_LOGIC; --! secondary clock
46 clk24_576MHz : IN STD_LOGIC; --! secondary clock
47 resetn : IN STD_LOGIC; --! Reset
47 resetn : IN STD_LOGIC; --! Reset
48
48
49 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
50
50
51 apbi : IN apb_slv_in_type; --! APB slave input signals
51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
53 ---------------------------------------------------------------------------
53 ---------------------------------------------------------------------------
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
54 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
55 HK_val : IN STD_LOGIC;
55 HK_val : IN STD_LOGIC;
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
56 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
57 ---------------------------------------------------------------------------
57 ---------------------------------------------------------------------------
58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
58 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
59 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 LFR_soft_rstn : OUT STD_LOGIC
61 LFR_soft_rstn : OUT STD_LOGIC
62 );
62 );
63
63
64 END apb_lfr_management;
64 END apb_lfr_management;
65
65
66 ARCHITECTURE Behavioral OF apb_lfr_management IS
66 ARCHITECTURE Behavioral OF apb_lfr_management IS
67
67
68 CONSTANT REVISION : INTEGER := 1;
68 CONSTANT REVISION : INTEGER := 1;
69 CONSTANT pconfig : apb_config_type := (
69 CONSTANT pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
70 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
71 1 => apb_iobar(paddr, pmask)
71 1 => apb_iobar(paddr, pmask)
72 );
72 );
73
73
74 TYPE apb_lfr_time_management_Reg IS RECORD
74 TYPE apb_lfr_time_management_Reg IS RECORD
75 ctrl : STD_LOGIC;
75 ctrl : STD_LOGIC;
76 soft_reset : STD_LOGIC;
76 soft_reset : STD_LOGIC;
77 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
77 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
79 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 LFR_soft_reset : STD_LOGIC;
80 LFR_soft_reset : STD_LOGIC;
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
82 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
83 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
84 END RECORD;
84 END RECORD;
85 SIGNAL r : apb_lfr_time_management_Reg;
85 SIGNAL r : apb_lfr_time_management_Reg;
86
86
87 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 SIGNAL force_tick : STD_LOGIC;
88 SIGNAL force_tick : STD_LOGIC;
89 SIGNAL previous_force_tick : STD_LOGIC;
89 SIGNAL previous_force_tick : STD_LOGIC;
90 SIGNAL soft_tick : STD_LOGIC;
90 SIGNAL soft_tick : STD_LOGIC;
91
91
92 SIGNAL coarsetime_reg_updated : STD_LOGIC;
92 SIGNAL coarsetime_reg_updated : STD_LOGIC;
93 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
93 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
94
94
95 --SIGNAL coarse_time_new : STD_LOGIC;
95 --SIGNAL coarse_time_new : STD_LOGIC;
96 SIGNAL coarse_time_new_49 : STD_LOGIC;
96 SIGNAL coarse_time_new_49 : STD_LOGIC;
97 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
99
99
100 --SIGNAL fine_time_new : STD_LOGIC;
100 --SIGNAL fine_time_new : STD_LOGIC;
101 --SIGNAL fine_time_new_temp : STD_LOGIC;
101 --SIGNAL fine_time_new_temp : STD_LOGIC;
102 SIGNAL fine_time_new_49 : STD_LOGIC;
102 SIGNAL fine_time_new_49 : STD_LOGIC;
103 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
103 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
105 SIGNAL tick : STD_LOGIC;
105 SIGNAL tick : STD_LOGIC;
106 SIGNAL new_timecode : STD_LOGIC;
106 SIGNAL new_timecode : STD_LOGIC;
107 SIGNAL new_coarsetime : STD_LOGIC;
107 SIGNAL new_coarsetime : STD_LOGIC;
108
108
109 SIGNAL time_new_49 : STD_LOGIC;
109 SIGNAL time_new_49 : STD_LOGIC;
110 SIGNAL time_new : STD_LOGIC;
110 SIGNAL time_new : STD_LOGIC;
111
111
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113 SIGNAL force_reset : STD_LOGIC;
113 SIGNAL force_reset : STD_LOGIC;
114 SIGNAL previous_force_reset : STD_LOGIC;
114 SIGNAL previous_force_reset : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
115 SIGNAL soft_reset : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
116 SIGNAL soft_reset_sync : STD_LOGIC;
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
118 SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
122
122
123 SIGNAL previous_fine_time_bit : STD_LOGIC;
124
123 SIGNAL rstn_LFR_TM : STD_LOGIC;
125 SIGNAL rstn_LFR_TM : STD_LOGIC;
124
126
125 BEGIN
127 BEGIN
126
128
127 LFR_soft_rstn <= NOT r.LFR_soft_reset;
129 LFR_soft_rstn <= NOT r.LFR_soft_reset;
128
130
129 PROCESS(resetn, clk25MHz)
131 PROCESS(resetn, clk25MHz)
130 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
132 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
131 BEGIN
133 BEGIN
132
134
133 IF resetn = '0' THEN
135 IF resetn = '0' THEN
134 Rdata <= (OTHERS => '0');
136 Rdata <= (OTHERS => '0');
135 r.coarse_time_load <= (OTHERS => '0');
137 r.coarse_time_load <= (OTHERS => '0');
136 r.soft_reset <= '0';
138 r.soft_reset <= '0';
137 r.ctrl <= '0';
139 r.ctrl <= '0';
138 r.LFR_soft_reset <= '1';
140 r.LFR_soft_reset <= '1';
139
141
140 force_tick <= '0';
142 force_tick <= '0';
141 previous_force_tick <= '0';
143 previous_force_tick <= '0';
142 soft_tick <= '0';
144 soft_tick <= '0';
143
145
144 coarsetime_reg_updated <= '0';
146 coarsetime_reg_updated <= '0';
145
147
146 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
148 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
147 coarsetime_reg_updated <= '0';
149 coarsetime_reg_updated <= '0';
148
150
149 force_tick <= r.ctrl;
151 force_tick <= r.ctrl;
150 previous_force_tick <= force_tick;
152 previous_force_tick <= force_tick;
151 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
153 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
152 soft_tick <= '1';
154 soft_tick <= '1';
153 ELSE
155 ELSE
154 soft_tick <= '0';
156 soft_tick <= '0';
155 END IF;
157 END IF;
156
158
157 force_reset <= r.soft_reset;
159 force_reset <= r.soft_reset;
158 previous_force_reset <= force_reset;
160 previous_force_reset <= force_reset;
159 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
161 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
160 soft_reset <= '1';
162 soft_reset <= '1';
161 ELSE
163 ELSE
162 soft_reset <= '0';
164 soft_reset <= '0';
163 END IF;
165 END IF;
164
166
165 paddr := "000000";
167 paddr := "000000";
166 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
168 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
167 Rdata <= (OTHERS => '0');
169 Rdata <= (OTHERS => '0');
168
170
169
171
170 IF apbi.psel(pindex) = '1' THEN
172 IF apbi.psel(pindex) = '1' THEN
171 --APB READ OP
173 --APB READ OP
172 CASE paddr(7 DOWNTO 2) IS
174 CASE paddr(7 DOWNTO 2) IS
173 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
175 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
174 Rdata(0) <= r.ctrl;
176 Rdata(0) <= r.ctrl;
175 Rdata(1) <= r.soft_reset;
177 Rdata(1) <= r.soft_reset;
176 Rdata(2) <= r.LFR_soft_reset;
178 Rdata(2) <= r.LFR_soft_reset;
177 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
179 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
178 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
180 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
179 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
181 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
180 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
182 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
181 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
183 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
182 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
184 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
183 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
185 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
184 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
186 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
185 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
187 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
186 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
188 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
187 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
189 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
188 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
190 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
189 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
191 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
190 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
192 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
191 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
193 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
192 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
194 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
193 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
195 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
194 WHEN OTHERS =>
196 WHEN OTHERS =>
195 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
197 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
196 END CASE;
198 END CASE;
197
199
198 --APB Write OP
200 --APB Write OP
199 IF (apbi.pwrite AND apbi.penable) = '1' THEN
201 IF (apbi.pwrite AND apbi.penable) = '1' THEN
200 CASE paddr(7 DOWNTO 2) IS
202 CASE paddr(7 DOWNTO 2) IS
201 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
203 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
202 r.ctrl <= apbi.pwdata(0);
204 r.ctrl <= apbi.pwdata(0);
203 r.soft_reset <= apbi.pwdata(1);
205 r.soft_reset <= apbi.pwdata(1);
204 r.LFR_soft_reset <= apbi.pwdata(2);
206 r.LFR_soft_reset <= apbi.pwdata(2);
205 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
207 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
206 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
208 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
207 coarsetime_reg_updated <= '1';
209 coarsetime_reg_updated <= '1';
208 WHEN OTHERS =>
210 WHEN OTHERS =>
209 NULL;
211 NULL;
210 END CASE;
212 END CASE;
211 ELSE
213 ELSE
212 IF r.ctrl = '1' THEN
214 IF r.ctrl = '1' THEN
213 r.ctrl <= '0';
215 r.ctrl <= '0';
214 END IF;
216 END IF;
215 IF r.soft_reset = '1' THEN
217 IF r.soft_reset = '1' THEN
216 r.soft_reset <= '0';
218 r.soft_reset <= '0';
217 END IF;
219 END IF;
218 END IF;
220 END IF;
219
221
220 END IF;
222 END IF;
221
223
222 END IF;
224 END IF;
223 END PROCESS;
225 END PROCESS;
224
226
225 apbo.pirq <= (OTHERS => '0');
227 apbo.pirq <= (OTHERS => '0');
226 apbo.prdata <= Rdata;
228 apbo.prdata <= Rdata;
227 apbo.pconfig <= pconfig;
229 apbo.pconfig <= pconfig;
228 apbo.pindex <= pindex;
230 apbo.pindex <= pindex;
229
231
230 -----------------------------------------------------------------------------
232 -----------------------------------------------------------------------------
231 -- IN
233 -- IN
232 coarse_time <= r.coarse_time;
234 coarse_time <= r.coarse_time;
233 fine_time <= r.fine_time;
235 fine_time <= r.fine_time;
234 coarsetime_reg <= r.coarse_time_load;
236 coarsetime_reg <= r.coarse_time_load;
235 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
236
238
237 -----------------------------------------------------------------------------
239 -----------------------------------------------------------------------------
238 -- OUT
240 -- OUT
239 r.coarse_time <= coarse_time_s;
241 r.coarse_time <= coarse_time_s;
240 r.fine_time <= fine_time_s;
242 r.fine_time <= fine_time_s;
241 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
242
244
243 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
244 tick <= grspw_tick OR soft_tick;
246 tick <= grspw_tick OR soft_tick;
245
247
246 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
248 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
247 GENERIC MAP (
249 GENERIC MAP (
248 NB_FF_OF_SYNC => 2)
250 NB_FF_OF_SYNC => 2)
249 PORT MAP (
251 PORT MAP (
250 clk_in => clk25MHz,
252 clk_in => clk25MHz,
251 clk_out => clk24_576MHz,
253 clk_out => clk24_576MHz,
252 rstn => resetn,
254 rstn => resetn,
253 sin => tick,
255 sin => tick,
254 sout => new_timecode);
256 sout => new_timecode);
255
257
256 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
258 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
257 GENERIC MAP (
259 GENERIC MAP (
258 NB_FF_OF_SYNC => 2)
260 NB_FF_OF_SYNC => 2)
259 PORT MAP (
261 PORT MAP (
260 clk_in => clk25MHz,
262 clk_in => clk25MHz,
261 clk_out => clk24_576MHz,
263 clk_out => clk24_576MHz,
262 rstn => resetn,
264 rstn => resetn,
263 sin => coarsetime_reg_updated,
265 sin => coarsetime_reg_updated,
264 sout => new_coarsetime);
266 sout => new_coarsetime);
265
267
266 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
268 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
267 GENERIC MAP (
269 GENERIC MAP (
268 NB_FF_OF_SYNC => 2)
270 NB_FF_OF_SYNC => 2)
269 PORT MAP (
271 PORT MAP (
270 clk_in => clk25MHz,
272 clk_in => clk25MHz,
271 clk_out => clk24_576MHz,
273 clk_out => clk24_576MHz,
272 rstn => resetn,
274 rstn => resetn,
273 sin => soft_reset,
275 sin => soft_reset,
274 sout => soft_reset_sync);
276 sout => soft_reset_sync);
275
277
276 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
277 --SYNC_FF_1 : SYNC_FF
279 --SYNC_FF_1 : SYNC_FF
278 -- GENERIC MAP (
280 -- GENERIC MAP (
279 -- NB_FF_OF_SYNC => 2)
281 -- NB_FF_OF_SYNC => 2)
280 -- PORT MAP (
282 -- PORT MAP (
281 -- clk => clk25MHz,
283 -- clk => clk25MHz,
282 -- rstn => resetn,
284 -- rstn => resetn,
283 -- A => fine_time_new_49,
285 -- A => fine_time_new_49,
284 -- A_sync => fine_time_new_temp);
286 -- A_sync => fine_time_new_temp);
285
287
286 --lpp_front_detection_1 : lpp_front_detection
288 --lpp_front_detection_1 : lpp_front_detection
287 -- PORT MAP (
289 -- PORT MAP (
288 -- clk => clk25MHz,
290 -- clk => clk25MHz,
289 -- rstn => resetn,
291 -- rstn => resetn,
290 -- sin => fine_time_new_temp,
292 -- sin => fine_time_new_temp,
291 -- sout => fine_time_new);
293 -- sout => fine_time_new);
292
294
293 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
295 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
294 -- GENERIC MAP (
296 -- GENERIC MAP (
295 -- NB_FF_OF_SYNC => 2)
297 -- NB_FF_OF_SYNC => 2)
296 -- PORT MAP (
298 -- PORT MAP (
297 -- clk_in => clk24_576MHz,
299 -- clk_in => clk24_576MHz,
298 -- clk_out => clk25MHz,
300 -- clk_out => clk25MHz,
299 -- rstn => resetn,
301 -- rstn => resetn,
300 -- sin => coarse_time_new_49,
302 -- sin => coarse_time_new_49,
301 -- sout => coarse_time_new);
303 -- sout => coarse_time_new);
302
304
303 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
305 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
304
306
305 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
307 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
306 GENERIC MAP (
308 GENERIC MAP (
307 NB_FF_OF_SYNC => 2)
309 NB_FF_OF_SYNC => 2)
308 PORT MAP (
310 PORT MAP (
309 clk_in => clk24_576MHz,
311 clk_in => clk24_576MHz,
310 clk_out => clk25MHz,
312 clk_out => clk25MHz,
311 rstn => resetn,
313 rstn => resetn,
312 sin => time_new_49,
314 sin => time_new_49,
313 sout => time_new);
315 sout => time_new);
314
316
315
317
316
318
317 PROCESS (clk25MHz, resetn)
319 PROCESS (clk25MHz, resetn)
318 BEGIN -- PROCESS
320 BEGIN -- PROCESS
319 IF resetn = '0' THEN -- asynchronous reset (active low)
321 IF resetn = '0' THEN -- asynchronous reset (active low)
320 fine_time_s <= (OTHERS => '0');
322 fine_time_s <= (OTHERS => '0');
321 coarse_time_s <= (OTHERS => '0');
323 coarse_time_s <= (OTHERS => '0');
322 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
324 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
323 IF time_new = '1' THEN
325 IF time_new = '1' THEN
324 fine_time_s <= fine_time_49;
326 fine_time_s <= fine_time_49;
325 coarse_time_s <= coarse_time_49;
327 coarse_time_s <= coarse_time_49;
326 END IF;
328 END IF;
327 END IF;
329 END IF;
328 END PROCESS;
330 END PROCESS;
329
331
330
332
331 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
333 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
332 '0' WHEN soft_reset_sync = '1' ELSE
334 '0' WHEN soft_reset_sync = '1' ELSE
333 '1';
335 '1';
334
336
335
337
336 -----------------------------------------------------------------------------
338 -----------------------------------------------------------------------------
337 -- LFR_TIME_MANAGMENT
339 -- LFR_TIME_MANAGMENT
338 -----------------------------------------------------------------------------
340 -----------------------------------------------------------------------------
339 lfr_time_management_1 : lfr_time_management
341 lfr_time_management_1 : lfr_time_management
340 GENERIC MAP (
342 GENERIC MAP (
341 FIRST_DIVISION => FIRST_DIVISION,
343 FIRST_DIVISION => FIRST_DIVISION,
342 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
344 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
343 PORT MAP (
345 PORT MAP (
344 clk => clk24_576MHz,
346 clk => clk24_576MHz,
345 rstn => rstn_LFR_TM,
347 rstn => rstn_LFR_TM,
346
348
347 tick => new_timecode,
349 tick => new_timecode,
348 new_coarsetime => new_coarsetime,
350 new_coarsetime => new_coarsetime,
349 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
351 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
350
352
351 fine_time => fine_time_49,
353 fine_time => fine_time_49,
352 fine_time_new => fine_time_new_49,
354 fine_time_new => fine_time_new_49,
353 coarse_time => coarse_time_49,
355 coarse_time => coarse_time_49,
354 coarse_time_new => coarse_time_new_49);
356 coarse_time_new => coarse_time_new_49);
355
357
356 -----------------------------------------------------------------------------
358 -----------------------------------------------------------------------------
357 -- HK
359 -- HK
358 -----------------------------------------------------------------------------
360 -----------------------------------------------------------------------------
359
361
360 PROCESS (clk25MHz, resetn)
362 PROCESS (clk25MHz, resetn)
363 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 11; -- freq = 2^(16-BIT)
364 -- for 11, the update frequency is 32Hz
365 -- for each HK, the update frequency is freq/3
361 BEGIN -- PROCESS
366 BEGIN -- PROCESS
362 IF resetn = '0' THEN -- asynchronous reset (active low)
367 IF resetn = '0' THEN -- asynchronous reset (active low)
363
368
364 r.HK_temp_0 <= (OTHERS => '0');
369 r.HK_temp_0 <= (OTHERS => '0');
365 r.HK_temp_1 <= (OTHERS => '0');
370 r.HK_temp_1 <= (OTHERS => '0');
366 r.HK_temp_2 <= (OTHERS => '0');
371 r.HK_temp_2 <= (OTHERS => '0');
367
372
368 HK_sel_s <= "00";
373 HK_sel_s <= "00";
374
375 previous_fine_time_bit <= '0';
369
376
370 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
377 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
371
378
372 IF HK_val = '1' THEN
379 IF HK_val = '1' THEN
373 CASE HK_sel_s IS
380 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
374 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
381 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
375 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
382 CASE HK_sel_s IS
376 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
383 WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
377 WHEN OTHERS => NULL;
384 WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
378 END CASE;
385 WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
379
386 WHEN OTHERS => NULL;
387 END CASE;
388 END IF;
380 END IF;
389 END IF;
381
390
382 END IF;
391 END IF;
383 END PROCESS;
392 END PROCESS;
384
393
385 HK_sel <= HK_sel_s;
394 HK_sel <= HK_sel_s;
386
395
387 END Behavioral;
396 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,565 +1,566
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 LIBRARY iap;
43 LIBRARY iap;
44 USE iap.memctrl.ALL;
44 USE iap.memctrl.ALL;
45
45
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := apa3e;
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
55 pclow : INTEGER := 2;
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 0;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
69 --
69 --
70 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 20;
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0
75 USES_IAP_MEMCTRLR : INTEGER := 0
76
76
77 );
77 );
78 PORT (
78 PORT (
79 clk : IN STD_ULOGIC;
79 clk : IN STD_ULOGIC;
80 reset : IN STD_ULOGIC;
80 reset : IN STD_ULOGIC;
81
81
82 errorn : OUT STD_ULOGIC;
82 errorn : OUT STD_ULOGIC;
83
83
84 -- UART AHB ---------------------------------------------------------------
84 -- UART AHB ---------------------------------------------------------------
85 ahbrxd : IN STD_ULOGIC; -- DSU rx data
85 ahbrxd : IN STD_ULOGIC; -- DSU rx data
86 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
86 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
87
87
88 -- UART APB ---------------------------------------------------------------
88 -- UART APB ---------------------------------------------------------------
89 urxd1 : IN STD_ULOGIC; -- UART1 rx data
89 urxd1 : IN STD_ULOGIC; -- UART1 rx data
90 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
90 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
91
91
92 -- RAM --------------------------------------------------------------------
92 -- RAM --------------------------------------------------------------------
93 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
93 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
94 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 nSRAM_BE0 : OUT STD_LOGIC;
95 nSRAM_BE0 : OUT STD_LOGIC;
96 nSRAM_BE1 : OUT STD_LOGIC;
96 nSRAM_BE1 : OUT STD_LOGIC;
97 nSRAM_BE2 : OUT STD_LOGIC;
97 nSRAM_BE2 : OUT STD_LOGIC;
98 nSRAM_BE3 : OUT STD_LOGIC;
98 nSRAM_BE3 : OUT STD_LOGIC;
99 nSRAM_WE : OUT STD_LOGIC;
99 nSRAM_WE : OUT STD_LOGIC;
100 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 nSRAM_OE : OUT STD_LOGIC;
101 nSRAM_OE : OUT STD_LOGIC;
102 nSRAM_READY : IN STD_LOGIC;
102 nSRAM_READY : IN STD_LOGIC;
103 SRAM_MBE : INOUT STD_LOGIC;
103 SRAM_MBE : INOUT STD_LOGIC;
104 -- APB --------------------------------------------------------------------
104 -- APB --------------------------------------------------------------------
105 apbi_ext : OUT apb_slv_in_type;
105 apbi_ext : OUT apb_slv_in_type;
106 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
106 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
107 -- AHB_Slave --------------------------------------------------------------
107 -- AHB_Slave --------------------------------------------------------------
108 ahbi_s_ext : OUT ahb_slv_in_type;
108 ahbi_s_ext : OUT ahb_slv_in_type;
109 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
109 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
110 -- AHB_Master -------------------------------------------------------------
110 -- AHB_Master -------------------------------------------------------------
111 ahbi_m_ext : OUT AHB_Mst_In_Type;
111 ahbi_m_ext : OUT AHB_Mst_In_Type;
112 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
112 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
113
113
114 );
114 );
115 END;
115 END;
116
116
117 ARCHITECTURE Behavioral OF leon3_soc IS
117 ARCHITECTURE Behavioral OF leon3_soc IS
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 -- CONFIG -------------------------------------------------------------------
120 -- CONFIG -------------------------------------------------------------------
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122
122
123 -- Clock generator
123 -- Clock generator
124 CONSTANT CFG_CLKMUL : INTEGER := (1);
124 CONSTANT CFG_CLKMUL : INTEGER := (1);
125 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
125 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
126 CONSTANT CFG_OCLKDIV : INTEGER := (1);
126 CONSTANT CFG_OCLKDIV : INTEGER := (1);
127 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
127 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
128 -- LEON3 processor core
128 -- LEON3 processor core
129 CONSTANT CFG_LEON3 : INTEGER := 1;
129 CONSTANT CFG_LEON3 : INTEGER := 1;
130 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
130 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
131 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
131 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
132 CONSTANT CFG_V8 : INTEGER := 0;
132 CONSTANT CFG_V8 : INTEGER := 0;
133 CONSTANT CFG_MAC : INTEGER := 0;
133 CONSTANT CFG_MAC : INTEGER := 0;
134 CONSTANT CFG_SVT : INTEGER := 0;
134 CONSTANT CFG_SVT : INTEGER := 0;
135 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
135 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
136 CONSTANT CFG_LDDEL : INTEGER := (1);
136 CONSTANT CFG_LDDEL : INTEGER := (1);
137 CONSTANT CFG_NWP : INTEGER := (0);
137 CONSTANT CFG_NWP : INTEGER := (0);
138 CONSTANT CFG_PWD : INTEGER := 1*2;
138 CONSTANT CFG_PWD : INTEGER := 1*2;
139 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
139 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
140 -- 1*(8 + 16 * 0) => grfpu-light
140 -- 1*(8 + 16 * 0) => grfpu-light
141 -- 1*(8 + 16 * 1) => netlist
141 -- 1*(8 + 16 * 1) => netlist
142 -- 0*(8 + 16 * 0) => No FPU
142 -- 0*(8 + 16 * 0) => No FPU
143 -- 0*(8 + 16 * 1) => No FPU;
143 -- 0*(8 + 16 * 1) => No FPU;
144 CONSTANT CFG_ICEN : INTEGER := 1;
144 CONSTANT CFG_ICEN : INTEGER := 1;
145 CONSTANT CFG_ISETS : INTEGER := 1;
145 CONSTANT CFG_ISETS : INTEGER := 1;
146 CONSTANT CFG_ISETSZ : INTEGER := 4;
146 CONSTANT CFG_ISETSZ : INTEGER := 4;
147 CONSTANT CFG_ILINE : INTEGER := 4;
147 CONSTANT CFG_ILINE : INTEGER := 4;
148 CONSTANT CFG_IREPL : INTEGER := 0;
148 CONSTANT CFG_IREPL : INTEGER := 0;
149 CONSTANT CFG_ILOCK : INTEGER := 0;
149 CONSTANT CFG_ILOCK : INTEGER := 0;
150 CONSTANT CFG_ILRAMEN : INTEGER := 0;
150 CONSTANT CFG_ILRAMEN : INTEGER := 0;
151 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
151 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
152 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
152 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
153 CONSTANT CFG_DCEN : INTEGER := 1;
153 CONSTANT CFG_DCEN : INTEGER := 1;
154 CONSTANT CFG_DSETS : INTEGER := 1;
154 CONSTANT CFG_DSETS : INTEGER := 1;
155 CONSTANT CFG_DSETSZ : INTEGER := 4;
155 CONSTANT CFG_DSETSZ : INTEGER := 4;
156 CONSTANT CFG_DLINE : INTEGER := 4;
156 CONSTANT CFG_DLINE : INTEGER := 4;
157 CONSTANT CFG_DREPL : INTEGER := 0;
157 CONSTANT CFG_DREPL : INTEGER := 0;
158 CONSTANT CFG_DLOCK : INTEGER := 0;
158 CONSTANT CFG_DLOCK : INTEGER := 0;
159 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
159 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
160 CONSTANT CFG_DLRAMEN : INTEGER := 0;
160 CONSTANT CFG_DLRAMEN : INTEGER := 0;
161 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
161 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
162 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
162 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
163 CONSTANT CFG_MMUEN : INTEGER := 0;
163 CONSTANT CFG_MMUEN : INTEGER := 0;
164 CONSTANT CFG_ITLBNUM : INTEGER := 2;
164 CONSTANT CFG_ITLBNUM : INTEGER := 2;
165 CONSTANT CFG_DTLBNUM : INTEGER := 2;
165 CONSTANT CFG_DTLBNUM : INTEGER := 2;
166 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
166 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
167 CONSTANT CFG_TLB_REP : INTEGER := 1;
167 CONSTANT CFG_TLB_REP : INTEGER := 1;
168
168
169 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
169 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
170 CONSTANT CFG_ITBSZ : INTEGER := 0;
170 CONSTANT CFG_ITBSZ : INTEGER := 0;
171 CONSTANT CFG_ATBSZ : INTEGER := 0;
171 CONSTANT CFG_ATBSZ : INTEGER := 0;
172
172
173 -- AMBA settings
173 -- AMBA settings
174 CONSTANT CFG_DEFMST : INTEGER := (0);
174 CONSTANT CFG_DEFMST : INTEGER := (0);
175 CONSTANT CFG_RROBIN : INTEGER := 1;
175 CONSTANT CFG_RROBIN : INTEGER := 1;
176 CONSTANT CFG_SPLIT : INTEGER := 0;
176 CONSTANT CFG_SPLIT : INTEGER := 0;
177 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
177 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
178 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
178 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
179
179
180 -- DSU UART
180 -- DSU UART
181 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
181 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
182
182
183 -- LEON2 memory controller
183 -- LEON2 memory controller
184 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
184 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
185
185
186 -- UART 1
186 -- UART 1
187 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
187 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
188 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
188 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
189
189
190 -- LEON3 interrupt controller
190 -- LEON3 interrupt controller
191 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
191 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
192
192
193 -- Modular timer
193 -- Modular timer
194 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
194 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
195 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
195 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
196 CONSTANT CFG_GPT_SW : INTEGER := (8);
196 CONSTANT CFG_GPT_SW : INTEGER := (8);
197 CONSTANT CFG_GPT_TW : INTEGER := (32);
197 CONSTANT CFG_GPT_TW : INTEGER := (32);
198 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
198 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
199 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
199 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
200 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
200 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
201 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
201 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
202 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 -- SIGNALs
205 -- SIGNALs
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
207 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
208 -- CLK & RST --
208 -- CLK & RST --
209 SIGNAL clk2x : STD_ULOGIC;
209 SIGNAL clk2x : STD_ULOGIC;
210 SIGNAL clkmn : STD_ULOGIC;
210 SIGNAL clkmn : STD_ULOGIC;
211 SIGNAL clkm : STD_ULOGIC;
211 SIGNAL clkm : STD_ULOGIC;
212 SIGNAL rstn : STD_ULOGIC;
212 SIGNAL rstn : STD_ULOGIC;
213 SIGNAL rstraw : STD_ULOGIC;
213 SIGNAL rstraw : STD_ULOGIC;
214 SIGNAL pciclk : STD_ULOGIC;
214 SIGNAL pciclk : STD_ULOGIC;
215 SIGNAL sdclkl : STD_ULOGIC;
215 SIGNAL sdclkl : STD_ULOGIC;
216 SIGNAL cgi : clkgen_in_type;
216 SIGNAL cgi : clkgen_in_type;
217 SIGNAL cgo : clkgen_out_type;
217 SIGNAL cgo : clkgen_out_type;
218 --- AHB / APB
218 --- AHB / APB
219 SIGNAL apbi : apb_slv_in_type;
219 SIGNAL apbi : apb_slv_in_type;
220 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
220 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
221 SIGNAL ahbsi : ahb_slv_in_type;
221 SIGNAL ahbsi : ahb_slv_in_type;
222 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
222 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
223 SIGNAL ahbmi : ahb_mst_in_type;
223 SIGNAL ahbmi : ahb_mst_in_type;
224 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
224 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
225 --UART
225 --UART
226 SIGNAL ahbuarti : uart_in_type;
226 SIGNAL ahbuarti : uart_in_type;
227 SIGNAL ahbuarto : uart_out_type;
227 SIGNAL ahbuarto : uart_out_type;
228 SIGNAL apbuarti : uart_in_type;
228 SIGNAL apbuarti : uart_in_type;
229 SIGNAL apbuarto : uart_out_type;
229 SIGNAL apbuarto : uart_out_type;
230 --MEM CTRLR
230 --MEM CTRLR
231 SIGNAL memi : memory_in_type;
231 SIGNAL memi : memory_in_type;
232 SIGNAL memo : memory_out_type;
232 SIGNAL memo : memory_out_type;
233 SIGNAL wpo : wprot_out_type;
233 SIGNAL wpo : wprot_out_type;
234 SIGNAL sdo : sdram_out_type;
234 SIGNAL sdo : sdram_out_type;
235 SIGNAL mbe : STD_LOGIC; -- enable memory programming
235 SIGNAL mbe : STD_LOGIC; -- enable memory programming
236 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
236 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
237 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
237 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 SIGNAL nSRAM_OE_s : STD_LOGIC;
238 SIGNAL nSRAM_OE_s : STD_LOGIC;
239 --IRQ
239 --IRQ
240 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
240 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
241 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
241 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
242 --Timer
242 --Timer
243 SIGNAL gpti : gptimer_in_type;
243 SIGNAL gpti : gptimer_in_type;
244 SIGNAL gpto : gptimer_out_type;
244 SIGNAL gpto : gptimer_out_type;
245 --DSU
245 --DSU
246 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
246 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
247 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
247 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
248 SIGNAL dsui : dsu_in_type;
248 SIGNAL dsui : dsu_in_type;
249 SIGNAL dsuo : dsu_out_type;
249 SIGNAL dsuo : dsu_out_type;
250 -----------------------------------------------------------------------------
250 -----------------------------------------------------------------------------
251
251
252
252
253 BEGIN
253 BEGIN
254
254
255
255
256 ----------------------------------------------------------------------
256 ----------------------------------------------------------------------
257 --- Reset and Clock generation -------------------------------------
257 --- Reset and Clock generation -------------------------------------
258 ----------------------------------------------------------------------
258 ----------------------------------------------------------------------
259
259
260 cgi.pllctrl <= "00";
260 cgi.pllctrl <= "00";
261 cgi.pllrst <= rstraw;
261 cgi.pllrst <= rstraw;
262
262
263 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
263 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
264
264
265 clkgen0 : clkgen -- clock generator
265 clkgen0 : clkgen -- clock generator
266 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
266 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
267 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
267 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
268 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
268 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
269
269
270 ----------------------------------------------------------------------
270 ----------------------------------------------------------------------
271 --- LEON3 processor / DSU / IRQ ------------------------------------
271 --- LEON3 processor / DSU / IRQ ------------------------------------
272 ----------------------------------------------------------------------
272 ----------------------------------------------------------------------
273
273
274 l3 : IF CFG_LEON3 = 1 GENERATE
274 l3 : IF CFG_LEON3 = 1 GENERATE
275 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
275 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
276 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
276 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
277 u0 : leon3s -- LEON3 processor
277 u0 : leon3s -- LEON3 processor
278 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
278 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
279 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
279 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
280 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
280 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
281 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
281 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
282 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
282 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
283 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
283 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
284 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
284 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
285 irqi(i), irqo(i), dbgi(i), dbgo(i));
285 irqi(i), irqo(i), dbgi(i), dbgo(i));
286 END GENERATE leon3_non_radhard;
286 END GENERATE leon3_non_radhard;
287
287 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
288 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
288 cpu : ENTITY gaisler.leon3ft
289 cpu : leon3ft
289 GENERIC MAP (
290 GENERIC MAP (
290 HINDEX => i, --: integer; --CPU_HINDEX,
291 HINDEX => i, --: integer; --CPU_HINDEX,
291 FABTECH => fabtech, --CFG_TECH,
292 FABTECH => fabtech, --CFG_TECH,
292 MEMTECH => memtech, --CFG_TECH,
293 MEMTECH => memtech, --CFG_TECH,
293 NWINDOWS => CFG_NWIN, --CFG_NWIN,
294 NWINDOWS => CFG_NWIN, --CFG_NWIN,
294 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
295 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
295 FPU => CFG_FPU, --CFG_FPU,
296 FPU => CFG_FPU, --CFG_FPU,
296 V8 => CFG_V8, --CFG_V8,
297 V8 => CFG_V8, --CFG_V8,
297 CP => 0, --CFG_CP,
298 CP => 0, --CFG_CP,
298 MAC => CFG_MAC, --CFG_MAC,
299 MAC => CFG_MAC, --CFG_MAC,
299 PCLOW => pclow, --CFG_PCLOW,
300 PCLOW => pclow, --CFG_PCLOW,
300 NOTAG => 0, --CFG_NOTAG,
301 NOTAG => 0, --CFG_NOTAG,
301 NWP => CFG_NWP, --CFG_NWP,
302 NWP => CFG_NWP, --CFG_NWP,
302 ICEN => CFG_ICEN, --CFG_ICEN,
303 ICEN => CFG_ICEN, --CFG_ICEN,
303 IREPL => CFG_IREPL, --CFG_IREPL,
304 IREPL => CFG_IREPL, --CFG_IREPL,
304 ISETS => CFG_ISETS, --CFG_ISETS,
305 ISETS => CFG_ISETS, --CFG_ISETS,
305 ILINESIZE => CFG_ILINE, --CFG_ILINE,
306 ILINESIZE => CFG_ILINE, --CFG_ILINE,
306 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
307 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
307 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
308 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
308 DCEN => CFG_DCEN, --CFG_DCEN,
309 DCEN => CFG_DCEN, --CFG_DCEN,
309 DREPL => CFG_DREPL, --CFG_DREPL,
310 DREPL => CFG_DREPL, --CFG_DREPL,
310 DSETS => CFG_DSETS, --CFG_DSETS,
311 DSETS => CFG_DSETS, --CFG_DSETS,
311 DLINESIZE => CFG_DLINE, --CFG_DLINE,
312 DLINESIZE => CFG_DLINE, --CFG_DLINE,
312 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
313 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
313 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
314 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
314 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
315 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
315 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
316 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
316 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
317 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
317 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
318 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
318 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
319 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
319 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
320 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
320 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
321 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
321 MMUEN => CFG_MMUEN, --CFG_MMUEN,
322 MMUEN => CFG_MMUEN, --CFG_MMUEN,
322 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
323 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
323 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
324 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
324 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
325 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
325 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
326 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
326 LDDEL => CFG_LDDEL, --CFG_LDDEL,
327 LDDEL => CFG_LDDEL, --CFG_LDDEL,
327 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
328 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
328 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
329 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
329 PWD => CFG_PWD, --CFG_PWD,
330 PWD => CFG_PWD, --CFG_PWD,
330 SVT => CFG_SVT, --CFG_SVT,
331 SVT => CFG_SVT, --CFG_SVT,
331 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
332 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
332 SMP => CFG_NCPU-1, --CFG_NCPU-1,
333 SMP => CFG_NCPU-1, --CFG_NCPU-1,
333 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
334 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
334 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
335 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
335 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
336 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
336 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
337 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
337 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
338 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
338 CACHED => 0, --: integer; --CFG_DFIXED,
339 CACHED => 0, --: integer; --CFG_DFIXED,
339 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
340 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
340 SCANTEST => 0, --: integer; --CFG_SCANTEST,
341 SCANTEST => 0, --: integer; --CFG_SCANTEST,
341 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
342 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
342 BP => 1) --CFG_BP
343 BP => 1) --CFG_BP
343 PORT MAP ( --
344 PORT MAP ( --
344 rstn => rstn, --rst_n,
345 rstn => rstn, --rst_n,
345 clk => clkm, --clk,
346 clk => clkm, --clk,
346 ahbi => ahbmi, --ahbmi,
347 ahbi => ahbmi, --ahbmi,
347 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
348 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
348 ahbsi => ahbsi, --ahbsi,
349 ahbsi => ahbsi, --ahbsi,
349 ahbso => ahbso, --ahbso,
350 ahbso => ahbso, --ahbso,
350 irqi => irqi(i), --irqi(CPU_HINDEX),
351 irqi => irqi(i), --irqi(CPU_HINDEX),
351 irqo => irqo(i), --irqo(CPU_HINDEX),
352 irqo => irqo(i), --irqo(CPU_HINDEX),
352 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
353 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
353 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
354 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
354 gclk => clkm --clk
355 gclk => clkm --clk
355 );
356 );
356 END GENERATE leon3_radhard_i;
357 END GENERATE leon3_radhard_i;
357
358
358 END GENERATE;
359 END GENERATE;
359 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
360 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
360
361
361 dsugen : IF CFG_DSU = 1 GENERATE
362 dsugen : IF CFG_DSU = 1 GENERATE
362 dsu0 : dsu3 -- LEON3 Debug Support Unit
363 dsu0 : dsu3 -- LEON3 Debug Support Unit
363 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
364 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
364 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
365 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
365 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
366 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
366 dsui.enable <= '1';
367 dsui.enable <= '1';
367 dsui.break <= '0';
368 dsui.break <= '0';
368 END GENERATE;
369 END GENERATE;
369 END GENERATE;
370 END GENERATE;
370
371
371 nodsu : IF CFG_DSU = 0 GENERATE
372 nodsu : IF CFG_DSU = 0 GENERATE
372 ahbso(2) <= ahbs_none;
373 ahbso(2) <= ahbs_none;
373 dsuo.tstop <= '0';
374 dsuo.tstop <= '0';
374 dsuo.active <= '0';
375 dsuo.active <= '0';
375 END GENERATE;
376 END GENERATE;
376
377
377 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
378 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
378 irqctrl0 : irqmp -- interrupt controller
379 irqctrl0 : irqmp -- interrupt controller
379 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
380 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
380 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
381 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
381 END GENERATE;
382 END GENERATE;
382 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
383 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
383 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
384 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
384 irqi(i).irl <= "0000";
385 irqi(i).irl <= "0000";
385 END GENERATE;
386 END GENERATE;
386 apbo(2) <= apb_none;
387 apbo(2) <= apb_none;
387 END GENERATE;
388 END GENERATE;
388
389
389 ----------------------------------------------------------------------
390 ----------------------------------------------------------------------
390 --- Memory controllers ---------------------------------------------
391 --- Memory controllers ---------------------------------------------
391 ----------------------------------------------------------------------
392 ----------------------------------------------------------------------
392 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
393 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
393 memctrlr : mctrl GENERIC MAP (
394 memctrlr : mctrl GENERIC MAP (
394 hindex => 0,
395 hindex => 0,
395 pindex => 0,
396 pindex => 0,
396 paddr => 0,
397 paddr => 0,
397 srbanks => 1
398 srbanks => 1
398 )
399 )
399 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
400 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
400 memi.bexcn <= '1';
401 memi.bexcn <= '1';
401 memi.brdyn <= '1';
402 memi.brdyn <= '1';
402
403
403 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
404 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
404 nSRAM_OE_s <= memo.ramoen(0);
405 nSRAM_OE_s <= memo.ramoen(0);
405 END GENERATE;
406 END GENERATE;
406
407
407 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
408 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
408 memctrlr : srctrle_0ws
409 memctrlr : srctrle_0ws
409 GENERIC MAP(
410 GENERIC MAP(
410 hindex => 0,
411 hindex => 0,
411 pindex => 0,
412 pindex => 0,
412 paddr => 0,
413 paddr => 0,
413 srbanks => 2,
414 srbanks => 2,
414 banksz => 8, --512k * 32
415 banksz => 8, --512k * 32
415 rmw => 1,
416 rmw => 1,
416 --Aeroflex memory generics:
417 --Aeroflex memory generics:
417 mprog => 1, -- program memory by default values after reset
418 mprog => 1, -- program memory by default values after reset
418 mpsrate => 12, -- default scrub rate period
419 mpsrate => 12, -- default scrub rate period
419 mpb2s => 4, -- default busy to scrub delay
420 mpb2s => 4, -- default busy to scrub delay
420 mpapb => 1, -- instantiate apb register
421 mpapb => 1, -- instantiate apb register
421 mchipcnt => 2,
422 mchipcnt => 2,
422 mpenall => 1 -- when 0 program only E1 chip, else program all dies
423 mpenall => 1 -- when 0 program only E1 chip, else program all dies
423 )
424 )
424 PORT MAP (
425 PORT MAP (
425 rst => rstn,
426 rst => rstn,
426 clk => clkm,
427 clk => clkm,
427 ahbsi => ahbsi,
428 ahbsi => ahbsi,
428 ahbso => ahbso(0),
429 ahbso => ahbso(0),
429 apbi => apbi,
430 apbi => apbi,
430 apbo => apbo(0),
431 apbo => apbo(0),
431 sri => memi,
432 sri => memi,
432 sro => memo,
433 sro => memo,
433 --Aeroflex memory signals:
434 --Aeroflex memory signals:
434 ucerr => OPEN, -- uncorrectable error signal
435 ucerr => OPEN, -- uncorrectable error signal
435 mbe => mbe, -- enable memory programming
436 mbe => mbe, -- enable memory programming
436 mbe_drive => mbe_drive -- drive the MBE memory signal
437 mbe_drive => mbe_drive -- drive the MBE memory signal
437 );
438 );
438
439
439 memi.brdyn <= nSRAM_READY;
440 memi.brdyn <= nSRAM_READY;
440
441
441 mbe_pad : iopad
442 mbe_pad : iopad
442 GENERIC MAP(tech => padtech)
443 GENERIC MAP(tech => padtech)
443 PORT MAP(pad => SRAM_MBE,
444 PORT MAP(pad => SRAM_MBE,
444 i => mbe,
445 i => mbe,
445 en => mbe_drive,
446 en => mbe_drive,
446 o => memi.bexcn);
447 o => memi.bexcn);
447
448
448 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
449 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
449 nSRAM_OE_s <= memo.oen;
450 nSRAM_OE_s <= memo.oen;
450
451
451 END GENERATE;
452 END GENERATE;
452
453
453
454
454 memi.writen <= '1';
455 memi.writen <= '1';
455 memi.wrn <= "1111";
456 memi.wrn <= "1111";
456 memi.bwidth <= "10";
457 memi.bwidth <= "10";
457
458
458 bdr : FOR i IN 0 TO 3 GENERATE
459 bdr : FOR i IN 0 TO 3 GENERATE
459 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
460 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
460 PORT MAP (
461 PORT MAP (
461 data(31-i*8 DOWNTO 24-i*8),
462 data(31-i*8 DOWNTO 24-i*8),
462 memo.data(31-i*8 DOWNTO 24-i*8),
463 memo.data(31-i*8 DOWNTO 24-i*8),
463 memo.bdrive(i),
464 memo.bdrive(i),
464 memi.data(31-i*8 DOWNTO 24-i*8));
465 memi.data(31-i*8 DOWNTO 24-i*8));
465 END GENERATE;
466 END GENERATE;
466
467
467 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
468 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
468 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
469 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
469 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
470 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
470 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
471 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
471 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
472 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
472 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
473 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
473 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
474 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
474 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
475 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
475 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
476 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
476
477
477
478
478
479
479 ----------------------------------------------------------------------
480 ----------------------------------------------------------------------
480 --- AHB CONTROLLER -------------------------------------------------
481 --- AHB CONTROLLER -------------------------------------------------
481 ----------------------------------------------------------------------
482 ----------------------------------------------------------------------
482 ahb0 : ahbctrl -- AHB arbiter/multiplexer
483 ahb0 : ahbctrl -- AHB arbiter/multiplexer
483 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
484 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
484 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
485 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
485 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
486 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
486 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
487 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
487
488
488 ----------------------------------------------------------------------
489 ----------------------------------------------------------------------
489 --- AHB UART -------------------------------------------------------
490 --- AHB UART -------------------------------------------------------
490 ----------------------------------------------------------------------
491 ----------------------------------------------------------------------
491 dcomgen : IF CFG_AHB_UART = 1 GENERATE
492 dcomgen : IF CFG_AHB_UART = 1 GENERATE
492 dcom0 : ahbuart
493 dcom0 : ahbuart
493 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
494 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
494 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
495 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
495 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
496 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
496 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
497 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
497 END GENERATE;
498 END GENERATE;
498 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
499 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
499
500
500 ----------------------------------------------------------------------
501 ----------------------------------------------------------------------
501 --- APB Bridge -----------------------------------------------------
502 --- APB Bridge -----------------------------------------------------
502 ----------------------------------------------------------------------
503 ----------------------------------------------------------------------
503 apb0 : apbctrl -- AHB/APB bridge
504 apb0 : apbctrl -- AHB/APB bridge
504 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
505 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
505 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
506 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
506
507
507 ----------------------------------------------------------------------
508 ----------------------------------------------------------------------
508 --- GPT Timer ------------------------------------------------------
509 --- GPT Timer ------------------------------------------------------
509 ----------------------------------------------------------------------
510 ----------------------------------------------------------------------
510 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
511 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
511 timer0 : gptimer -- timer unit
512 timer0 : gptimer -- timer unit
512 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
513 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
513 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
514 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
514 nbits => CFG_GPT_TW)
515 nbits => CFG_GPT_TW)
515 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
516 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
516 gpti.dhalt <= dsuo.tstop;
517 gpti.dhalt <= dsuo.tstop;
517 gpti.extclk <= '0';
518 gpti.extclk <= '0';
518 END GENERATE;
519 END GENERATE;
519 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
520 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
520
521
521
522
522 ----------------------------------------------------------------------
523 ----------------------------------------------------------------------
523 --- APB UART -------------------------------------------------------
524 --- APB UART -------------------------------------------------------
524 ----------------------------------------------------------------------
525 ----------------------------------------------------------------------
525 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
526 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
526 uart1 : apbuart -- UART 1
527 uart1 : apbuart -- UART 1
527 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
528 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
528 fifosize => CFG_UART1_FIFO)
529 fifosize => CFG_UART1_FIFO)
529 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
530 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
530 apbuarti.rxd <= urxd1;
531 apbuarti.rxd <= urxd1;
531 apbuarti.extclk <= '0';
532 apbuarti.extclk <= '0';
532 utxd1 <= apbuarto.txd;
533 utxd1 <= apbuarto.txd;
533 apbuarti.ctsn <= '0';
534 apbuarti.ctsn <= '0';
534 END GENERATE;
535 END GENERATE;
535 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
536 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
536
537
537 -------------------------------------------------------------------------------
538 -------------------------------------------------------------------------------
538 -- AMBA BUS -------------------------------------------------------------------
539 -- AMBA BUS -------------------------------------------------------------------
539 -------------------------------------------------------------------------------
540 -------------------------------------------------------------------------------
540
541
541 -- APB --------------------------------------------------------------------
542 -- APB --------------------------------------------------------------------
542 apbi_ext <= apbi;
543 apbi_ext <= apbi;
543 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
544 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
544 max_16_apb : IF I + 5 < 16 GENERATE
545 max_16_apb : IF I + 5 < 16 GENERATE
545 apbo(I+5) <= apbo_ext(I+5);
546 apbo(I+5) <= apbo_ext(I+5);
546 END GENERATE max_16_apb;
547 END GENERATE max_16_apb;
547 END GENERATE all_apb;
548 END GENERATE all_apb;
548 -- AHB_Slave --------------------------------------------------------------
549 -- AHB_Slave --------------------------------------------------------------
549 ahbi_s_ext <= ahbsi;
550 ahbi_s_ext <= ahbsi;
550 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
551 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
551 max_16_ahbs : IF I + 3 < 16 GENERATE
552 max_16_ahbs : IF I + 3 < 16 GENERATE
552 ahbso(I+3) <= ahbo_s_ext(I+3);
553 ahbso(I+3) <= ahbo_s_ext(I+3);
553 END GENERATE max_16_ahbs;
554 END GENERATE max_16_ahbs;
554 END GENERATE all_ahbs;
555 END GENERATE all_ahbs;
555 -- AHB_Master -------------------------------------------------------------
556 -- AHB_Master -------------------------------------------------------------
556 ahbi_m_ext <= ahbmi;
557 ahbi_m_ext <= ahbmi;
557 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
558 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
558 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
559 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
559 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
560 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
560 END GENERATE max_16_ahbm;
561 END GENERATE max_16_ahbm;
561 END GENERATE all_ahbm;
562 END GENERATE all_ahbm;
562
563
563
564
564
565
565 END Behavioral;
566 END Behavioral; No newline at end of file
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