HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r363:453f650415b6

Dispatch into library the MS files

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r363:453f650415b6

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lib/lpp/lpp_spectral_matrix/MS_calculation.vhd created 644 +224 0

@@ -0,0 +1,224
	1	LIBRARY IEEE;
	2	USE IEEE.std_logic_1164.ALL;
	3
	4	LIBRARY lpp;
	5	USE lpp.general_purpose.ALL;
	6
	7	ENTITY MS_calculation IS
	8	PORT (
	9	clk : IN STD_LOGIC;
	10	rstn : IN STD_LOGIC;
	11	-- IN
	12	fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
	13	fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	14	fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	15	-- OUT
	16	fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
	17	fifo_out_wen : OUT STD_LOGIC;
	18	fifo_out_full : IN STD_LOGIC;
	19	--
	20	correlation_start : IN STD_LOGIC;
	21	correlation_auto : IN STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
	22
	23	correlation_begin : OUT STD_LOGIC;
	24	correlation_done : OUT STD_LOGIC
	25	);
	26	END MS_calculation;
	27
	28	ARCHITECTURE beh OF MS_calculation IS
	29
	30	TYPE fsm_calculation_MS IS (IDLE, WF, S1, S2, S3, S4, WFa, S1a, S2a);
	31	SIGNAL state : fsm_calculation_MS;
	32
	33	SIGNAL OP1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	34	SIGNAL OP2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	35	SIGNAL RES : STD_LOGIC_VECTOR(31 DOWNTO 0);
	36
	37	SIGNAL ALU_CTRL : STD_LOGIC_VECTOR(4 DOWNTO 0);
	38
	39
	40	CONSTANT ALU_CTRL_NOP : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
	41	CONSTANT ALU_CTRL_MULT : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00010";
	42	CONSTANT ALU_CTRL_MAC : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00001";
	43	CONSTANT ALU_CTRL_MACn : STD_LOGIC_VECTOR(4 DOWNTO 0) := "10001";
	44
	45
	46
	47	SIGNAL select_op1 : STD_LOGIC;
	48	SIGNAL select_op2 : STD_LOGIC_VECTOR(1 DOWNTO 0) ;
	49
	50	CONSTANT select_R0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
	51	CONSTANT select_I0 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
	52	CONSTANT select_R1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
	53	CONSTANT select_I1 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
	54
	55	SIGNAL res_wen : STD_LOGIC;
	56	SIGNAL res_wen_reg1 : STD_LOGIC;
	57	-- SIGNAL res_wen_reg2 : STD_LOGIC;
	58	--SIGNAL res_wen_reg3 : STD_LOGIC;
	59
	60	BEGIN
	61
	62
	63
	64	PROCESS (clk, rstn)
	65	BEGIN
	66	IF rstn = '0' THEN
	67
	68	correlation_begin <= '0';
	69	correlation_done <= '0';
	70	state <= IDLE;
	71	fifo_in_ren <= "11";
	72	ALU_CTRL <= ALU_CTRL_NOP;
	73	select_op1 <= select_R0(0);
	74	select_op2 <= select_R0;
	75	res_wen <= '1';
	76
	77	ELSIF clk'EVENT AND clk = '1' THEN
	78	correlation_begin <= '0';
	79	fifo_in_ren <= "11";
	80	res_wen <= '1';
	81	correlation_done <= '0';
	82	CASE state IS
	83	WHEN IDLE =>
	84	IF correlation_start = '1' THEN
	85	IF correlation_auto = '1' THEN
	86	IF fifo_out_full = '1' THEN
	87	state <= WFa;
	88	ELSE
	89	correlation_begin <= '1';
	90	state <= S1a;
	91	fifo_in_ren <= "10";
	92	END IF;
	93	ELSE
	94	IF fifo_out_full = '1' THEN
	95	state <= WF;
	96	ELSE
	97	correlation_begin <= '1';
	98	state <= S1;
	99	fifo_in_ren <= "00";
	100	END IF;
	101	END IF;
	102	END IF;
	103
	104	---------------------------------------------------------------------
	105	-- INTER CORRELATION
	106	---------------------------------------------------------------------
	107	WHEN WF =>
	108	IF fifo_out_full = '0' THEN
	109	correlation_begin <= '1';
	110	state <= S1;
	111	fifo_in_ren <= "00";
	112	END IF;
	113	WHEN S1 =>
	114	ALU_CTRL <= ALU_CTRL_MULT;
	115	select_op1 <= select_R0(0);
	116	select_op2 <= select_R1;
	117	state <= S2;
	118	WHEN S2 =>
	119	ALU_CTRL <= ALU_CTRL_MAC;
	120	select_op1 <= select_I0(0);
	121	select_op2 <= select_I1;
	122	res_wen <= '0';
	123	state <= S3;
	124	WHEN S3 =>
	125	ALU_CTRL <= ALU_CTRL_MULT;
	126	select_op1 <= select_I0(0);
	127	select_op2 <= select_R1;
	128	state <= S4;
	129	WHEN S4 =>
	130	ALU_CTRL <= ALU_CTRL_MACn;
	131	select_op1 <= select_R0(0);
	132	select_op2 <= select_I1;
	133	res_wen <= '0';
	134	IF fifo_in_empty = "00" THEN
	135	state <= S1;
	136	fifo_in_ren <= "00";
	137	ELSE
	138	correlation_done <= '1';
	139	state <= IDLE;
	140	END IF;
	141
	142
	143
	144	---------------------------------------------------------------------
	145	-- AUTO CORRELATION
	146	---------------------------------------------------------------------
	147	WHEN WFa =>
	148	IF fifo_out_full = '0' THEN
	149	correlation_begin <= '1';
	150	state <= S1a;
	151	fifo_in_ren <= "10";
	152	END IF;
	153	WHEN S1a =>
	154	ALU_CTRL <= ALU_CTRL_MULT;
	155	select_op1 <= select_R0(0);
	156	select_op2 <= select_R0;
	157	state <= S2a;
	158	WHEN S2a =>
	159	ALU_CTRL <= ALU_CTRL_MAC;
	160	select_op1 <= select_I0(0);
	161	select_op2 <= select_I0;
	162	res_wen <= '0';
	163	IF fifo_in_empty(0) = '0' THEN
	164	state <= S1a;
	165	fifo_in_ren <= "10";
	166	ELSE
	167	correlation_done <= '1';
	168	state <= IDLE;
	169	END IF;
	170
	171
	172	WHEN OTHERS => NULL;
	173	END CASE;
	174
	175	END IF;
	176	END PROCESS;
	177
	178	OP1 <= fifo_in_data(15 DOWNTO 0) WHEN select_op1 = select_R0(0) ELSE
	179	fifo_in_data(31 DOWNTO 16); -- WHEN select_op1 = select_I0(0) ELSE
	180
	181	OP2 <= fifo_in_data(15 DOWNTO 0) WHEN select_op2 = select_R0 ELSE
	182	fifo_in_data(31 DOWNTO 16) WHEN select_op2 = select_I0 ELSE
	183	fifo_in_data(47 DOWNTO 32) WHEN select_op2 = select_R1 ELSE
	184	fifo_in_data(63 DOWNTO 48); -- WHEN select_op2 = select_I1 ELSE
	185
	186	ALU_MS : ALU
	187	GENERIC MAP (
	188	Arith_en => 1,
	189	Logic_en => 0,
	190	Input_SZ_1 => 16,
	191	Input_SZ_2 => 16,
	192	COMP_EN => 1)
	193	PORT MAP (
	194	clk => clk,
	195	reset => rstn,
	196
	197	ctrl => ALU_CTRL(2 DOWNTO 0),
	198	comp => ALU_CTRL(4 DOWNTO 3),
	199
	200	OP1 => OP1,
	201	OP2 => OP2,
	202
	203	RES => RES);
	204
	205	fifo_out_data <= RES;
	206
	207
	208	PROCESS (clk, rstn)
	209	BEGIN
	210	IF rstn = '0' THEN
	211	res_wen_reg1 <= '1';
	212	--res_wen_reg2 <= '1';
	213	--res_wen_reg3 <= '1';
	214	fifo_out_wen <= '1';
	215	ELSIF clk'event AND clk = '1' THEN
	216	res_wen_reg1 <= res_wen;
	217	--res_wen_reg2 <= res_wen_reg1;
	218	--res_wen_reg3 <= res_wen_reg2;
	219	fifo_out_wen <= res_wen_reg1;
	220	END IF;
	221	END PROCESS;
	222
	223
	224	END beh;

lib/lpp/lpp_spectral_matrix/MS_control.vhd created 644 +148 0

@@ -0,0 +1,148
	1	LIBRARY IEEE;
	2	USE IEEE.std_logic_1164.ALL;
	3	USE IEEE.numeric_std.ALL;
	4
	5	ENTITY MS_control IS
	6	PORT (
	7	clk : IN STD_LOGIC;
	8	rstn : IN STD_LOGIC;
	9	-- IN
	10	current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0)
	11
	12	-- IN
	13	fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	14	fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
	15	fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	16	fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	17	fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	18	fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	19	-- OUT
	20	fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
	21	fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	22	fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	23	-- OUT
	24	current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) &
	25	-- Matrix_type (1..0)
	26	-- ComponentType (3..0)
	27	correlation_start : OUT STD_LOGIC;
	28	correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
	29	correlation_done : IN STD_LOGIC
	30	);
	31	END MS_control;
	32
	33	ARCHITECTURE beh OF MS_control IS
	34
	35	TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING);
	36	SIGNAL state : fsm_control_MS;
	37
	38	SUBTYPE fifo_pointer IS INTEGER RANGE 0 TO 4;
	39	SIGNAL fifo_1 : fifo_pointer;
	40	SIGNAL fifo_2 : fifo_pointer;
	41
	42	SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
	43	SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
	44
	45	BEGIN -- beh
	46
	47	fifo_in_lock <= fifo_in_lock_s;
	48	fifo_in_reuse <= fifo_in_reuse_s;
	49
	50	PROCESS (clk, rstn)
	51	BEGIN
	52	IF rstn = '0' THEN
	53	state <= WAIT_DATA;
	54	fifo_1 <= 0;
	55	fifo_2 <= 0;
	56	fifo_in_lock_s <= (OTHERS => '0');
	57	fifo_in_reuse_s <= (OTHERS => '0');
	58	correlation_start <= '0';
	59	correlation_auto <= '0';
	60	current_status_component <= (OTHERS => '0');
	61	ELSIF clk'event AND clk = '1' THEN
	62	CASE state IS
	63
	64	WHEN WAIT_DATA =>
	65	fifo_in_reuse_s <= (OTHERS => '0');
	66	IF fifo_in_full(fifo_1) = '1' AND fifo_in_full(fifo_2) = '1' THEN
	67	fifo_in_lock_s(fifo_1) <= '1';
	68	fifo_in_lock_s(fifo_2) <= '1';
	69	correlation_start <= '1';
	70	IF fifo_1 = fifo_2 THEN
	71	correlation_auto <= '1';
	72	END IF;
	73	state <= CORRELATION_ONGOING;
	74	IF fifo_1 = 0 AND fifo_2 = 0 THEN
	75	current_status_component(53 DOWNTO 4) <= current_status_ms;
	76	END IF;
	77	CASE fifo_1 IS
	78	WHEN 0 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned( fifo_2,4));
	79	WHEN 1 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(4+fifo_2,4));
	80	WHEN 2 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(7+fifo_2,4));
	81	WHEN 3 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(9+fifo_2,4));
	82	WHEN 4 => current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(14 ,4));
	83	WHEN OTHERS => NULL;
	84	END CASE;
	85	--current_status_component(3 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(fifo_1*5+fifo_2,4));
	86	END IF;
	87
	88	WHEN CORRELATION_ONGOING =>
	89	correlation_start <= '0';
	90	correlation_auto <= '0';
	91	IF correlation_done = '1' THEN
	92	state <= WAIT_DATA;
	93	IF fifo_2 = 4 THEN
	94	fifo_in_lock_s(fifo_1) <= '0';
	95	IF fifo_1 = 4 THEN
	96	fifo_1 <= 0;
	97	fifo_2 <= 0;
	98	ELSE
	99	fifo_in_reuse_s(fifo_2) <= '1';
	100	fifo_1 <= fifo_1 + 1;
	101	fifo_2 <= fifo_1 + 1;
	102	END IF;
	103	ELSE
	104	fifo_in_reuse_s(fifo_2) <= '1';
	105	fifo_in_reuse_s(fifo_1) <= '1';
	106	fifo_2 <= fifo_2 + 1;
	107	END IF;
	108	END IF;
	109
	110	WHEN OTHERS => NULL;
	111	END CASE;
	112	END IF;
	113	END PROCESS;
	114
	115
	116	fifo_out_data(31 DOWNTO 0) <= fifo_in_data(321-1 DOWNTO 320) WHEN fifo_1 = 0 ELSE
	117	fifo_in_data(322-1 DOWNTO 321) WHEN fifo_1 = 1 ELSE
	118	fifo_in_data(323-1 DOWNTO 322) WHEN fifo_1 = 2 ELSE
	119	fifo_in_data(324-1 DOWNTO 323) WHEN fifo_1 = 3 ELSE
	120	fifo_in_data(325-1 DOWNTO 324);-- WHEN fifo_1 = 4
	121
	122
	123	fifo_out_data(63 DOWNTO 32) <= fifo_in_data(321-1 DOWNTO 320) WHEN fifo_2 = 0 ELSE
	124	fifo_in_data(322-1 DOWNTO 321) WHEN fifo_2 = 1 ELSE
	125	fifo_in_data(323-1 DOWNTO 322) WHEN fifo_2 = 2 ELSE
	126	fifo_in_data(324-1 DOWNTO 323) WHEN fifo_2 = 3 ELSE
	127	fifo_in_data(325-1 DOWNTO 324);-- WHEN fifo_2 = 4
	128
	129	fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE
	130	fifo_in_empty(1) WHEN fifo_1 = 1 ELSE
	131	fifo_in_empty(2) WHEN fifo_1 = 2 ELSE
	132	fifo_in_empty(3) WHEN fifo_1 = 3 ELSE
	133	fifo_in_empty(4);
	134
	135	fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE
	136	fifo_in_empty(1) WHEN fifo_2 = 1 ELSE
	137	fifo_in_empty(2) WHEN fifo_2 = 2 ELSE
	138	fifo_in_empty(3) WHEN fifo_2 = 3 ELSE
	139	fifo_in_empty(4);
	140
	141
	142	all_fifo: FOR I IN 0 TO 4 GENERATE
	143	fifo_in_ren(I) <= fifo_out_ren(0) WHEN fifo_1 = I ELSE
	144	fifo_out_ren(1) WHEN fifo_2 = I ELSE
	145	'1';
	146	END GENERATE all_fifo;
	147
	148	END beh;

lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd created 644 +65 0

@@ -0,0 +1,65
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3
	4	PACKAGE spectral_matrix_package IS
	5
	6	COMPONENT spectral_matrix_switch_f0
	7	PORT (
	8	clk : IN STD_LOGIC;
	9	rstn : IN STD_LOGIC;
	10	sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	11	fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	12	fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	13	fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	14	fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	15	fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	16	fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	17	error_wen : OUT STD_LOGIC);
	18	END COMPONENT;
	19
	20	COMPONENT spectral_matrix_time_managment
	21	PORT (
	22	clk : IN STD_LOGIC;
	23	rstn : IN STD_LOGIC;
	24	time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	25	update_1 : IN STD_LOGIC;
	26	time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
	27	END COMPONENT;
	28
	29	COMPONENT MS_control
	30	PORT (
	31	clk : IN STD_LOGIC;
	32	rstn : IN STD_LOGIC;
	33	current_status_ms : IN STD_LOGIC_VECTOR(49 DOWNTO 0); -- TIME(47 .. 0) & Matrix_type(1..0)
	34	fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	35	fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
	36	fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	37	fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	38	fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	39	fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	40	fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
	41	fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	42	fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	43	current_status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); -- TIME(47 .. 0) &
	44	correlation_start : OUT STD_LOGIC;
	45	correlation_auto : OUT STD_LOGIC;
	46	correlation_done : IN STD_LOGIC);
	47	END COMPONENT;
	48
	49	COMPONENT MS_calculation
	50	PORT (
	51	clk : IN STD_LOGIC;
	52	rstn : IN STD_LOGIC;
	53	fifo_in_data : IN STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
	54	fifo_in_ren : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	55	fifo_in_empty : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	56	fifo_out_data : OUT STD_LOGIC_VECTOR(32-1 DOWNTO 0);
	57	fifo_out_wen : OUT STD_LOGIC;
	58	fifo_out_full : IN STD_LOGIC;
	59	correlation_start : IN STD_LOGIC;
	60	correlation_auto : IN STD_LOGIC;
	61	correlation_begin : OUT STD_LOGIC;
	62	correlation_done : OUT STD_LOGIC);
	63	END COMPONENT;
	64
	65	END spectral_matrix_package;

lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd created 644 +99 0

@@ -0,0 +1,99
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3
	4
	5	ENTITY spectral_matrix_switch_f0 IS
	6
	7	PORT (
	8	clk : IN STD_LOGIC;
	9	rstn : IN STD_LOGIC;
	10	--INPUT
	11	sample_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	12	--OUTPUT A
	13	fifo_A_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	14	fifo_A_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	15	fifo_A_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	16	--OUTPUT B
	17	fifo_B_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	18	fifo_B_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	19	fifo_B_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	20	--ERROR
	21	error_wen : OUT STD_LOGIC
	22	);
	23
	24	END spectral_matrix_switch_f0;
	25
	26	ARCHITECTURE beh OF spectral_matrix_switch_f0 IS
	27	SIGNAL ALL_1_sample_wen : STD_LOGIC;
	28
	29	SIGNAL ALL_1_fifo_A_empty : STD_LOGIC;
	30	SIGNAL ALL_1_fifo_A_full : STD_LOGIC;
	31	SIGNAL ALL_1_fifo_B_empty : STD_LOGIC;
	32	SIGNAL ALL_1_fifo_B_full : STD_LOGIC;
	33
	34	TYPE state_fsm_switch_f0 IS (state_A,state_B,state_AtoB,state_BtoA);
	35	SIGNAL state_fsm : state_fsm_switch_f0;
	36
	37	BEGIN -- beh
	38	ALL_1_sample_wen <= '1' WHEN sample_wen = "11111" ELSE '0';
	39
	40	ALL_1_fifo_A_empty <= '1' WHEN fifo_A_empty = "11111" ELSE '0';
	41	ALL_1_fifo_A_full <= '1' WHEN fifo_A_full = "11111" ELSE '0';
	42	ALL_1_fifo_B_empty <= '1' WHEN fifo_B_empty = "11111" ELSE '0';
	43	ALL_1_fifo_B_full <= '1' WHEN fifo_B_full = "11111" ELSE '0';
	44
	45	fifo_A_wen <= sample_wen WHEN state_fsm = state_A ELSE (OTHERS => '1');
	46	fifo_B_wen <= sample_wen WHEN state_fsm = state_B ELSE (OTHERS => '1');
	47
	48	PROCESS (clk, rstn)
	49	BEGIN
	50	IF rstn = '0' THEN
	51	state_fsm <= state_A;
	52	error_wen <= '0';
	53
	54	ELSIF clk'event AND clk = '1' THEN
	55	CASE state_fsm IS
	56
	57	WHEN state_A =>
	58	error_wen <= '0';
	59	IF ALL_1_fifo_A_full = '1' THEN
	60	--error_wen <= NOT ALL_1_sample_wen;
	61	IF ALL_1_fifo_B_empty = '1' THEN
	62	state_fsm <= state_B;
	63	ELSE
	64	state_fsm <= state_AtoB;
	65	END IF;
	66	END IF;
	67
	68	WHEN state_B =>
	69	error_wen <= '0';
	70	IF ALL_1_fifo_B_full = '1' THEN
	71	--error_wen <= NOT ALL_1_sample_wen;
	72	IF ALL_1_fifo_A_empty = '1' THEN
	73	state_fsm <= state_A;
	74	ELSE
	75	state_fsm <= state_BtoA;
	76	END IF;
	77	END IF;
	78
	79	WHEN state_AtoB =>
	80	error_wen <= NOT ALL_1_sample_wen;
	81	IF ALL_1_fifo_B_empty = '1' THEN
	82	state_fsm <= state_B;
	83	END IF;
	84
	85	WHEN state_BtoA =>
	86	error_wen <= NOT ALL_1_sample_wen;
	87	IF ALL_1_fifo_A_empty = '1' THEN
	88	state_fsm <= state_A;
	89	END IF;
	90
	91	WHEN OTHERS => NULL;
	92	END CASE;
	93
	94
	95	END IF;
	96	END PROCESS;
	97
	98
	99	END beh;

lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd created 644 +36 0

@@ -0,0 +1,36
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3
	4	ENTITY spectral_matrix_time_managment IS
	5
	6	PORT (
	7	clk : IN STD_LOGIC;
	8	rstn : IN STD_LOGIC;
	9
	10	time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
	11	update_1 : IN STD_LOGIC;
	12	time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
	13	);
	14
	15	END spectral_matrix_time_managment;
	16
	17	ARCHITECTURE beh OF spectral_matrix_time_managment IS
	18
	19	SIGNAL time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
	20
	21	BEGIN -- beh
	22
	23	PROCESS (clk, rstn)
	24	BEGIN
	25	IF rstn = '0' THEN
	26	time_reg <= (OTHERS => '0');
	27	ELSIF clk'event AND clk = '1' THEN
	28	IF update_1 = '1' THEN
	29	time_reg <= time_in;
	30	END IF;
	31	END IF;
	32	END PROCESS;
	33
	34	time_out <= time_in;
	35
	36	END beh;

lib/lpp/lpp_spectral_matrix/vhdlsyn.txt created 644 +5 0

@@ -0,0 +1,5
	1	spectral_matrix_package.vhd
	2	MS_calculation.vhd
	3	MS_control.vhd
	4	spectral_matrix_switch_f0.vhd
	5	spectral_matrix_time_managment.vhd

designs/Validation_LFR_SpectralMatrix/Makefile +14 -11

             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=TB
             CMD_VLIB=vlib
             CMD_VMAP=vmap
             CMD_VCOM=@vcom -quiet -93 -work
             ##################  project specific targets ##########################
             all:
             	@echo "make vsim"
             	@echo "make libs"
             	@echo "make clean"
             	@echo "make vcom_grlib vcom_lpp vcom_tb"
             run:
             	@vsim work.TB -do run.do
             #	@vsim work.TB
             #	@vsim lpp.lpp_lfr_ms
             vsim:   libs vcom run
             libs:
             	@$(CMD_VLIB) modelsim
             	@$(CMD_VMAP) modelsim modelsim
             	@$(CMD_VLIB) modelsim/techmap
             	@$(CMD_VMAP) techmap modelsim/techmap
             	@$(CMD_VLIB) modelsim/grlib
             	@$(CMD_VMAP) grlib modelsim/grlib
             	@$(CMD_VLIB) modelsim/gaisler
             	@$(CMD_VMAP) gaisler modelsim/gaisler
             	@$(CMD_VLIB) modelsim/work
             	@$(CMD_VMAP) work modelsim/work
             	@$(CMD_VLIB) modelsim/lpp
             	@$(CMD_VMAP) lpp modelsim/lpp
             	@echo "libs done"
             clean:
             	@rm -Rf modelsim
             	@rm -Rf modelsim.ini
             	@rm -Rf *~
             	@rm -Rf transcript
             	@rm -Rf wlft*
             	@rm -Rf *.wlf
             	@rm -Rf vish_stacktrace.vstf
             	@rm -Rf libs.do
             vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
             vcom_tb:
-            	$(CMD_VCOM) lpp  lpp_memory.vhd
+            ##	$(CMD_VCOM) lpp  lpp_memory.vhd
-            	$(CMD_VCOM) lpp  lppFIFOxN.vhd
+            ##	$(CMD_VCOM) lpp  lppFIFOxN.vhd
-            	$(CMD_VCOM) lpp  lpp_FIFO.vhd
+            ##	$(CMD_VCOM) lpp  lpp_FIFO.vhd
-            	$(CMD_VCOM) lpp  spectral_matrix_package.vhd
+            ##	$(CMD_VCOM) lpp  lpp_lfr_ms.vhd
-            	$(CMD_VCOM) lpp  spectral_matrix_switch_f0.vhd
-            	$(CMD_VCOM) lpp  spectral_matrix_time_managment.vhd
-            	$(CMD_VCOM) lpp  MS_control.vhd
-            	$(CMD_VCOM) lpp  MS_calculation.vhd
-            	$(CMD_VCOM) lpp  lpp_lfr_ms.vhd
             	$(CMD_VCOM) work TB.vhd
             	@echo "vcom done"
             vcom_grlib:
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
             	@echo "vcom grlib done"
             vcom_gaisler:
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
             ##	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
             	@echo "vcom gaisler done"
             vcom_techmap:
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
             	@echo "vcom techmap done"
             vcom_lpp:
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
-            	$(CMD_VCOM) lpp  lpp_memory.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
-            	$(CMD_VCOM) lpp lpp_lfr_ms_fsmdma.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
             	@echo "vcom lpp done"
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
             # 	@echo "vcom lpp done"
             #include Makefile_vcom_lpp

lib/lpp/dirs.txt +1 0

             ./amba_lcd_16x2_ctrlr
             ./general_purpose
             ./general_purpose/lpp_AMR
             ./general_purpose/lpp_balise
             ./general_purpose/lpp_delay
             ./lpp_amba
             ./dsp/iir_filter
             ./dsp/lpp_downsampling
             ./dsp/lpp_fft
             ./lfr_time_management
             ./lpp_ad_Conv
             ./lpp_bootloader
             ./lpp_cna
+            ./lpp_spectral_matrix
             ./lpp_demux
             ./lpp_Header
             ./lpp_matrix
             ./lpp_memory
             ./lpp_dma
             ./lpp_uart
             ./lpp_usb
             ./lpp_waveform
             ./lpp_top_lfr
             ./lpp_Header
             ./lpp_leon3_soc
             ./lpp_debug_lfr
             ./lpp_sim/CY7C1061DV33

lib/lpp/lpp_memory/lppFIFOxN.vhd +54 -37

@@ -1,65 +1,82
1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
3	-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4	--	4	--
5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
8	-- (at your option) any later version.	8	-- (at your option) any later version.
9	--	9	--
10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
14	--	14	--
15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18	------------------------------------------------------------------------------	18	------------------------------------------------------------------------------
19	-- Author : Martin Morlot	19	-- Author : Martin Morlot
20	-- Mail : martin.morlot@lpp.polytechnique.fr	20	-- Mail : martin.morlot@lpp.polytechnique.fr
21	------------------------------------------------------------------------------	21	------------------------------------------------------------------------------
22	library IEEE;	22	LIBRARY IEEE;
23	~~use~~ IEEE.std_logic_1164.~~all~~;	23	USE IEEE.std_logic_1164.ALL;
24	~~use~~ IEEE.numeric_std.~~all~~;	24	USE IEEE.numeric_std.ALL;
25	library lpp;	25	LIBRARY lpp;
26	~~use~~ lpp.lpp_memory.~~all~~;	26	USE lpp.lpp_memory.ALL;
27	~~use~~ lpp.iir_filter.~~all~~;	27	USE lpp.iir_filter.ALL;
28	library techmap;	28	LIBRARY techmap;
29	~~use~~ techmap.gencomp.~~all~~;	29	USE techmap.gencomp.ALL;
30		30
31	entity lppFIFOxN is	31	ENTITY lppFIFOxN IS
32	generic(	32	GENERIC(
33	tech : ~~integer~~ := 0;	33	tech : INTEGER := 0;
34	Mem_use : ~~integer~~ := use_RAM;	34	Mem_use : INTEGER := use_RAM;
35	Data_sz : ~~integer~~ ~~range~~ 1 to 32 := 8;	35	Data_sz : INTEGER RANGE 1 TO 32 := 8;
36	Addr_sz : ~~integer~~ ~~range~~ 2 to 12 := 8;	36	Addr_sz : INTEGER RANGE 2 TO 12 := 8;
37	FifoCnt : ~~integer~~ := 1;	37	FifoCnt : INTEGER := 1
38	Enable_ReUse : std_logic := '0'
39	);	38	);
40	port(	39	PORT(
41	rstn : in std_logic;	40	clk : IN STD_LOGIC;
42	wclk : in std_logic;	41	rstn : IN STD_LOGIC;
43	rclk : in std_logic;	42
44	ReUse : in std_logic_vector(FifoCnt-1 downto 0);	43	ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
45	wen : in std_logic_vector(FifoCnt-1 downto 0);	44
46	ren : in std_logic_vector(FifoCnt-1 downto 0);	45	wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
47	wdata : in ~~std_logic_vector~~((FifoCnt*Data_sz)-1 ~~downto~~ 0);	46	wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
48	rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);	47
49	full : out std_logic_vector(FifoCnt-1 downto 0);	48	ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
50	empty : out std_logic_vector(FifoCnt-1 downto 0)	49	rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
51	);	50
52	end entity;	51	empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		52	full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		53	almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
		54	);
		55	END ENTITY;
53		56
54		57
55	~~architecture~~ ar_lppFIFOxN of lppFIFOxN is	58	ARCHITECTURE ar_lppFIFOxN OF lppFIFOxN IS
56		59
57	begin	60	BEGIN
58		61
59	fifos: for i in 0 to FifoCnt-1 generate	62	fifos : FOR i IN 0 TO FifoCnt-1 GENERATE
60	~~FIFO0~~ : lpp_fifo	63	lpp_fifo_1: lpp_fifo
61	generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)	64	GENERIC MAP (
62	port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)Data_sz-1 downto iData_sz),empty(i),open,wclk,wen(i),wdata((i+1)Data_sz-1 downto iData_sz),full(i),open);	65	tech => tech,
63	end generate;	66	Mem_use => Mem_use,
		67	DataSz => Data_sz,
		68	AddrSz => Addr_sz)
		69	PORT MAP (
		70	clk => clk,
		71	rstn => rstn,
		72	reUse => reUse(I),
		73	ren => ren(I),
		74	rdata => rdata( ((I+1)Data_sz)-1 DOWNTO (IData_sz) ),
		75	wen => wen(I),
		76	wdata => wdata(((I+1)Data_sz)-1 DOWNTO (IData_sz)),
		77	empty => empty(I),
		78	full => full(I),
		79	almost_full => almost_full(I));
		80	END GENERATE;
64		81
65	end architecture;	82	END ARCHITECTURE;

lib/lpp/lpp_memory/lpp_FIFO.vhd +112 -101

@@ -1,179 +1,190
1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
3	-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4	--	4	--
5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
8	-- (at your option) any later version.	8	-- (at your option) any later version.
9	--	9	--
10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
14	--	14	--
15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18	------------------------------------------------------------------------------	18	------------------------------------------------------------------------------
19	-- Author : Martin Morlot	19	-- Author : Martin Morlot
20	-- Mail : martin.morlot@lpp.polytechnique.fr	20	-- Mail : martin.morlot@lpp.polytechnique.fr
21	------------------------------------------------------------------------------	21	------------------------------------------------------------------------------
22	library IEEE;	22	LIBRARY IEEE;
23	~~use~~ IEEE.std_logic_1164.~~all~~;	23	USE IEEE.std_logic_1164.ALL;
24	~~use~~ IEEE.numeric_std.~~all~~;	24	USE IEEE.numeric_std.ALL;
25	library lpp;	25	LIBRARY lpp;
26	~~use~~ lpp.lpp_memory.~~all~~;	26	USE lpp.lpp_memory.ALL;
27	~~use~~ lpp.iir_filter.~~all~~;	27	USE lpp.iir_filter.ALL;
28	library techmap;	28	LIBRARY techmap;
29	~~use~~ techmap.gencomp.~~all~~;	29	USE techmap.gencomp.ALL;
30		30
31	entity lpp_fifo is	31	ENTITY lpp_fifo IS
32	generic(	32	GENERIC(
33	tech : ~~integer~~ := 0;	33	tech : INTEGER := 0;
34	Mem_use : ~~integer~~ := use_RAM;	34	Mem_use : INTEGER := use_RAM;
35	Enable_ReUse : std_logic := '0';	35	DataSz : INTEGER RANGE 1 TO 32 := 8;
36	DataSz : integer range 1 to 32 := 8;	36	AddrSz : INTEGER RANGE 2 TO 12 := 8
37	AddrSz : integer range 2 to 12 := 8
38	);	37	);
39	port(	38	PORT(
40	rstn : in std_logic;	39	clk : IN STD_LOGIC;
41	ReUse : in std_logic;	40	rstn : IN STD_LOGIC;
42	rclk : in std_logic;	41	--
43	ren : in std_logic;	42	reUse : IN STD_LOGIC;
44	rdata : out std_logic_vector(DataSz-1 downto 0);	43
45	empty : out std_logic;	44	--IN
46	raddr : out std_logic_vector(AddrSz-1 downto 0);	45	ren : IN STD_LOGIC;
47	wclk : in std_logic;	46	rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
48	wen : in std_logic;	47
49	wdata : in std_logic_vector(DataSz-1 downto 0);	48	--OUT
50	full : out std_logic;	49	wen : IN STD_LOGIC;
51	waddr : out std_logic_vector(AddrSz-1 downto 0)	50	wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
52	);	51
53	end entity;	52	empty : OUT STD_LOGIC;
		53	full : OUT STD_LOGIC;
		54	almost_full : OUT STD_LOGIC
		55	);
		56	END ENTITY;
54		57
55		58
56	architecture ar_lpp_fifo of lpp_fifo is	59	ARCHITECTURE ar_lpp_fifo OF lpp_fifo IS
57		60
58	signal sFull : std_logic;	61	SIGNAL sFull : STD_LOGIC;
59	signal sFull_s : std_logic;	62	SIGNAL sFull_s : STD_LOGIC;
60	signal sEmpty_s : std_logic;	63	SIGNAL sEmpty_s : STD_LOGIC;
61		64
62	signal sEmpty : std_logic;	65	SIGNAL sEmpty : STD_LOGIC;
63	signal sREN : std_logic;	66	SIGNAL sREN : STD_LOGIC;
64	signal sWEN : std_logic;	67	SIGNAL sWEN : STD_LOGIC;
65	signal sRE : std_logic;	68	SIGNAL sRE : STD_LOGIC;
66	signal sWE : std_logic;	69	SIGNAL sWE : STD_LOGIC;
67		70
68	signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');	71	SIGNAL Waddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
69	signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');	72	SIGNAL Raddr_vect : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
70	signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');	73	SIGNAL Waddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
71	signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');	74	SIGNAL Raddr_vect_s : STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0) := (OTHERS => '0');
72		75
73	begin	76	SIGNAL almost_full_s : STD_LOGIC;
		77	SIGNAL almost_full_r : STD_LOGIC;
		78	BEGIN
74		79
75	--==================================================================================	80	--==================================================================================
76	-- /!\ syncram_2p Write et Read actif a l'�tat haut /!\	81	-- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
77	-- A l'inverse de RAM_CEL !!!	82	-- A l'inverse de RAM_CEL !!!
78	--==================================================================================	83	--==================================================================================
79	memRAM : IF Mem_use = use_RAM GENERATE	84	memRAM : IF Mem_use = use_RAM GENERATE
80	SRAM : syncram_2p	85	SRAM : syncram_2p
81	~~generic~~ ~~map~~(tech,AddrSz,DataSz)	86	GENERIC MAP(tech, AddrSz, DataSz)
82	~~port~~ ~~map~~(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);	87	PORT MAP(CLK, sRE, Raddr_vect, rdata, CLK, sWE, Waddr_vect, wdata);
83	END GENERATE;	88	END GENERATE;
84	--==================================================================================	89	--==================================================================================
85	memCEL : IF Mem_use = use_CEL GENERATE	90	memCEL : IF Mem_use = use_CEL GENERATE
86	CRAM : RAM_CEL	91	CRAM : RAM_CEL
87	~~generic~~ ~~map~~(DataSz,AddrSz)	92	GENERIC MAP(DataSz, AddrSz)
88	~~port~~ ~~map~~(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);	93	PORT MAP(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, CLK, rstn);
89	END GENERATE;	94	END GENERATE;
90	--==================================================================================	95	--==================================================================================
91		96
92	--=============================	97	--=============================
93	-- Read section	98	-- Read section
94	--=============================	99	--=============================
95	sREN <= REN or sEmpty;	100	sREN <= REN OR sEmpty;
96	sRE <= ~~not~~ sREN;	101	sRE <= NOT sREN;
97		102
98	sEmpty_s <= '0' ~~when~~ ReUse = '1' ~~and~~ ~~Enable_ReUse~~=~~'1'~~ else	103	sEmpty_s <= '0' WHEN ReUse = '1' else
99	'1' when sEmpty = '1' and Wen = '1' else	104	'1' WHEN sEmpty = '1' AND Wen = '1' ELSE
100	'1' ~~when~~ sEmpty = '0' ~~and~~ (Wen = '1' ~~and~~ Ren = '0' ~~and~~ Raddr_vect_s = Waddr_vect) ~~else~~	105	'1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
101	'0';	106	'0';
102		107
103	Raddr_vect_s <= ~~std_logic_vector~~(~~unsigned~~(Raddr_vect) +1);	108	Raddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Raddr_vect) +1);
104		109
105	process (rclk,rstn)	110	PROCESS (clk, rstn)
106	begin	111	BEGIN
107	if(rstn='0')then	112	IF(rstn = '0')then
108	Raddr_vect <= (~~others~~ =>'0');	113	Raddr_vect <= (OTHERS => '0');
109	sempty <= '1';	114	sempty <= '1';
110	elsif(rclk'event and rclk='1')then	115	ELSIF(clk'EVENT AND clk = '1')then
111	sEmpty <= sempty_s;	116	sEmpty <= sempty_s;
112
113	if(sREN='0' and sempty = '0')then
114	Raddr_vect <= Raddr_vect_s;
115	end if;
116		117
117	end if;	118	IF(sREN = '0' and sempty = '0')then
118	end process;	119	Raddr_vect <= Raddr_vect_s;
		120	END IF;
		121
		122	END IF;
		123	END PROCESS;
119		124
120	--=============================	125	--=============================
121	-- Write section	126	-- Write section
122	--=============================	127	--=============================
123	sWEN <= WEN or sFull;	128	sWEN <= WEN OR sFull;
124	sWE <= ~~not~~ sWEN;	129	sWE <= NOT sWEN;
125		130
126	sFull_s <= '1' ~~when~~ ReUse = '1' ~~and~~ ~~Enable_ReUse~~=~~'1'~~ else	131	sFull_s <= '1' WHEN ReUse = '1' else
127	'1' ~~when~~ Waddr_vect_s = Raddr_vect ~~and~~ REN = '1' ~~and~~ WEN = '0' ~~else~~	132	'1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
128	'1' ~~when~~ sFull = '1' ~~and~~ REN = '1' ~~else~~	133	'1' WHEN sFull = '1' AND REN = '1' ELSE
129	'0';	134	'0';
130		135
131	Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1);	136	almost_full_s <= '1' WHEN STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +2) = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
		137	'1' WHEN almost_full_r = '1' AND WEN = REN ELSE
		138	'0';
		139
		140	Waddr_vect_s <= STD_LOGIC_VECTOR(UNSIGNED(Waddr_vect) +1);
132		141
133	process (wclk,rstn)	142	PROCESS (clk, rstn)
134	begin	143	BEGIN
135	if(rstn='0')then	144	IF(rstn = '0')then
136	Waddr_vect <= (~~others~~ =>'0');	145	Waddr_vect <= (OTHERS => '0');
137	sfull <= '0';	146	sfull <= '0';
138	elsif(wclk'event and wclk='1')then	147	almost_full_r <= '0';
139	sfull <= sfull_s;	148	ELSIF(clk'EVENT AND clk = '1')then
		149	sfull <= sfull_s;
		150	almost_full_r <= almost_full_s;
140		151
141	if(sWEN='0' and sfull='0')~~then~~	152	IF(sWEN = '0' and sfull = '0')THEN
142	Waddr_vect <= Waddr_vect_s;	153	Waddr_vect <= Waddr_vect_s;
143	end if;	154	END IF;
144		155
145	end if;	156	END IF;
146	end process;	157	END PROCESS;
		158
		159	almost_full <= almost_full_s;
		160	full <= sFull_s;
		161	empty <= sEmpty_s;
147		162
148		163
149	full <= sFull_s;	164
150	empty <= sEmpty_s;	165	END ARCHITECTURE;
151	waddr <= Waddr_vect;
152	raddr <= Raddr_vect;
153
154	end architecture;
155		166
156		167
157		168
158		169
159		170
160		171
161		172
162		173
163		174
164		175
165		176
166		177
167		178
168		179
169		180
170		181
171		182
172		183
173		184
174		185
175		186
176		187
177		188
178		189
179		190

lib/lpp/lpp_memory/lpp_memory.vhd +209 -165

@@ -1,197 +1,241
1	------------------------------------------------------------------------------	1	------------------------------------------------------------------------------
2	-- This file is a part of the LPP VHDL IP LIBRARY	2	-- This file is a part of the LPP VHDL IP LIBRARY
3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4	--	4	--
5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
7	-- the Free Software Foundation; either version 3 of the License, or	7	-- the Free Software Foundation; either version 3 of the License, or
8	-- (at your option) any later version.	8	-- (at your option) any later version.
9	--	9	--
10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
14	--	14	--
15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18	------------------------------------------------------------------------------	18	------------------------------------------------------------------------------
19	-- Author : Martin Morlot	19	-- Author : Martin Morlot
20	-- Mail : martin.morlot@lpp.polytechnique.fr	20	-- Mail : martin.morlot@lpp.polytechnique.fr
21	------------------------------------------------------------------------------	21	------------------------------------------------------------------------------
22	library ieee;	22	LIBRARY ieee;
23	~~use~~ ieee.std_logic_1164.~~all~~;	23	USE ieee.std_logic_1164.ALL;
24	library grlib;	24	LIBRARY grlib;
25	~~use~~ grlib.amba.~~all~~;	25	USE grlib.amba.ALL;
26	~~use~~ std.textio.~~all~~;	26	USE std.textio.ALL;
27	library lpp;	27	LIBRARY lpp;
28	~~use~~ lpp.lpp_amba.~~all~~;	28	USE lpp.lpp_amba.ALL;
29	~~use~~ lpp.iir_filter.~~all~~;	29	USE lpp.iir_filter.ALL;
30	library gaisler;	30	LIBRARY gaisler;
31	~~use~~ gaisler.misc.~~all~~;	31	USE gaisler.misc.ALL;
32	~~use~~ gaisler.memctrl.~~all~~;	32	USE gaisler.memctrl.ALL;
33	library techmap;	33	LIBRARY techmap;
34	~~use~~ techmap.gencomp.~~all~~;	34	USE techmap.gencomp.ALL;
35		35
36	--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on	36	--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
37		37
38	package lpp_memory is	38	PACKAGE lpp_memory IS
39
40	component APB_FIFO is
41	generic (
42	tech : integer := apa3;
43	pindex : integer := 0;
44	paddr : integer := 0;
45	pmask : integer := 16#fff#;
46	pirq : integer := 0;
47	abits : integer := 8;
48	FifoCnt : integer := 2;
49	Data_sz : integer := 16;
50	Addr_sz : integer := 9;
51	Enable_ReUse : std_logic := '0';
52	Mem_use : integer := use_RAM;
53	R : integer := 1;
54	W : integer := 1
55	);
56	port (
57	clk : in std_logic; --! Horloge du composant
58	rst : in std_logic; --! Reset general du composant
59	rclk : in std_logic;
60	wclk : in std_logic;
61	ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62	REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
63	WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
64	Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
65	Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
66	RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
67	WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
68	WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
69	RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70	apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
71	apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72	);
73	end component;
74		39
75	component FIFO_pipeline is	40	COMPONENT lpp_fifo
76	generic(	41	GENERIC (
77	tech : integer := 0;	42	tech : INTEGER;
78	Mem_use : integer := use_RAM;	43	Mem_use : INTEGER;
79	fifoCount : integer range 2 to 32 := 8;	44	DataSz : INTEGER RANGE 1 TO 32;
80	DataSz : integer range 1 to 32 := 8;	45	AddrSz : INTEGER RANGE 2 TO 12);
81	abits : integer range 2 to 12 := 8	46	PORT (
82	);	47	clk : IN STD_LOGIC;
83	port(	48	rstn : IN STD_LOGIC;
84	rstn : in std_logic;	49	reUse : IN STD_LOGIC;
85	ReUse : in std_logic;	50	ren : IN STD_LOGIC;
86	rclk : in std_logic;	51	rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
87	ren : in std_logic;	52	wen : IN STD_LOGIC;
88	rdata : out std_logic_vector(DataSz-1 downto 0);	53	wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
89	empty : out std_logic;	54	empty : OUT STD_LOGIC;
90	raddr : out std_logic_vector(abits-1 downto 0);	55	full : OUT STD_LOGIC;
91	wclk : in std_logic;	56	almost_full : OUT STD_LOGIC);
92	wen : in std_logic;	57	END COMPONENT;
93	wdata : in std_logic_vector(DataSz-1 downto 0);
94	full : out std_logic;
95	waddr : out std_logic_vector(abits-1 downto 0)
96	);
97	end component;
98		58
99	component lpp_fifo is	59	COMPONENT lppFIFOxN
100	generic(	60	GENERIC (
101	tech : integer := 0;	61	tech : INTEGER;
102	Mem_use : integer := use_RAM;	62	Mem_use : INTEGER;
103	Enable_ReUse : std_logic := '0';	63	Data_sz : INTEGER RANGE 1 TO 32;
104	DataSz : integer range 1 to 32 := 8;	64	Addr_sz : INTEGER RANGE 2 TO 12;
105	AddrSz : integer range 2 to 12 := 8	65	FifoCnt : INTEGER);
106	);	66	PORT (
107	port(	67	clk : IN STD_LOGIC;
108	rstn : in std_logic;	68	rstn : IN STD_LOGIC;
109	ReUse : in std_logic; --27/01/12	69	ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
110	rclk : in std_logic;	70	wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
111	ren : in std_logic;	71	wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
112	rdata : out std_logic_vector(DataSz-1 downto 0);	72	ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
113	empty : out std_logic;	73	rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
114	raddr : out std_logic_vector(AddrSz-1 downto 0);	74	empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
115	wclk : in std_logic;	75	full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
116	wen : in std_logic;	76	almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0));
117	wdata : in std_logic_vector(DataSz-1 downto 0);	77	END COMPONENT;
118	full : out std_logic;
119	waddr : out std_logic_vector(AddrSz-1 downto 0)
120	);
121	end component;
122		78
123		79
124	component lppFIFOxN is	80
125	generic(
126	tech : integer := 0;
127	Mem_use : integer := use_RAM;
128	Data_sz : integer range 1 to 32 := 8;
129	Addr_sz : integer range 1 to 32 := 8;
130	FifoCnt : integer := 1;
131	Enable_ReUse : std_logic := '0'
132	);
133	port(
134	rstn : in std_logic;
135	wclk : in std_logic;
136	rclk : in std_logic;
137	ReUse : in std_logic_vector(FifoCnt-1 downto 0);
138	wen : in std_logic_vector(FifoCnt-1 downto 0);
139	ren : in std_logic_vector(FifoCnt-1 downto 0);
140	wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
141	rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
142	full : out std_logic_vector(FifoCnt-1 downto 0);
143	empty : out std_logic_vector(FifoCnt-1 downto 0)
144	);
145	end component;
146		81
147	component FillFifo is	82	COMPONENT APB_FIFO IS
148	generic(	83	GENERIC (
149	Data_sz : integer range 1 to 32 := 16;	84	tech : INTEGER := apa3;
150	Fifo_cnt : integer range 1 to 8 := 5	85	pindex : INTEGER := 0;
151	);	86	paddr : INTEGER := 0;
152	port(	87	pmask : INTEGER := 16#fff#;
153	clk : in std_logic;	88	pirq : INTEGER := 0;
154	raz : in std_logic;	89	abits : INTEGER := 8;
155	write : out std_logic_vector(Fifo_cnt-1 downto 0);	90	FifoCnt : INTEGER := 2;
156	reuse : out std_logic_vector(Fifo_cnt-1 downto 0);	91	Data_sz : INTEGER := 16;
157	data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)	92	Addr_sz : INTEGER := 9;
158	);	93	Enable_ReUse : STD_LOGIC := '0';
159	end component;	94	Mem_use : INTEGER := use_RAM;
		95	R : INTEGER := 1;
		96	W : INTEGER := 1
		97	);
		98	PORT (
		99	clk : IN STD_LOGIC; --! Horloge du composant
		100	rst : IN STD_LOGIC; --! Reset general du composant
		101	rclk : IN STD_LOGIC;
		102	wclk : IN STD_LOGIC;
		103	ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		104	REN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction de lecture en m�moire
		105	WEN : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Instruction d'�criture en m�moire
		106	Empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, M�moire vide
		107	Full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0); --! Flag, M�moire pleine
		108	RDATA : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donn�es en entr�e
		109	WDATA : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0); --! Registre de donn�es en sortie
		110	WADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (�criture)
		111	RADDR : OUT STD_LOGIC_VECTOR((FifoCnt*Addr_sz)-1 DOWNTO 0); --! Registre d'addresse (lecture)
		112	apbi : IN apb_slv_in_type; --! Registre de gestion des entr�es du bus
		113	apbo : OUT apb_slv_out_type --! Registre de gestion des sorties du bus
		114	);
		115	END COMPONENT;
		116
		117	COMPONENT FIFO_pipeline IS
		118	GENERIC(
		119	tech : INTEGER := 0;
		120	Mem_use : INTEGER := use_RAM;
		121	fifoCount : INTEGER RANGE 2 TO 32 := 8;
		122	DataSz : INTEGER RANGE 1 TO 32 := 8;
		123	abits : INTEGER RANGE 2 TO 12 := 8
		124	);
		125	PORT(
		126	rstn : IN STD_LOGIC;
		127	ReUse : IN STD_LOGIC;
		128	rclk : IN STD_LOGIC;
		129	ren : IN STD_LOGIC;
		130	rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
		131	empty : OUT STD_LOGIC;
		132	raddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
		133	wclk : IN STD_LOGIC;
		134	wen : IN STD_LOGIC;
		135	wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
		136	full : OUT STD_LOGIC;
		137	waddr : OUT STD_LOGIC_VECTOR(abits-1 DOWNTO 0)
		138	);
		139	END COMPONENT;
160		140
161	component Bridge is	141	--COMPONENT lpp_fifo IS
162	port(	142	-- GENERIC(
163	clk : in std_logic;	143	-- tech : INTEGER := 0;
164	raz : in std_logic;	144	-- Mem_use : INTEGER := use_RAM;
165	EmptyUp : in std_logic;	145	-- Enable_ReUse : STD_LOGIC := '0';
166	FullDwn : in std_logic;	146	-- DataSz : INTEGER RANGE 1 TO 32 := 8;
167	WriteDwn : out std_logic;	147	-- AddrSz : INTEGER RANGE 2 TO 12 := 8
168	ReadUp : out std_logic	148	-- );
169	);	149	-- PORT(
170	end component;	150	-- rstn : IN STD_LOGIC;
		151	-- ReUse : IN STD_LOGIC; --27/01/12
		152	-- rclk : IN STD_LOGIC;
		153	-- ren : IN STD_LOGIC;
		154	-- rdata : OUT STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
		155	-- empty : OUT STD_LOGIC;
		156	-- raddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0);
		157	-- wclk : IN STD_LOGIC;
		158	-- wen : IN STD_LOGIC;
		159	-- wdata : IN STD_LOGIC_VECTOR(DataSz-1 DOWNTO 0);
		160	-- full : OUT STD_LOGIC;
		161	-- almost_full : OUT STD_LOGIC;
		162	-- waddr : OUT STD_LOGIC_VECTOR(AddrSz-1 DOWNTO 0)
		163	-- );
		164	--END COMPONENT;
		165
		166
		167	--COMPONENT lppFIFOxN IS
		168	-- GENERIC(
		169	-- tech : INTEGER := 0;
		170	-- Mem_use : INTEGER := use_RAM;
		171	-- Data_sz : INTEGER RANGE 1 TO 32 := 8;
		172	-- Addr_sz : INTEGER RANGE 1 TO 32 := 8;
		173	-- FifoCnt : INTEGER := 1;
		174	-- Enable_ReUse : STD_LOGIC := '0'
		175	-- );
		176	-- PORT(
		177	-- rstn : IN STD_LOGIC;
		178	-- wclk : IN STD_LOGIC;
		179	-- rclk : IN STD_LOGIC;
		180	-- ReUse : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		181	-- wen : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		182	-- ren : IN STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		183	-- wdata : IN STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
		184	-- rdata : OUT STD_LOGIC_VECTOR((FifoCnt*Data_sz)-1 DOWNTO 0);
		185	-- full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		186	-- almost_full : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0);
		187	-- empty : OUT STD_LOGIC_VECTOR(FifoCnt-1 DOWNTO 0)
		188	-- );
		189	--END COMPONENT;
171		190
172	component ssram_plugin is	191	COMPONENT FillFifo IS
173	generic (tech : integer := 0);	192	GENERIC(
174	port	193	Data_sz : INTEGER RANGE 1 TO 32 := 16;
175	(	194	Fifo_cnt : INTEGER RANGE 1 TO 8 := 5
176	clk : in std_logic;	195	);
177	mem_ctrlr_o : in memory_out_type;	196	PORT(
178	SSRAM_CLK : out std_logic;	197	clk : IN STD_LOGIC;
179	nBWa : out std_logic;	198	raz : IN STD_LOGIC;
180	nBWb : out std_logic;	199	write : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
181	nBWc : out std_logic;	200	reuse : OUT STD_LOGIC_VECTOR(Fifo_cnt-1 DOWNTO 0);
182	nBWd : out std_logic;	201	data : OUT STD_LOGIC_VECTOR(Fifo_cnt*Data_sz-1 DOWNTO 0)
183	nBWE : out std_logic;	202	);
184	nADSC : out std_logic;	203	END COMPONENT;
185	nADSP : out std_logic;	204
186	nADV : out std_logic;	205	COMPONENT Bridge IS
187	nGW : out std_logic;	206	PORT(
188	nCE1 : out std_logic;	207	clk : IN STD_LOGIC;
189	CE2 : out std_logic;	208	raz : IN STD_LOGIC;
190	nCE3 : out std_logic;	209	EmptyUp : IN STD_LOGIC;
191	nOE : out std_logic;	210	FullDwn : IN STD_LOGIC;
192	MODE : out std_logic;	211	WriteDwn : OUT STD_LOGIC;
193	ZZ : out std_logic	212	ReadUp : OUT STD_LOGIC
194	);	213	);
195	end component;	214	END COMPONENT;
196		215
197	end; No newline at end of file	216	COMPONENT ssram_plugin IS
		217	GENERIC (tech : INTEGER := 0);
		218	PORT
		219	(
		220	clk : IN STD_LOGIC;
		221	mem_ctrlr_o : IN memory_out_type;
		222	SSRAM_CLK : OUT STD_LOGIC;
		223	nBWa : OUT STD_LOGIC;
		224	nBWb : OUT STD_LOGIC;
		225	nBWc : OUT STD_LOGIC;
		226	nBWd : OUT STD_LOGIC;
		227	nBWE : OUT STD_LOGIC;
		228	nADSC : OUT STD_LOGIC;
		229	nADSP : OUT STD_LOGIC;
		230	nADV : OUT STD_LOGIC;
		231	nGW : OUT STD_LOGIC;
		232	nCE1 : OUT STD_LOGIC;
		233	CE2 : OUT STD_LOGIC;
		234	nCE3 : OUT STD_LOGIC;
		235	nOE : OUT STD_LOGIC;
		236	MODE : OUT STD_LOGIC;
		237	ZZ : OUT STD_LOGIC
		238	);
		239	END COMPONENT;
		240
		241	END;

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +962 -278

This diff has been collapsed as it changes many lines, (1240 lines changed) Show them Hide them
	@@ -1,394 +1,1078
	1	LIBRARY ieee;	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;	2	USE ieee.std_logic_1164.ALL;
	3		3
			4
	4	LIBRARY lpp;	5	LIBRARY lpp;
	5	USE lpp.lpp_amba.ALL;
	6	USE lpp.lpp_memory.ALL;	6	USE lpp.lpp_memory.ALL;
	7	--USE lpp.~~lpp_uart~~.ALL;	7	USE lpp.iir_filter.ALL;
			8	USE lpp.spectral_matrix_package.ALL;
			9	USE lpp.lpp_dma_pkg.ALL;
			10	USE lpp.lpp_Header.ALL;
	8	USE lpp.lpp_matrix.ALL;	11	USE lpp.lpp_matrix.ALL;
	9	--USE lpp.lpp_~~delay~~.ALL;	12	USE lpp.lpp_matrix.ALL;
			13	USE lpp.lpp_lfr_pkg.ALL;
	10	USE lpp.lpp_fft.ALL;	14	USE lpp.lpp_fft.ALL;
	11	USE lpp.fft_components.ALL;	15	USE lpp.fft_components.ALL;
	12	USE lpp.lpp_ad_conv.ALL;
	13	USE lpp.iir_filter.ALL;
	14	USE lpp.general_purpose.ALL;
	15	USE lpp.Filtercfg.ALL;
	16	USE lpp.lpp_demux.ALL;
	17	USE lpp.lpp_top_lfr_pkg.ALL;
	18	USE lpp.lpp_dma_pkg.ALL;
	19	USE lpp.lpp_Header.ALL;
	20	USE lpp.lpp_lfr_pkg.ALL;
	21
	22	LIBRARY grlib;
	23	USE grlib.amba.ALL;
	24	USE grlib.stdlib.ALL;
	25	USE grlib.devices.ALL;
	26	USE GRLIB.DMA2AHB_Package.ALL;
	27
	28		16
	29	ENTITY lpp_lfr_ms IS	17	ENTITY lpp_lfr_ms IS
	30	GENERIC (	18	GENERIC (
	31	Mem_use : INTEGER := use_RAM	19	Mem_use : INTEGER := use_RAM
	32	);	20	);
	33	PORT (	21	PORT (
	34	clk : IN STD_LOGIC;	22	clk : IN STD_LOGIC;
	35	rstn : IN STD_LOGIC;	23	rstn : IN STD_LOGIC;
	36		24
	37	---------------------------------------------------------------------------	25	---------------------------------------------------------------------------
	38	-- DATA INPUT	26	-- DATA INPUT
	39	---------------------------------------------------------------------------	27	---------------------------------------------------------------------------
	40	-- TIME	28	-- TIME
	41	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo	29	coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
	42	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo	30	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
	43	--	31	--
	44	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	32	sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	45	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	33	sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	46	--	34	--
	47	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	35	sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	48	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	36	sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	49	--	37	--
	50	sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);	38	sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	51	sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);	39	sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	52		40
	53	---------------------------------------------------------------------------	41	---------------------------------------------------------------------------
	54	-- DMA	42	-- DMA
	55	---------------------------------------------------------------------------	43	---------------------------------------------------------------------------
	56	dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	44	dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	57	dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	45	dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	58	dma_valid : OUT STD_LOGIC;	46	dma_valid : OUT STD_LOGIC;
	59	dma_valid_burst : OUT STD_LOGIC;	47	dma_valid_burst : OUT STD_LOGIC;
	60	dma_ren : IN STD_LOGIC;	48	dma_ren : IN STD_LOGIC;
	61	dma_done : IN STD_LOGIC;	49	dma_done : IN STD_LOGIC;
	62		50
	63	-- Reg out	51	-- Reg out
	64	ready_matrix_f0_0 : OUT STD_LOGIC;	52	ready_matrix_f0 : OUT STD_LOGIC;
	65	ready_matrix_f0_1 : OUT STD_LOGIC;	53	-- ready_matrix_f0 : OUT STD_LOGIC;
	66	ready_matrix_f1 : OUT STD_LOGIC;	54	ready_matrix_f1 : OUT STD_LOGIC;
	67	ready_matrix_f2 : OUT STD_LOGIC;	55	ready_matrix_f2 : OUT STD_LOGIC;
	68	error_anticipating_empty_fifo : OUT STD_LOGIC;	56	--error_anticipating_empty_fifo : OUT STD_LOGIC;
	69	error_bad_component_error : OUT STD_LOGIC;	57	error_bad_component_error : OUT STD_LOGIC;
			58	error_buffer_full : OUT STD_LOGIC;
			59	error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
			60
	70	debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);	61	debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	71		62
	72	-- Reg In	63	-- Reg In
	73	status_ready_matrix_f0_0 :IN STD_LOGIC;	64	status_ready_matrix_f0 : IN STD_LOGIC;
	74	status_ready_matrix_f0_1 :IN STD_LOGIC;	65	-- status_ready_matrix_f0_1 : IN STD_LOGIC;
	75	status_ready_matrix_f1 :IN STD_LOGIC;	66	status_ready_matrix_f1 : IN STD_LOGIC;
	76	status_ready_matrix_f2 :IN STD_LOGIC;	67	status_ready_matrix_f2 : IN STD_LOGIC;
	77	status_error_anticipating_empty_fifo :IN STD_LOGIC;	68	-- status_error_anticipating_empty_fifo : IN STD_LOGIC;
	78	status_error_bad_component_error :IN STD_LOGIC;	69	-- status_error_bad_component_error : IN STD_LOGIC;
	79		70	-- status_error_buffer_full : IN STD_LOGIC;
			71
	80	config_active_interruption_onNewMatrix : IN STD_LOGIC;	72	config_active_interruption_onNewMatrix : IN STD_LOGIC;
	81	config_active_interruption_onError : IN STD_LOGIC;	73	config_active_interruption_onError : IN STD_LOGIC;
	82	addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	74	-- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	83	addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	75	addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	84	addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	76	addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	85	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);	77	addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
	86		78
	87	matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	79	matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	88	matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	80	-- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	89	matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);	81	matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
	90	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)	82	matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
	91		83
	92	);	84	);
	93	END;	85	END;
	94		86
	95	ARCHITECTURE Behavioral OF lpp_lfr_ms IS	87	ARCHITECTURE Behavioral OF lpp_lfr_ms IS
	96	-----------------------------------------------------------------------------	88
	97	SIGNAL ~~FifoF0_Empty~~ : STD_LOGIC_VECTOR(4 DOWNTO 0);	89	SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	98	SIGNAL ~~FifoF1_Empty~~ : STD_LOGIC_VECTOR(4 DOWNTO 0);	90	SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
	99	SIGNAL ~~FifoF3_Empty~~ : STD_LOGIC_VECTOR(4 DOWNTO 0);	91	SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
	100	SIGNAL ~~FifoF0_Data~~ : STD_LOGIC_VECTOR(79 DOWNTO 0);	92	SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	101	SIGNAL ~~FifoF1_Data~~ : STD_LOGIC_VECTOR(79 DOWNTO 0);	93	SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	102	SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);	94
	103		95	SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	104	-----------------------------------------------------------------------------	96	SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
	105	SIGNAL ~~DMUX_Read~~ : STD_LOGIC_VECTOR(14 DOWNTO 0);	97	SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
	106	SIGNAL ~~DMUX_Empty~~ : STD_LOGIC_VECTOR(4 DOWNTO 0);	98	SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	107	SIGNAL ~~DMUX_Data~~ : STD_LOGIC_VECTOR(79 DOWNTO 0);	99	SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	108	SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
	109		100
	110	-----------------------------------------------------------------------------	101	SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	111	SIGNAL FFT_Load : STD_LOGIC;	102	SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
	112	SIGNAL ~~FFT_Read~~ : STD_LOGIC_VECTOR(4 DOWNTO 0);	103	SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	113	SIGNAL ~~FFT_Write~~ : STD_LOGIC_VECTOR(4 DOWNTO 0);	104	SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	114	SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
	115	SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	116		105
	117	-----------------------------------------------------------------------------	106	SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	118	SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	119	SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
	120		107
	121	-----------------------------------------------------------------------------	108	SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	122	SIGNAL SM_FlagError : STD_LOGIC;	109	SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
	123	-- SIGNAL SM_Pong : STD_LOGIC;	110	SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	124	SIGNAL SM_Wen : STD_LOGIC;	111	SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	125	SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
	126	SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
	127	SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
	128	SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
	129	SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
	130		112
	131	-----------------------------------------------------------------------------	113	SIGNAL error_wen_f0 : STD_LOGIC;
	132	SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);	114	SIGNAL error_wen_f1 : STD_LOGIC;
	133	SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);	115	SIGNAL error_wen_f2 : STD_LOGIC;
	134	SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);	116
			117	SIGNAL one_sample_f1_full : STD_LOGIC;
			118	SIGNAL one_sample_f1_wen : STD_LOGIC;
			119	SIGNAL one_sample_f2_full : STD_LOGIC;
			120	SIGNAL one_sample_f2_wen : STD_LOGIC;
	135		121
	136	-----------------------------------------------------------------------------	122	-----------------------------------------------------------------------------
	137	SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);	123	-- FSM / SWITCH SELECT CHANNEL
	138	SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
	139	SIGNAL Head_Empty : STD_LOGIC;
	140	SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
	141	SIGNAL Head_Valid : STD_LOGIC;
	142	SIGNAL Head_Val : STD_LOGIC;
	143
	144	-----------------------------------------------------------------------------	124	-----------------------------------------------------------------------------
	145	SIGNAL DMA_Read : STD_LOGIC;	125	TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
	146	SIGNAL DMA_ack : STD_LOGIC;	126	SIGNAL state_fsm_select_channel : fsm_select_channel;
	147		127	SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
	148	-----------------------------------------------------------------------------
	149	SIGNAL data_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
	150		128
	151	SIGNAL ~~debug_reg_s~~ : STD_LOGIC_VECTOR(31 DOWNTO 0);	129	SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
	152	SIGNAL dma_valid_s : STD_LOGIC;	130	SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
	153	SIGNAL dma_valid_burst_s : STD_LOGIC;	131	SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
	154		132	SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
	155	BEGIN
	156		133
	157	-----------------------------------------------------------------------------	134	-----------------------------------------------------------------------------
	158	Memf0: lppFIFOxN	135	-- FSM LOAD FFT
	159	GENERIC MAP (
	160	tech => 0, Mem_use => Mem_use, Data_sz => 16,
	161	Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
	162	PORT MAP (
	163	rstn => rstn, wclk => clk, rclk => clk,
	164	ReUse => (OTHERS => '0'),
	165	wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
	166	wdata => sample_f0_wdata, rdata => FifoF0_Data,
	167	full => OPEN, empty => FifoF0_Empty);
	168
	169	Memf1: lppFIFOxN
	170	GENERIC MAP (
	171	tech => 0, Mem_use => Mem_use, Data_sz => 16,
	172	Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
	173	PORT MAP (
	174	rstn => rstn, wclk => clk, rclk => clk,
	175	ReUse => (OTHERS => '0'),
	176	wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
	177	wdata => sample_f1_wdata, rdata => FifoF1_Data,
	178	full => OPEN, empty => FifoF1_Empty);
	179
	180
	181	Memf2: lppFIFOxN
	182	GENERIC MAP (
	183	tech => 0, Mem_use => Mem_use, Data_sz => 16,
	184	Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
	185	PORT MAP (
	186	rstn => rstn, wclk => clk, rclk => clk,
	187	ReUse => (OTHERS => '0'),
	188	wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
	189	wdata => sample_f3_wdata, rdata => FifoF3_Data,
	190	full => OPEN, empty => FifoF3_Empty);
	191	-----------------------------------------------------------------------------	136	-----------------------------------------------------------------------------
			137	TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
			138	SIGNAL state_fsm_load_FFT : fsm_load_FFT;
			139	SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
			140
			141	SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
			142	SIGNAL sample_load : STD_LOGIC;
			143	SIGNAL sample_valid : STD_LOGIC;
			144	SIGNAL sample_valid_r : STD_LOGIC;
			145	SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
	192		146
	193		147
	194	-----------------------------------------------------------------------------	148	-----------------------------------------------------------------------------
	195	DMUX0 : DEMUX	149	-- FFT
	196	GENERIC MAP (	150	-----------------------------------------------------------------------------
	197	Data_sz => 16)	151	SIGNAL fft_read : STD_LOGIC;
			152	SIGNAL fft_pong : STD_LOGIC;
			153	SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
			154	SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
			155	SIGNAL fft_data_valid : STD_LOGIC;
			156	SIGNAL fft_ready : STD_LOGIC;
			157	-----------------------------------------------------------------------------
			158	SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
			159	-----------------------------------------------------------------------------
			160	TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
			161	SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
			162	SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
			163	SIGNAL current_fifo_empty : STD_LOGIC;
			164	SIGNAL current_fifo_locked : STD_LOGIC;
			165	SIGNAL current_fifo_full : STD_LOGIC;
			166	SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
			167
			168	-----------------------------------------------------------------------------
			169	SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
			170	SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
			171	SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
			172	SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
			173	SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(1625-1 DOWNTO 0);
			174	SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(1625-1 DOWNTO 0);
			175	SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
			176	SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
			177	-----------------------------------------------------------------------------
			178	SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
			179	SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
			180	SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
			181
			182	SIGNAL SM_correlation_start : STD_LOGIC;
			183	SIGNAL SM_correlation_auto : STD_LOGIC;
			184	SIGNAL SM_correlation_done : STD_LOGIC;
			185	SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
			186	SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
			187	SIGNAL SM_correlation_begin : STD_LOGIC;
			188
			189	SIGNAL temp_ongoing : STD_LOGIC;
			190	SIGNAL temp_auto : STD_LOGIC;
			191
			192	SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
			193	SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
			194	SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
			195
			196	SIGNAL current_matrix_write : STD_LOGIC;
			197	SIGNAL current_matrix_wait_empty : STD_LOGIC;
			198
			199	--SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0);
			200
			201	-----------------------------------------------------------------------------
			202	SIGNAL fifo_0_ready : STD_LOGIC;
			203	SIGNAL fifo_1_ready : STD_LOGIC;
			204	SIGNAL fifo_ongoing : STD_LOGIC;
			205
			206	SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
			207	SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
			208	SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
			209	SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
			210
			211	-----------------------------------------------------------------------------
			212	SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
			213	SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
			214	SIGNAL HEAD_SM_Wen : STD_LOGIC;
			215	SIGNAL HEAD_Valid : STD_LOGIC;
			216	SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
			217	SIGNAL HEAD_Empty : STD_LOGIC;
			218	SIGNAL HEAD_Read : STD_LOGIC;
			219	-----------------------------------------------------------------------------
			220	SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
			221	SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
			222	SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
			223	SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
			224	SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
			225	SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
			226	SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
			227	-----------------------------------------------------------------------------
			228	SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
			229	SIGNAL DMA_Header_Val : STD_LOGIC;
			230	SIGNAL DMA_Header_Ack : STD_LOGIC;
			231
			232	-----------------------------------------------------------------------------
			233	-- TIME REG & INFOs
			234	-----------------------------------------------------------------------------
			235	SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
			236
			237	SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
			238	SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
			239	SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			240	SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
			241
			242	SIGNAL time_update_f0_A : STD_LOGIC;
			243	SIGNAL time_update_f0_B : STD_LOGIC;
			244	SIGNAL time_update_f1 : STD_LOGIC;
			245	SIGNAL time_update_f2 : STD_LOGIC;
			246	--
			247	SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
			248	SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
			249	SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
			250
			251	SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
			252	SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
			253	SIGNAL status_component_fifo_0_new : STD_LOGIC;
			254	SIGNAL status_component_fifo_1_new : STD_LOGIC;
			255	SIGNAL status_component_fifo_0_end : STD_LOGIC;
			256	SIGNAL status_component_fifo_1_end : STD_LOGIC;
			257
			258	SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
			259	-----------------------------------------------------------------------------
			260
			261	BEGIN
			262
			263
			264	error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
			265
			266
			267	switch_f0_inst : spectral_matrix_switch_f0
	198	PORT MAP (	268	PORT MAP (
	199	clk => clk,	269	clk => clk,
	200	rstn => rstn,	270	rstn => rstn,
	201	Read => FFT_Read,	271
	202	Load => FFT_Load,	272	sample_wen => sample_f0_wen,
	203	EmptyF0 => FifoF0_Empty,	273
	204	EmptyF1 => FifoF1_Empty,	274	fifo_A_empty => sample_f0_A_empty,
	205	EmptyF2 => FifoF3_Empty,	275	fifo_A_full => sample_f0_A_full,
	206	DataF0 => FifoF0_Data,	276	fifo_A_wen => sample_f0_A_wen,
	207	DataF1 => FifoF1_Data,	277
	208	DataF2 => FifoF3_Data,	278	fifo_B_empty => sample_f0_B_empty,
	209	WorkFreq => DMUX_WorkFreq,	279	fifo_B_full => sample_f0_B_full,
	210	Read_DEMUX => DMUX_Read,	280	fifo_B_wen => sample_f0_B_wen,
	211	Empty => DMUX_Empty,	281
	212	Data => DMUX_Data);	282	error_wen => error_wen_f0); -- TODO
			283
			284	-----------------------------------------------------------------------------
			285	-- FIFO IN
	213	-----------------------------------------------------------------------------	286	-----------------------------------------------------------------------------
			287	lppFIFOxN_f0_a : lppFIFOxN
			288	GENERIC MAP (
			289	tech => 0,
			290	Mem_use => Mem_use,
			291	Data_sz => 16,
			292	Addr_sz => 8,
			293	FifoCnt => 5)
			294	PORT MAP (
			295	clk => clk,
			296	rstn => rstn,
			297
			298	ReUse => (OTHERS => '0'),
			299
			300	wen => sample_f0_A_wen,
			301	wdata => sample_f0_wdata,
			302
			303	ren => sample_f0_A_ren,
			304	rdata => sample_f0_A_rdata,
			305
			306	empty => sample_f0_A_empty,
			307	full => sample_f0_A_full,
			308	almost_full => OPEN);
			309
			310	lppFIFOxN_f0_b : lppFIFOxN
			311	GENERIC MAP (
			312	tech => 0,
			313	Mem_use => Mem_use,
			314	Data_sz => 16,
			315	Addr_sz => 8,
			316	FifoCnt => 5)
			317	PORT MAP (
			318	clk => clk,
			319	rstn => rstn,
			320
			321	ReUse => (OTHERS => '0'),
			322
			323	wen => sample_f0_B_wen,
			324	wdata => sample_f0_wdata,
			325	ren => sample_f0_B_ren,
			326	rdata => sample_f0_B_rdata,
			327	empty => sample_f0_B_empty,
			328	full => sample_f0_B_full,
			329	almost_full => OPEN);
			330
			331	lppFIFOxN_f1 : lppFIFOxN
			332	GENERIC MAP (
			333	tech => 0,
			334	Mem_use => Mem_use,
			335	Data_sz => 16,
			336	Addr_sz => 8,
			337	FifoCnt => 5)
			338	PORT MAP (
			339	clk => clk,
			340	rstn => rstn,
			341
			342	ReUse => (OTHERS => '0'),
			343
			344	wen => sample_f1_wen,
			345	wdata => sample_f1_wdata,
			346	ren => sample_f1_ren,
			347	rdata => sample_f1_rdata,
			348	empty => sample_f1_empty,
			349	full => sample_f1_full,
			350	almost_full => sample_f1_almost_full);
	214		351
	215		352
	216	-----------------------------------------------------------------------------	353	one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
	217	FFT0: FFT	354
	218	GENERIC MAP (	355	PROCESS (clk, rstn)
	219	Data_sz => 16,	356	BEGIN -- PROCESS
	220	NbData => 256)	357	IF rstn = '0' THEN -- asynchronous reset (active low)
	221	PORT MAP (	358	one_sample_f1_full <= '0';
	222	clkm => clk,	359	error_wen_f1 <= '0';
	223	rstn => rstn,	360	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	224	FifoIN_Empty => DMUX_Empty,	361	IF sample_f1_full = "00000" THEN
	225	FifoIN_Data => DMUX_Data,	362	one_sample_f1_full <= '0';
	226	FifoOUT_Full => FifoINT_Full,	363	ELSE
	227	Load => FFT_Load,	364	one_sample_f1_full <= '1';
	228	Read => FFT_Read,	365	END IF;
	229	Write => FFT_Write,	366	error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
	230	ReUse => FFT_ReUse,	367	END IF;
	231	Data => FFT_Data);	368	END PROCESS;
	232	-----------------------------------------------------------------------------
	233		369
	234		370
	235	-----------------------------------------------------------------------------	371	lppFIFOxN_f2 : lppFIFOxN
	236	MemInt : lppFIFOxN
	237	GENERIC MAP (	372	GENERIC MAP (
	238	tech => 0,	373	tech => 0,
	239	Mem_use => Mem_use,	374	Mem_use => Mem_use,
	240	Data_sz => 16,	375	Data_sz => 16,
	241	Addr_sz => 8,	376	Addr_sz => 8,
	242	FifoCnt => 5,	377	FifoCnt => 5)
	243	Enable_ReUse => '1')
	244	PORT MAP (	378	PORT MAP (
	245	~~rstn~~ => ~~rstn~~,	379	clk => clk,
	246	~~wclk~~ => ~~clk~~,	380	rstn => rstn,
	247	rclk => clk,	381
	248	ReUse => ~~SM_ReUse~~,	382	ReUse => (OTHERS => '0'),
	249	wen => FFT_Write,	383
	250	ren => SM_Read,	384	wen => sample_f2_wen,
	251	wdata => ~~FFT_D~~ata,	385	wdata => sample_f2_wdata,
	252	rdata => FifoINT_Data,	386	ren => sample_f2_ren,
	253	full => FifoINT_Full,	387	rdata => sample_f2_rdata,
	254	empty => OPEN);	388	empty => sample_f2_empty,
			389	full => sample_f2_full,
			390	almost_full => OPEN);
			391
			392
			393	one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
			394
			395	PROCESS (clk, rstn)
			396	BEGIN -- PROCESS
			397	IF rstn = '0' THEN -- asynchronous reset (active low)
			398	one_sample_f2_full <= '0';
			399	error_wen_f2 <= '0';
			400	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
			401	IF sample_f2_full = "00000" THEN
			402	one_sample_f2_full <= '0';
			403	ELSE
			404	one_sample_f2_full <= '1';
			405	END IF;
			406	error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
			407	END IF;
			408	END PROCESS;
			409
			410	-----------------------------------------------------------------------------
			411	-- FSM SELECT CHANNEL
			412	-----------------------------------------------------------------------------
			413	PROCESS (clk, rstn)
			414	BEGIN
			415	IF rstn = '0' THEN
			416	state_fsm_select_channel <= IDLE;
			417	ELSIF clk'EVENT AND clk = '1' THEN
			418	CASE state_fsm_select_channel IS
			419	WHEN IDLE =>
			420	IF sample_f1_full = "11111" THEN
			421	state_fsm_select_channel <= SWITCH_F1;
			422	ELSIF sample_f1_almost_full = "00000" THEN
			423	IF sample_f0_A_full = "11111" THEN
			424	state_fsm_select_channel <= SWITCH_F0_A;
			425	ELSIF sample_f0_B_full = "11111" THEN
			426	state_fsm_select_channel <= SWITCH_F0_B;
			427	ELSIF sample_f2_full = "11111" THEN
			428	state_fsm_select_channel <= SWITCH_F2;
			429	END IF;
			430	END IF;
			431
			432	WHEN SWITCH_F0_A =>
			433	IF sample_f0_A_empty = "11111" THEN
			434	state_fsm_select_channel <= IDLE;
			435	END IF;
			436	WHEN SWITCH_F0_B =>
			437	IF sample_f0_B_empty = "11111" THEN
			438	state_fsm_select_channel <= IDLE;
			439	END IF;
			440	WHEN SWITCH_F1 =>
			441	IF sample_f1_empty = "11111" THEN
			442	state_fsm_select_channel <= IDLE;
			443	END IF;
			444	WHEN SWITCH_F2 =>
			445	IF sample_f2_empty = "11111" THEN
			446	state_fsm_select_channel <= IDLE;
			447	END IF;
			448	WHEN OTHERS => NULL;
			449	END CASE;
			450
			451	END IF;
			452	END PROCESS;
			453
			454	PROCESS (clk, rstn)
			455	BEGIN
			456	IF rstn = '0' THEN
			457	pre_state_fsm_select_channel <= IDLE;
			458	ELSIF clk'EVENT AND clk = '1' THEN
			459	pre_state_fsm_select_channel <= state_fsm_select_channel;
			460	END IF;
			461	END PROCESS;
			462
			463
			464	-----------------------------------------------------------------------------
			465	-- SWITCH SELECT CHANNEL
			466	-----------------------------------------------------------------------------
			467	sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
			468	sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
			469	sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
			470	sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
			471	(OTHERS => '1');
			472
			473	sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
			474	sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
			475	sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
			476	sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
			477	(OTHERS => '0');
			478
			479	sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
			480	sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
			481	sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
			482	sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
			483
			484
			485	sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
			486	sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
			487	sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
			488	sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
			489
			490
			491	status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
			492	time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
			493	time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
			494	time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
			495
	255	-----------------------------------------------------------------------------	496	-----------------------------------------------------------------------------
			497	-- FSM LOAD FFT
			498	-----------------------------------------------------------------------------
			499
			500	sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
			501
			502	PROCESS (clk, rstn)
			503	BEGIN
			504	IF rstn = '0' THEN
			505	sample_ren_s <= (OTHERS => '1');
			506	state_fsm_load_FFT <= IDLE;
			507	status_MS_input <= (OTHERS => '0');
			508	--next_state_fsm_load_FFT <= IDLE;
			509	--sample_valid <= '0';
			510	ELSIF clk'EVENT AND clk = '1' THEN
			511	CASE state_fsm_load_FFT IS
			512	WHEN IDLE =>
			513	--sample_valid <= '0';
			514	sample_ren_s <= (OTHERS => '1');
			515	IF sample_full = "11111" AND sample_load = '1' THEN
			516	state_fsm_load_FFT <= FIFO_1;
			517	status_MS_input <= status_channel;
			518	END IF;
			519
			520	WHEN FIFO_1 =>
			521	sample_ren_s <= "1111" & NOT(sample_load);
			522	IF sample_empty(0) = '1' THEN
			523	sample_ren_s <= (OTHERS => '1');
			524	state_fsm_load_FFT <= FIFO_2;
			525	END IF;
			526
			527	WHEN FIFO_2 =>
			528	sample_ren_s <= "111" & NOT(sample_load) & '1';
			529	IF sample_empty(1) = '1' THEN
			530	sample_ren_s <= (OTHERS => '1');
			531	state_fsm_load_FFT <= FIFO_3;
			532	END IF;
			533
			534	WHEN FIFO_3 =>
			535	sample_ren_s <= "11" & NOT(sample_load) & "11";
			536	IF sample_empty(2) = '1' THEN
			537	sample_ren_s <= (OTHERS => '1');
			538	state_fsm_load_FFT <= FIFO_4;
			539	END IF;
			540
			541	WHEN FIFO_4 =>
			542	sample_ren_s <= '1' & NOT(sample_load) & "111";
			543	IF sample_empty(3) = '1' THEN
			544	sample_ren_s <= (OTHERS => '1');
			545	state_fsm_load_FFT <= FIFO_5;
			546	END IF;
			547
			548	WHEN FIFO_5 =>
			549	sample_ren_s <= NOT(sample_load) & "1111";
			550	IF sample_empty(4) = '1' THEN
			551	sample_ren_s <= (OTHERS => '1');
			552	state_fsm_load_FFT <= IDLE;
			553	END IF;
			554	WHEN OTHERS => NULL;
			555	END CASE;
			556	END IF;
			557	END PROCESS;
			558
			559	PROCESS (clk, rstn)
			560	BEGIN
			561	IF rstn = '0' THEN
			562	sample_valid_r <= '0';
			563	next_state_fsm_load_FFT <= IDLE;
			564	ELSIF clk'EVENT AND clk = '1' THEN
			565	next_state_fsm_load_FFT <= state_fsm_load_FFT;
			566	IF sample_ren_s = "11111" THEN
			567	sample_valid_r <= '0';
			568	ELSE
			569	sample_valid_r <= '1';
			570	END IF;
			571	END IF;
			572	END PROCESS;
			573
			574	sample_valid <= sample_valid_r AND sample_load;
			575
			576	sample_data <= sample_rdata(161-1 DOWNTO 160) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
			577	sample_rdata(162-1 DOWNTO 161) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
			578	sample_rdata(163-1 DOWNTO 162) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
			579	sample_rdata(164-1 DOWNTO 163) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
			580	sample_rdata(165-1 DOWNTO 164); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
			581
			582	-----------------------------------------------------------------------------
			583	-- FFT
			584	-----------------------------------------------------------------------------
			585	CoreFFT_1 : CoreFFT
			586	GENERIC MAP (
			587	LOGPTS => gLOGPTS,
			588	LOGLOGPTS => gLOGLOGPTS,
			589	WSIZE => gWSIZE,
			590	TWIDTH => gTWIDTH,
			591	DWIDTH => gDWIDTH,
			592	TDWIDTH => gTDWIDTH,
			593	RND_MODE => gRND_MODE,
			594	SCALE_MODE => gSCALE_MODE,
			595	PTS => gPTS,
			596	HALFPTS => gHALFPTS,
			597	inBuf_RWDLY => gInBuf_RWDLY)
			598	PORT MAP (
			599	clk => clk,
			600	ifiStart => '1',
			601	ifiNreset => rstn,
			602
			603	ifiD_valid => sample_valid, -- IN
			604	ifiRead_y => fft_read,
			605	ifiD_im => (OTHERS => '0'), -- IN
			606	ifiD_re => sample_data, -- IN
			607	ifoLoad => sample_load, -- IN
			608
			609	ifoPong => fft_pong,
			610	ifoY_im => fft_data_im,
			611	ifoY_re => fft_data_re,
			612	ifoY_valid => fft_data_valid,
			613	ifoY_rdy => fft_ready);
	256		614
	257	-----------------------------------------------------------------------------	615	-----------------------------------------------------------------------------
	258	SM0 : MatriceSpectrale	616	-- in fft_data_im & fft_data_re
			617	-- in fft_data_valid
			618	-- in fft_ready
			619	-- out fft_read
			620	PROCESS (clk, rstn)
			621	BEGIN
			622	IF rstn = '0' THEN
			623	state_fsm_load_MS_memory <= IDLE;
			624	current_fifo_load <= "00001";
			625	ELSIF clk'event AND clk = '1' THEN
			626	CASE state_fsm_load_MS_memory IS
			627	WHEN IDLE =>
			628	IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
			629	state_fsm_load_MS_memory <= LOAD_FIFO;
			630	END IF;
			631	WHEN LOAD_FIFO =>
			632	IF current_fifo_full = '1' THEN
			633	state_fsm_load_MS_memory <= TRASH_FFT;
			634	END IF;
			635	WHEN TRASH_FFT =>
			636	IF fft_ready = '0' THEN
			637	state_fsm_load_MS_memory <= IDLE;
			638	current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
			639	END IF;
			640	WHEN OTHERS => NULL;
			641	END CASE;
			642
			643	END IF;
			644	END PROCESS;
			645
			646	current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
			647	MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
			648	MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
			649	MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
			650	MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
			651
			652	current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
			653	MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
			654	MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
			655	MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
			656	MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
			657
			658	current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
			659	MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
			660	MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
			661	MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
			662	MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
			663
			664	fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
			665
			666	all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
			667	MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
			668	AND state_fsm_load_MS_memory = LOAD_FIFO
			669	AND current_fifo_load(I) = '1'
			670	ELSE '1';
			671	END GENERATE all_fifo;
			672
			673	PROCESS (clk, rstn)
			674	BEGIN
			675	IF rstn = '0' THEN
			676	MEM_IN_SM_wen <= (OTHERS => '1');
			677	ELSIF clk'event AND clk = '1' THEN
			678	MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
			679	END IF;
			680	END PROCESS;
			681
			682	MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
			683	(fft_data_im & fft_data_re) &
			684	(fft_data_im & fft_data_re) &
			685	(fft_data_im & fft_data_re) &
			686	(fft_data_im & fft_data_re);
			687
			688
			689	-- out SM_MEM_IN_wData
			690	-- out SM_MEM_IN_wen
			691	-- out SM_MEM_IN_Full
			692
			693	-- out SM_MEM_IN_locked
			694	-----------------------------------------------------------------------------
			695	-----------------------------------------------------------------------------
			696	-----------------------------------------------------------------------------
			697	-----------------------------------------------------------------------------
			698	--Linker_FFT_1 : Linker_FFT
			699	-- GENERIC MAP (
			700	-- Data_sz => 16,
			701	-- NbData => 256)
			702	-- PORT MAP (
			703	-- clk => clk,
			704	-- rstn => rstn,
			705
			706	-- Ready => fft_ready,
			707	-- Valid => fft_data_valid,
			708
			709	-- Full => MEM_IN_SM_Full,
			710
			711	-- Data_re => fft_data_re,
			712	-- Data_im => fft_data_im,
			713	-- Read => fft_read,
			714
			715	-- Write => MEM_IN_SM_wen,
			716	-- ReUse => fft_linker_ReUse,
			717	-- DATA => MEM_IN_SM_wData);
			718
			719	-----------------------------------------------------------------------------
			720	Mem_In_SpectralMatrix : lppFIFOxN
	259	GENERIC MAP (	721	GENERIC MAP (
	260	Input_SZ => 16,	722	tech => 0,
	261	Result_SZ => 32)	723	Mem_use => Mem_use,
			724	Data_sz => 32, --16,
			725	Addr_sz => 7, --8
			726	FifoCnt => 5)
	262	PORT MAP (	727	PORT MAP (
	263	clkm => clk,	728	clk => clk,
	264	rstn => rstn,	729	rstn => rstn,
	265	FifoIN_Full => FifoINT_Full, --	730
	266	~~Set~~ReUse => ~~FFT~~_ReUse, --	731	ReUse => MEM_IN_SM_ReUse,
	267	Valid => Head_Valid, -- HeaderBuilder	732
	268	Data_IN => FifoINT_Data, --	733	wen => MEM_IN_SM_wen,
	269	ACK => DMA_ack, -- HeaderBuilder	734	wdata => MEM_IN_SM_wData,
	270	SM_Write => SM_Wen, -- HeaderBuilder	735
	271	FlagError => SM_FlagError, -- UNUSED	736	ren => MEM_IN_SM_ren,
	272	-- Pong => SM_Pong,	737	rdata => MEM_IN_SM_rData,
	273	Statu => SM_Param, -- HeaderBuilder	738	full => MEM_IN_SM_Full,
	274	Write => SM_Write, -- FIFO MemOut	739	empty => MEM_IN_SM_Empty);
	275	Read => SM_Read, --	740
	276	ReUse => SM_ReUse, --	741
	277	Data_OUT => SM_Data); -- FIFO MemOut	742	--all_lock: FOR I IN 4 DOWNTO 0 GENERATE
			743	-- PROCESS (clk, rstn)
			744	-- BEGIN
			745	-- IF rstn = '0' THEN
			746	-- MEM_IN_SM_locked(I) <= '0';
			747	-- ELSIF clk'event AND clk = '1' THEN
			748	-- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
			749	-- END IF;
			750	-- END PROCESS;
			751	--END GENERATE all_lock;
			752
			753	-----------------------------------------------------------------------------
			754	MS_control_1: MS_control
			755	PORT MAP (
			756	clk => clk,
			757	rstn => rstn,
			758
			759	current_status_ms => status_MS_input,
			760
			761	fifo_in_lock => MEM_IN_SM_locked,
			762	fifo_in_data => MEM_IN_SM_rdata,
			763	fifo_in_full => MEM_IN_SM_Full,
			764	fifo_in_empty => MEM_IN_SM_Empty,
			765	fifo_in_ren => MEM_IN_SM_ren,
			766	fifo_in_reuse => MEM_IN_SM_ReUse,
			767
			768	fifo_out_data => SM_in_data,
			769	fifo_out_ren => SM_in_ren,
			770	fifo_out_empty => SM_in_empty,
			771
			772	current_status_component => status_component,
			773
			774	correlation_start => SM_correlation_start,
			775	correlation_auto => SM_correlation_auto,
			776	correlation_done => SM_correlation_done);
			777
			778
			779	MS_calculation_1: MS_calculation
			780	PORT MAP (
			781	clk => clk,
			782	rstn => rstn,
			783
			784	fifo_in_data => SM_in_data,
			785	fifo_in_ren => SM_in_ren,
			786	fifo_in_empty => SM_in_empty,
			787
			788	fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
			789	fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
			790	fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
			791
			792	correlation_start => SM_correlation_start,
			793	correlation_auto => SM_correlation_auto,
			794	correlation_begin => SM_correlation_begin,
			795	correlation_done => SM_correlation_done);
			796
	278	-----------------------------------------------------------------------------	797	-----------------------------------------------------------------------------
			798	PROCESS (clk, rstn)
			799	BEGIN -- PROCESS
			800	IF rstn = '0' THEN -- asynchronous reset (active low)
			801	current_matrix_write <= '0';
			802	current_matrix_wait_empty <= '1';
			803	status_component_fifo_0 <= (OTHERS => '0');
			804	status_component_fifo_1 <= (OTHERS => '0');
			805	status_component_fifo_0_new <= '0';
			806	status_component_fifo_1_new <= '0';
			807	status_component_fifo_0_end <= '0';
			808	status_component_fifo_1_end <= '0';
			809	SM_correlation_done_reg1 <= '0';
			810	SM_correlation_done_reg2 <= '0';
			811
			812	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
			813	SM_correlation_done_reg1 <= SM_correlation_done;
			814	SM_correlation_done_reg2 <= SM_correlation_done_reg1;
			815
			816	status_component_fifo_0_new <= '0';
			817	status_component_fifo_1_new <= '0';
			818	status_component_fifo_0_end <= '0';
			819	status_component_fifo_1_end <= '0';
	279		820
			821
			822
			823	IF SM_correlation_begin = '1' THEN
			824	IF current_matrix_write = '0' THEN
			825	status_component_fifo_0_new <= '1';
			826	status_component_fifo_0 <= status_component;
			827	ELSE
			828	status_component_fifo_1_new <= '1';
			829	status_component_fifo_1 <= status_component;
			830	END IF;
			831	END IF;
			832
			833	IF SM_correlation_done_reg2 = '1' THEN
			834	IF current_matrix_write = '0' THEN
			835	status_component_fifo_0_end <= '1';
			836	ELSE
			837	status_component_fifo_1_end <= '1';
			838	END IF;
			839	current_matrix_wait_empty <= '1';
			840	current_matrix_write <= NOT current_matrix_write;
			841	END IF;
			842
			843	IF current_matrix_wait_empty <= '1' THEN
			844	IF current_matrix_write = '0' THEN
			845	current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
			846	ELSE
			847	current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
			848	END IF;
			849	END IF;
			850
			851	END IF;
			852	END PROCESS;
			853
			854	MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
			855	'1' WHEN SM_correlation_done_reg1 = '1' ELSE
			856	'1' WHEN SM_correlation_done_reg2 = '1' ELSE
			857	'1' WHEN current_matrix_wait_empty = '1' ELSE
			858	MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
			859	MEM_OUT_SM_Full(1);
			860
			861	MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
			862	MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
			863
			864	MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
	280	-----------------------------------------------------------------------------	865	-----------------------------------------------------------------------------
	281	MemOut : lppFIFOxN	866
			867	Mem_Out_SpectralMatrix : lppFIFOxN
	282	GENERIC MAP (	868	GENERIC MAP (
	283	tech => 0,	869	tech => 0,
	284	Mem_use => Mem_use,	870	Mem_use => Mem_use,
	285	Data_sz => 32,	871	Data_sz => 32,
	286	Addr_sz => 8,	872	Addr_sz => 8,
	287	FifoCnt => 2,	873	FifoCnt => 2)
	288	Enable_ReUse => '0')
	289	PORT MAP (	874	PORT MAP (
	290	rstn => rstn,	875	clk => clk,
	291	wclk => clk,	876	rstn => rstn,
	292	rclk => clk,	877
	293	ReUse => (OTHERS => '0'),	878	ReUse => (OTHERS => '0'),
	294	wen => SM_Write,	879
	295	ren => Head_Read,	880	wen => MEM_OUT_SM_Write,
	296	wdata => SM_Data,	881	wdata => MEM_OUT_SM_Data_in,
	297	rdata => FifoOUT_Data,	882
	298	full => FifoOUT_Full,	883	ren => MEM_OUT_SM_Read,
	299	empty => FifoOUT_Empty);	884	rdata => MEM_OUT_SM_Data_out,
			885
			886	full => MEM_OUT_SM_Full,
			887	empty => MEM_OUT_SM_Empty,
			888	almost_full => OPEN);
			889
	300	-----------------------------------------------------------------------------	890	-----------------------------------------------------------------------------
			891	-- MEM_OUT_SM_Read <= "00";
			892	PROCESS (clk, rstn)
			893	BEGIN
			894	IF rstn = '0' THEN
			895	fifo_0_ready <= '0';
			896	fifo_1_ready <= '0';
			897	fifo_ongoing <= '0';
			898	ELSIF clk'event AND clk = '1' THEN
			899	IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
			900	fifo_ongoing <= '1';
			901	fifo_0_ready <= '0';
			902	ELSIF status_component_fifo_0_end = '1' THEN
			903	fifo_0_ready <= '1';
			904	END IF;
			905
			906	IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
			907	fifo_ongoing <= '0';
			908	fifo_1_ready <= '0';
			909	ELSIF status_component_fifo_1_end = '1' THEN
			910	fifo_1_ready <= '1';
			911	END IF;
			912
			913	END IF;
			914	END PROCESS;
			915
			916	MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
			917	'1' WHEN fifo_0_ready = '0' ELSE
			918	FSM_DMA_fifo_ren;
			919
			920	MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
			921	'1' WHEN fifo_1_ready = '0' ELSE
			922	FSM_DMA_fifo_ren;
			923
			924	FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
			925	MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
			926	'1';
			927
			928	FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
			929	status_component_fifo_1;
			930
			931	FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
			932	MEM_OUT_SM_Data_out(63 DOWNTO 32);
	301		933
	302	-----------------------------------------------------------------------------	934	-----------------------------------------------------------------------------
	303	Head0 : HeaderBuilder	935	lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
	304	GENERIC MAP (
	305	Data_sz => 32)
	306	PORT MAP (	936	PORT MAP (
	307	~~clkm~~ => clk,	937	HCLK => clk,
	308	~~rstn~~ => rstn,	938	HRESETn => rstn,
	309	-- pong => SM_Pong,	939
	310	Statu => SM_Param,	940	fifo_matrix_type => FSM_DMA_fifo_status( 5 DOWNTO 4),
	311	Matrix_Type => DMUX_WorkFreq,	941	fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0),
	312	Matrix_Write => SM_Wen,	942	fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
	313	Valid => Head_Valid,	943	fifo_data => FSM_DMA_fifo_data,
	314		944	fifo_empty => FSM_DMA_fifo_empty,
	315	dataIN => FifoOUT_Data,	945	fifo_ren => FSM_DMA_fifo_ren,
	316	emptyIN => FifoOUT_Empty,
	317	RenOUT => Head_Read,
	318
	319	dataOUT => Head_Data,
	320	emptyOUT => Head_Empty,
	321	RenIN => DMA_Read,
	322		946
	323	header => Head_Header,	947	---- FIFO IN
	324	header_val => Head_Val,	948	--data_time => dma_time,
	325	header_ack => DMA_ack );	949
	326	-----------------------------------------------------------------------------	950	--fifo_data => HEAD_Data,
	327	data_time(31 DOWNTO 0) <= coarse_time;	951	--fifo_empty => HEAD_Empty,
	328	data_time(47 DOWNTO 32) <= fine_time;	952	--fifo_ren => HEAD_Read,
	329		953
	330	lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma	954	--header => DMA_Header,
	331	PORT MAP (	955	--header_val => DMA_Header_Val,
	332	HCLK => clk,	956	--header_ack => DMA_Header_Ack,
	333	HRESETn => rstn,	957
	334		958	dma_addr => dma_addr,
	335	data_time => data_time,	959	dma_data => dma_data,
	336		960	dma_valid => dma_valid,
	337	fifo_data => Head_Data,	961	dma_valid_burst => dma_valid_burst,
	338	fifo_empty => Head_Empty,	962	dma_ren => dma_ren,
	339	fifo_ren => DMA_Read,	963	dma_done => dma_done,
	340		964
	341	~~header~~ => ~~Head_Header~~,	965	ready_matrix_f0 => ready_matrix_f0,
	342	~~header_val~~ => ~~Head_Val~~,	966	-- ready_matrix_f0_1 => ready_matrix_f0_1,
	343	header_ack => DMA_ack,
	344
	345	dma_addr => dma_addr,
	346	dma_data => dma_data,
	347	dma_valid => dma_valid_s,
	348	dma_valid_burst => dma_valid_burst_s,
	349	dma_ren => dma_ren,
	350	dma_done => dma_done,
	351
	352	ready_matrix_f0_0 => ready_matrix_f0_0,
	353	ready_matrix_f0_1 => ready_matrix_f0_1,
	354	ready_matrix_f1 => ready_matrix_f1,	967	ready_matrix_f1 => ready_matrix_f1,
	355	ready_matrix_f2 => ready_matrix_f2,	968	ready_matrix_f2 => ready_matrix_f2,
	356	error_anticipating_empty_fifo => error_anticipating_empty_fifo,	969	-- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
	357	error_bad_component_error => error_bad_component_error,	970	error_bad_component_error => error_bad_component_error,
	358	~~debug_reg~~ => ~~debug_reg_s~~,	971	error_buffer_full => error_buffer_full,
	359	status_ready_matrix_f0_0 => status_ready_matrix_f0_0,	972	debug_reg => debug_reg,
	360	status_ready_matrix_f0_1 => status_ready_matrix_f0_1,	973	status_ready_matrix_f0 => status_ready_matrix_f0,
			974	-- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
	361	status_ready_matrix_f1 => status_ready_matrix_f1,	975	status_ready_matrix_f1 => status_ready_matrix_f1,
	362	status_ready_matrix_f2 => status_ready_matrix_f2,	976	status_ready_matrix_f2 => status_ready_matrix_f2,
	363	status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,	977	-- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
	364	status_error_bad_component_error => status_error_bad_component_error,	978	-- status_error_bad_component_error => status_error_bad_component_error,
			979	-- status_error_buffer_full => status_error_buffer_full,
	365	config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,	980	config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
	366	config_active_interruption_onError => config_active_interruption_onError,	981	config_active_interruption_onError => config_active_interruption_onError,
	367	addr_matrix_f0_0 => addr_matrix_f0_0,	982	addr_matrix_f0 => addr_matrix_f0,
	368	addr_matrix_f0_1 => addr_matrix_f0_1,	983	-- addr_matrix_f0_1 => addr_matrix_f0_1,
	369	addr_matrix_f1 => addr_matrix_f1,	984	addr_matrix_f1 => addr_matrix_f1,
	370	addr_matrix_f2 => addr_matrix_f2,	985	addr_matrix_f2 => addr_matrix_f2,
	371		986
	372	matrix_time_f0_0 => matrix_time_f0_0,	987	matrix_time_f0 => matrix_time_f0,
	373	matrix_time_f0_1 => matrix_time_f0_1,	988	-- matrix_time_f0_1 => matrix_time_f0_1,
	374	matrix_time_f1 => matrix_time_f1,	989	matrix_time_f1 => matrix_time_f1,
	375	matrix_time_f2 => matrix_time_f2	990	matrix_time_f2 => matrix_time_f2
	376	);	991	);
			992	-----------------------------------------------------------------------------
	377		993
	378	dma_valid <= dma_valid_s;	994
	379	dma_valid_burst <= dma_valid_burst_s;	995
			996
			997
			998
			999
			1000
			1001
			1002
			1003
			1004	-----------------------------------------------------------------------------
			1005	-----------------------------------------------------------------------------
			1006	-----------------------------------------------------------------------------
			1007	-----------------------------------------------------------------------------
			1008	-----------------------------------------------------------------------------
			1009	-----------------------------------------------------------------------------
			1010
			1011
			1012
			1013
			1014
			1015
			1016	-----------------------------------------------------------------------------
			1017	-- TIME MANAGMENT
			1018	-----------------------------------------------------------------------------
			1019	all_time <= coarse_time & fine_time;
			1020	--
			1021	time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
			1022	'1' WHEN sample_f0_A_empty = "11111" ELSE
			1023	'0';
	380		1024
	381	debug_reg(9 DOWNTO 0) <= debug_reg_s(9 DOWNTO 0);	1025	s_m_t_m_f0_A : spectral_matrix_time_managment
	382	debug_reg(10) <= Head_Empty;	1026	PORT MAP (
	383	debug_reg(11) <= DMA_Read;	1027	clk => clk,
	384	debug_reg(12) <= Head_Val;	1028	rstn => rstn,
	385	debug_reg(13) <= DMA_ack;	1029	time_in => all_time,
	386	debug_reg(14) <= dma_ren;	1030	update_1 => time_update_f0_A,
	387	debug_reg(15) <= dma_done;	1031	time_out => time_reg_f0_A);
	388	debug_reg(16) <= dma_valid_s;	1032
	389	debug_reg(17) <= dma_valid_burst_s;	1033	--
	390	debug_reg(31 DOWNTO 18) <= (OTHERS => '0');	1034	time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
			1035	'1' WHEN sample_f0_B_empty = "11111" ELSE
			1036	'0';
			1037
			1038	s_m_t_m_f0_B : spectral_matrix_time_managment
			1039	PORT MAP (
			1040	clk => clk,
			1041	rstn => rstn,
			1042	time_in => all_time,
			1043	update_1 => time_update_f0_B,
			1044	time_out => time_reg_f0_B);
			1045
			1046	--
			1047	time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
			1048	'1' WHEN sample_f1_empty = "11111" ELSE
			1049	'0';
	391		1050
	392		1051	s_m_t_m_f1 : spectral_matrix_time_managment
			1052	PORT MAP (
			1053	clk => clk,
			1054	rstn => rstn,
			1055	time_in => all_time,
			1056	update_1 => time_update_f1,
			1057	time_out => time_reg_f1);
			1058
			1059	--
			1060	time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
			1061	'1' WHEN sample_f2_empty = "11111" ELSE
			1062	'0';
	393		1063
			1064	s_m_t_m_f2 : spectral_matrix_time_managment
			1065	PORT MAP (
			1066	clk => clk,
			1067	rstn => rstn,
			1068	time_in => all_time,
			1069	update_1 => time_update_f2,
			1070	time_out => time_reg_f2);
			1071
			1072	-----------------------------------------------------------------------------
			1073	dma_time <= (OTHERS => '0'); -- TODO
			1074	-----------------------------------------------------------------------------
			1075
			1076
			1077
	394	END Behavioral;	1078	END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +76 -214

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
-            -- 1.0 - initial version
-            -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY lpp;
             USE lpp.lpp_amba.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_lfr_ms_fsmdma IS
               PORT (
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
-                --TIME
+                ---------------------------------------------------------------------------
-                data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+                -- FIFO - IN
+                fifo_matrix_type      : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-                -- fifo interface
+                fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+                fifo_matrix_time      : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 fifo_data  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fifo_empty : IN  STD_LOGIC;
                 fifo_ren   : OUT STD_LOGIC;
-                -- header
+                ---------------------------------------------------------------------------
-                header     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+                -- DMA - OUT
-                header_val : IN  STD_LOGIC;
-                header_ack : OUT STD_LOGIC;
-                -- DMA
                 dma_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 dma_valid       : OUT STD_LOGIC;
                 dma_valid_burst : OUT STD_LOGIC;
                 dma_ren         : IN  STD_LOGIC;
                 dma_done        : IN  STD_LOGIC;
+                ---------------------------------------------------------------------------
                 -- Reg out
-                ready_matrix_f0_0             : OUT STD_LOGIC;
+                ready_matrix_f0             : OUT STD_LOGIC;
-                ready_matrix_f0_1             : OUT STD_LOGIC;
+            --    ready_matrix_f0_1             : OUT STD_LOGIC;
                 ready_matrix_f1               : OUT STD_LOGIC;
                 ready_matrix_f2               : OUT STD_LOGIC;
-                error_anticipating_empty_fifo : OUT STD_LOGIC;
+                --error_anticipating_empty_fifo : OUT STD_LOGIC;
                 error_bad_component_error     : OUT STD_LOGIC;
+                error_buffer_full             : OUT STD_LOGIC;
                 debug_reg                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 -- Reg In
-                status_ready_matrix_f0_0             : IN STD_LOGIC;
+                status_ready_matrix_f0             : IN STD_LOGIC;
-                status_ready_matrix_f0_1             : IN STD_LOGIC;
+            --    status_ready_matrix_f0_1             : IN STD_LOGIC;
                 status_ready_matrix_f1               : IN STD_LOGIC;
                 status_ready_matrix_f2               : IN STD_LOGIC;
-                status_error_anticipating_empty_fifo : IN STD_LOGIC;
+            --    status_error_anticipating_empty_fifo : IN STD_LOGIC;
-                status_error_bad_component_error     : IN STD_LOGIC;
+            --    status_error_bad_component_error     : IN STD_LOGIC;
+            --    status_error_buffer_full             : IN STD_LOGIC;
                 config_active_interruption_onNewMatrix : IN STD_LOGIC;
                 config_active_interruption_onError     : IN STD_LOGIC;
-                addr_matrix_f0_0                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+                addr_matrix_f0                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-                addr_matrix_f0_1                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --s    addr_matrix_f0_1                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-                matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
-                matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --    matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f1   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f2   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
               -----------------------------------------------------------------------------
-            --  SIGNAL DMAIn          : DMA_In_Type;
-            --  SIGNAL header_dmai    : DMA_In_Type;
-            --  SIGNAL component_dmai : DMA_In_Type;
-            --  SIGNAL DMAOut         : DMA_OUt_Type;
-              -----------------------------------------------------------------------------
-              -----------------------------------------------------------------------------
-              -----------------------------------------------------------------------------
               TYPE state_DMAWriteBurst IS (IDLE,
                                            CHECK_COMPONENT_TYPE,
                                            WRITE_COARSE_TIME,
                                            WRITE_FINE_TIME,
                                            TRASH_FIFO,
                                            SEND_DATA,
                                            WAIT_DATA_ACK
                                            );
-              SIGNAL state : state_DMAWriteBurst;   -- := IDLE;
+              SIGNAL state : state_DMAWriteBurst;
-              -- SIGNAL nbSend                 : INTEGER;
               SIGNAL matrix_type        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL component_type     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL header_check_ok    : STD_LOGIC;
               SIGNAL address_matrix     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL send_matrix        : STD_LOGIC;
-              -- SIGNAL request                : STD_LOGIC;
-            --  SIGNAL remaining_data_request : INTEGER;
               SIGNAL Address            : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
-              SIGNAL header_select      : STD_LOGIC;
-              SIGNAL header_send    : STD_LOGIC;
-              SIGNAL header_data    : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL header_send_ok : STD_LOGIC;
-              SIGNAL header_send_ko : STD_LOGIC;
               SIGNAL component_send     : STD_LOGIC;
               SIGNAL component_send_ok  : STD_LOGIC;
-              SIGNAL component_send_ko  : STD_LOGIC;
+            --  SIGNAL component_send_ko  : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fifo_ren_trash     : STD_LOGIC;
               SIGNAL component_fifo_ren : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL debug_reg_s   : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL log_empty_fifo : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL header_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL header_reg_val : STD_LOGIC;
               SIGNAL header_reg_ack : STD_LOGIC;
               SIGNAL header_error   : STD_LOGIC;
+              SIGNAL matrix_buffer_ready : STD_LOGIC;
             BEGIN
               debug_reg <= debug_reg_s;
-              send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
+              matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
-                             '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
+                                     --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
-                             '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0'   ELSE
+                                     '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0'   ELSE
-                             '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0'   ELSE
+                                     '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0'   ELSE
-                             '0';
+                                     '0';
               header_check_ok <= '0' WHEN component_type = "1111" ELSE  -- ?? component_type_pre = "1111"
                                  '1' WHEN component_type = "0000" ELSE  --AND component_type_pre = "0000" ELSE
-                                 '1' WHEN component_type = component_type_pre + "0001"            ELSE
+                                 '1' WHEN component_type = component_type_pre + "0001" ELSE
                                  '0';
-              address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
+              address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
-                                addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
+                                --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
-                                addr_matrix_f1   WHEN matrix_type = "10" ELSE
+                                addr_matrix_f1   WHEN matrix_type = "01" ELSE
-                                addr_matrix_f2   WHEN matrix_type = "11" ELSE
+                                addr_matrix_f2   WHEN matrix_type = "10" ELSE
                                 (OTHERS => '0');
               -----------------------------------------------------------------------------
               -- DMA control
               -----------------------------------------------------------------------------
               DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
-              BEGIN  -- PROCESS DMAWriteBurst_p
+              BEGIN
-                IF HRESETn = '0' THEN               -- asynchronous reset (active low)
+                IF HRESETn = '0' THEN
                   matrix_type                   <= (OTHERS => '0');
                   component_type                <= (OTHERS => '0');
                   state                         <= IDLE;
-            --      header_ack                    <= '0';
+                  ready_matrix_f0             <= '0';
-                  ready_matrix_f0_0             <= '0';
+            --      ready_matrix_f0_1             <= '0';
-                  ready_matrix_f0_1             <= '0';
                   ready_matrix_f1               <= '0';
                   ready_matrix_f2               <= '0';
-                  error_anticipating_empty_fifo <= '0';
+            --      error_anticipating_empty_fifo <= '0';
                   error_bad_component_error     <= '0';
+                  error_buffer_full             <= '0';  -- TODO
                   component_type_pre            <= "0000";
                   fifo_ren_trash                <= '1';
                   component_send                <= '0';
                   address                       <= (OTHERS => '0');
-                  header_select                 <= '0';
-                  header_send                   <= '0';
-                  header_data                   <= (OTHERS => '0');
-                  fine_time_reg                 <= (OTHERS => '0');
                   debug_reg_s(2 DOWNTO 0)  <= (OTHERS => '0');
                   debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0');
                   log_empty_fifo <= '0';
-                ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
+                ELSIF HCLK'EVENT AND HCLK = '1' THEN
                   debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
-                  header_reg_ack            <= '0';
+                  ready_matrix_f0         <= '0';
+            --      ready_matrix_f0_1         <= '0';
+                  ready_matrix_f1           <= '0';
+                  ready_matrix_f2           <= '0';
+                  error_bad_component_error <= '0';
+                  error_buffer_full         <= '0';
                   CASE state IS
                     WHEN IDLE =>
                       debug_reg_s(2 DOWNTO 0) <= "000";
+                      IF fifo_empty = '0' THEN
-                      --matrix_type <= header(1 DOWNTO 0);
+                        state              <= CHECK_COMPONENT_TYPE;
-                      --component_type <= header(5 DOWNTO 2);
+                        matrix_type        <= fifo_matrix_type;
+                        component_type     <= fifo_matrix_component;
-                      ready_matrix_f0_0         <= '0';
-                      ready_matrix_f0_1         <= '0';
-                      ready_matrix_f1           <= '0';
-                      ready_matrix_f2           <= '0';
-                      error_bad_component_error <= '0';
-                      --header_select             <= '1';
-                      IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
-                        header_reg_ack          <= '1';
-                        debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0);
-                        debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2);
-                        matrix_type        <= header_reg(1 DOWNTO 0);
-                        component_type     <= header_reg(5 DOWNTO 2);
                         component_type_pre <= component_type;
-                        state              <= CHECK_COMPONENT_TYPE;
                       END IF;
                       log_empty_fifo <= '0';
                     WHEN CHECK_COMPONENT_TYPE =>
                       debug_reg_s(2 DOWNTO 0) <= "001";
-                      --header_ack              <= '0';
-                      IF header_check_ok = '1' THEN
+                      IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
-                        header_send <= '0';
-                        --
                         IF component_type = "0000" THEN
                           address <= address_matrix;
                           CASE matrix_type IS
-                            WHEN "00"   => matrix_time_f0_0 <= data_time;
+                            WHEN "00"   => matrix_time_f0 <= fifo_matrix_time;
-                            WHEN "01"   => matrix_time_f0_1 <= data_time;
+                            WHEN "01"   => matrix_time_f1   <= fifo_matrix_time;
-                            WHEN "10"   => matrix_time_f1   <= data_time;
+                            WHEN "10"   => matrix_time_f2   <= fifo_matrix_time;
-                            WHEN "11"   => matrix_time_f2   <= data_time;
                             WHEN OTHERS => NULL;
                           END CASE;
-                          header_data    <= data_time(31 DOWNTO 0);
-                          fine_time_reg  <= data_time(47 DOWNTO 32);
-                          --state         <= WRITE_COARSE_TIME;
-                          --header_send   <= '1';
-                          state          <= SEND_DATA;
-                          header_send    <= '0';
                           component_send <= '1';
-                          header_select  <= '0';
-                        ELSE
-                          state <= SEND_DATA;
                         END IF;
+                        state <= SEND_DATA;
                         --
                       ELSE
-                        error_bad_component_error <= '1';
+                        error_bad_component_error <= NOT header_check_ok;
+                        error_buffer_full         <= NOT matrix_buffer_ready;  -- TODO
                         component_type_pre        <= "0000";
                         state                     <= TRASH_FIFO;
                       END IF;
-                      --WHEN WRITE_COARSE_TIME =>
-                      --  debug_reg_s(2 DOWNTO 0) <= "010";
-                      --  header_ack <= '0';
-                      --  IF dma_ren = '0' THEN
-                      --    header_send <= '0';
-                      --  ELSE
-                      --    header_send <= header_send;
-                      --  END IF;
-                      --  IF header_send_ko = '1' THEN
-                      --    header_send                   <= '0';
-                      --    state                         <= TRASH_FIFO;
-                      --    error_anticipating_empty_fifo <= '1';
-                      --    -- TODO : error sending header
-                      --  ELSIF header_send_ok = '1' THEN
-                      --    header_send               <= '1';
-                      --    header_select             <= '1';
-                      --    header_data(15 DOWNTO 0)  <= fine_time_reg;
-                      --    header_data(31 DOWNTO 16) <= (OTHERS => '0');
-                      --    state                     <= WRITE_FINE_TIME;
-                      --    address                   <= address + 4;
-                      --  END IF;
-                      --WHEN WRITE_FINE_TIME =>
-                      --  debug_reg_s(2 DOWNTO 0) <= "011";
-                      --  header_ack <= '0';
-                      --  IF dma_ren = '0' THEN
-                      --    header_send <= '0';
-                      --  ELSE
-                      --    header_send <= header_send;
-                      --  END IF;
-                      --  IF header_send_ko = '1' THEN
-                      --    header_send                   <= '0';
-                      --    state                         <= TRASH_FIFO;
-                      --    error_anticipating_empty_fifo <= '1';
-                      --    -- TODO : error sending header
-                      --  ELSIF header_send_ok = '1' THEN
-                      --    header_send   <= '0';
-                      --    header_select <= '0';
-                      --    state         <= SEND_DATA;
-                      --    address       <= address + 4;
-                      --  END IF;
                     WHEN TRASH_FIFO =>
                       debug_reg_s(2 DOWNTO 0) <= "100";
-            --          header_ack                    <= '0';
                       error_bad_component_error     <= '0';
-                      error_anticipating_empty_fifo <= '0';
+            --          error_anticipating_empty_fifo <= '0';
                       IF fifo_empty = '1' THEN
                         state          <= IDLE;
                         fifo_ren_trash <= '1';
                       ELSE
                         fifo_ren_trash <= '0';
                       END IF;
                     WHEN SEND_DATA =>
-            --          header_ack <= '0';
                       debug_reg_s(2 DOWNTO 0) <= "101";
                       IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
                         state <= IDLE;
-                        IF component_type = "1110" THEN  --"1110" -- JC
+                        IF component_type = "1110" THEN
                           CASE matrix_type IS
-                            WHEN "00"   => ready_matrix_f0_0 <= '1';
+                            WHEN "00"   => ready_matrix_f0   <= '1';
-                            WHEN "01"   => ready_matrix_f0_1 <= '1';
+                            WHEN "01"   => ready_matrix_f1   <= '1';
-                            WHEN "10"   => ready_matrix_f1   <= '1';
+                            WHEN "10"   => ready_matrix_f2   <= '1';
-                            WHEN "11"   => ready_matrix_f2   <= '1';
                             WHEN OTHERS => NULL;
                           END CASE;
                         END IF;
                       ELSE
                         component_send <= '1';
                         address        <= address;
                         state          <= WAIT_DATA_ACK;
                       END IF;
                     WHEN WAIT_DATA_ACK =>
                       log_empty_fifo <= fifo_empty OR log_empty_fifo;
                       debug_reg_s(2 DOWNTO 0) <= "110";
                       component_send <= '0';
                       IF component_send_ok = '1' THEN
                         address <= address + 64;
                         state   <= SEND_DATA;
-                      ELSIF component_send_ko = '1' THEN
+            --          ELSIF component_send_ko = '1' THEN
-                        error_anticipating_empty_fifo <= '0';
+            --            error_anticipating_empty_fifo <= '0';
-                        state                         <= TRASH_FIFO;
+            --            state                         <= TRASH_FIFO;
                       END IF;
-                      --WHEN CHECK_LENGTH =>
-                      --  component_send <= '0';
-                      --  debug_reg_s(2 DOWNTO 0) <= "111";
-                      --  state <= IDLE;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS DMAWriteFSM_p;
-              dma_valid_burst <= '0'            WHEN header_select = '1' ELSE component_send;
+              dma_valid_burst <= component_send;
-              dma_valid       <= header_send    WHEN header_select = '1' ELSE '0';
+              dma_valid       <= '0';
-              dma_data        <= header_data    WHEN header_select = '1' ELSE fifo_data;
+              dma_data        <= fifo_data;
               dma_addr        <= address;
-              fifo_ren        <= fifo_ren_trash WHEN header_select = '1' ELSE dma_ren;
+              fifo_ren        <= dma_ren AND fifo_ren_trash;
-              component_send_ok <= '0' WHEN header_select = '1' ELSE dma_done;
-              component_send_ko <= '0';
-              header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done;
-              header_send_ko <= '0';
-              -----------------------------------------------------------------------------
+              component_send_ok <= dma_done;
-              -- FSM HEADER ACK
+            --  component_send_ko <= '0';
-              -----------------------------------------------------------------------------
-              PROCESS (HCLK, HRESETn)
-              BEGIN  -- PROCESS
-                IF HRESETn = '0' THEN                 -- asynchronous reset (active low)
-                  header_ack     <= '0';
-                  header_reg     <= (OTHERS => '0');
-                  header_reg_val <= '0';
-                ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
-                  header_ack <= '0';
-                  IF header_val = '1' THEN
-                    header_ack <= '1';
-                    header_reg <= header;
-                  END IF;
-                  IF header_val = '1' THEN
-                    header_reg_val <= '1';
-                  ELSIF header_reg_ack = '1' THEN
-                    header_reg_val <= '0';
-                  END IF;
-                  header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack);
-                END IF;
-              END PROCESS;
-              debug_reg_s(3) <= header_error;
             END Behavioral;

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designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms_fsmdma.vhd removed 0 -293

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designs/Validation_LFR_SpectralMatrix/spectral_matrix_time_managment.vhd removed 0 -36

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