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designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd created 644 +261 0

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		1	------------------------------------------------------------------------------
		2	-- This file is a part of the LPP VHDL IP LIBRARY
		3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 3 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	--
		15	-- You should have received a copy of the GNU General Public License
		16	-- along with this program; if not, write to the Free Software
		17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		18	-------------------------------------------------------------------------------
		19	-- Author : Jean-christophe Pellion
		20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
		21	-------------------------------------------------------------------------------
		22	LIBRARY IEEE;
		23	USE IEEE.numeric_std.ALL;
		24	USE IEEE.std_logic_1164.ALL;
		25	LIBRARY grlib;
		26	USE grlib.amba.ALL;
		27	USE grlib.stdlib.ALL;
		28	LIBRARY techmap;
		29	USE techmap.gencomp.ALL;
		30	LIBRARY gaisler;
		31	USE gaisler.memctrl.ALL;
		32	USE gaisler.leon3.ALL;
		33	USE gaisler.uart.ALL;
		34	USE gaisler.misc.ALL;
		35	USE gaisler.spacewire.ALL; -- PLE
		36	LIBRARY esa;
		37	USE esa.memoryctrl.ALL;
		38	USE work.config.ALL;
		39	LIBRARY lpp;
		40	USE lpp.lpp_memory.ALL;
		41	USE lpp.lpp_ad_conv.ALL;
		42	USE lpp.lpp_lfr_pkg.ALL;
		43	USE lpp.iir_filter.ALL;
		44	USE lpp.general_purpose.ALL;
		45	USE lpp.lpp_lfr_time_management.ALL;
		46
		47	ENTITY MINI_LFR_top IS
		48
		49	PORT (
		50	clk_50 : IN STD_LOGIC;
		51	clk_49 : IN STD_LOGIC;
		52	reset : IN STD_LOGIC;
		53	--BPs
		54	BP0 : IN STD_LOGIC;
		55	BP1 : IN STD_LOGIC;
		56	--LEDs
		57	LED0 : OUT STD_LOGIC;
		58	LED1 : OUT STD_LOGIC;
		59	LED2 : OUT STD_LOGIC;
		60	--UARTs
		61	TXD1 : IN STD_LOGIC;
		62	RXD1 : OUT STD_LOGIC;
		63	nCTS1 : OUT STD_LOGIC;
		64	nRTS1 : IN STD_LOGIC;
		65
		66	TXD2 : IN STD_LOGIC;
		67	RXD2 : OUT STD_LOGIC;
		68	nCTS2 : OUT STD_LOGIC;
		69	nDTR2 : IN STD_LOGIC;
		70	nRTS2 : IN STD_LOGIC;
		71	nDCD2 : OUT STD_LOGIC;
		72
		73	--EXT CONNECTOR
		74	IO0 : INOUT STD_LOGIC;
		75	IO1 : INOUT STD_LOGIC;
		76	IO2 : INOUT STD_LOGIC;
		77	IO3 : INOUT STD_LOGIC;
		78	IO4 : INOUT STD_LOGIC;
		79	IO5 : INOUT STD_LOGIC;
		80	IO6 : INOUT STD_LOGIC;
		81	IO7 : INOUT STD_LOGIC;
		82	IO8 : INOUT STD_LOGIC;
		83	IO9 : INOUT STD_LOGIC;
		84	IO10 : INOUT STD_LOGIC;
		85	IO11 : INOUT STD_LOGIC;
		86
		87	--SPACE WIRE
		88	SPW_EN : OUT STD_LOGIC; -- 0 => off
		89	SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
		90	SPW_NOM_SIN : IN STD_LOGIC;
		91	SPW_NOM_DOUT : OUT STD_LOGIC;
		92	SPW_NOM_SOUT : OUT STD_LOGIC;
		93	SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
		94	SPW_RED_SIN : IN STD_LOGIC;
		95	SPW_RED_DOUT : OUT STD_LOGIC;
		96	SPW_RED_SOUT : OUT STD_LOGIC;
		97	-- MINI LFR ADC INPUTS
		98	ADC_nCS : OUT STD_LOGIC;
		99	ADC_CLK : OUT STD_LOGIC;
		100	ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		101
		102	-- SRAM
		103	SRAM_nWE : OUT STD_LOGIC;
		104	SRAM_CE : OUT STD_LOGIC;
		105	SRAM_nOE : OUT STD_LOGIC;
		106	SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		107	SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
		108	SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
		109	);
		110
		111	END MINI_LFR_top;
		112
		113
		114	ARCHITECTURE beh OF MINI_LFR_top IS
		115
		116	COMPONENT leon3_soc
		117	GENERIC (
		118	fabtech : INTEGER;
		119	memtech : INTEGER;
		120	padtech : INTEGER;
		121	clktech : INTEGER;
		122	disas : INTEGER;
		123	dbguart : INTEGER;
		124	pclow : INTEGER);
		125	PORT (
		126	clk100MHz : IN STD_ULOGIC;
		127	clk49_152MHz : IN STD_ULOGIC;
		128	reset : IN STD_ULOGIC;
		129	errorn : OUT STD_ULOGIC;
		130	ahbrxd : IN STD_ULOGIC;
		131	ahbtxd : OUT STD_ULOGIC;
		132	urxd1 : IN STD_ULOGIC;
		133	utxd1 : OUT STD_ULOGIC;
		134	address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
		135	data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		136	nSRAM_BE0 : OUT STD_LOGIC;
		137	nSRAM_BE1 : OUT STD_LOGIC;
		138	nSRAM_BE2 : OUT STD_LOGIC;
		139	nSRAM_BE3 : OUT STD_LOGIC;
		140	nSRAM_WE : OUT STD_LOGIC;
		141	nSRAM_CE : OUT STD_LOGIC;
		142	nSRAM_OE : OUT STD_LOGIC;
		143	spw1_din : IN STD_LOGIC;
		144	spw1_sin : IN STD_LOGIC;
		145	spw1_dout : OUT STD_LOGIC;
		146	spw1_sout : OUT STD_LOGIC;
		147	spw2_din : IN STD_LOGIC;
		148	spw2_sin : IN STD_LOGIC;
		149	spw2_dout : OUT STD_LOGIC;
		150	spw2_sout : OUT STD_LOGIC;
		151	apbi_wfp : OUT apb_slv_in_type;
		152	apbo_wfp : IN apb_slv_out_type;
		153	ahbi_wfp : OUT AHB_Mst_In_Type;
		154	ahbo_wfp : IN AHB_Mst_Out_Type;
		155	coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		156	fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
		157	END COMPONENT;
		158
		159	BEGIN -- beh
		160
		161	PROCESS (clk_50, reset)
		162	BEGIN -- PROCESS
		163	IF reset = '0' THEN -- asynchronous reset (active low)
		164	LED0 <= '0';
		165	LED1 <= '0';
		166	LED2 <= '0';
		167	ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
		168	LED0 <= '0';
		169	LED1 <= '1';
		170	LED2 <= BP0;
		171	END IF;
		172	END PROCESS;
		173
		174	--UARTs
		175	RXD1 <= '0';
		176	nCTS1 <= '0';
		177	RXD2 <= '0';
		178	nCTS2 <= '0';
		179	nDCD2 <= '0';
		180
		181	--EXT CONNECTOR
		182	IO0 <= clk_49;
		183	IO1 <= clk_50;
		184
		185	IO2 <= SPW_NOM_DIN OR
		186	SPW_NOM_SIN OR
		187	SPW_RED_DIN OR
		188	SPW_RED_SIN;
		189
		190	IO3 <= ADC_SDO(0);
		191	IO4 <= ADC_SDO(1);
		192	IO5 <= ADC_SDO(2);
		193	IO6 <= ADC_SDO(3);
		194	IO7 <= ADC_SDO(4);
		195	IO8 <= ADC_SDO(5);
		196	IO9 <= ADC_SDO(6);
		197	IO10 <= ADC_SDO(7);
		198	IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1;
		199
		200	--SPACE WIRE
		201	SPW_EN <= '0'; -- 0 => off
		202	SPW_NOM_DOUT <= '0';
		203	SPW_NOM_SOUT <= '0';
		204	SPW_RED_DOUT <= '0';
		205	SPW_RED_SOUT <= '0';
		206	ADC_nCS <= '0';
		207	ADC_CLK <= '0';
		208
		209	-- SRAM
		210	SRAM_nWE <= '1';
		211	SRAM_CE <= '0';
		212	SRAM_nOE <= '1';
		213	SRAM_nBE <= (OTHERS => '1');
		214	SRAM_A <= (OTHERS => '0');
		215	SRAM_DQ <= (OTHERS => '0');
		216
		217
		218	leon3mp_1: leon3_soc
		219	GENERIC MAP (
		220	fabtech => fabtech,
		221	memtech => memtech,
		222	padtech => padtech,
		223	clktech => clktech,
		224	disas => disas,
		225	dbguart => dbguart,
		226	pclow => pclow)
		227	PORT MAP (
		228	clk100MHz => clk100MHz,
		229	clk49_152MHz => clk49_152MHz,
		230	reset => reset,
		231	errorn => errorn,
		232	ahbrxd => ahbrxd,
		233	ahbtxd => ahbtxd,
		234	urxd1 => urxd1,
		235	utxd1 => utxd1,
		236	address => address,
		237	data => data,
		238	nSRAM_BE0 => nSRAM_BE0,
		239	nSRAM_BE1 => nSRAM_BE1,
		240	nSRAM_BE2 => nSRAM_BE2,
		241	nSRAM_BE3 => nSRAM_BE3,
		242	nSRAM_WE => nSRAM_WE,
		243	nSRAM_CE => nSRAM_CE,
		244	nSRAM_OE => nSRAM_OE,
		245	spw1_din => spw1_din,
		246	spw1_sin => spw1_sin,
		247	spw1_dout => spw1_dout,
		248	spw1_sout => spw1_sout,
		249	spw2_din => spw2_din,
		250	spw2_sin => spw2_sin,
		251	spw2_dout => spw2_dout,
		252	spw2_sout => spw2_sout,
		253	apbi_wfp => apbi_wfp,
		254	apbo_wfp => apbo_wfp,
		255	ahbi_wfp => ahbi_wfp,
		256	ahbo_wfp => ahbo_wfp,
		257	coarse_time => coarse_time,
		258	fine_time => fine_time);
		259
		260
		261	END beh;

designs/MINI-LFR_waveformPicker/Makefile created 644 +49 0

			@@ -0,0 +1,49
		1	VHDLIB=../..
		2	SCRIPTSDIR=$(VHDLIB)/scripts/
		3	GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
		4	TOP=MINI_LFR_top
		5	BOARD=MINI-LFR
		6	include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
		7	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		8	UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
		9	QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
		10	EFFORT=high
		11	XSTOPT=
		12	SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
		13	VHDLSYNFILES= MINI_LFR_top.vhd \
		14	config.vhd \
		15	leon3_soc.vhd
		16
		17	PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
		18	BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
		19	CLEAN=soft-clean
		20
		21	TECHLIBS = proasic3e
		22
		23	LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		24	tmtc openchip hynix ihp gleichmann micron usbhc
		25
		26	DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
		27	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
		28	./amba_lcd_16x2_ctrlr \
		29	./general_purpose/lpp_AMR \
		30	./general_purpose/lpp_balise \
		31	./general_purpose/lpp_delay \
		32	./dsp/lpp_fft \
		33	./lpp_bootloader \
		34	./lpp_cna \
		35	./lpp_demux \
		36	./lpp_matrix \
		37	./lpp_uart \
		38	./lpp_usb \
		39	./lpp_Header \
		40
		41	FILESKIP = i2cmst.vhd \
		42	APB_MULTI_DIODE.vhd \
		43	APB_SIMPLE_DIODE.vhd
		44
		45	include $(GRLIB)/bin/Makefile
		46	include $(GRLIB)/software/leon3/Makefile
		47
		48	################## project specific targets ##########################
		49

designs/MINI-LFR_waveformPicker/config.vhd created 644 +185 0

			@@ -0,0 +1,185
		1	-----------------------------------------------------------------------------
		2	-- LEON3 Demonstration design test bench configuration
		3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 2 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	------------------------------------------------------------------------------
		15
		16
		17	library techmap;
		18	use techmap.gencomp.all;
		19
		20	package config is
		21
		22
		23	-- Technology and synthesis options
		24	constant CFG_FABTECH : integer := apa3e;
		25	constant CFG_MEMTECH : integer := apa3e;
		26	constant CFG_PADTECH : integer := inferred;
		27	constant CFG_NOASYNC : integer := 0;
		28	constant CFG_SCAN : integer := 0;
		29
		30	-- Clock generator
		31	constant CFG_CLKTECH : integer := inferred;
		32	constant CFG_CLKMUL : integer := (1);
		33	constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
		34	constant CFG_OCLKDIV : integer := (1);
		35	constant CFG_PCIDLL : integer := 0;
		36	constant CFG_PCISYSCLK: integer := 0;
		37	constant CFG_CLK_NOFB : integer := 0;
		38
		39	-- LEON3 processor core
		40	constant CFG_LEON3 : integer := 1;
		41	constant CFG_NCPU : integer := (1);
		42	--constant CFG_NWIN : integer := (7); -- PLE
		43	constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
		44	constant CFG_V8 : integer := 0;
		45	constant CFG_MAC : integer := 0;
		46	constant CFG_SVT : integer := 0;
		47	constant CFG_RSTADDR : integer := 16#00000#;
		48	constant CFG_LDDEL : integer := (1);
		49	constant CFG_NWP : integer := (0);
		50	constant CFG_PWD : integer := 1*2;
		51	constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
		52	--constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
		53	constant CFG_GRFPUSH : integer := 0;
		54	constant CFG_ICEN : integer := 1;
		55	constant CFG_ISETS : integer := 1;
		56	constant CFG_ISETSZ : integer := 4;
		57	constant CFG_ILINE : integer := 4;
		58	constant CFG_IREPL : integer := 0;
		59	constant CFG_ILOCK : integer := 0;
		60	constant CFG_ILRAMEN : integer := 0;
		61	constant CFG_ILRAMADDR: integer := 16#8E#;
		62	constant CFG_ILRAMSZ : integer := 1;
		63	constant CFG_DCEN : integer := 1;
		64	constant CFG_DSETS : integer := 1;
		65	constant CFG_DSETSZ : integer := 4;
		66	constant CFG_DLINE : integer := 4;
		67	constant CFG_DREPL : integer := 0;
		68	constant CFG_DLOCK : integer := 0;
		69	constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
		70	constant CFG_DFIXED : integer := 16#00F3#;
		71	constant CFG_DLRAMEN : integer := 0;
		72	constant CFG_DLRAMADDR: integer := 16#8F#;
		73	constant CFG_DLRAMSZ : integer := 1;
		74	constant CFG_MMUEN : integer := 0;
		75	constant CFG_ITLBNUM : integer := 2;
		76	constant CFG_DTLBNUM : integer := 2;
		77	constant CFG_TLB_TYPE : integer := 1 + 0*2;
		78	constant CFG_TLB_REP : integer := 1;
		79	constant CFG_DSU : integer := 1;
		80	constant CFG_ITBSZ : integer := 0;
		81	constant CFG_ATBSZ : integer := 0;
		82	constant CFG_LEON3FT_EN : integer := 0;
		83	constant CFG_IUFT_EN : integer := 0;
		84	constant CFG_FPUFT_EN : integer := 0;
		85	constant CFG_RF_ERRINJ : integer := 0;
		86	constant CFG_CACHE_FT_EN : integer := 0;
		87	constant CFG_CACHE_ERRINJ : integer := 0;
		88	constant CFG_LEON3_NETLIST: integer := 0;
		89	constant CFG_DISAS : integer := 0 + 0;
		90	constant CFG_PCLOW : integer := 2;
		91
		92	-- AMBA settings
		93	constant CFG_DEFMST : integer := (0);
		94	constant CFG_RROBIN : integer := 1;
		95	constant CFG_SPLIT : integer := 0;
		96	constant CFG_AHBIO : integer := 16#FFF#;
		97	constant CFG_APBADDR : integer := 16#800#;
		98	constant CFG_AHB_MON : integer := 0;
		99	constant CFG_AHB_MONERR : integer := 0;
		100	constant CFG_AHB_MONWAR : integer := 0;
		101
		102	-- DSU UART
		103	constant CFG_AHB_UART : integer := 1;
		104
		105	-- JTAG based DSU interface
		106	constant CFG_AHB_JTAG : integer := 0;
		107
		108	-- Ethernet DSU
		109	constant CFG_DSU_ETH : integer := 0 + 0;
		110	constant CFG_ETH_BUF : integer := 1;
		111	constant CFG_ETH_IPM : integer := 16#C0A8#;
		112	constant CFG_ETH_IPL : integer := 16#0033#;
		113	constant CFG_ETH_ENM : integer := 16#00007A#;
		114	constant CFG_ETH_ENL : integer := 16#CC0001#;
		115
		116	-- LEON2 memory controller
		117	constant CFG_MCTRL_LEON2 : integer := 1;
		118	constant CFG_MCTRL_RAM8BIT : integer := 0;
		119	constant CFG_MCTRL_RAM16BIT : integer := 0;
		120	constant CFG_MCTRL_5CS : integer := 0;
		121	constant CFG_MCTRL_SDEN : integer := 0;
		122	constant CFG_MCTRL_SEPBUS : integer := 0;
		123	constant CFG_MCTRL_INVCLK : integer := 0;
		124	constant CFG_MCTRL_SD64 : integer := 0;
		125	constant CFG_MCTRL_PAGE : integer := 0 + 0;
		126
		127	-- SSRAM controller
		128	constant CFG_SSCTRL : integer := 0;
		129	constant CFG_SSCTRLP16 : integer := 0;
		130
		131	-- AHB ROM
		132	constant CFG_AHBROMEN : integer := 0;
		133	constant CFG_AHBROPIP : integer := 0;
		134	constant CFG_AHBRODDR : integer := 16#000#;
		135	constant CFG_ROMADDR : integer := 16#000#;
		136	constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
		137
		138	-- AHB RAM
		139	constant CFG_AHBRAMEN : integer := 0;
		140	constant CFG_AHBRSZ : integer := 1;
		141	constant CFG_AHBRADDR : integer := 16#A00#;
		142
		143	-- Gaisler Ethernet core
		144	constant CFG_GRETH : integer := 0;
		145	constant CFG_GRETH1G : integer := 0;
		146	constant CFG_ETH_FIFO : integer := 8;
		147
		148	-- CAN 2.0 interface
		149	constant CFG_CAN : integer := 0;
		150	constant CFG_CANIO : integer := 16#0#;
		151	constant CFG_CANIRQ : integer := 0;
		152	constant CFG_CANLOOP : integer := 0;
		153	constant CFG_CAN_SYNCRST : integer := 0;
		154	constant CFG_CANFT : integer := 0;
		155
		156	-- UART 1
		157	constant CFG_UART1_ENABLE : integer := 1;
		158	constant CFG_UART1_FIFO : integer := 1;
		159
		160	-- LEON3 interrupt controller
		161	constant CFG_IRQ3_ENABLE : integer := 1;
		162
		163	-- Modular timer
		164	constant CFG_GPT_ENABLE : integer := 1;
		165	constant CFG_GPT_NTIM : integer := (2);
		166	constant CFG_GPT_SW : integer := (8);
		167	constant CFG_GPT_TW : integer := (32);
		168	constant CFG_GPT_IRQ : integer := (8);
		169	constant CFG_GPT_SEPIRQ : integer := 1;
		170	constant CFG_GPT_WDOGEN : integer := 0;
		171	constant CFG_GPT_WDOG : integer := 16#0#;
		172
		173	-- GPIO port
		174	constant CFG_GRGPIO_ENABLE : integer := 1;
		175	constant CFG_GRGPIO_IMASK : integer := 16#0000#;
		176	constant CFG_GRGPIO_WIDTH : integer := (7);
		177
		178	-- GRLIB debugging
		179	constant CFG_DUART : integer := 0;
		180
		181	-- SPACEWIRE
		182	constant CFG_SPW_ENABLE : integer := 0;
		183
		184
		185	end;

designs/MINI-LFR_waveformPicker/leon3_soc.vhd created 644 +473 0

			@@ -0,0 +1,473
		1	-----------------------------------------------------------------------------
		2	-- LEON3 Demonstration design
		3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 2 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	--
		15	-- You should have received a copy of the GNU General Public License
		16	-- along with this program; if not, write to the Free Software
		17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		18	------------------------------------------------------------------------------
		19
		20
		21	LIBRARY ieee;
		22	USE ieee.std_logic_1164.ALL;
		23	LIBRARY grlib;
		24	USE grlib.amba.ALL;
		25	USE grlib.stdlib.ALL;
		26	LIBRARY techmap;
		27	USE techmap.gencomp.ALL;
		28	LIBRARY gaisler;
		29	USE gaisler.memctrl.ALL;
		30	USE gaisler.leon3.ALL;
		31	USE gaisler.uart.ALL;
		32	USE gaisler.misc.ALL;
		33	USE gaisler.spacewire.ALL; -- PLE
		34	LIBRARY esa;
		35	USE esa.memoryctrl.ALL;
		36	USE work.config.ALL;
		37	LIBRARY lpp;
		38	USE lpp.lpp_memory.ALL;
		39	USE lpp.lpp_ad_conv.ALL;
		40	USE lpp.lpp_lfr_pkg.ALL;
		41	USE lpp.iir_filter.ALL;
		42	USE lpp.general_purpose.ALL;
		43	USE lpp.lpp_lfr_time_management.ALL;
		44
		45	ENTITY leon3_soc IS
		46	GENERIC (
		47	fabtech : INTEGER := CFG_FABTECH;
		48	memtech : INTEGER := CFG_MEMTECH;
		49	padtech : INTEGER := CFG_PADTECH;
		50	clktech : INTEGER := CFG_CLKTECH;
		51	disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
		52	dbguart : INTEGER := CFG_DUART; -- Print UART on console
		53	pclow : INTEGER := CFG_PCLOW
		54	);
		55	PORT (
		56	clk100MHz : IN STD_ULOGIC;
		57	clk49_152MHz : IN STD_ULOGIC;
		58	reset : IN STD_ULOGIC;
		59
		60	errorn : OUT STD_ULOGIC;
		61
		62	-- UART AHB ---------------------------------------------------------------
		63	ahbrxd : IN STD_ULOGIC; -- DSU rx data
		64	ahbtxd : OUT STD_ULOGIC; -- DSU tx data
		65
		66	-- UART APB ---------------------------------------------------------------
		67	urxd1 : IN STD_ULOGIC; -- UART1 rx data
		68	utxd1 : OUT STD_ULOGIC; -- UART1 tx data
		69
		70	-- RAM --------------------------------------------------------------------
		71	address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
		72	data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		73	nSRAM_BE0 : OUT STD_LOGIC;
		74	nSRAM_BE1 : OUT STD_LOGIC;
		75	nSRAM_BE2 : OUT STD_LOGIC;
		76	nSRAM_BE3 : OUT STD_LOGIC;
		77	nSRAM_WE : OUT STD_LOGIC;
		78	nSRAM_CE : OUT STD_LOGIC;
		79	nSRAM_OE : OUT STD_LOGIC;
		80
		81	-- SPW --------------------------------------------------------------------
		82	spw1_din : IN STD_LOGIC; -- PLE
		83	spw1_sin : IN STD_LOGIC; -- PLE
		84	spw1_dout : OUT STD_LOGIC; -- PLE
		85	spw1_sout : OUT STD_LOGIC; -- PLE
		86
		87	spw2_din : IN STD_LOGIC; -- JCPE --TODO
		88	spw2_sin : IN STD_LOGIC; -- JCPE --TODO
		89	spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
		90	spw2_sout : OUT STD_LOGIC;
		91
		92	-- WAVEFORM PICKER --------------------------------------------------------
		93	apbi_wfp : OUT apb_slv_in_type;
		94	apbo_wfp : IN apb_slv_out_type;
		95	ahbi_wfp : OUT AHB_Mst_In_Type;
		96	ahbo_wfp : IN AHB_Mst_Out_Type;
		97	-- TIME -------------------------------------------------------------------
		98	coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		99	fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
		100
		101	);
		102	END;
		103
		104	ARCHITECTURE Behavioral OF leon3_soc IS
		105
		106	--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
		107	-- CFG_GRETH+CFG_AHB_JTAG;
		108	CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
		109	CFG_AHB_UART
		110	+2;
		111	-- 1 is for the SpaceWire module grspw, which is a master
		112	-- 1 is for the LFR
		113
		114	CONSTANT maxahbm : INTEGER := maxahbmsp;
		115
		116	--Clk & Rst g�n�
		117	SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
		118	SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
		119	SIGNAL resetnl : STD_ULOGIC;
		120	SIGNAL clk2x : STD_ULOGIC;
		121	SIGNAL lclk2x : STD_ULOGIC;
		122	SIGNAL lclk25MHz : STD_ULOGIC;
		123	SIGNAL lclk50MHz : STD_ULOGIC;
		124	SIGNAL lclk100MHz : STD_ULOGIC;
		125	SIGNAL clkm : STD_ULOGIC;
		126	SIGNAL rstn : STD_ULOGIC;
		127	SIGNAL rstraw : STD_ULOGIC;
		128	SIGNAL pciclk : STD_ULOGIC;
		129	SIGNAL sdclkl : STD_ULOGIC;
		130	SIGNAL cgi : clkgen_in_type;
		131	SIGNAL cgo : clkgen_out_type;
		132	--- AHB / APB
		133	SIGNAL apbi : apb_slv_in_type;
		134	SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
		135	SIGNAL ahbsi : ahb_slv_in_type;
		136	SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
		137	SIGNAL ahbmi : ahb_mst_in_type;
		138	SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
		139	--UART
		140	SIGNAL ahbuarti : uart_in_type;
		141	SIGNAL ahbuarto : uart_out_type;
		142	SIGNAL apbuarti : uart_in_type;
		143	SIGNAL apbuarto : uart_out_type;
		144	--MEM CTRLR
		145	SIGNAL memi : memory_in_type;
		146	SIGNAL memo : memory_out_type;
		147	SIGNAL wpo : wprot_out_type;
		148	SIGNAL sdo : sdram_out_type;
		149	SIGNAL ramcs : STD_ULOGIC;
		150	--IRQ
		151	SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
		152	SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
		153	--Timer
		154	SIGNAL gpti : gptimer_in_type;
		155	SIGNAL gpto : gptimer_out_type;
		156	--GPIO
		157	SIGNAL gpioi : gpio_in_type;
		158	SIGNAL gpioo : gpio_out_type;
		159	--DSU
		160	SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
		161	SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
		162	SIGNAL dsui : dsu_in_type;
		163	SIGNAL dsuo : dsu_out_type;
		164
		165	---------------------------------------------------------------------
		166	--- AJOUT TEST ------------------------Signaux----------------------
		167	---------------------------------------------------------------------
		168
		169	---------------------------------------------------------------------
		170	CONSTANT IOAEN : INTEGER := CFG_CAN;
		171	CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
		172
		173	-- Spacewire signals
		174	SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
		175	SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
		176	SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
		177	SIGNAL spw_rxtxclk : STD_ULOGIC;
		178	SIGNAL spw_rxclkn : STD_ULOGIC;
		179	SIGNAL spw_clk : STD_LOGIC;
		180	SIGNAL swni : grspw_in_type; -- PLE
		181	SIGNAL swno : grspw_out_type; -- PLE
		182	SIGNAL clkmn : STD_ULOGIC; -- PLE
		183	SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
		184	-----------------------------------------------------------------------------
		185
		186	BEGIN
		187
		188
		189	----------------------------------------------------------------------
		190	--- Reset and Clock generation -------------------------------------
		191	----------------------------------------------------------------------
		192
		193	vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
		194	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
		195
		196	rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
		197
		198
		199	clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
		200
		201	clkgen0 : clkgen -- clock generator
		202	GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
		203	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
		204	PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
		205
		206	PROCESS(lclk100MHz)
		207	BEGIN
		208	IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
		209	lclk50MHz <= NOT lclk50MHz;
		210	END IF;
		211	END PROCESS;
		212
		213	PROCESS(lclk50MHz)
		214	BEGIN
		215	IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
		216	lclk25MHz <= NOT lclk25MHz;
		217	END IF;
		218	END PROCESS;
		219
		220	lclk2x <= lclk50MHz;
		221	spw_clk <= lclk50MHz;
		222
		223	----------------------------------------------------------------------
		224	--- LEON3 processor / DSU / IRQ ------------------------------------
		225	----------------------------------------------------------------------
		226
		227	l3 : IF CFG_LEON3 = 1 GENERATE
		228	cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
		229	u0 : leon3s -- LEON3 processor
		230	GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
		231	0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
		232	CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
		233	CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
		234	CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
		235	CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
		236	PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
		237	irqi(i), irqo(i), dbgi(i), dbgo(i));
		238	END GENERATE;
		239	errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
		240
		241	dsugen : IF CFG_DSU = 1 GENERATE
		242	dsu0 : dsu3 -- LEON3 Debug Support Unit
		243	GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
		244	ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
		245	PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
		246	dsui.enable <= '1';
		247	dsui.break <= '0';
		248	END GENERATE;
		249	END GENERATE;
		250
		251	nodsu : IF CFG_DSU = 0 GENERATE
		252	ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
		253	END GENERATE;
		254
		255	irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
		256	irqctrl0 : irqmp -- interrupt controller
		257	GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
		258	PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
		259	END GENERATE;
		260	irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
		261	x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
		262	irqi(i).irl <= "0000";
		263	END GENERATE;
		264	apbo(2) <= apb_none;
		265	END GENERATE;
		266
		267	----------------------------------------------------------------------
		268	--- Memory controllers ---------------------------------------------
		269	----------------------------------------------------------------------
		270	memctrlr : mctrl GENERIC MAP (
		271	hindex => 0,
		272	pindex => 0,
		273	paddr => 0,
		274	srbanks => 1
		275	)
		276	PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
		277
		278	memi.brdyn <= '1';
		279	memi.bexcn <= '1';
		280	memi.writen <= '1';
		281	memi.wrn <= "1111";
		282	memi.bwidth <= "10";
		283
		284	bdr : FOR i IN 0 TO 3 GENERATE
		285	data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
		286	PORT MAP (
		287	data(31-i8 DOWNTO 24-i8),
		288	memo.data(31-i8 DOWNTO 24-i8),
		289	memo.bdrive(i),
		290	memi.data(31-i8 DOWNTO 24-i8));
		291	END GENERATE;
		292
		293	addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
		294	PORT MAP (address, memo.address(21 DOWNTO 2));
		295
		296	rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
		297	oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
		298	nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
		299	nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
		300	nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
		301	nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
		302	nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
		303
		304	----------------------------------------------------------------------
		305	--- AHB CONTROLLER -------------------------------------------------
		306	----------------------------------------------------------------------
		307	ahb0 : ahbctrl -- AHB arbiter/multiplexer
		308	GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
		309	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
		310	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
		311	PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
		312
		313	----------------------------------------------------------------------
		314	--- AHB UART -------------------------------------------------------
		315	----------------------------------------------------------------------
		316	dcomgen : IF CFG_AHB_UART = 1 GENERATE
		317	dcom0 : ahbuart
		318	GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
		319	PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
		320	dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
		321	dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
		322	END GENERATE;
		323	nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
		324
		325	----------------------------------------------------------------------
		326	--- APB Bridge -----------------------------------------------------
		327	----------------------------------------------------------------------
		328	apb0 : apbctrl -- AHB/APB bridge
		329	GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
		330	PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
		331
		332	----------------------------------------------------------------------
		333	--- GPT Timer ------------------------------------------------------
		334	----------------------------------------------------------------------
		335	gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
		336	timer0 : gptimer -- timer unit
		337	GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
		338	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
		339	nbits => CFG_GPT_TW)
		340	PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
		341	gpti.dhalt <= dsuo.tstop;
		342	gpti.extclk <= '0';
		343	END GENERATE;
		344	notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
		345
		346
		347	----------------------------------------------------------------------
		348	--- APB UART -------------------------------------------------------
		349	----------------------------------------------------------------------
		350	ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
		351	uart1 : apbuart -- UART 1
		352	GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
		353	fifosize => CFG_UART1_FIFO)
		354	PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
		355	apbuarti.rxd <= urxd1;
		356	apbuarti.extclk <= '0';
		357	utxd1 <= apbuarto.txd;
		358	apbuarti.ctsn <= '0';
		359	END GENERATE;
		360	noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
		361
		362	-------------------------------------------------------------------------------
		363	-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
		364	-------------------------------------------------------------------------------
		365	apb_lfr_time_management_1: apb_lfr_time_management
		366	GENERIC MAP (
		367	pindex => 6,
		368	paddr => 6,
		369	pmask => 16#fff#,
		370	pirq => 12)
		371	PORT MAP (
		372	clk25MHz => clkm,
		373	clk49_152MHz => clk49_152MHz,
		374	resetn => rstn,
		375	grspw_tick => swno.tickout,
		376	apbi => apbi,
		377	apbo => apbo(6),
		378	coarse_time => coarse_time,
		379	fine_time => fine_time);
		380
		381	-----------------------------------------------------------------------
		382	--- SpaceWire --------------------------------------------------------
		383	-----------------------------------------------------------------------
		384
		385	spw_rxtxclk <= spw_clk;
		386	spw_rxclkn <= NOT spw_rxtxclk;
		387
		388	-- PADS for SPW1
		389	spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
		390	PORT MAP (spw1_din, dtmp(0));
		391	spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
		392	PORT MAP (spw1_sin, stmp(0));
		393	spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
		394	PORT MAP (spw1_dout, swno.d(0));
		395	spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
		396	PORT MAP (spw1_sout, swno.s(0));
		397	-- PADS FOR SPW2
		398	spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
		399	PORT MAP (spw2_din, dtmp(1));
		400	spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
		401	PORT MAP (spw2_sin, stmp(1));
		402	spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
		403	PORT MAP (spw2_dout, swno.d(1));
		404	spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
		405	PORT MAP (spw2_sout, swno.s(1));
		406
		407	-- GRSPW PHY
		408	--spw1_input: if CFG_SPW_GRSPW = 1 generate
		409	spw_inputloop : FOR j IN 0 TO 1 GENERATE
		410	spw_phy0 : grspw_phy
		411	GENERIC MAP(
		412	tech => fabtech,
		413	rxclkbuftype => 1,
		414	scantest => 0)
		415	PORT MAP(
		416	rxrst => swno.rxrst,
		417	di => dtmp(j),
		418	si => stmp(j),
		419	rxclko => spw_rxclk(j),
		420	do => swni.d(j),
		421	ndo => swni.nd(j5+4 DOWNTO j5),
		422	dconnect => swni.dconnect(j2+1 DOWNTO j2));
		423	END GENERATE spw_inputloop;
		424
		425	-- SPW core
		426	sw0 : grspwm
		427	GENERIC MAP(
		428	tech => apa3e,
		429	hindex => 1,
		430	pindex => 5,
		431	paddr => 5,
		432	pirq => 11,
		433	sysfreq => 25000, -- CPU_FREQ
		434	rmap => 1,
		435	rmapcrc => 1,
		436	fifosize1 => 16,
		437	fifosize2 => 16,
		438	rxclkbuftype => 1,
		439	rxunaligned => 0,
		440	rmapbufs => 4,
		441	ft => 0,
		442	netlist => 0,
		443	ports => 2,
		444	--dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
		445	memtech => apa3e,
		446	destkey => 2,
		447	spwcore => 1
		448	--input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
		449	--output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
		450	--rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
		451	)
		452	PORT MAP(rstn, clkm, spw_rxclk(0),
		453	spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
		454	ahbmi, ahbmo(1), apbi, apbo(5),
		455	swni, swno);
		456
		457	swni.tickin <= '0';
		458	swni.rmapen <= '1';
		459	swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
		460	swni.tickinraw <= '0';
		461	swni.timein <= (OTHERS => '0');
		462	swni.dcrstval <= (OTHERS => '0');
		463	swni.timerrstval <= (OTHERS => '0');
		464
		465	-------------------------------------------------------------------------------
		466	-- LFR
		467	-------------------------------------------------------------------------------
		468	apbi_wfp <= apbi;
		469	apbo(15) <= apbo_wfp;
		470	ahbi_wfp <= ahbmi;
		471	ahbmo(2) <= ahbo_wfp;
		472
		473	END Behavioral;

designs/MINI-LFR_waveformPicker/leon3mp.vhd created 644 +330 0

			@@ -0,0 +1,330
		1	-----------------------------------------------------------------------------
		2	-- LEON3 Demonstration design
		3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
		4	--
		5	-- This program is free software; you can redistribute it and/or modify
		6	-- it under the terms of the GNU General Public License as published by
		7	-- the Free Software Foundation; either version 2 of the License, or
		8	-- (at your option) any later version.
		9	--
		10	-- This program is distributed in the hope that it will be useful,
		11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
		12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		13	-- GNU General Public License for more details.
		14	--
		15	-- You should have received a copy of the GNU General Public License
		16	-- along with this program; if not, write to the Free Software
		17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
		18	------------------------------------------------------------------------------
		19
		20
		21	LIBRARY ieee;
		22	USE ieee.std_logic_1164.ALL;
		23	LIBRARY grlib;
		24	USE grlib.amba.ALL;
		25	USE grlib.stdlib.ALL;
		26	LIBRARY techmap;
		27	USE techmap.gencomp.ALL;
		28	LIBRARY gaisler;
		29	USE gaisler.memctrl.ALL;
		30	USE gaisler.leon3.ALL;
		31	USE gaisler.uart.ALL;
		32	USE gaisler.misc.ALL;
		33	USE gaisler.spacewire.ALL; -- PLE
		34	LIBRARY esa;
		35	USE esa.memoryctrl.ALL;
		36	USE work.config.ALL;
		37	LIBRARY lpp;
		38	--use lpp.lpp_amba.all;
		39	USE lpp.lpp_memory.ALL;
		40	USE lpp.lpp_ad_conv.ALL;
		41	USE lpp.lpp_top_lfr_pkg.ALL;
		42	--use lpp.lpp_uart.all;
		43	--use lpp.lpp_matrix.all;
		44	--use lpp.lpp_delay.all;
		45	--use lpp.lpp_fft.all;
		46	--use lpp.fft_components.all;
		47	use lpp.iir_filter.all;
		48	USE lpp.general_purpose.ALL;
		49	--use lpp.Filtercfg.all;
		50	USE lpp.lpp_lfr_time_management.ALL; -- PLE
		51	--use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE
		52
		53	ENTITY leon3mp IS
		54	GENERIC (
		55	fabtech : INTEGER := CFG_FABTECH;
		56	memtech : INTEGER := CFG_MEMTECH;
		57	padtech : INTEGER := CFG_PADTECH;
		58	clktech : INTEGER := CFG_CLKTECH;
		59	disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
		60	dbguart : INTEGER := CFG_DUART; -- Print UART on console
		61	pclow : INTEGER := CFG_PCLOW
		62	);
		63	PORT (
		64	clk50MHz : IN STD_ULOGIC;
		65	clk49_152MHz : IN STD_ULOGIC;
		66	reset : IN STD_ULOGIC;
		67
		68	errorn : OUT STD_ULOGIC;
		69
		70	-- UART AHB ---------------------------------------------------------------
		71	ahbrxd : IN STD_ULOGIC; -- DSU rx data
		72	ahbtxd : OUT STD_ULOGIC; -- DSU tx data
		73
		74	-- UART APB ---------------------------------------------------------------
		75	urxd1 : IN STD_ULOGIC; -- UART1 rx data
		76	utxd1 : OUT STD_ULOGIC; -- UART1 tx data
		77
		78	-- RAM --------------------------------------------------------------------
		79	address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
		80	data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
		81	nSRAM_BE0 : OUT STD_LOGIC;
		82	nSRAM_BE1 : OUT STD_LOGIC;
		83	nSRAM_BE2 : OUT STD_LOGIC;
		84	nSRAM_BE3 : OUT STD_LOGIC;
		85	nSRAM_WE : OUT STD_LOGIC;
		86	nSRAM_CE : OUT STD_LOGIC;
		87	nSRAM_OE : OUT STD_LOGIC;
		88
		89	-- SPW --------------------------------------------------------------------
		90	spw1_din : IN STD_LOGIC; -- PLE
		91	spw1_sin : IN STD_LOGIC; -- PLE
		92	spw1_dout : OUT STD_LOGIC; -- PLE
		93	spw1_sout : OUT STD_LOGIC; -- PLE
		94
		95	-- ADC --------------------------------------------------------------------
		96	bias_fail_sw : OUT STD_LOGIC;
		97	ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		98	ADC_smpclk : OUT STD_LOGIC;
		99	ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
		100
		101	---------------------------------------------------------------------------
		102	led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
		103	);
		104	END;
		105
		106	ARCHITECTURE Behavioral OF leon3mp IS
		107
		108	--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
		109	-- CFG_GRETH+CFG_AHB_JTAG;
		110	CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
		111	CFG_AHB_UART+
		112	CFG_GRETH+
		113	CFG_AHB_JTAG
		114	+2; -- 1 is for the SpaceWire module grspw2, which is a master
		115	CONSTANT maxahbm : INTEGER := maxahbmsp;
		116
		117	--Clk & Rst g�n�
		118	SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
		119	SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
		120	SIGNAL clk2x : STD_ULOGIC;
		121	SIGNAL lclk2x : STD_ULOGIC;
		122	SIGNAL lclk25MHz : STD_ULOGIC;
		123	SIGNAL lclk50MHz : STD_ULOGIC;
		124	SIGNAL lclk100MHz : STD_ULOGIC;
		125	SIGNAL clkm : STD_ULOGIC;
		126	SIGNAL rstn : STD_ULOGIC;
		127	SIGNAL rstraw : STD_ULOGIC;
		128	SIGNAL pciclk : STD_ULOGIC;
		129	SIGNAL sdclkl : STD_ULOGIC;
		130	SIGNAL cgi : clkgen_in_type;
		131	SIGNAL cgo : clkgen_out_type;
		132	--- AHB / APB
		133	SIGNAL apbi : apb_slv_in_type;
		134	SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
		135	SIGNAL ahbsi : ahb_slv_in_type;
		136	SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
		137	SIGNAL ahbmi : ahb_mst_in_type;
		138	SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
		139	--UART
		140	SIGNAL ahbuarti : uart_in_type;
		141	SIGNAL ahbuarto : uart_out_type;
		142	SIGNAL apbuarti : uart_in_type;
		143	SIGNAL apbuarto : uart_out_type;
		144	--MEM CTRLR
		145	SIGNAL memi : memory_in_type;
		146	SIGNAL memo : memory_out_type;
		147	SIGNAL wpo : wprot_out_type;
		148	SIGNAL sdo : sdram_out_type;
		149	SIGNAL ramcs : STD_ULOGIC;
		150	--IRQ
		151	SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
		152	SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
		153	--Timer
		154	SIGNAL gpti : gptimer_in_type;
		155	SIGNAL gpto : gptimer_out_type;
		156	--GPIO
		157	SIGNAL gpioi : gpio_in_type;
		158	SIGNAL gpioo : gpio_out_type;
		159	--DSU
		160	SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
		161	SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
		162	SIGNAL dsui : dsu_in_type;
		163	SIGNAL dsuo : dsu_out_type;
		164
		165	---------------------------------------------------------------------
		166	--- AJOUT TEST ------------------------Signaux----------------------
		167	---------------------------------------------------------------------
		168
		169	---------------------------------------------------------------------
		170	CONSTANT IOAEN : INTEGER := CFG_CAN;
		171	CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
		172
		173	-- time management signal
		174	SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
		175	SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
		176
		177	-- Spacewire signals
		178	SIGNAL dtmp : STD_ULOGIC; -- PLE
		179	SIGNAL stmp : STD_ULOGIC; -- PLE
		180	SIGNAL rxclko : STD_ULOGIC; -- PLE
		181	SIGNAL swni : grspw_in_type; -- PLE
		182	SIGNAL swno : grspw_out_type; -- PLE
		183	SIGNAL clkmn : STD_ULOGIC; -- PLE
		184	SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
		185
		186	-- AD Converter RHF1401
		187	SIGNAL sample : Samples14v(7 DOWNTO 0);
		188	SIGNAL sample_val : STD_LOGIC;
		189	-----------------------------------------------------------------------------
		190	SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
		191
		192	BEGIN
		193
		194
		195	----------------------------------------------------------------------
		196	--- Reset and Clock generation -------------------------------------
		197	----------------------------------------------------------------------
		198
		199	vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
		200	cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
		201
		202	rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
		203
		204
		205	clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz);
		206
		207	clkgen0 : clkgen -- clock generator
		208	GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
		209	CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
		210	PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
		211
		212	PROCESS(lclk100MHz)
		213	BEGIN
		214	IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
		215	lclk50MHz <= NOT lclk50MHz;
		216	END IF;
		217	END PROCESS;
		218
		219	PROCESS(lclk50MHz)
		220	BEGIN
		221	IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
		222	lclk25MHz <= NOT lclk25MHz;
		223	END IF;
		224	END PROCESS;
		225
		226	lclk2x <= lclk50MHz;
		227
		228
		229
		230	----------------------------------------------------------------------
		231	--- Memory controllers ---------------------------------------------
		232	----------------------------------------------------------------------
		233	memctrlr : mctrl GENERIC MAP (
		234	hindex => 0,
		235	pindex => 0,
		236	paddr => 0,
		237	srbanks => 1
		238	)
		239	PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
		240
		241	memi.brdyn <= '1';
		242	memi.bexcn <= '1';
		243	memi.writen <= '1';
		244	memi.wrn <= "1111";
		245	memi.bwidth <= "10";
		246
		247	bdr : FOR i IN 0 TO 3 GENERATE
		248	data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
		249	PORT MAP (
		250	data(31-i8 DOWNTO 24-i8),
		251	memo.data(31-i8 DOWNTO 24-i8),
		252	memo.bdrive(i),
		253	memi.data(31-i8 DOWNTO 24-i8));
		254	END GENERATE;
		255
		256	addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
		257	PORT MAP (address, memo.address(21 DOWNTO 2));
		258
		259	rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
		260	oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
		261	nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
		262	nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
		263	nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
		264	nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
		265	nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
		266
		267	----------------------------------------------------------------------
		268	--- AHB CONTROLLER -------------------------------------------------
		269	----------------------------------------------------------------------
		270	ahb0 : ahbctrl -- AHB arbiter/multiplexer
		271	GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
		272	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
		273	ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
		274	PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
		275
		276	----------------------------------------------------------------------
		277	--- AHB UART -------------------------------------------------------
		278	----------------------------------------------------------------------
		279	dcomgen : IF CFG_AHB_UART = 1 GENERATE
		280	dcom0 : ahbuart
		281	GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4)
		282	PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
		283	dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
		284	dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
		285	led(0) <= NOT ahbuarti.rxd;
		286	led(1) <= NOT ahbuarto.txd;
		287	END GENERATE;
		288	nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
		289
		290	----------------------------------------------------------------------
		291	--- APB Bridge -----------------------------------------------------
		292	----------------------------------------------------------------------
		293	apb0 : apbctrl -- AHB/APB bridge
		294	GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
		295	PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
		296
		297	----------------------------------------------------------------------
		298	--- GPT Timer ------------------------------------------------------
		299	----------------------------------------------------------------------
		300	gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
		301	timer0 : gptimer -- timer unit
		302	GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
		303	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
		304	nbits => CFG_GPT_TW)
		305	PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
		306	gpti.dhalt <= dsuo.tstop;
		307	gpti.extclk <= '0';
		308	END GENERATE;
		309	notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
		310
		311
		312	----------------------------------------------------------------------
		313	--- APB UART -------------------------------------------------------
		314	----------------------------------------------------------------------
		315	ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
		316	uart1 : apbuart -- UART 1
		317	GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
		318	fifosize => CFG_UART1_FIFO)
		319	PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
		320	apbuarti.rxd <= urxd1;
		321	apbuarti.extclk <= '0';
		322	utxd1 <= apbuarto.txd;
		323	apbuarti.ctsn <= '0';
		324	END GENERATE;
		325	noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
		326
		327
		328
		329
		330	END Behavioral; No newline at end of file

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