# HG changeset patch # User JC # Date 2013-11-27 15:00:45 # Node ID 40654893b5ba312794f74b312a057ec10f2a410b # Parent 708a8ff959a73193e810d27f597c281b5efe88ad temp diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd @@ -0,0 +1,261 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; + +ENTITY MINI_LFR_top IS + + PORT ( + clk_50 : IN STD_LOGIC; + clk_49 : IN STD_LOGIC; + reset : IN STD_LOGIC; + --BPs + BP0 : IN STD_LOGIC; + BP1 : IN STD_LOGIC; + --LEDs + LED0 : OUT STD_LOGIC; + LED1 : OUT STD_LOGIC; + LED2 : OUT STD_LOGIC; + --UARTs + TXD1 : IN STD_LOGIC; + RXD1 : OUT STD_LOGIC; + nCTS1 : OUT STD_LOGIC; + nRTS1 : IN STD_LOGIC; + + TXD2 : IN STD_LOGIC; + RXD2 : OUT STD_LOGIC; + nCTS2 : OUT STD_LOGIC; + nDTR2 : IN STD_LOGIC; + nRTS2 : IN STD_LOGIC; + nDCD2 : OUT STD_LOGIC; + + --EXT CONNECTOR + IO0 : INOUT STD_LOGIC; + IO1 : INOUT STD_LOGIC; + IO2 : INOUT STD_LOGIC; + IO3 : INOUT STD_LOGIC; + IO4 : INOUT STD_LOGIC; + IO5 : INOUT STD_LOGIC; + IO6 : INOUT STD_LOGIC; + IO7 : INOUT STD_LOGIC; + IO8 : INOUT STD_LOGIC; + IO9 : INOUT STD_LOGIC; + IO10 : INOUT STD_LOGIC; + IO11 : INOUT STD_LOGIC; + + --SPACE WIRE + SPW_EN : OUT STD_LOGIC; -- 0 => off + SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK + SPW_NOM_SIN : IN STD_LOGIC; + SPW_NOM_DOUT : OUT STD_LOGIC; + SPW_NOM_SOUT : OUT STD_LOGIC; + SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK + SPW_RED_SIN : IN STD_LOGIC; + SPW_RED_DOUT : OUT STD_LOGIC; + SPW_RED_SOUT : OUT STD_LOGIC; + -- MINI LFR ADC INPUTS + ADC_nCS : OUT STD_LOGIC; + ADC_CLK : OUT STD_LOGIC; + ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + -- SRAM + SRAM_nWE : OUT STD_LOGIC; + SRAM_CE : OUT STD_LOGIC; + SRAM_nOE : OUT STD_LOGIC; + SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END MINI_LFR_top; + + +ARCHITECTURE beh OF MINI_LFR_top IS + + COMPONENT leon3_soc + GENERIC ( + fabtech : INTEGER; + memtech : INTEGER; + padtech : INTEGER; + clktech : INTEGER; + disas : INTEGER; + dbguart : INTEGER; + pclow : INTEGER); + PORT ( + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + errorn : OUT STD_ULOGIC; + ahbrxd : IN STD_ULOGIC; + ahbtxd : OUT STD_ULOGIC; + urxd1 : IN STD_ULOGIC; + utxd1 : OUT STD_ULOGIC; + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + spw1_din : IN STD_LOGIC; + spw1_sin : IN STD_LOGIC; + spw1_dout : OUT STD_LOGIC; + spw1_sout : OUT STD_LOGIC; + spw2_din : IN STD_LOGIC; + spw2_sin : IN STD_LOGIC; + spw2_dout : OUT STD_LOGIC; + spw2_sout : OUT STD_LOGIC; + apbi_wfp : OUT apb_slv_in_type; + apbo_wfp : IN apb_slv_out_type; + ahbi_wfp : OUT AHB_Mst_In_Type; + ahbo_wfp : IN AHB_Mst_Out_Type; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); + END COMPONENT; + +BEGIN -- beh + + PROCESS (clk_50, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + LED0 <= '0'; + LED1 <= '0'; + LED2 <= '0'; + ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge + LED0 <= '0'; + LED1 <= '1'; + LED2 <= BP0; + END IF; + END PROCESS; + + --UARTs + RXD1 <= '0'; + nCTS1 <= '0'; + RXD2 <= '0'; + nCTS2 <= '0'; + nDCD2 <= '0'; + + --EXT CONNECTOR + IO0 <= clk_49; + IO1 <= clk_50; + + IO2 <= SPW_NOM_DIN OR + SPW_NOM_SIN OR + SPW_RED_DIN OR + SPW_RED_SIN; + + IO3 <= ADC_SDO(0); + IO4 <= ADC_SDO(1); + IO5 <= ADC_SDO(2); + IO6 <= ADC_SDO(3); + IO7 <= ADC_SDO(4); + IO8 <= ADC_SDO(5); + IO9 <= ADC_SDO(6); + IO10 <= ADC_SDO(7); + IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1; + + --SPACE WIRE + SPW_EN <= '0'; -- 0 => off + SPW_NOM_DOUT <= '0'; + SPW_NOM_SOUT <= '0'; + SPW_RED_DOUT <= '0'; + SPW_RED_SOUT <= '0'; + ADC_nCS <= '0'; + ADC_CLK <= '0'; + + -- SRAM + SRAM_nWE <= '1'; + SRAM_CE <= '0'; + SRAM_nOE <= '1'; + SRAM_nBE <= (OTHERS => '1'); + SRAM_A <= (OTHERS => '0'); + SRAM_DQ <= (OTHERS => '0'); + + + leon3mp_1: leon3_soc + GENERIC MAP ( + fabtech => fabtech, + memtech => memtech, + padtech => padtech, + clktech => clktech, + disas => disas, + dbguart => dbguart, + pclow => pclow) + PORT MAP ( + clk100MHz => clk100MHz, + clk49_152MHz => clk49_152MHz, + reset => reset, + errorn => errorn, + ahbrxd => ahbrxd, + ahbtxd => ahbtxd, + urxd1 => urxd1, + utxd1 => utxd1, + address => address, + data => data, + nSRAM_BE0 => nSRAM_BE0, + nSRAM_BE1 => nSRAM_BE1, + nSRAM_BE2 => nSRAM_BE2, + nSRAM_BE3 => nSRAM_BE3, + nSRAM_WE => nSRAM_WE, + nSRAM_CE => nSRAM_CE, + nSRAM_OE => nSRAM_OE, + spw1_din => spw1_din, + spw1_sin => spw1_sin, + spw1_dout => spw1_dout, + spw1_sout => spw1_sout, + spw2_din => spw2_din, + spw2_sin => spw2_sin, + spw2_dout => spw2_dout, + spw2_sout => spw2_sout, + apbi_wfp => apbi_wfp, + apbo_wfp => apbo_wfp, + ahbi_wfp => ahbi_wfp, + ahbo_wfp => ahbo_wfp, + coarse_time => coarse_time, + fine_time => fine_time); + + +END beh; diff --git a/designs/MINI-LFR_waveformPicker/Makefile b/designs/MINI-LFR_waveformPicker/Makefile new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_waveformPicker/Makefile @@ -0,0 +1,49 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=MINI_LFR_top +BOARD=MINI-LFR +include $(VHDLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +VHDLSYNFILES= MINI_LFR_top.vhd \ + config.vhd \ + leon3_soc.vhd + +PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc +BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./dsp/lpp_fft \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_demux \ + ./lpp_matrix \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_Header \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_SIMPLE_DIODE.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/MINI-LFR_waveformPicker/config.vhd b/designs/MINI-LFR_waveformPicker/config.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_waveformPicker/config.vhd @@ -0,0 +1,185 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is + + +-- Technology and synthesis options + constant CFG_FABTECH : integer := apa3e; + constant CFG_MEMTECH : integer := apa3e; + constant CFG_PADTECH : integer := inferred; + constant CFG_NOASYNC : integer := 0; + constant CFG_SCAN : integer := 0; + +-- Clock generator + constant CFG_CLKTECH : integer := inferred; + constant CFG_CLKMUL : integer := (1); + constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz + constant CFG_OCLKDIV : integer := (1); + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; + +-- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := (1); + --constant CFG_NWIN : integer := (7); -- PLE + constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC + constant CFG_V8 : integer := 0; + constant CFG_MAC : integer := 0; + constant CFG_SVT : integer := 0; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NWP : integer := (0); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist + --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE + constant CFG_GRFPUSH : integer := 0; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 1; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 0; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 1; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 0; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DFIXED : integer := 16#00F3#; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 0; + constant CFG_ITLBNUM : integer := 2; + constant CFG_DTLBNUM : integer := 2; + constant CFG_TLB_TYPE : integer := 1 + 0*2; + constant CFG_TLB_REP : integer := 1; + constant CFG_DSU : integer := 1; + constant CFG_ITBSZ : integer := 0; + constant CFG_ATBSZ : integer := 0; + constant CFG_LEON3FT_EN : integer := 0; + constant CFG_IUFT_EN : integer := 0; + constant CFG_FPUFT_EN : integer := 0; + constant CFG_RF_ERRINJ : integer := 0; + constant CFG_CACHE_FT_EN : integer := 0; + constant CFG_CACHE_ERRINJ : integer := 0; + constant CFG_LEON3_NETLIST: integer := 0; + constant CFG_DISAS : integer := 0 + 0; + constant CFG_PCLOW : integer := 2; + +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + +-- DSU UART + constant CFG_AHB_UART : integer := 1; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 0; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := 0 + 0; + constant CFG_ETH_BUF : integer := 1; + constant CFG_ETH_IPM : integer := 16#C0A8#; + constant CFG_ETH_IPL : integer := 16#0033#; + constant CFG_ETH_ENM : integer := 16#00007A#; + constant CFG_ETH_ENL : integer := 16#CC0001#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 0; + constant CFG_MCTRL_RAM16BIT : integer := 0; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; + +-- SSRAM controller + constant CFG_SSCTRL : integer := 0; + constant CFG_SSCTRLP16 : integer := 0; + +-- AHB ROM + constant CFG_AHBROMEN : integer := 0; + constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBRODDR : integer := 16#000#; + constant CFG_ROMADDR : integer := 16#000#; + constant CFG_ROMMASK : integer := 16#E00# + 16#000#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := 0; + constant CFG_AHBRSZ : integer := 1; + constant CFG_AHBRADDR : integer := 16#A00#; + +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + constant CFG_GRETH1G : integer := 0; + constant CFG_ETH_FIFO : integer := 8; + +-- CAN 2.0 interface + constant CFG_CAN : integer := 0; + constant CFG_CANIO : integer := 16#0#; + constant CFG_CANIRQ : integer := 0; + constant CFG_CANLOOP : integer := 0; + constant CFG_CAN_SYNCRST : integer := 0; + constant CFG_CANFT : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 1; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := 1; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := 1; + constant CFG_GPT_NTIM : integer := (2); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := 1; + constant CFG_GRGPIO_IMASK : integer := 16#0000#; + constant CFG_GRGPIO_WIDTH : integer := (7); + +-- GRLIB debugging + constant CFG_DUART : integer := 0; + +-- SPACEWIRE + constant CFG_SPW_ENABLE : integer := 0; + + +end; diff --git a/designs/MINI-LFR_waveformPicker/leon3_soc.vhd b/designs/MINI-LFR_waveformPicker/leon3_soc.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_waveformPicker/leon3_soc.vhd @@ -0,0 +1,473 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_time_management.ALL; + +ENTITY leon3_soc IS + GENERIC ( + fabtech : INTEGER := CFG_FABTECH; + memtech : INTEGER := CFG_MEMTECH; + padtech : INTEGER := CFG_PADTECH; + clktech : INTEGER := CFG_CLKTECH; + disas : INTEGER := CFG_DISAS; -- Enable disassembly to console + dbguart : INTEGER := CFG_DUART; -- Print UART on console + pclow : INTEGER := CFG_PCLOW + ); + PORT ( + clk100MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- SPW -------------------------------------------------------------------- + spw1_din : IN STD_LOGIC; -- PLE + spw1_sin : IN STD_LOGIC; -- PLE + spw1_dout : OUT STD_LOGIC; -- PLE + spw1_sout : OUT STD_LOGIC; -- PLE + + spw2_din : IN STD_LOGIC; -- JCPE --TODO + spw2_sin : IN STD_LOGIC; -- JCPE --TODO + spw2_dout : OUT STD_LOGIC; -- JCPE --TODO + spw2_sout : OUT STD_LOGIC; + + -- WAVEFORM PICKER -------------------------------------------------------- + apbi_wfp : OUT apb_slv_in_type; + apbo_wfp : IN apb_slv_out_type; + ahbi_wfp : OUT AHB_Mst_In_Type; + ahbo_wfp : IN AHB_Mst_Out_Type; + -- TIME ------------------------------------------------------------------- + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + + ); +END; + +ARCHITECTURE Behavioral OF leon3_soc IS + +--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ +-- CFG_GRETH+CFG_AHB_JTAG; + CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ + CFG_AHB_UART + +2; + -- 1 is for the SpaceWire module grspw, which is a master + -- 1 is for the LFR + + CONSTANT maxahbm : INTEGER := maxahbmsp; + +--Clk & Rst g�n� + SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL resetnl : STD_ULOGIC; + SIGNAL clk2x : STD_ULOGIC; + SIGNAL lclk2x : STD_ULOGIC; + SIGNAL lclk25MHz : STD_ULOGIC; + SIGNAL lclk50MHz : STD_ULOGIC; + SIGNAL lclk100MHz : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; +--- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); +--UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; +--MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + SIGNAL ramcs : STD_ULOGIC; +--IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); +--Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; +--DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- + CONSTANT IOAEN : INTEGER := CFG_CAN; + CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz + +-- Spacewire signals + SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE + SIGNAL spw_rxtxclk : STD_ULOGIC; + SIGNAL spw_rxclkn : STD_ULOGIC; + SIGNAL spw_clk : STD_LOGIC; + SIGNAL swni : grspw_in_type; -- PLE + SIGNAL swno : grspw_out_type; -- PLE + SIGNAL clkmn : STD_ULOGIC; -- PLE + SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 + ----------------------------------------------------------------------------- + +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + + PROCESS(lclk100MHz) + BEGIN + IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN + lclk50MHz <= NOT lclk50MHz; + END IF; + END PROCESS; + + PROCESS(lclk50MHz) + BEGIN + IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN + lclk25MHz <= NOT lclk25MHz; + END IF; + END PROCESS; + + lclk2x <= lclk50MHz; + spw_clk <= lclk50MHz; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3s -- LEON3 processor + GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + END GENERATE; + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => 3, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +------------------------------------------------------------------------------- + apb_lfr_time_management_1: apb_lfr_time_management + GENERIC MAP ( + pindex => 6, + paddr => 6, + pmask => 16#fff#, + pirq => 12) + PORT MAP ( + clk25MHz => clkm, + clk49_152MHz => clk49_152MHz, + resetn => rstn, + grspw_tick => swno.tickout, + apbi => apbi, + apbo => apbo(6), + coarse_time => coarse_time, + fine_time => fine_time); + +----------------------------------------------------------------------- +--- SpaceWire -------------------------------------------------------- +----------------------------------------------------------------------- + + spw_rxtxclk <= spw_clk; + spw_rxclkn <= NOT spw_rxtxclk; + + -- PADS for SPW1 + spw1_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_din, dtmp(0)); + spw1_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sin, stmp(0)); + spw1_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_dout, swno.d(0)); + spw1_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw1_sout, swno.s(0)); + -- PADS FOR SPW2 + spw2_rxd_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_din, dtmp(1)); + spw2_rxs_pad : inpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sin, stmp(1)); + spw2_txd_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_dout, swno.d(1)); + spw2_txs_pad : outpad GENERIC MAP (tech => padtech) + PORT MAP (spw2_sout, swno.s(1)); + + -- GRSPW PHY + --spw1_input: if CFG_SPW_GRSPW = 1 generate + spw_inputloop : FOR j IN 0 TO 1 GENERATE + spw_phy0 : grspw_phy + GENERIC MAP( + tech => fabtech, + rxclkbuftype => 1, + scantest => 0) + PORT MAP( + rxrst => swno.rxrst, + di => dtmp(j), + si => stmp(j), + rxclko => spw_rxclk(j), + do => swni.d(j), + ndo => swni.nd(j*5+4 DOWNTO j*5), + dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); + END GENERATE spw_inputloop; + + -- SPW core + sw0 : grspwm + GENERIC MAP( + tech => apa3e, + hindex => 1, + pindex => 5, + paddr => 5, + pirq => 11, + sysfreq => 25000, -- CPU_FREQ + rmap => 1, + rmapcrc => 1, + fifosize1 => 16, + fifosize2 => 16, + rxclkbuftype => 1, + rxunaligned => 0, + rmapbufs => 4, + ft => 0, + netlist => 0, + ports => 2, + --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 + memtech => apa3e, + destkey => 2, + spwcore => 1 + --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 + --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 + --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 + ) + PORT MAP(rstn, clkm, spw_rxclk(0), + spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, + ahbmi, ahbmo(1), apbi, apbo(5), + swni, swno); + + swni.tickin <= '0'; + swni.rmapen <= '1'; + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz + swni.tickinraw <= '0'; + swni.timein <= (OTHERS => '0'); + swni.dcrstval <= (OTHERS => '0'); + swni.timerrstval <= (OTHERS => '0'); + +------------------------------------------------------------------------------- +-- LFR +------------------------------------------------------------------------------- + apbi_wfp <= apbi; + apbo(15) <= apbo_wfp; + ahbi_wfp <= ahbmi; + ahbmo(2) <= ahbo_wfp; + +END Behavioral; diff --git a/designs/MINI-LFR_waveformPicker/leon3mp.vhd b/designs/MINI-LFR_waveformPicker/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/designs/MINI-LFR_waveformPicker/leon3mp.vhd @@ -0,0 +1,330 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +USE work.config.ALL; +LIBRARY lpp; +--use lpp.lpp_amba.all; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +--use lpp.lpp_uart.all; +--use lpp.lpp_matrix.all; +--use lpp.lpp_delay.all; +--use lpp.lpp_fft.all; +--use lpp.fft_components.all; +use lpp.iir_filter.all; +USE lpp.general_purpose.ALL; +--use lpp.Filtercfg.all; +USE lpp.lpp_lfr_time_management.ALL; -- PLE +--use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE + +ENTITY leon3mp IS + GENERIC ( + fabtech : INTEGER := CFG_FABTECH; + memtech : INTEGER := CFG_MEMTECH; + padtech : INTEGER := CFG_PADTECH; + clktech : INTEGER := CFG_CLKTECH; + disas : INTEGER := CFG_DISAS; -- Enable disassembly to console + dbguart : INTEGER := CFG_DUART; -- Print UART on console + pclow : INTEGER := CFG_PCLOW + ); + PORT ( + clk50MHz : IN STD_ULOGIC; + clk49_152MHz : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- SPW -------------------------------------------------------------------- + spw1_din : IN STD_LOGIC; -- PLE + spw1_sin : IN STD_LOGIC; -- PLE + spw1_dout : OUT STD_LOGIC; -- PLE + spw1_sout : OUT STD_LOGIC; -- PLE + + -- ADC -------------------------------------------------------------------- + bias_fail_sw : OUT STD_LOGIC; + ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + ADC_smpclk : OUT STD_LOGIC; + ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); + + --------------------------------------------------------------------------- + led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF leon3mp IS + +--constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ +-- CFG_GRETH+CFG_AHB_JTAG; + CONSTANT maxahbmsp : INTEGER := CFG_NCPU+ + CFG_AHB_UART+ + CFG_GRETH+ + CFG_AHB_JTAG + +2; -- 1 is for the SpaceWire module grspw2, which is a master + CONSTANT maxahbm : INTEGER := maxahbmsp; + +--Clk & Rst g�n� + SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL clk2x : STD_ULOGIC; + SIGNAL lclk2x : STD_ULOGIC; + SIGNAL lclk25MHz : STD_ULOGIC; + SIGNAL lclk50MHz : STD_ULOGIC; + SIGNAL lclk100MHz : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; +--- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); +--UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; +--MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + SIGNAL ramcs : STD_ULOGIC; +--IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); +--Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; +--GPIO + SIGNAL gpioi : gpio_in_type; + SIGNAL gpioo : gpio_out_type; +--DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- + CONSTANT IOAEN : INTEGER := CFG_CAN; + CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz + +-- time management signal + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + +-- Spacewire signals + SIGNAL dtmp : STD_ULOGIC; -- PLE + SIGNAL stmp : STD_ULOGIC; -- PLE + SIGNAL rxclko : STD_ULOGIC; -- PLE + SIGNAL swni : grspw_in_type; -- PLE + SIGNAL swno : grspw_out_type; -- PLE + SIGNAL clkmn : STD_ULOGIC; -- PLE + SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14 + +-- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + + PROCESS(lclk100MHz) + BEGIN + IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN + lclk50MHz <= NOT lclk50MHz; + END IF; + END PROCESS; + + PROCESS(lclk50MHz) + BEGIN + IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN + lclk25MHz <= NOT lclk25MHz; + END IF; + END PROCESS; + + lclk2x <= lclk50MHz; + + + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0))); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4) + PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + led(0) <= NOT ahbuarti.rxd; + led(1) <= NOT ahbuarto.txd; + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + + + + +END Behavioral; \ No newline at end of file