@@ -85,6 +85,8 ARCHITECTURE Behavioral OF lpp_dma_SEND1 | |||
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85 | 85 | |
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86 | 86 | SIGNAL bus_request : STD_LOGIC; |
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87 | 87 | SIGNAL bus_lock : STD_LOGIC; |
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88 | ||
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89 | SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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88 | 90 | |
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89 | 91 | BEGIN |
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90 | 92 | |
@@ -111,8 +113,8 BEGIN | |||
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111 | 113 | |
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112 | 114 | ----------------------------------------------------------------------------- |
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113 | 115 | AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00"; |
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114 | AHB_Master_Out.HWDATA <= ahbdrivedata(data); | |
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115 | ||
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116 | AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg); | |
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117 | ||
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116 | 118 |
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117 | 119 | --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY ); |
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118 | 120 | --ren <= NOT beat; |
@@ -122,12 +124,21 BEGIN | |||
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122 | 124 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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123 | 125 | state <= IDLE; |
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124 | 126 | done <= '0'; |
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127 | ren <= '1'; | |
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125 | 128 |
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126 | 129 | AHB_Master_Out.HTRANS <= HTRANS_IDLE; |
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127 | 130 | AHB_Master_Out.HBUSREQ <= '0'; |
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128 | 131 | AHB_Master_Out.HLOCK <= '0'; |
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132 | ||
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133 | data_reg <= (OTHERS => '0'); | |
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129 | 134 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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135 | ||
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136 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN | |
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137 | data_reg <= data; | |
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138 | END IF; | |
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139 | ||
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130 | 140 |
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141 | ren <= '1'; | |
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131 | 142 | CASE state IS |
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132 | 143 | WHEN IDLE => |
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133 | 144 | AHB_Master_Out.HBUSREQ <= '0'; |
@@ -159,6 +170,7 BEGIN | |||
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159 | 170 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN |
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160 | 171 | AHB_Master_Out.HTRANS <= HTRANS_SEQ; |
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161 | 172 | state <= s_CTRL_DATA; |
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173 | ren <= '0'; | |
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162 | 174 | END IF; |
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163 | 175 | |
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164 | 176 | WHEN s_CTRL_DATA => |
@@ -176,6 +188,11 BEGIN | |||
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176 | 188 | state <= s_DATA; |
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177 | 189 | END IF; |
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178 | 190 | |
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191 | IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN | |
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192 | ren <= '0'; | |
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193 | END IF; | |
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194 | ||
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195 | ||
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179 | 196 | WHEN s_DATA => |
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180 | 197 | AHB_Master_Out.HBUSREQ <= '0'; |
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181 | 198 | --AHB_Master_Out.HLOCK <= '0'; |
@@ -194,7 +211,9 BEGIN | |||
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194 | 211 | ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0'; |
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195 | 212 | data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0'; |
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196 | 213 | ----------------------------------------------------------------------------- |
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197 | ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; | |
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214 | ||
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215 | ||
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216 | --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1'; | |
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198 | 217 | |
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199 | 218 | ----------------------------------------------------------------------------- |
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200 | 219 | --PROCESS (clk, rstn) |
@@ -422,7 +422,7 BEGIN | |||
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422 | 422 | --Aeroflex memory generics: |
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423 | 423 | mbpedac => BYPASS_EDAC_MEMCTRLR, |
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424 | 424 | mprog => 1, -- program memory by default values after reset |
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425 |
mpsrate => |
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425 | mpsrate => 5, -- default scrub rate period | |
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426 | 426 | mpb2s => 14, -- default busy to scrub delay |
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427 | 427 | mpapb => 1, -- instantiate apb register |
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428 | 428 | mchipcnt => 2, |
@@ -83,6 +83,9 ARCHITECTURE beh OF lpp_lfr IS | |||
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83 | 83 | SIGNAL sample_f2_val : STD_LOGIC; |
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84 | 84 | SIGNAL sample_f3_val : STD_LOGIC; |
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85 | 85 | -- |
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86 | SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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87 | SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0); | |
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88 | -- | |
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86 | 89 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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87 | 90 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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88 | 91 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
@@ -262,20 +265,66 BEGIN | |||
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262 | 265 | data_shaping_R0 => data_shaping_R0, |
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263 | 266 | data_shaping_R1 => data_shaping_R1, |
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264 | 267 | data_shaping_R2 => data_shaping_R2, |
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265 |
sample_f0_val => sample_f |
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266 |
sample_f1_val => sample_f |
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267 |
sample_f2_val => sample_f |
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268 |
sample_f3_val => sample_f |
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269 |
sample_f0_wdata => |
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270 |
sample_f1_wdata => |
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271 |
sample_f2_wdata => |
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272 |
sample_f3_wdata => |
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268 | sample_f0_val => sample_f_val(0), | |
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269 | sample_f1_val => sample_f_val(1), | |
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270 | sample_f2_val => sample_f_val(2), | |
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271 | sample_f3_val => sample_f_val(3), | |
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272 | sample_f0_wdata => OPEN, | |
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273 | sample_f1_wdata => OPEN, | |
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274 | sample_f2_wdata => OPEN, | |
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275 | sample_f3_wdata => OPEN, | |
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273 | 276 | sample_f0_time => sample_f0_time, |
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274 | 277 | sample_f1_time => sample_f1_time, |
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275 | 278 | sample_f2_time => sample_f2_time, |
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276 | 279 | sample_f3_time => sample_f3_time |
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277 | 280 | ); |
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281 | ----------------------------------------------------------------------------- | |
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282 | ALL_lane: FOR J IN 0 TO 3 GENERATE | |
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283 | ALL_channel: FOR I IN 0 TO 5 GENERATE | |
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284 | sample_f_data(15 + I*16 + J*6*16 DOWNTO 14 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(J,2)); | |
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285 | sample_f_data(13 + I*16 + J*6*16 DOWNTO 11 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(I,3)); | |
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278 | 286 | |
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287 | PROCESS (clk, rstn) | |
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288 | BEGIN -- PROCESS | |
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289 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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290 | sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16 ) <= STD_LOGIC_VECTOR(to_unsigned(2**11/6*I,11)); | |
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291 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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292 | IF sample_f_val(J) = '1' THEN | |
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293 | sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned( | |
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294 | to_integer(UNSIGNED(sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16))) + 1, | |
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295 | 11)); | |
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296 | END IF; | |
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297 | END IF; | |
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298 | END PROCESS; | |
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299 | ||
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300 | END GENERATE ALL_channel; | |
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301 | END GENERATE ALL_lane; | |
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302 | ||
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303 | PROCESS (clk, rstn) | |
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304 | BEGIN -- PROCESS | |
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305 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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306 | sample_f0_val <= '0'; | |
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307 | sample_f1_val <= '0'; | |
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308 | sample_f2_val <= '0'; | |
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309 | sample_f3_val <= '0'; | |
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310 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
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311 | sample_f0_val <= sample_f_val(0); | |
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312 | sample_f1_val <= sample_f_val(1); | |
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313 | sample_f2_val <= sample_f_val(2); | |
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314 | sample_f3_val <= sample_f_val(3); | |
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315 | END IF; | |
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316 | END PROCESS; | |
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317 | ||
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318 | ||
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319 | sample_f0_data <= sample_f_data(1*6*16-1 DOWNTO 0*6*16); | |
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320 | sample_f1_data <= sample_f_data(2*6*16-1 DOWNTO 1*6*16); | |
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321 | sample_f2_data <= sample_f_data(3*6*16-1 DOWNTO 2*6*16); | |
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322 | sample_f3_data <= sample_f_data(4*6*16-1 DOWNTO 3*6*16); | |
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323 | ||
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324 | --sample_f0_data <= X"0020" & X"0010" & X"0008" & X"0004" & X"0002" & X"0001"; | |
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325 | --sample_f1_data <= X"1020" & X"1010" & X"1008" & X"1004" & X"1002" & X"1001"; | |
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326 | --sample_f2_data <= X"2020" & X"2010" & X"2008" & X"2004" & X"2002" & X"2001"; | |
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327 | --sample_f3_data <= X"4020" & X"4010" & X"4008" & X"4004" & X"4002" & X"4001"; | |
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279 | 328 | ----------------------------------------------------------------------------- |
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280 | 329 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
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281 | 330 | GENERIC MAP ( |
@@ -539,4 +588,4 BEGIN | |||
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539 | 588 | buffer_full_err => dma_buffer_full_err, --buffer_full_err, |
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540 | 589 | grant_error => dma_grant_error); --grant_error); |
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541 | 590 | |
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542 | END beh; No newline at end of file | |
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591 | END beh; |
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