##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

ReName some files
martin -
r242:30d38bdb4700 martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,125
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_cna.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34
35 entity APB_DAC is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
48 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
49 SCLK : out std_logic; --! Horloge systeme du convertisseur
50 DATA : out std_logic --! Donn�e num�rique s�rialis�
51 );
52 end entity;
53
54 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
55 --! et les sorties seront cabl�es vers le convertisseur.
56
57 architecture ar_APB_DAC of APB_DAC is
58
59 constant REVISION : integer := 1;
60
61 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask));
64
65 signal enable : std_logic;
66 signal flag_sd : std_logic;
67
68 type DAC_ctrlr_Reg is record
69 DAC_Cfg : std_logic_vector(1 downto 0);
70 DAC_Data : std_logic_vector(15 downto 0);
71 end record;
72
73 signal Rec : DAC_ctrlr_Reg;
74 signal Rdata : std_logic_vector(31 downto 0);
75
76 begin
77
78 enable <= Rec.DAC_Cfg(0);
79 Rec.DAC_Cfg(1) <= flag_sd;
80
81 CONV0 : DacDriver
82 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
83
84
85 process(rst,clk)
86 begin
87 if(rst='0')then
88 Rec.DAC_Data <= (others => '0');
89
90 elsif(clk'event and clk='1')then
91
92
93 --APB Write OP
94 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
95 case apbi.paddr(abits-1 downto 2) is
96 when "000000" =>
97 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
98 when "000001" =>
99 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 end if;
104
105 --APB Read OP
106 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
110 Rdata(1 downto 0) <= Rec.DAC_Cfg;
111 when "000001" =>
112 Rdata(31 downto 16) <= X"FD18";
113 Rdata(15 downto 0) <= Rec.DAC_Data;
114 when others =>
115 Rdata <= (others => '0');
116 end case;
117 end if;
118
119 end if;
120 apbo.pconfig <= pconfig;
121 end process;
122
123 apbo.prdata <= Rdata when apbi.penable = '1';
124 Cal_EN <= enable;
125 end architecture;
Show file before | Show file after | Hide comments
@@ -0,0 +1,68
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.Convertisseur_config.all;
26 use lpp.lpp_cna.all;
27
28 --! Programme du Convertisseur Num�rique/Analogique
29
30 entity DacDriver is
31 port(
32 clk : in std_logic; --! Horloge du composant
33 rst : in std_logic; --! Reset general du composant
34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
39 Data : out std_logic --! Donn�e num�rique s�rialis�
40 );
41 end entity;
42
43 --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
44 --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
45
46 architecture ar_DacDriver of DacDriver is
47
48 signal s_SCLK : std_logic;
49 signal OKAI_send : std_logic;
50
51 begin
52
53 SystemCLK : Systeme_Clock
54 generic map (nb_serial)
55 port map (clk,rst,s_SCLK);
56
57
58 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
60
61
62 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
64
65
66 SCLK <= s_SCLK;
67
68 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -31,7 +31,7 use lpp.lpp_amba.all;
31 31
32 32 package lpp_cna is
33 33
34 component APB_CNA is
34 component APB_DAC is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
@@ -51,7 +51,7 component APB_CNA is
51 51 end component;
52 52
53 53
54 component CNA_TabloC is
54 component DacDriver is
55 55 port(
56 56 clk : in std_logic;
57 57 rst : in std_logic;
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now