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CORRECTION ALU For Filter
pellion -
r161:2f796119d1bb JC
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
5
6 -------------------------------------------------------------------------------
7
8 ENTITY TB_Data_Acquisition IS
9
10 END TB_Data_Acquisition;
11
12 -------------------------------------------------------------------------------
13
14 ARCHITECTURE tb OF TB_Data_Acquisition IS
15
16 COMPONENT TestModule_ADS7886
17 GENERIC (
18 freq : INTEGER;
19 amplitude : INTEGER;
20 impulsion : INTEGER);
21 PORT (
22 cnv_run : IN STD_LOGIC;
23 cnv : IN STD_LOGIC;
24 sck : IN STD_LOGIC;
25 sdo : OUT STD_LOGIC);
26 END COMPONENT;
27
28 COMPONENT Top_Data_Acquisition
29 PORT (
30 cnv_run : IN STD_LOGIC;
31 cnv : OUT STD_LOGIC;
32 sck : OUT STD_LOGIC;
33 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
34 cnv_clk : IN STD_LOGIC;
35 cnv_rstn : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 --
39 sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
41 sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 --
44 sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
46 sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --
49 sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
50 sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
51 sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
52 sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
53 --
54 sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
55 sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
56 sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
57 sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
58 END COMPONENT;
59
60 -- component ports
61 SIGNAL cnv_rstn : STD_LOGIC;
62 SIGNAL cnv : STD_LOGIC;
63 SIGNAL rstn : STD_LOGIC;
64 SIGNAL sck : STD_LOGIC;
65 SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
66 SIGNAL run_cnv : STD_LOGIC;
67
68
69 -- clock
70 signal Clk : STD_LOGIC := '1';
71 SIGNAL cnv_clk : STD_LOGIC := '1';
72
73 -----------------------------------------------------------------------------
74 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
76 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 -----------------------------------------------------------------------------
79 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
81 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 -----------------------------------------------------------------------------
84 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
86 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 -----------------------------------------------------------------------------
89 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
91 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
93
94
95 BEGIN -- tb
96
97 MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
98 TestModule_ADS7886_u: TestModule_ADS7886
99 GENERIC MAP (
100 freq => 24*(I+1),
101 amplitude => 30000/(I+1),
102 impulsion => 0)
103 PORT MAP (
104 cnv_run => run_cnv,
105 cnv => cnv,
106 sck => sck,
107 sdo => sdo(I));
108 END GENERATE MODULE_ADS7886;
109
110 TestModule_ADS7886_u: TestModule_ADS7886
111 GENERIC MAP (
112 freq => 0,
113 amplitude => 30000,
114 impulsion => 1)
115 PORT MAP (
116 cnv_run => run_cnv,
117 cnv => cnv,
118 sck => sck,
119 sdo => sdo(7));
120
121
122 -- clock generation
123 Clk <= not Clk after 20 ns; -- 25 Mhz
124 cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
125
126 -- waveform generation
127 WaveGen_Proc: process
128 begin
129 -- insert signal assignments here
130 wait until Clk = '1';
131 rstn <= '0';
132 cnv_rstn <= '0';
133 run_cnv <= '0';
134 wait until Clk = '1';
135 wait until Clk = '1';
136 wait until Clk = '1';
137 rstn <= '1';
138 cnv_rstn <= '1';
139 wait until Clk = '1';
140 wait until Clk = '1';
141 wait until Clk = '1';
142 wait until Clk = '1';
143 wait until Clk = '1';
144 wait until Clk = '1';
145 run_cnv <= '1';
146 wait;
147
148 end process WaveGen_Proc;
149
150 -----------------------------------------------------------------------------
151
152 Top_Data_Acquisition_1: Top_Data_Acquisition
153 PORT MAP (
154 cnv_run => run_cnv,
155 cnv => cnv,
156 sck => sck,
157 sdo => sdo,
158 cnv_clk => cnv_clk,
159 cnv_rstn => cnv_rstn,
160 clk => clk,
161 rstn => rstn,
162 --
163 sample_f0_0_ren => sample_f0_0_ren,
164 sample_f0_0_rdata => sample_f0_0_rdata,
165 sample_f0_0_full => sample_f0_0_full,
166 sample_f0_0_empty => sample_f0_0_empty,
167 --
168 sample_f0_1_ren => sample_f0_1_ren,
169 sample_f0_1_rdata => sample_f0_1_rdata,
170 sample_f0_1_full => sample_f0_1_full,
171 sample_f0_1_empty => sample_f0_1_empty,
172 --
173 sample_f1_ren => sample_f1_ren,
174 sample_f1_rdata => sample_f1_rdata,
175 sample_f1_full => sample_f1_full,
176 sample_f1_empty => sample_f1_empty,
177 --
178 sample_f3_ren => sample_f3_ren,
179 sample_f3_rdata => sample_f3_rdata,
180 sample_f3_full => sample_f3_full,
181 sample_f3_empty => sample_f3_empty
182 );
183 sample_f0_0_ren <= (OTHERS => '1');
184 sample_f0_1_ren <= (OTHERS => '1');
185 sample_f1_ren <= (OTHERS => '1');
186 sample_f3_ren <= (OTHERS => '1');
187
188 END tb;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.lpp_top_lfr_pkg.ALL;
6
7 -------------------------------------------------------------------------------
8
9 ENTITY TB_Data_Acquisition IS
10
11 END TB_Data_Acquisition;
12
13 -------------------------------------------------------------------------------
14
15 ARCHITECTURE tb OF TB_Data_Acquisition IS
16
17 COMPONENT TestModule_ADS7886
18 GENERIC (
19 freq : INTEGER;
20 amplitude : INTEGER;
21 impulsion : INTEGER);
22 PORT (
23 cnv_run : IN STD_LOGIC;
24 cnv : IN STD_LOGIC;
25 sck : IN STD_LOGIC;
26 sdo : OUT STD_LOGIC);
27 END COMPONENT;
28
29 -- component ports
30 SIGNAL cnv_rstn : STD_LOGIC;
31 SIGNAL cnv : STD_LOGIC;
32 SIGNAL rstn : STD_LOGIC;
33 SIGNAL sck : STD_LOGIC;
34 SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
35 SIGNAL run_cnv : STD_LOGIC;
36
37
38 -- clock
39 signal Clk : STD_LOGIC := '1';
40 SIGNAL cnv_clk : STD_LOGIC := '1';
41
42 -----------------------------------------------------------------------------
43 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
44 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 -----------------------------------------------------------------------------
46 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
47 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 -----------------------------------------------------------------------------
49 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
50 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 -----------------------------------------------------------------------------
52 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
53 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
54
55 BEGIN -- tb
56
57 MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
58 TestModule_ADS7886_u: TestModule_ADS7886
59 GENERIC MAP (
60 freq => 24*(I+1),
61 amplitude => 30000/(I+1),
62 impulsion => 0)
63 PORT MAP (
64 cnv_run => run_cnv,
65 cnv => cnv,
66 sck => sck,
67 sdo => sdo(I));
68 END GENERATE MODULE_ADS7886;
69
70 TestModule_ADS7886_u: TestModule_ADS7886
71 GENERIC MAP (
72 freq => 0,
73 amplitude => 30000,
74 impulsion => 1)
75 PORT MAP (
76 cnv_run => run_cnv,
77 cnv => cnv,
78 sck => sck,
79 sdo => sdo(7));
80
81
82 -- clock generation
83 Clk <= not Clk after 20 ns; -- 25 Mhz
84 cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
85
86 -- waveform generation
87 WaveGen_Proc: process
88 begin
89 -- insert signal assignments here
90 wait until Clk = '1';
91 rstn <= '0';
92 cnv_rstn <= '0';
93 run_cnv <= '0';
94 wait until Clk = '1';
95 wait until Clk = '1';
96 wait until Clk = '1';
97 rstn <= '1';
98 cnv_rstn <= '1';
99 wait until Clk = '1';
100 wait until Clk = '1';
101 wait until Clk = '1';
102 wait until Clk = '1';
103 wait until Clk = '1';
104 wait until Clk = '1';
105 run_cnv <= '1';
106 wait;
107
108 end process WaveGen_Proc;
109
110 -----------------------------------------------------------------------------
111
112 Top_Data_Acquisition_1: lpp_top_acq
113 PORT MAP (
114 cnv_run => run_cnv,
115 cnv => cnv,
116 sck => sck,
117 sdo => sdo,
118 cnv_clk => cnv_clk,
119 cnv_rstn => cnv_rstn,
120 clk => clk,
121 rstn => rstn,
122 --
123 sample_f0_wen => sample_f0_wen,
124 sample_f0_wdata => sample_f0_wdata,
125 --
126 sample_f1_wen => sample_f1_wen,
127 sample_f1_wdata => sample_f1_wdata,
128 --
129 sample_f2_wen => sample_f2_wen,
130 sample_f2_wdata => sample_f2_wdata,
131 --
132 sample_f3_wen => sample_f3_wen,
133 sample_f3_wdata => sample_f3_wdata
134 );
135
136
137
138
139
140 END tb;
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@@ -1,49 +1,54
1
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
17
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
22 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
23
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
28
29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
32
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
34
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
37
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
41
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
44
45 #vsim work.TB_Data_Acquisition
46
47 #log -r *
48 #do wave_data_acquisition.do
1
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
17
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
23 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
24
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
28 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
29
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
32 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
33
34 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
35
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
37 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
38
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd
41 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
42
43
44 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
45 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
46 #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd
47
48 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
49
50 vsim work.TB_Data_Acquisition
51
52 #log -r *
53 #do wave_data_acquisition.do
49 54 #run 5 ms No newline at end of file
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@@ -1,231 +1,38
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/chanelcount
4 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv_high
5 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv
6 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_clk
7 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_rstn
8 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run
9 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv
10 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/clk
11 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/rstn
12 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sck
13 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sdo
14 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample
15 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val
16 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_cycle_counter
17 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_s
18 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync
19 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync_r
20 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_done
21 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_bit_counter
22 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/shift_reg
23 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run_sync
24 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/tech
25 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_sz
26 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/chanelscount
27 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coef_sz
28 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefcntpercel
29 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/cels_count
30 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/mem_use
31 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/reset
32 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/clk
33 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk
34 add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in
35 add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out
36 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos
37 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest
38 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs
39 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old
40 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel
41 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read
42 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr
43 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count
44 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write
45 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel
46 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0
47 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in
48 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk
49 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out
50 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl
51 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in
52 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in
53 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out
54 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel
55 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan
56 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff
57 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff
58 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg
59 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state
60 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run
61 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv
62 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck
63 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo
64 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk
65 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn
66 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk
67 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn
68 add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample
69 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val
70 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs
71 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in
72 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out
73 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state
74 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff
75 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing
76 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing
77 add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk
78 add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset
79 add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl
80 add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1
81 add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2
82 add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res
83 add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input
84 add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
85 add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
86 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn
87 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk
88 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos
89 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs
90 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src
91 add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata
92 add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input
93 add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write
94 add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read
95 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst
96 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1
97 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous
98 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input
99 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff
100 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl
101 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in
102 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out
103 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
104 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
105 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
106 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample
107 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s
108 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff
109 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s
110 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef
111 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn
112 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk
113 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos
114 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs
115 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val
116 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in
117 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val
118 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out
119 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src
120 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata
121 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write
122 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read
123 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst
124 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1
125 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous
126 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input
127 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff
128 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl
129 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf
130 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate
131 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s
132 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s
133 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2
134 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s
135 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s
136 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2
137 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src
138 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
139 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
140 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in
141 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
142 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous
143 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write
144 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata
145 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
146 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
147 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
148 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input
149 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read
150 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst
151 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1
152 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
153 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff
154 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s
155 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef
156 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff
157 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input
158 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
159 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
160 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl
161 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef
162 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample
163 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s
164 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
165 add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state
166 add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing
167 add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing
168 add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out
169 add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn
170 add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk
171 add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray
172 add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter
173 add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst
174 add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1
175 add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous
176 add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write
177 add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen
178 add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr
179 add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd
180 add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in
181 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read
182 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren
183 add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr
184 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd
185 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out
186 add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val
187 add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in
188 add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val
189 add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out
190 add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4)
191 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk
192 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset
193 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac
194 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add
195 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1
196 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2
197 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res
198 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add
199 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult
200 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout
201 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina
202 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb
203 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout
204 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel
205 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz
206 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz
207 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel
208 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d
209 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d
210 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d
211 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d
212 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d
213 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d
214 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d
215 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d
216 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d
217 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val
218 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot
219 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state
220 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out
221 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s
222 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2
223 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s
224 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s
225 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2
3 add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample
4 add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val
5 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val
6 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in
7 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val
8 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out
9 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val
10 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in
11 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val
12 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out
13 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val
14 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in
15 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val
16 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out
17 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val
18 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in
19 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val
20 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out
21 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val
22 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in
23 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val
24 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out
25 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen
26 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata
27 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen
28 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata
29 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen
30 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata
31 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen
32 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata
226 33 TreeUpdate [SetDefaultTree]
227 WaveRestoreCursors {{Cursor 1} {4520000 ps} 0}
228 configure wave -namecolwidth 677
34 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
35 configure wave -namecolwidth 430
229 36 configure wave -valuecolwidth 100
230 37 configure wave -justifyvalue left
231 38 configure wave -signalnamewidth 0
@@ -239,4 +46,4 configure wave -griddelta 40
239 46 configure wave -timeline 0
240 47 configure wave -timelineunits ns
241 48 update
242 WaveRestoreZoom {2722930 ps} {6210191 ps}
49 WaveRestoreZoom {0 ps} {754717 ps}
Show file before | Show file after | Hide comments
@@ -196,7 +196,8 BEGIN
196 196 GENERIC MAP (
197 197 Arith_en => 1,
198 198 Input_SZ_1 => Sample_SZ,
199 Input_SZ_2 => Coef_SZ)
199 Input_SZ_2 => Coef_SZ,
200 COMP_EN => 1)
200 201 PORT MAP (
201 202 clk => clk,
202 203 reset => rstn,
Show file before | Show file after | Hide comments
@@ -72,7 +72,7 BEGIN
72 72 memCEL : IF Mem_use = use_CEL GENERATE
73 73 WEN <= NOT ram_write;
74 74 REN <= NOT ram_read;
75 RAMblk : RAM_CEL
75 RAMblk : RAM_CEL_N
76 76 GENERIC MAP(Input_SZ_1)
77 77 PORT MAP(
78 78 WD => WD,
Show file before | Show file after | Hide comments
@@ -216,6 +216,18 PACKAGE iir_filter IS
216 216 RWCLK, RESET : IN STD_LOGIC);
217 217 END COMPONENT;
218 218
219 COMPONENT RAM_CEL_N
220 GENERIC (
221 size : INTEGER);
222 PORT (
223 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
224 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
225 WEN, REN : IN STD_LOGIC;
226 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
227 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
228 RWCLK, RESET : IN STD_LOGIC);
229 END COMPONENT;
230
219 231 COMPONENT IIR_CEL_FILTER IS
220 232 GENERIC(
221 233 tech : INTEGER := 0;
Show file before | Show file after | Hide comments
@@ -32,7 +32,9 generic(
32 32 Arith_en : integer := 1;
33 33 Logic_en : integer := 1;
34 34 Input_SZ_1 : integer := 16;
35 Input_SZ_2 : integer := 16);
35 Input_SZ_2 : integer := 16;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37 );
36 38 port(
37 39 clk : in std_logic; --! Horloge du composant
38 40 reset : in std_logic; --! Reset general du composant
@@ -56,8 +58,8 begin
56 58
57 59 arith : if Arith_en = 1 generate
58 60 MACinst : MAC
59 generic map(Input_SZ_1,Input_SZ_2)
61 generic map(Input_SZ_1,Input_SZ_2,COMP_EN)
60 62 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
61 63 end generate;
62 64
63 end architecture; No newline at end of file
65 end architecture;
Show file before | Show file after | Hide comments
@@ -32,7 +32,8 USE lpp.general_purpose.ALL;
32 32 ENTITY MAC IS
33 33 GENERIC(
34 34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8
35 Input_SZ_B : INTEGER := 8;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
36 37
37 38 );
38 39 PORT(
@@ -52,35 +53,35 END MAC;
52 53
53 54 ARCHITECTURE ar_MAC OF MAC IS
54 55
55 signal add,mult : std_logic;
56 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56 SIGNAL add, mult : STD_LOGIC;
57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
57 58
58 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
59 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
60 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
59 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 62
62 signal MACMUXsel : std_logic;
63 signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
63 SIGNAL MACMUXsel : STD_LOGIC;
64 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 66
66 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
67 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
67 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
68 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
68 69
69 signal MACMUX2sel : std_logic;
70 SIGNAL MACMUX2sel : STD_LOGIC;
70 71
71 signal add_D : std_logic;
72 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
73 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
74 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
75 signal MACMUXsel_D : std_logic;
76 signal MACMUX2sel_D : std_logic;
77 signal MACMUX2sel_D_D : std_logic;
78 signal clr_MAC_D : std_logic;
79 signal clr_MAC_D_D : std_logic;
80 signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0);
72 SIGNAL add_D : STD_LOGIC;
73 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
74 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
75 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
76 SIGNAL MACMUXsel_D : STD_LOGIC;
77 SIGNAL MACMUX2sel_D : STD_LOGIC;
78 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
79 SIGNAL clr_MAC_D : STD_LOGIC;
80 SIGNAL clr_MAC_D_D : STD_LOGIC;
81 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
81 82
82 SIGNAL load_mult_result : STD_LOGIC;
83 SIGNAL load_mult_result_D : STD_LOGIC;
83 SIGNAL load_mult_result : STD_LOGIC;
84 SIGNAL load_mult_result_D : STD_LOGIC;
84 85
85 86 BEGIN
86 87
@@ -113,25 +114,25 BEGIN
113 114 Input_SZ_A => Input_SZ_A,
114 115 Input_SZ_B => Input_SZ_B
115 116 )
116 port map(
117 clk => clk,
118 reset => reset,
119 mult => mult,
120 OP1 => OP1_2C,
121 OP2 => OP2_2C,
122 RES => MULTout
123 );
117 PORT MAP(
118 clk => clk,
119 reset => reset,
120 mult => mult,
121 OP1 => OP1_2C,
122 OP2 => OP2_2C,
123 RES => MULTout
124 );
124 125 --==============================================================
125 126
126 127 PROCESS (clk, reset)
127 128 BEGIN -- PROCESS
128 129 IF reset = '0' THEN -- asynchronous reset (active low)
129 130 load_mult_result_D <= '0';
130 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
131 132 load_mult_result_D <= load_mult_result;
132 133 END IF;
133 134 END PROCESS;
134
135
135 136 --==============================================================
136 137 --======================A D D E R ==============================
137 138 --==============================================================
@@ -154,32 +155,38 port map(
154 155 --==============================================================
155 156 --===================TWO COMPLEMENTERS==========================
156 157 --==============================================================
157 TWO_COMPLEMENTER1 : TwoComplementer
158 generic map(
159 Input_SZ => Input_SZ_A
160 )
161 port map(
162 clk => clk,
163 reset => reset,
164 clr => clr_MAC,
165 TwoComp => Comp_2C(0),
166 OP => OP1,
167 RES => OP1_2C
168 );
158 gen_comp : IF COMP_EN = 0 GENERATE
159 TWO_COMPLEMENTER1 : TwoComplementer
160 GENERIC MAP(
161 Input_SZ => Input_SZ_A
162 )
163 PORT MAP(
164 clk => clk,
165 reset => reset,
166 clr => clr_MAC,
167 TwoComp => Comp_2C(0),
168 OP => OP1,
169 RES => OP1_2C
170 );
169 171
170
171 TWO_COMPLEMENTER2 : TwoComplementer
172 generic map(
173 Input_SZ => Input_SZ_B
174 )
175 port map(
176 clk => clk,
177 reset => reset,
178 clr => clr_MAC,
179 TwoComp => Comp_2C(1),
180 OP => OP2,
181 RES => OP2_2C
182 );
172 TWO_COMPLEMENTER2 : TwoComplementer
173 GENERIC MAP(
174 Input_SZ => Input_SZ_B
175 )
176 PORT MAP(
177 clk => clk,
178 reset => reset,
179 clr => clr_MAC,
180 TwoComp => Comp_2C(1),
181 OP => OP2,
182 RES => OP2_2C
183 );
184 END GENERATE gen_comp;
185
186 no_gen_comp : IF COMP_EN = 1 GENERATE
187 OP2_2C <= OP2;
188 OP1_2C <= OP1;
189 END GENERATE no_gen_comp;
183 190 --==============================================================
184 191
185 192 clr_MACREG1 : MAC_REG
@@ -200,24 +207,24 port map(
200 207 Q(0) => add_D
201 208 );
202 209
203 OP1REG : MAC_REG
204 generic map(size => Input_SZ_A)
205 port map(
206 reset => reset,
207 clk => clk,
208 D => OP1_2C,
209 Q => OP1_2C_D
210 );
210 OP1REG : MAC_REG
211 GENERIC MAP(size => Input_SZ_A)
212 PORT MAP(
213 reset => reset,
214 clk => clk,
215 D => OP1_2C,
216 Q => OP1_2C_D
217 );
211 218
212 219
213 OP2REG : MAC_REG
214 generic map(size => Input_SZ_B)
215 port map(
216 reset => reset,
217 clk => clk,
218 D => OP2_2C,
219 Q => OP2_2C_D
220 );
220 OP2REG : MAC_REG
221 GENERIC MAP(size => Input_SZ_B)
222 PORT MAP(
223 reset => reset,
224 clk => clk,
225 D => OP2_2C,
226 Q => OP2_2C_D
227 );
221 228
222 229 MULToutREG : MAC_REG
223 230 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
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@@ -83,7 +83,8 PACKAGE general_purpose IS
83 83 Arith_en : INTEGER := 1;
84 84 Logic_en : INTEGER := 1;
85 85 Input_SZ_1 : INTEGER := 16;
86 Input_SZ_2 : INTEGER := 9
86 Input_SZ_2 : INTEGER := 9;
87 COMP_EN : INTEGER := 0 -- 1 => No Comp
87 88
88 89 );
89 90 PORT(
@@ -110,7 +111,8 Constant ctrl_CLRMAC : std_logic_vector(
110 111 COMPONENT MAC IS
111 112 GENERIC(
112 113 Input_SZ_A : INTEGER := 8;
113 Input_SZ_B : INTEGER := 8
114 Input_SZ_B : INTEGER := 8;
115 COMP_EN : INTEGER := 0 -- 1 => No Comp
114 116 );
115 117 PORT(
116 118 clk : IN STD_LOGIC;
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (606 lines changed) Show them Hide them
@@ -1,303 +1,303
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
11
12 ENTITY lpp_top_acq IS
13 GENERIC(
14 tech : INTEGER := 0
15 );
16 PORT (
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
25 --
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
28 --
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 --
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
40 );
41 END lpp_top_acq;
42
43 ARCHITECTURE tb OF lpp_top_acq IS
44
45 COMPONENT Downsampling
46 GENERIC (
47 ChanelCount : INTEGER;
48 SampleSize : INTEGER;
49 DivideParam : INTEGER);
50 PORT (
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_out_val : OUT STD_LOGIC;
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 END COMPONENT;
58
59 -----------------------------------------------------------------------------
60 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv : INTEGER := 500;
63
64 -----------------------------------------------------------------------------
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
68 -----------------------------------------------------------------------------
69 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
73
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 --
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 -----------------------------------------------------------------------------
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 --
87 SIGNAL sample_f0_val : STD_LOGIC;
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 -----------------------------------------------------------------------------
90 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
93 SIGNAL sample_f2_val : STD_LOGIC;
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 --
96 SIGNAL sample_f3_val : STD_LOGIC;
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98
99 BEGIN
100
101 -- component instantiation
102 -----------------------------------------------------------------------------
103 DIGITAL_acquisition : ADS7886_drvr
104 GENERIC MAP (
105 ChanelCount => ChanelCount,
106 ncycle_cnv_high => ncycle_cnv_high,
107 ncycle_cnv => ncycle_cnv)
108 PORT MAP (
109 cnv_clk => cnv_clk, --
110 cnv_rstn => cnv_rstn, --
111 cnv_run => cnv_run, --
112 cnv => cnv, --
113 clk => clk, --
114 rstn => rstn, --
115 sck => sck, --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
117 sample => sample,
118 sample_val => sample_val);
119
120 -----------------------------------------------------------------------------
121
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 sample_val_delay <= '0';
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 sample_val_delay <= sample_val;
128 END IF;
129 END PROCESS;
130
131 -----------------------------------------------------------------------------
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
134 sample_filter_in(i, j) <= sample(i)(j);
135 END GENERATE;
136
137 sample_filter_in(i, 16) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
139 END GENERATE;
140
141 coefs_v2 <= CoefsInitValCst_v2;
142
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 GENERIC MAP (
145 tech => 0,
146 Mem_use => use_RAM,
147 Sample_SZ => 18,
148 Coef_SZ => Coef_SZ,
149 Coef_Nb => 25, -- TODO
150 Coef_sel_SZ => 5, -- TODO
151 Cels_count => Cels_count,
152 ChanelsCount => ChanelCount)
153 PORT MAP (
154 rstn => rstn,
155 clk => clk,
156 virg_pos => 7,
157 coefs => coefs_v2,
158 sample_in_val => sample_val_delay,
159 sample_in => sample_filter_in,
160 sample_out_val => sample_filter_v2_out_val,
161 sample_out => sample_filter_v2_out);
162
163 -----------------------------------------------------------------------------
164 PROCESS (clk, rstn)
165 BEGIN -- PROCESS
166 IF rstn = '0' THEN -- asynchronous reset (active low)
167 sample_filter_v2_out_r_val <= '0';
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
170 sample_filter_v2_out_r(I, J) <= '0';
171 END LOOP rst_all_bits;
172 END LOOP rst_all_chanel;
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
175 IF sample_filter_v2_out_val = '1' THEN
176 sample_filter_v2_out_r <= sample_filter_v2_out;
177 END IF;
178 END IF;
179 END PROCESS;
180
181 -----------------------------------------------------------------------------
182 -- F0 -- @24.576 kHz
183 -----------------------------------------------------------------------------
184 Downsampling_f0 : Downsampling
185 GENERIC MAP (
186 ChanelCount => ChanelCount,
187 SampleSize => 18,
188 DivideParam => 4)
189 PORT MAP (
190 clk => clk,
191 rstn => rstn,
192 sample_in_val => sample_filter_v2_out_val ,
193 sample_in => sample_filter_v2_out,
194 sample_out_val => sample_f0_val,
195 sample_out => sample_f0);
196
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
198 sample_f0_wdata(I) <= sample_f0(0, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
203 END GENERATE all_bit_sample_f0;
204
205 sample_f0_wen <= NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
209 NOT(sample_f0_val);
210
211 -----------------------------------------------------------------------------
212 -- F1 -- @4096 Hz
213 -----------------------------------------------------------------------------
214 Downsampling_f1 : Downsampling
215 GENERIC MAP (
216 ChanelCount => ChanelCount,
217 SampleSize => 18,
218 DivideParam => 6)
219 PORT MAP (
220 clk => clk,
221 rstn => rstn,
222 sample_in_val => sample_f0_val ,
223 sample_in => sample_f0,
224 sample_out_val => sample_f1_val,
225 sample_out => sample_f1);
226
227 sample_f1_wen <= NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
231 NOT(sample_f1_val);
232
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
234 sample_f1_wdata(I) <= sample_f1(0, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
239 END GENERATE all_bit_sample_f1;
240
241 -----------------------------------------------------------------------------
242 -- F2 -- @16 Hz
243 -----------------------------------------------------------------------------
244 Downsampling_f2 : Downsampling
245 GENERIC MAP (
246 ChanelCount => ChanelCount,
247 SampleSize => 18,
248 DivideParam => 256)
249 PORT MAP (
250 clk => clk,
251 rstn => rstn,
252 sample_in_val => sample_f1_val ,
253 sample_in => sample_f1,
254 sample_out_val => sample_f2_val,
255 sample_out => sample_f2);
256
257 sample_f2_wen <= NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
261 NOT(sample_f2_val);
262
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
264 sample_f2_wdata(I) <= sample_f2(0, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
269 END GENERATE all_bit_sample_f2;
270
271 -----------------------------------------------------------------------------
272 -- F3 -- @256 Hz
273 -----------------------------------------------------------------------------
274 Downsampling_f3 : Downsampling
275 GENERIC MAP (
276 ChanelCount => ChanelCount,
277 SampleSize => 18,
278 DivideParam => 96)
279 PORT MAP (
280 clk => clk,
281 rstn => rstn,
282 sample_in_val => sample_f0_val ,
283 sample_in => sample_f0,
284 sample_out_val => sample_f3_val,
285 sample_out => sample_f3);
286
287 sample_f3_wen <= (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
291 (NOT sample_f3_val);
292
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
294 sample_f3_wdata(I) <= sample_f3(0, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
299 END GENERATE all_bit_sample_f3;
300
301
302
303 END tb;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
11
12 ENTITY lpp_top_acq IS
13 GENERIC(
14 tech : INTEGER := 0
15 );
16 PORT (
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
25 --
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
28 --
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 --
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
40 );
41 END lpp_top_acq;
42
43 ARCHITECTURE tb OF lpp_top_acq IS
44
45 COMPONENT Downsampling
46 GENERIC (
47 ChanelCount : INTEGER;
48 SampleSize : INTEGER;
49 DivideParam : INTEGER);
50 PORT (
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_out_val : OUT STD_LOGIC;
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 END COMPONENT;
58
59 -----------------------------------------------------------------------------
60 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv : INTEGER := 500;
63
64 -----------------------------------------------------------------------------
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
68 -----------------------------------------------------------------------------
69 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
73
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 --
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 -----------------------------------------------------------------------------
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 --
87 SIGNAL sample_f0_val : STD_LOGIC;
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 -----------------------------------------------------------------------------
90 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
93 SIGNAL sample_f2_val : STD_LOGIC;
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 --
96 SIGNAL sample_f3_val : STD_LOGIC;
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98
99 BEGIN
100
101 -- component instantiation
102 -----------------------------------------------------------------------------
103 DIGITAL_acquisition : AD7688_drvr
104 GENERIC MAP (
105 ChanelCount => ChanelCount,
106 ncycle_cnv_high => ncycle_cnv_high,
107 ncycle_cnv => ncycle_cnv)
108 PORT MAP (
109 cnv_clk => cnv_clk, --
110 cnv_rstn => cnv_rstn, --
111 cnv_run => cnv_run, --
112 cnv => cnv, --
113 clk => clk, --
114 rstn => rstn, --
115 sck => sck, --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
117 sample => sample,
118 sample_val => sample_val);
119
120 -----------------------------------------------------------------------------
121
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 sample_val_delay <= '0';
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 sample_val_delay <= sample_val;
128 END IF;
129 END PROCESS;
130
131 -----------------------------------------------------------------------------
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
134 sample_filter_in(i, j) <= sample(i)(j);
135 END GENERATE;
136
137 sample_filter_in(i, 16) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
139 END GENERATE;
140
141 coefs_v2 <= CoefsInitValCst_v2;
142
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 GENERIC MAP (
145 tech => 0,
146 Mem_use => use_CEL,
147 Sample_SZ => 18,
148 Coef_SZ => Coef_SZ,
149 Coef_Nb => 25, -- TODO
150 Coef_sel_SZ => 5, -- TODO
151 Cels_count => Cels_count,
152 ChanelsCount => ChanelCount)
153 PORT MAP (
154 rstn => rstn,
155 clk => clk,
156 virg_pos => 7,
157 coefs => coefs_v2,
158 sample_in_val => sample_val_delay,
159 sample_in => sample_filter_in,
160 sample_out_val => sample_filter_v2_out_val,
161 sample_out => sample_filter_v2_out);
162
163 -----------------------------------------------------------------------------
164 PROCESS (clk, rstn)
165 BEGIN -- PROCESS
166 IF rstn = '0' THEN -- asynchronous reset (active low)
167 sample_filter_v2_out_r_val <= '0';
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
170 sample_filter_v2_out_r(I, J) <= '0';
171 END LOOP rst_all_bits;
172 END LOOP rst_all_chanel;
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
175 IF sample_filter_v2_out_val = '1' THEN
176 sample_filter_v2_out_r <= sample_filter_v2_out;
177 END IF;
178 END IF;
179 END PROCESS;
180
181 -----------------------------------------------------------------------------
182 -- F0 -- @24.576 kHz
183 -----------------------------------------------------------------------------
184 Downsampling_f0 : Downsampling
185 GENERIC MAP (
186 ChanelCount => ChanelCount,
187 SampleSize => 18,
188 DivideParam => 4)
189 PORT MAP (
190 clk => clk,
191 rstn => rstn,
192 sample_in_val => sample_filter_v2_out_val ,
193 sample_in => sample_filter_v2_out,
194 sample_out_val => sample_f0_val,
195 sample_out => sample_f0);
196
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
198 sample_f0_wdata(I) <= sample_f0(0, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
203 END GENERATE all_bit_sample_f0;
204
205 sample_f0_wen <= NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
209 NOT(sample_f0_val);
210
211 -----------------------------------------------------------------------------
212 -- F1 -- @4096 Hz
213 -----------------------------------------------------------------------------
214 Downsampling_f1 : Downsampling
215 GENERIC MAP (
216 ChanelCount => ChanelCount,
217 SampleSize => 18,
218 DivideParam => 6)
219 PORT MAP (
220 clk => clk,
221 rstn => rstn,
222 sample_in_val => sample_f0_val ,
223 sample_in => sample_f0,
224 sample_out_val => sample_f1_val,
225 sample_out => sample_f1);
226
227 sample_f1_wen <= NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
231 NOT(sample_f1_val);
232
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
234 sample_f1_wdata(I) <= sample_f1(0, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
239 END GENERATE all_bit_sample_f1;
240
241 -----------------------------------------------------------------------------
242 -- F2 -- @16 Hz
243 -----------------------------------------------------------------------------
244 Downsampling_f2 : Downsampling
245 GENERIC MAP (
246 ChanelCount => ChanelCount,
247 SampleSize => 18,
248 DivideParam => 256)
249 PORT MAP (
250 clk => clk,
251 rstn => rstn,
252 sample_in_val => sample_f1_val ,
253 sample_in => sample_f1,
254 sample_out_val => sample_f2_val,
255 sample_out => sample_f2);
256
257 sample_f2_wen <= NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
261 NOT(sample_f2_val);
262
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
264 sample_f2_wdata(I) <= sample_f2(0, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
269 END GENERATE all_bit_sample_f2;
270
271 -----------------------------------------------------------------------------
272 -- F3 -- @256 Hz
273 -----------------------------------------------------------------------------
274 Downsampling_f3 : Downsampling
275 GENERIC MAP (
276 ChanelCount => ChanelCount,
277 SampleSize => 18,
278 DivideParam => 96)
279 PORT MAP (
280 clk => clk,
281 rstn => rstn,
282 sample_in_val => sample_f0_val ,
283 sample_in => sample_f0,
284 sample_out_val => sample_f3_val,
285 sample_out => sample_f3);
286
287 sample_f3_wen <= (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
291 (NOT sample_f3_val);
292
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
294 sample_f3_wdata(I) <= sample_f3(0, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
299 END GENERATE all_bit_sample_f3;
300
301
302
303 END tb;
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